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2005-09-19 David Edelsohn <edelsohn@gnu.org>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3eb17e6b
PB		 12005-09-08 Paul Brook <paul@codesourcery.com>
2
3 * arm-dis.c (arm_opcodes, thumb32_opcodes): Rename smi to smc.
4
61cc0267
CF		 52005-09-06 Chao-ying Fu <fu@mips.com>
6
7 * mips-opc.c (MT32): New define.
8 (mips_builtin_opcodes): Move "bc0f", "bc0fl", "bc0t", "bc0tl" to the
9 bottom to avoid opcode collision with "mftr" and "mttr".
10 Add MT instructions.
11 * mips-dis.c (mips_arch_choices): Enable INSN_MT for mips32r2.
12 (print_insn_args): Add supports for +t, +T, !, $, *, &, g operand
13 formats.
14
b13dd07a
PB		 152005-09-02 Paul Brook <paul@codesourcery.com>
16
17 * arm-dis.c (coprocessor_opcodes): Add null terminator.
18
8f06b2d8
PB		 192005-09-02 Paul Brook <paul@codesourcery.com>
20
21 * arm-dis.c (coprocessor_opcodes): New.
22 (arm_opcodes, thumb32_opcodes): Remove coprocessor insns.
23 (print_insn_coprocessor): New function.
24 (print_insn_arm): Use print_insn_coprocessor. Remove coprocessor
25 format characters.
26 (print_insn_thumb32): Use print_insn_coprocessor.
27
a2dfd01f
PB		 282005-08-30 Paul Brook <paul@codesourcery.com>
29
30 * arm-dis.c (thumb_opcodes): Disassemble sub(3) as subs.
31
3f31e633
JB		 322005-08-26 Jan Beulich <jbeulich@novell.com>
33
34 * i386-dis.c (intel_operand_size): New, broken out from OP_E for
35 re-use.
36 (OP_E): Call intel_operand_size, move call site out of mode
37 dependent code.
38 (OP_OFF): Call intel_operand_size if suffix_always. Remove
39 ATTRIBUTE_UNUSED from parameters.
40 (OP_OFF64): Likewise.
41 (OP_ESreg): Call intel_operand_size.
42 (OP_DSreg): Likewise.
43 (OP_DIR): Use colon rather than semicolon as separator of far
44 jump/call operands.
45
fd25c5a9
CF		 462005-08-25 Chao-ying Fu <fu@mips.com>
47
48 * mips-opc.c (WR_a, RD_a, MOD_a, DSP_VOLA, D32): New define.
49 (mips_builtin_opcodes): Add DSP instructions.
50 * mips-dis.c (mips_arch_choices): Enable INSN_DSP for mips32, mips32r2,
51 mips64, mips64r2.
52 (print_insn_args): Add supports for 3, 4, 5, 6, 7, 8, 9, 0, :, ', @
53 operand formats.
54
dd8b7c22
DU		 552005-08-23 David Ung <davidu@mips.com>
56
57 * mips16-opc.c (mips16_opcodes): Add the MIPS16e jalrc/jrc
58 instructions to the table.
59
c17ae8a2
AM		 602005-08-18 Alan Modra <amodra@bigpond.net.au>
61
848cf006 62 * a29k-dis.c: Delete.
c17ae8a2
AM		 63 * Makefile.am: Remove a29k support.
64 * configure.in: Likewise.
65 * disassemble.c: Likewise.
66 * Makefile.in: Regenerate.
67 * configure: Regenerate.
68 * po/POTFILES.in: Regenerate.
69
36ae0db3
DJ		 702005-08-15 Daniel Jacobowitz <dan@codesourcery.com>
71
72 * ppc-dis.c (powerpc_dialect): Handle e300.
73 (print_ppc_disassembler_options): Likewise.
74 * ppc-opc.c (PPCE300): Define.
75 (powerpc_opcodes): Mark icbt as available for the e300.
76
63a3357b
DA		 772005-08-13 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
78
79 * hppa-dis.c (print_insn_hppa): Don't print '%' before register names.
80 Use "rp" instead of "%r2" in "b,l" insns.
81
ad101263
MS		 822005-08-12 Martin Schwidefsky <schwidefsky@de.ibm.com>
83
84 * s390-dis.c (print_insn_s390): Print unsigned operands with %u.
85 * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z9-109.
86 (main): Likewise.
87 * s390-opc.c (I32_16, U32_16, M_16): Add defines 32 bit immediates
88 and 4 bit optional masks.
89 (INSTR_RIL_RI, INSTR_RIL_RU, INSTR_RRF_M0RR, INSTR_RSE_CCRD,
90 INSTR_RSY_CCRD, INSTR_SSF_RRDRD): Add new instruction formats.
91 (MASK_RIL_RI, MASK_RIL_RU, MASK_RRF_M0RR, MASK_RSE_CCRD,
92 MASK_RSY_CCRD, MASK_SSF_RRDRD): Likewise.
93 (s390_opformats): Likewise.
94 * s390-opc.txt: Add new instructions for cpu type z9-109.
95
f1fa1093
DA		 962005-08-05 John David Anglin <dave.anglin@nrc-crnc.gc.ca>
97
98 * hppa-dis.c (print_insn_hppa): Prefix 21-bit values with "L%".
99
e9f89963
PB		 1002005-07-29 Paul Brook <paul@codesourcery.com>
101
102 * arm-dis.c: Fix disassebly of thumb2 writeback addressing modes.
103
92e90b6e
PB		 1042005-07-29 Paul Brook <paul@codesourcery.com>
105
106 * arm-dis.c (thumb32_opc): Fix addressing mode for tbh.
107 (print_insn_thumb32): Fix decoding of thumb2 'I' operands.
108
fd54057a
DD		 1092005-07-25 DJ Delorie <dj@redhat.com>
110
111 * m32c-asm.c Regenerate.
112 * m32c-dis.c Regenerate.
113
760c0f6a
DD		 1142005-07-20 DJ Delorie <dj@redhat.com>
115
116 * disassemble.c (disassemble_init_for_target): M32C ISAs are
117 enums, so convert them to bit masks, which attributes are.
118
85da3a56
NC		 1192005-07-18 Nick Clifton <nickc@redhat.com>
120
121 * configure.in: Restore alpha ordering to list of arches.
122 * configure: Regenerate.
123 * disassemble.c: Restore alpha ordering to list of arches.
124
1252005-07-18 Nick Clifton <nickc@redhat.com>
126
127 * m32c-asm.c: Regenerate.
128 * m32c-desc.c: Regenerate.
129 * m32c-desc.h: Regenerate.
130 * m32c-dis.c: Regenerate.
131 * m32c-ibld.h: Regenerate.
132 * m32c-opc.c: Regenerate.
133 * m32c-opc.h: Regenerate.
134
22cbf2e7
L		 1352005-07-18 H.J. Lu <hongjiu.lu@intel.com>
136
137 * i386-dis.c (PNI_Fixup): Update comment.
138 (VMX_Fixup): Properly handle the suffix check.
139
0aea0460
DA		 1402005-07-16 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
141
142 * hppa-dis.c (print_insn_hppa): Add space after 'w' in wide-mode
143 mfctl disassembly.
144
0f82ff91
AM		 1452005-07-16 Alan Modra <amodra@bigpond.net.au>
146
147 * Makefile.am: Run "make dep-am".
148 (stamp-m32c): Fix cpu dependencies.
149 * Makefile.in: Regenerate.
150 * ip2k-dis.c: Regenerate.
151
90700ea2
L		 1522007-07-15 H.J. Lu <hongjiu.lu@intel.com>
153
154 * i386-dis.c (OP_VMX): New. Handle Intel VMX Instructions.
155 (VMX_Fixup): New. Fix up Intel VMX Instructions.
156 (Em): New.
157 (Gm): New.
158 (VM): New.
159 (dis386_twobyte): Updated entries 0x78 and 0x79.
160 (twobyte_has_modrm): Likewise.
161 (grps): Use OP_VMX in the "sgdtIQ" entry. Updated GRP9.
162 (OP_G): Handle m_mode.
163
49f58d10
JB		 1642005-07-14 Jim Blandy <jimb@redhat.com>
165
166 Add support for the Renesas M32C and M16C.
167 * m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c: New.
168 * m32c-desc.h, m32c-opc.h: New.
169 * Makefile.am (HFILES): List m32c-desc.h and m32c-opc.h.
170 (CFILES): List m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c,
171 m32c-opc.c.
172 (ALL_MACHINES): List m32c-asm.lo, m32c-desc.lo, m32c-dis.lo,
173 m32c-ibld.lo, m32c-opc.lo.
174 (CLEANFILES): List stamp-m32c.
175 (M32C_DEPS): List stamp-m32c, if CGEN_MAINT.
176 (CGEN_CPUS): Add m32c.
177 (m32c-asm.c, m32c-desc.c, m32c-dis.c, m32c-ibld.c, m32c-opc.c)
178 (m32c-desc.h, m32c-opc.h): Depend on M32C_DEPS.
179 (m32c_opc_h): New variable.
180 (stamp-m32c, m32c-asm.lo, m32c-desc.lo, m32c-dis.lo, m32c-ibld.lo)
181 (m32c-opc.lo): New rules.
182 * Makefile.in: Regenerated.
183 * configure.in: Add case for bfd_m32c_arch.
184 * configure: Regenerated.
185 * disassemble.c (ARCH_m32c): New.
186 [ARCH_m32c]: #include "m32c-desc.h".
187 (disassembler) [ARCH_m32c]: Add case for bfd_arch_m32c.
188 (disassemble_init_for_target) [ARCH_m32c]: Same.
189
190 * cgen-ops.h, cgen-types.h: New files.
191 * Makefile.am (HFILES): List them.
192 * Makefile.in: Regenerated.
193
0fd3a477
JW		 1942005-07-07 Kaveh R. Ghazi <ghazi@caip.rutgers.edu>
195
196 * arc-dis.c, arm-dis.c, cris-dis.c, crx-dis.c, d10v-dis.c,
197 d30v-dis.c, fr30-dis.c, h8300-dis.c, h8500-dis.c, i860-dis.c,
198 ia64-dis.c, ip2k-dis.c, m10200-dis.c, m10300-dis.c,
199 m88k-dis.c, mcore-dis.c, mips-dis.c, ms1-dis.c, or32-dis.c,
200 ppc-dis.c, sh64-dis.c, sparc-dis.c, tic4x-dis.c, tic80-dis.c,
201 v850-dis.c: Fix format bugs.
202 * ia64-gen.c (fail, warn): Add format attribute.
203 * or32-opc.c (debug): Likewise.
204
22f8fcbd
NC		 2052005-07-07 Khem Raj <kraj@mvista.com>
206
207 * arm-dis.c (opcode32 arm_opcodes): Fix ARM VFP fadds instruction
208 disassembly pattern.
209
d125c27b
AM		 2102005-07-06 Alan Modra <amodra@bigpond.net.au>
211
212 * Makefile.am (stamp-m32r): Fix path to cpu files.
213 (stamp-m32r, stamp-iq2000): Likewise.
214 * Makefile.in: Regenerate.
215 * m32r-asm.c: Regenerate.
216 * po/POTFILES.in: Remove arm-opc.h. Add ms1-asm.c, ms1-desc.c,
217 ms1-desc.h, ms1-dis.c, ms1-ibld.c, ms1-opc.c, ms1-opc.h.
218
3ec2b351
NC		 2192005-07-05 Nick Clifton <nickc@redhat.com>
220
221 * iq2000-asm.c: Regenerate.
222 * ms1-asm.c: Regenerate.
223
30123838
JB		 2242005-07-05 Jan Beulich <jbeulich@novell.com>
225
226 * i386-dis.c (SVME_Fixup): New.
227 (grps): Use it for the lidt entry.
228 (PNI_Fixup): Call OP_M rather than OP_E.
229 (INVLPG_Fixup): Likewise.
230
b0eec63e
L		 2312005-07-04 H.J. Lu <hongjiu.lu@intel.com>
232
233 * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
234
47b0e7ad
NC		 2352005-07-01 Nick Clifton <nickc@redhat.com>
236
237 * a29k-dis.c: Update to ISO C90 style function declarations and
238 fix formatting.
239 * alpha-opc.c: Likewise.
240 * arc-dis.c: Likewise.
241 * arc-opc.c: Likewise.
242 * avr-dis.c: Likewise.
243 * cgen-asm.in: Likewise.
244 * cgen-dis.in: Likewise.
245 * cgen-ibld.in: Likewise.
246 * cgen-opc.c: Likewise.
247 * cris-dis.c: Likewise.
248 * d10v-dis.c: Likewise.
249 * d30v-dis.c: Likewise.
250 * d30v-opc.c: Likewise.
251 * dis-buf.c: Likewise.
252 * dlx-dis.c: Likewise.
253 * h8300-dis.c: Likewise.
254 * h8500-dis.c: Likewise.
255 * hppa-dis.c: Likewise.
256 * i370-dis.c: Likewise.
257 * i370-opc.c: Likewise.
258 * m10200-dis.c: Likewise.
259 * m10300-dis.c: Likewise.
260 * m68k-dis.c: Likewise.
261 * m88k-dis.c: Likewise.
262 * mips-dis.c: Likewise.
263 * mmix-dis.c: Likewise.
264 * msp430-dis.c: Likewise.
265 * ns32k-dis.c: Likewise.
266 * or32-dis.c: Likewise.
267 * or32-opc.c: Likewise.
268 * pdp11-dis.c: Likewise.
269 * pj-dis.c: Likewise.
270 * s390-dis.c: Likewise.
271 * sh-dis.c: Likewise.
272 * sh64-dis.c: Likewise.
273 * sparc-dis.c: Likewise.
274 * sparc-opc.c: Likewise.
275 * sysdep.h: Likewise.
276 * tic30-dis.c: Likewise.
277 * tic4x-dis.c: Likewise.
278 * tic80-dis.c: Likewise.
279 * v850-dis.c: Likewise.
280 * v850-opc.c: Likewise.
281 * vax-dis.c: Likewise.
282 * w65-dis.c: Likewise.
283 * z8kgen.c: Likewise.
284
285 * fr30-*: Regenerate.
286 * frv-*: Regenerate.
287 * ip2k-*: Regenerate.
288 * iq2000-*: Regenerate.
289 * m32r-*: Regenerate.
290 * ms1-*: Regenerate.
291 * openrisc-*: Regenerate.
292 * xstormy16-*: Regenerate.
293
cc16ba8c
BE		 2942005-06-23 Ben Elliston <bje@gnu.org>
295
296 * m68k-dis.c: Use ISC C90.
297 * m68k-opc.c: Formatting fixes.
298
4b185e97
DU		 2992005-06-16 David Ung <davidu@mips.com>
300
301 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
302 instructions to the table; seb/seh/sew/zeb/zeh/zew.
303
ac188222
DB		 3042005-06-15 Dave Brolley <brolley@redhat.com>
305
306 Contribute Morpho ms1 on behalf of Red Hat
307 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
308 ms1-opc.h: New files, Morpho ms1 target.
309
310 2004-05-14 Stan Cox <scox@redhat.com>
311
312 * disassemble.c (ARCH_ms1): Define.
313 (disassembler): Handle bfd_arch_ms1
314
315 2004-05-13 Michael Snyder <msnyder@redhat.com>
316
317 * Makefile.am, Makefile.in: Add ms1 target.
318 * configure.in: Ditto.
319
6b5d3a4d
ZW		 3202005-06-08 Zack Weinberg <zack@codesourcery.com>
321
322 * arm-opc.h: Delete; fold contents into ...
323 * arm-dis.c: ... here. Move includes of internal COFF headers
324 next to includes of internal ELF headers.
325 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
326 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
327 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
328 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
329 (iwmmxt_wwnames, iwmmxt_wwssnames):
330 Make const.
331 (regnames): Remove iWMMXt coprocessor register sets.
332 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
333 (get_arm_regnames): Adjust fourth argument to match above changes.
334 (set_iwmmxt_regnames): Delete.
335 (print_insn_arm): Constify 'c'. Use ISO syntax for function
336 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
337 and iwmmxt_cregnames, not set_iwmmxt_regnames.
338 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
339 ISO syntax for function pointer calls.
340
4a5329c6
ZW		 3412005-06-07 Zack Weinberg <zack@codesourcery.com>
342
343 * arm-dis.c: Split up the comments describing the format codes, so
344 that the ARM and 16-bit Thumb opcode tables each have comments
345 preceding them that describe all the codes, and only the codes,
346 valid in those tables. (32-bit Thumb table is already like this.)
347 Reorder the lists in all three comments to match the order in
348 which the codes are implemented.
349 Remove all forward declarations of static functions. Convert all
350 function definitions to ISO C format.
351 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
352 Return nothing.
353 (print_insn_thumb16): Remove unused case 'I'.
354 (print_insn): Update for changed calling convention of subroutines.
355
3d456fa1
JB		 3562005-05-25 Jan Beulich <jbeulich@novell.com>
357
358 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
359 hex (but retain it being displayed as signed). Remove redundant
360 checks. Add handling of displacements for 16-bit addressing in Intel
361 mode.
362
2888cb7a
JB		 3632005-05-25 Jan Beulich <jbeulich@novell.com>
364
365 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
366 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
367 masking of 'rm' in 16-bit memory address handling.
368
1ed8e1e4
AM		 3692005-05-19 Anton Blanchard <anton@samba.org>
370
371 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
372 (print_ppc_disassembler_options): Document it.
373 * ppc-opc.c (SVC_LEV): Define.
374 (LEV): Allow optional operand.
375 (POWER5): Define.
376 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
377 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
378
49cc2e69
KC		 3792005-05-19 Kelley Cook <kcook@gcc.gnu.org>
380
381 * Makefile.in: Regenerate.
382
c19d1205
ZW		 3832005-05-17 Zack Weinberg <zack@codesourcery.com>
384
385 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
386 instructions. Adjust disassembly of some opcodes to match
387 unified syntax.
388 (thumb32_opcodes): New table.
389 (print_insn_thumb): Rename print_insn_thumb16; don't handle
390 two-halfword branches here.
391 (print_insn_thumb32): New function.
392 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
393 and print_insn_thumb32. Be consistent about order of
394 halfwords when printing 32-bit instructions.
395
003519a7
L		 3962005-05-07 H.J. Lu <hongjiu.lu@intel.com>
397
398 PR 843
399 * i386-dis.c (branch_v_mode): New.
400 (indirEv): Use branch_v_mode instead of v_mode.
401 (OP_E): Handle branch_v_mode.
402
920a34a7
L		 4032005-05-07 H.J. Lu <hongjiu.lu@intel.com>
404
405 * d10v-dis.c (dis_2_short): Support 64bit host.
406
5de773c1
NC		 4072005-05-07 Nick Clifton <nickc@redhat.com>
408
409 * po/nl.po: Updated translation.
410
f4321104
NC		 4112005-05-07 Nick Clifton <nickc@redhat.com>
412
413 * Update the address and phone number of the FSF organization in
414 the GPL notices in the following files:
415 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
416 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
417 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
418 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
419 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
420 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
421 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
422 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
423 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
424 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
425 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
426 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
427 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
428 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
429 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
430 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
431 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
432 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
433 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
434 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
435 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
436 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
437 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
438 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
439 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
440 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
441 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
442 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
443 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
444 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
445 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
446 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
447 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
448
10b076a2
JW		 4492005-05-05 James E Wilson <wilson@specifixinc.com>
450
451 * ia64-opc.c: Include sysdep.h before libiberty.h.
452
022716b6
NC		 4532005-05-05 Nick Clifton <nickc@redhat.com>
454
455 * configure.in (ALL_LINGUAS): Add vi.
456 * configure: Regenerate.
457 * po/vi.po: New.
458
db5152b4
JG		 4592005-04-26 Jerome Guitton <guitton@gnat.com>
460
461 * configure.in: Fix the check for basename declaration.
462 * configure: Regenerate.
463
eed0d89a
AM		 4642005-04-19 Alan Modra <amodra@bigpond.net.au>
465
466 * ppc-opc.c (RTO): Define.
467 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
468 entries to suit PPC440.
469
791fe849
MK		 4702005-04-18 Mark Kettenis <kettenis@gnu.org>
471
472 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
473 Add xcrypt-ctr.
474
ffe58f7c
NC		 4752005-04-14 Nick Clifton <nickc@redhat.com>
476
477 * po/fi.po: New translation: Finnish.
478 * configure.in (ALL_LINGUAS): Add fi.
479 * configure: Regenerate.
480
9e9b66a9
AM		 4812005-04-14 Alan Modra <amodra@bigpond.net.au>
482
483 * Makefile.am (NO_WERROR): Define.
484 * configure.in: Invoke AM_BINUTILS_WARNINGS.
485 * Makefile.in: Regenerate.
486 * aclocal.m4: Regenerate.
487 * configure: Regenerate.
488
9494d739
NC		 4892005-04-04 Nick Clifton <nickc@redhat.com>
490
491 * fr30-asm.c: Regenerate.
492 * frv-asm.c: Regenerate.
493 * iq2000-asm.c: Regenerate.
494 * m32r-asm.c: Regenerate.
495 * openrisc-asm.c: Regenerate.
496
6128c599
JB		 4972005-04-01 Jan Beulich <jbeulich@novell.com>
498
499 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
500 visible operands in Intel mode. The first operand of monitor is
501 %rax in 64-bit mode.
502
373ff435
JB		 5032005-04-01 Jan Beulich <jbeulich@novell.com>
504
505 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
506 easier future additions.
507
4bd60896
JG		 5082005-03-31 Jerome Guitton <guitton@gnat.com>
509
510 * configure.in: Check for basename.
511 * configure: Regenerate.
512 * config.in: Ditto.
513
4cc91dba
L		 5142005-03-29 H.J. Lu <hongjiu.lu@intel.com>
515
516 * i386-dis.c (SEG_Fixup): New.
517 (Sv): New.
518 (dis386): Use "Sv" for 0x8c and 0x8e.
519
ec72cfe5
NC		 5202005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
521 Nick Clifton <nickc@redhat.com>
c19d1205 522
ec72cfe5
NC		 523 * vax-dis.c: (entry_addr): New varible: An array of user supplied
524 function entry mask addresses.
525 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 526 elements in entry_addr.
ec72cfe5
NC		 527 (entry_addr_total_slots): New variable: The total number of
528 elements in entry_addr.
529 (parse_disassembler_options): New function. Fills in the entry_addr
530 array.
531 (free_entry_array): New function. Release the memory used by the
532 entry addr array. Suppressed because there is no way to call it.
533 (is_function_entry): Check if a given address is a function's
534 start address by looking at supplied entry mask addresses and
535 symbol information, if available.
536 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
537
85064c79
L		 5382005-03-23 H.J. Lu <hongjiu.lu@intel.com>
539
540 * cris-dis.c (print_with_operands): Use ~31L for long instead
541 of ~31.
542
de7141c7
L		 5432005-03-20 H.J. Lu <hongjiu.lu@intel.com>
544
545 * mmix-opc.c (O): Revert the last change.
546 (Z): Likewise.
547
e493ab45
L		 5482005-03-19 H.J. Lu <hongjiu.lu@intel.com>
549
550 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
551 (Z): Likewise.
552
d8d7c459
HPN		 5532005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
554
555 * mmix-opc.c (O, Z): Force expression as unsigned long.
556
ebdb0383
NC		 5572005-03-18 Nick Clifton <nickc@redhat.com>
558
559 * ip2k-asm.c: Regenerate.
560 * op/opcodes.pot: Regenerate.
561
1ad12f97
NC		 5622005-03-16 Nick Clifton <nickc@redhat.com>
563 Ben Elliston <bje@au.ibm.com>
564
569acd2c 565 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 566 compiler command line. Enabled by default. Disable via
569acd2c 567 --disable-werror.
1ad12f97
NC		 568 * configure: Regenerate.
569
4eb30afc
AM		 5702005-03-16 Alan Modra <amodra@bigpond.net.au>
571
572 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
573 BOOKE.
574
ea8409f7
AM		 5752005-03-15 Alan Modra <amodra@bigpond.net.au>
576
729ae8d2
AM		 577 * po/es.po: Commit new Spanish translation.
578
ea8409f7
AM		 579 * po/fr.po: Commit new French translation.
580
4f495e61
NC		 5812005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
582
583 * vax-dis.c: Fix spelling error
584 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
585 of just "Entry mask: < r1 ... >"
586
0a003adc
ZW		 5872005-03-12 Zack Weinberg <zack@codesourcery.com>
588
589 * arm-dis.c (arm_opcodes): Document %E and %V.
590 Add entries for v6T2 ARM instructions:
591 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
592 (print_insn_arm): Add support for %E and %V.
885fc257 593 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 594
da99ee72
AM		 5952005-03-10 Jeff Baker <jbaker@qnx.com>
596 Alan Modra <amodra@bigpond.net.au>
597
598 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
599 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
600 (SPRG_MASK): Delete.
601 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 602 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 603 mfsprg4..7 after msprg and consolidate.
604
220abb21
AM		 6052005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
606
607 * vax-dis.c (entry_mask_bit): New array.
608 (print_insn_vax): Decode function entry mask.
609
0e06657a
AH		 6102005-03-07 Aldy Hernandez <aldyh@redhat.com>
611
612 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
613
06647dfd
AM		 6142005-03-05 Alan Modra <amodra@bigpond.net.au>
615
616 * po/opcodes.pot: Regenerate.
617
82b829a7
RR		 6182005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
619
220abb21 620 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 621 (dsmOneArcInst): Use the enum values for the decoding class.
622 Remove redundant case in the switch for decodingClass value 11.
82b829a7 623
c4a530c5
JB		 6242005-03-02 Jan Beulich <jbeulich@novell.com>
625
626 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
627 accesses.
628 (OP_C): Consider lock prefix in non-64-bit modes.
629
47d8304e
AM		 6302005-02-24 Alan Modra <amodra@bigpond.net.au>
631
632 * cris-dis.c (format_hex): Remove ineffective warning fix.
633 * crx-dis.c (make_instruction): Warning fix.
634 * frv-asm.c: Regenerate.
635
ec36c4a4
NC		 6362005-02-23 Nick Clifton <nickc@redhat.com>
637
33b71eeb
NC		 638 * cgen-dis.in: Use bfd_byte for buffers that are passed to
639 read_memory.
06647dfd 640
33b71eeb 641 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 642
ec36c4a4
NC		 643 * crx-dis.c (make_instruction): Move argument structure into inner
644 scope and ensure that all of its fields are initialised before
645 they are used.
646
33b71eeb
NC		 647 * fr30-asm.c: Regenerate.
648 * fr30-dis.c: Regenerate.
649 * frv-asm.c: Regenerate.
650 * frv-dis.c: Regenerate.
651 * ip2k-asm.c: Regenerate.
652 * ip2k-dis.c: Regenerate.
653 * iq2000-asm.c: Regenerate.
654 * iq2000-dis.c: Regenerate.
655 * m32r-asm.c: Regenerate.
656 * m32r-dis.c: Regenerate.
657 * openrisc-asm.c: Regenerate.
658 * openrisc-dis.c: Regenerate.
659 * xstormy16-asm.c: Regenerate.
660 * xstormy16-dis.c: Regenerate.
661
53c9ebc5
AM		 6622005-02-22 Alan Modra <amodra@bigpond.net.au>
663
664 * arc-ext.c: Warning fixes.
665 * arc-ext.h: Likewise.
666 * cgen-opc.c: Likewise.
667 * ia64-gen.c: Likewise.
668 * maxq-dis.c: Likewise.
669 * ns32k-dis.c: Likewise.
670 * w65-dis.c: Likewise.
671 * ia64-asmtab.c: Regenerate.
672
610ad19b
AM		 6732005-02-22 Alan Modra <amodra@bigpond.net.au>
674
675 * fr30-desc.c: Regenerate.
676 * fr30-desc.h: Regenerate.
677 * fr30-opc.c: Regenerate.
678 * fr30-opc.h: Regenerate.
679 * frv-desc.c: Regenerate.
680 * frv-desc.h: Regenerate.
681 * frv-opc.c: Regenerate.
682 * frv-opc.h: Regenerate.
683 * ip2k-desc.c: Regenerate.
684 * ip2k-desc.h: Regenerate.
685 * ip2k-opc.c: Regenerate.
686 * ip2k-opc.h: Regenerate.
687 * iq2000-desc.c: Regenerate.
688 * iq2000-desc.h: Regenerate.
689 * iq2000-opc.c: Regenerate.
690 * iq2000-opc.h: Regenerate.
691 * m32r-desc.c: Regenerate.
692 * m32r-desc.h: Regenerate.
693 * m32r-opc.c: Regenerate.
694 * m32r-opc.h: Regenerate.
695 * m32r-opinst.c: Regenerate.
696 * openrisc-desc.c: Regenerate.
697 * openrisc-desc.h: Regenerate.
698 * openrisc-opc.c: Regenerate.
699 * openrisc-opc.h: Regenerate.
700 * xstormy16-desc.c: Regenerate.
701 * xstormy16-desc.h: Regenerate.
702 * xstormy16-opc.c: Regenerate.
703 * xstormy16-opc.h: Regenerate.
704
db9db6f2
AM		 7052005-02-21 Alan Modra <amodra@bigpond.net.au>
706
707 * Makefile.am: Run "make dep-am"
708 * Makefile.in: Regenerate.
709
bf143b25
NC		 7102005-02-15 Nick Clifton <nickc@redhat.com>
711
712 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
713 compile time warnings.
714 (print_keyword): Likewise.
715 (default_print_insn): Likewise.
716
717 * fr30-desc.c: Regenerated.
718 * fr30-desc.h: Regenerated.
719 * fr30-dis.c: Regenerated.
720 * fr30-opc.c: Regenerated.
721 * fr30-opc.h: Regenerated.
722 * frv-desc.c: Regenerated.
723 * frv-dis.c: Regenerated.
724 * frv-opc.c: Regenerated.
725 * ip2k-asm.c: Regenerated.
726 * ip2k-desc.c: Regenerated.
727 * ip2k-desc.h: Regenerated.
728 * ip2k-dis.c: Regenerated.
729 * ip2k-opc.c: Regenerated.
730 * ip2k-opc.h: Regenerated.
731 * iq2000-desc.c: Regenerated.
732 * iq2000-dis.c: Regenerated.
733 * iq2000-opc.c: Regenerated.
734 * m32r-asm.c: Regenerated.
735 * m32r-desc.c: Regenerated.
736 * m32r-desc.h: Regenerated.
737 * m32r-dis.c: Regenerated.
738 * m32r-opc.c: Regenerated.
739 * m32r-opc.h: Regenerated.
740 * m32r-opinst.c: Regenerated.
741 * openrisc-desc.c: Regenerated.
742 * openrisc-desc.h: Regenerated.
743 * openrisc-dis.c: Regenerated.
744 * openrisc-opc.c: Regenerated.
745 * openrisc-opc.h: Regenerated.
746 * xstormy16-desc.c: Regenerated.
747 * xstormy16-desc.h: Regenerated.
748 * xstormy16-dis.c: Regenerated.
749 * xstormy16-opc.c: Regenerated.
750 * xstormy16-opc.h: Regenerated.
751
d6098898
L		 7522005-02-14 H.J. Lu <hongjiu.lu@intel.com>
753
754 * dis-buf.c (perror_memory): Use sprintf_vma to print out
755 address.
756
5a84f3e0
NC		 7572005-02-11 Nick Clifton <nickc@redhat.com>
758
bc18c937
NC		 759 * iq2000-asm.c: Regenerate.
760
5a84f3e0
NC		 761 * frv-dis.c: Regenerate.
762
0a40490e
JB		 7632005-02-07 Jim Blandy <jimb@redhat.com>
764
765 * Makefile.am (CGEN): Load guile.scm before calling the main
766 application script.
767 * Makefile.in: Regenerated.
768 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
769 Simply pass the cgen-opc.scm path to ${cgen} as its first
770 argument; ${cgen} itself now contains the '-s', or whatever is
771 appropriate for the Scheme being used.
772
c46f8c51
AC		 7732005-01-31 Andrew Cagney <cagney@gnu.org>
774
775 * configure: Regenerate to track ../gettext.m4.
776
60b9a617
JB		 7772005-01-31 Jan Beulich <jbeulich@novell.com>
778
779 * ia64-gen.c (NELEMS): Define.
780 (shrink): Generate alias with missing second predicate register when
781 opcode has two outputs and these are both predicates.
782 * ia64-opc-i.c (FULL17): Define.
783 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
784 here to generate output template.
785 (TBITCM, TNATCM): Undefine after use.
786 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
787 first input. Add ld16 aliases without ar.csd as second output. Add
788 st16 aliases without ar.csd as second input. Add cmpxchg aliases
789 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
790 ar.ccv as third/fourth inputs. Consolidate through...
791 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
792 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
793 * ia64-asmtab.c: Regenerate.
794
a53bf506
AC		 7952005-01-27 Andrew Cagney <cagney@gnu.org>
796
797 * configure: Regenerate to track ../gettext.m4 change.
798
90219bd0
AO		 7992005-01-25 Alexandre Oliva <aoliva@redhat.com>
800
801 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
802 * frv-asm.c: Rebuilt.
803 * frv-desc.c: Rebuilt.
804 * frv-desc.h: Rebuilt.
805 * frv-dis.c: Rebuilt.
806 * frv-ibld.c: Rebuilt.
807 * frv-opc.c: Rebuilt.
808 * frv-opc.h: Rebuilt.
809
45181ed1
AC		 8102005-01-24 Andrew Cagney <cagney@gnu.org>
811
812 * configure: Regenerate, ../gettext.m4 was updated.
813
9e836e3d
FF		 8142005-01-21 Fred Fish <fnf@specifixinc.com>
815
816 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
817 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
818 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
819 * mips-dis.c: Ditto.
820
5e8cb021
AM		 8212005-01-20 Alan Modra <amodra@bigpond.net.au>
822
823 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
824
986e18a5
FF		 8252005-01-19 Fred Fish <fnf@specifixinc.com>
826
827 * mips-dis.c (no_aliases): New disassembly option flag.
828 (set_default_mips_dis_options): Init no_aliases to zero.
829 (parse_mips_dis_option): Handle no-aliases option.
830 (print_insn_mips): Ignore table entries that are aliases
831 if no_aliases is set.
832 (print_insn_mips16): Ditto.
833 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
834 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
835 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
836 * mips16-opc.c (mips16_opcodes): Ditto.
837
e38bc3b5
NC		 8382005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
839
840 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
841 (inheritance diagram): Add missing edge.
842 (arch_sh1_up): Rename arch_sh_up to match external name to make life
843 easier for the testsuite.
844 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
845 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 846 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 847 arch_sh2a_or_sh4_up child.
848 (sh_table): Do renaming as above.
849 Correct comment for ldc.l for gas testsuite to read.
850 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
851 Correct comments for movy.w and movy.l for gas testsuite to read.
852 Correct comments for fmov.d and fmov.s for gas testsuite to read.
853
9df48ba9
L		 8542005-01-12 H.J. Lu <hongjiu.lu@intel.com>
855
856 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
857
2033b4b9
L		 8582005-01-12 H.J. Lu <hongjiu.lu@intel.com>
859
860 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
861
0bcb06d2
AS		 8622005-01-10 Andreas Schwab <schwab@suse.de>
863
864 * disassemble.c (disassemble_init_for_target) <case
865 bfd_arch_ia64>: Set skip_zeroes to 16.
866 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
867
47add74d
TL		 8682004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
869
870 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
871
246f4c05
SS		 8722004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
873
874 * avr-dis.c: Prettyprint. Added printing of symbol names in all
875 memory references. Convert avr_operand() to C90 formatting.
876
0e1200e5
TL		 8772004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
878
879 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
880
89a649f7
TL		 8812004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
882
883 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
884 (no_op_insn): Initialize array with instructions that have no
885 operands.
886 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
887
6255809c
RE		 8882004-11-29 Richard Earnshaw <rearnsha@arm.com>
889
890 * arm-dis.c: Correct top-level comment.
891
2fbad815
RE		 8922004-11-27 Richard Earnshaw <rearnsha@arm.com>
893
894 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
895 architecuture defining the insn.
896 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 897 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
898 field.
2fbad815
RE		 899 Also include opcode/arm.h.
900 * Makefile.am (arm-dis.lo): Update dependency list.
901 * Makefile.in: Regenerate.
902
d81acc42
NC		 9032004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
904
905 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
906 reflect the change to the short immediate syntax.
907
ca4f2377
AM		 9082004-11-19 Alan Modra <amodra@bigpond.net.au>
909
5da8bf1b
AM		 910 * or32-opc.c (debug): Warning fix.
911 * po/POTFILES.in: Regenerate.
912
ca4f2377
AM		 913 * maxq-dis.c: Formatting.
914 (print_insn): Warning fix.
915
b7693d02
DJ		 9162004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
917
918 * arm-dis.c (WORD_ADDRESS): Define.
919 (print_insn): Use it. Correct big-endian end-of-section handling.
920
300dac7e
NC		 9212004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
922 Vineet Sharma <vineets@noida.hcltech.com>
923
924 * maxq-dis.c: New file.
925 * disassemble.c (ARCH_maxq): Define.
610ad19b 926 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 927 instructions..
928 * configure.in: Add case for bfd_maxq_arch.
929 * configure: Regenerate.
930 * Makefile.am: Add support for maxq-dis.c
931 * Makefile.in: Regenerate.
932 * aclocal.m4: Regenerate.
933
42048ee7
TL		 9342004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
935
936 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
937 mode.
938 * crx-dis.c: Likewise.
939
bd21e58e
HPN		 9402004-11-04 Hans-Peter Nilsson <hp@axis.com>
941
942 Generally, handle CRISv32.
943 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
944 (struct cris_disasm_data): New type.
945 (format_reg, format_hex, cris_constraint, print_flags)
946 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
947 callers changed.
948 (format_sup_reg, print_insn_crisv32_with_register_prefix)
949 (print_insn_crisv32_without_register_prefix)
950 (print_insn_crisv10_v32_with_register_prefix)
951 (print_insn_crisv10_v32_without_register_prefix)
952 (cris_parse_disassembler_options): New functions.
953 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
954 parameter. All callers changed.
955 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
956 failure.
957 (cris_constraint) <case 'Y', 'U'>: New cases.
958 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
959 for constraint 'n'.
960 (print_with_operands) <case 'Y'>: New case.
961 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
962 <case 'N', 'Y', 'Q'>: New cases.
963 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
964 (print_insn_cris_with_register_prefix)
965 (print_insn_cris_without_register_prefix): Call
966 cris_parse_disassembler_options.
967 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
968 for CRISv32 and the size of immediate operands. New v32-only
969 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
970 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
971 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
972 Change brp to be v3..v10.
973 (cris_support_regs): New vector.
974 (cris_opcodes): Update head comment. New format characters '[',
975 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
976 Add new opcodes for v32 and adjust existing opcodes to accommodate
977 differences to earlier variants.
978 (cris_cond15s): New vector.
979
9306ca4a
JB		 9802004-11-04 Jan Beulich <jbeulich@novell.com>
981
982 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
983 (indirEb): Remove.
984 (Mp): Use f_mode rather than none at all.
985 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
986 replaces what previously was x_mode; x_mode now means 128-bit SSE
987 operands.
988 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
989 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
990 pinsrw's second operand is Edqw.
991 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
992 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
993 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
994 mode when an operand size override is present or always suffixing.
995 More instructions will need to be added to this group.
996 (putop): Handle new macro chars 'C' (short/long suffix selector),
997 'I' (Intel mode override for following macro char), and 'J' (for
998 adding the 'l' prefix to far branches in AT&T mode). When an
999 alternative was specified in the template, honor macro character when
1000 specified for Intel mode.
1001 (OP_E): Handle new *_mode values. Correct pointer specifications for
1002 memory operands. Consolidate output of index register.
1003 (OP_G): Handle new *_mode values.
1004 (OP_I): Handle const_1_mode.
1005 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
1006 respective opcode prefix bits have been consumed.
1007 (OP_EM, OP_EX): Provide some default handling for generating pointer
1008 specifications.
1009
f39c96a9
TL		 10102004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
1011
1012 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
1013 COP_INST macro.
1014
812337be
TL		 10152004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
1016
1017 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
1018 (getregliststring): Support HI/LO and user registers.
610ad19b 1019 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 1020 rearrangement done in CRX opcode header file.
1021 (crx_regtab): Likewise.
1022 (crx_optab): Likewise.
610ad19b 1023 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 1024 formats.
1025 support new Co-Processor instruction 'cpi'.
1026
4030fa5a
NC		 10272004-10-27 Nick Clifton <nickc@redhat.com>
1028
1029 * opcodes/iq2000-asm.c: Regenerate.
1030 * opcodes/iq2000-desc.c: Regenerate.
1031 * opcodes/iq2000-desc.h: Regenerate.
1032 * opcodes/iq2000-dis.c: Regenerate.
1033 * opcodes/iq2000-ibld.c: Regenerate.
1034 * opcodes/iq2000-opc.c: Regenerate.
1035 * opcodes/iq2000-opc.h: Regenerate.
1036
fc3d45e8
TL		 10372004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
1038
1039 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
1040 us4, us5 (respectively).
1041 Remove unsupported 'popa' instruction.
1042 Reverse operands order in store co-processor instructions.
1043
3c55da70
AM		 10442004-10-15 Alan Modra <amodra@bigpond.net.au>
1045
1046 * Makefile.am: Run "make dep-am"
1047 * Makefile.in: Regenerate.
1048
7fa3d080
BW		 10492004-10-12 Bob Wilson <bob.wilson@acm.org>
1050
1051 * xtensa-dis.c: Use ISO C90 formatting.
1052
e612bb4d
AM		 10532004-10-09 Alan Modra <amodra@bigpond.net.au>
1054
1055 * ppc-opc.c: Revert 2004-09-09 change.
1056
43cd72b9
BW		 10572004-10-07 Bob Wilson <bob.wilson@acm.org>
1058
1059 * xtensa-dis.c (state_names): Delete.
1060 (fetch_data): Use xtensa_isa_maxlength.
1061 (print_xtensa_operand): Replace operand parameter with opcode/operand
1062 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
1063 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
1064 instruction bundles. Use xmalloc instead of malloc.
1065
bbac1f2a
NC		 10662004-10-07 David Gibson <david@gibson.dropbear.id.au>
1067
1068 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
1069 initializers.
1070
48c9f030
NC		 10712004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
1072
1073 * crx-opc.c (crx_instruction): Support Co-processor insns.
1074 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
1075 (getregliststring): Change function to use the above enum.
1076 (print_arg): Handle CO-Processor insns.
1077 (crx_cinvs): Add 'b' option to invalidate the branch-target
1078 cache.
1079
12c64a4e
AH		 10802004-10-06 Aldy Hernandez <aldyh@redhat.com>
1081
1082 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
1083 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
1084 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
1085 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
1086 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
1087
14127cc4
NC		 10882004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
1089
1090 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
1091 rather than add it.
1092
0dd132b6
NC		 10932004-09-30 Paul Brook <paul@codesourcery.com>
1094
1095 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
1096 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
1097
3f85e526
L		 10982004-09-17 H.J. Lu <hongjiu.lu@intel.com>
1099
1100 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
1101 (CONFIG_STATUS_DEPENDENCIES): New.
1102 (Makefile): Removed.
1103 (config.status): Likewise.
1104 * Makefile.in: Regenerated.
1105
8ae85421
AM		 11062004-09-17 Alan Modra <amodra@bigpond.net.au>
1107
1108 * Makefile.am: Run "make dep-am".
1109 * Makefile.in: Regenerate.
1110 * aclocal.m4: Regenerate.
1111 * configure: Regenerate.
1112 * po/POTFILES.in: Regenerate.
1113 * po/opcodes.pot: Regenerate.
1114
24443139
AS		 11152004-09-11 Andreas Schwab <schwab@suse.de>
1116
1117 * configure: Rebuild.
1118
2a309db0
AM		 11192004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
1120
1121 * ppc-opc.c (L): Make this field not optional.
1122
42851540
NC		 11232004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
1124
1125 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
1126 Fix parameter to 'm[t|f]csr' insns.
1127
979273e3
NN		 11282004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
1129
1130 * configure.in: Autoupdate to autoconf 2.59.
1131 * aclocal.m4: Rebuild with aclocal 1.4p6.
1132 * configure: Rebuild with autoconf 2.59.
1133 * Makefile.in: Rebuild with automake 1.4p6 (picking up
1134 bfd changes for autoconf 2.59 on the way).
1135 * config.in: Rebuild with autoheader 2.59.
1136
ac28a1cb
RS		 11372004-08-27 Richard Sandiford <rsandifo@redhat.com>
1138
1139 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
1140
30d1c836
ML		 11412004-07-30 Michal Ludvig <mludvig@suse.cz>
1142
1143 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
1144 (GRPPADLCK2): New define.
1145 (twobyte_has_modrm): True for 0xA6.
1146 (grps): GRPPADLCK2 for opcode 0xA6.
1147
0b0ac059
AO		 11482004-07-29 Alexandre Oliva <aoliva@redhat.com>
1149
1150 Introduce SH2a support.
1151 * sh-opc.h (arch_sh2a_base): Renumber.
1152 (arch_sh2a_nofpu_base): Remove.
1153 (arch_sh_base_mask): Adjust.
1154 (arch_opann_mask): New.
1155 (arch_sh2a, arch_sh2a_nofpu): Adjust.
1156 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
1157 (sh_table): Adjust whitespace.
1158 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
1159 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
1160 instruction list throughout.
1161 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
1162 of arch_sh2a in instruction list throughout.
1163 (arch_sh2e_up): Accomodate above changes.
1164 (arch_sh2_up): Ditto.
1165 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
1166 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
1167 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
1168 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
1169 * sh-opc.h (arch_sh2a_nofpu): New.
1170 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
1171 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
1172 instruction.
1173 2004-01-20 DJ Delorie <dj@redhat.com>
1174 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
1175 2003-12-29 DJ Delorie <dj@redhat.com>
1176 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
1177 sh_opcode_info, sh_table): Add sh2a support.
1178 (arch_op32): New, to tag 32-bit opcodes.
1179 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
1180 2003-12-02 Michael Snyder <msnyder@redhat.com>
1181 * sh-opc.h (arch_sh2a): Add.
1182 * sh-dis.c (arch_sh2a): Handle.
1183 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
1184
670ec21d
NC		 11852004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
1186
1187 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
1188
ed049af3
NC		 11892004-07-22 Nick Clifton <nickc@redhat.com>
1190
1191 PR/280
1192 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
1193 insns - this is done by objdump itself.
1194 * h8500-dis.c (print_insn_h8500): Likewise.
1195
20f0a1fc
NC		 11962004-07-21 Jan Beulich <jbeulich@novell.com>
1197
1198 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
1199 regardless of address size prefix in effect.
1200 (ptr_reg): Size or address registers does not depend on rex64, but
1201 on the presence of an address size override.
1202 (OP_MMX): Use rex.x only for xmm registers.
1203 (OP_EM): Use rex.z only for xmm registers.
1204
6f14957b
MR		 12052004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1206
1207 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
1208 move/branch operations to the bottom so that VR5400 multimedia
1209 instructions take precedence in disassembly.
1210
1586d91e
MR		 12112004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
1212
1213 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
1214 ISA-specific "break" encoding.
1215
982de27a
NC		 12162004-07-13 Elvis Chiang <elvisfb@gmail.com>
1217
1218 * arm-opc.h: Fix typo in comment.
1219
4300ab10
AS		 12202004-07-11 Andreas Schwab <schwab@suse.de>
1221
1222 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
1223
8577e690
AS		 12242004-07-09 Andreas Schwab <schwab@suse.de>
1225
1226 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
1227
1fe1f39c
NC		 12282004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1229
1230 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
1231 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
1232 (crx-dis.lo): New target.
1233 (crx-opc.lo): Likewise.
1234 * Makefile.in: Regenerate.
1235 * configure.in: Handle bfd_crx_arch.
1236 * configure: Regenerate.
1237 * crx-dis.c: New file.
1238 * crx-opc.c: New file.
1239 * disassemble.c (ARCH_crx): Define.
1240 (disassembler): Handle ARCH_crx.
1241
7a33b495
JW		 12422004-06-29 James E Wilson <wilson@specifixinc.com>
1243
1244 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
1245 * ia64-asmtab.c: Regnerate.
1246
98e69875
AM		 12472004-06-28 Alan Modra <amodra@bigpond.net.au>
1248
1249 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
1250 (extract_fxm): Don't test dialect.
1251 (XFXFXM_MASK): Include the power4 bit.
1252 (XFXM): Add p4 param.
1253 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
1254
a53b85e2
AO		 12552004-06-27 Alexandre Oliva <aoliva@redhat.com>
1256
1257 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
1258 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
1259
d0618d1c
AM		 12602004-06-26 Alan Modra <amodra@bigpond.net.au>
1261
1262 * ppc-opc.c (BH, XLBH_MASK): Define.
1263 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
1264
1d9f512f
AM		 12652004-06-24 Alan Modra <amodra@bigpond.net.au>
1266
1267 * i386-dis.c (x_mode): Comment.
1268 (two_source_ops): File scope.
1269 (float_mem): Correct fisttpll and fistpll.
1270 (float_mem_mode): New table.
1271 (dofloat): Use it.
1272 (OP_E): Correct intel mode PTR output.
1273 (ptr_reg): Use open_char and close_char.
1274 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
1275 operands. Set two_source_ops.
1276
52886d70
AM		 12772004-06-15 Alan Modra <amodra@bigpond.net.au>
1278
1279 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
1280 instead of _raw_size.
1281
bad9ceea
JJ		 12822004-06-08 Jakub Jelinek <jakub@redhat.com>
1283
1284 * ia64-gen.c (in_iclass): Handle more postinc st
1285 and ld variants.
1286 * ia64-asmtab.c: Rebuilt.
1287
0451f5df
MS		 12882004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
1289
1290 * s390-opc.txt: Correct architecture mask for some opcodes.
1291 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
1292 in the esa mode as well.
1293
f6f9408f
JR		 12942004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1295
1296 * sh-dis.c (target_arch): Make unsigned.
1297 (print_insn_sh): Replace (most of) switch with a call to
1298 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1299 * sh-opc.h: Redefine architecture flags values.
1300 Add sh3-nommu architecture.
1301 Reorganise <arch>_up macros so they make more visual sense.
1302 (SH_MERGE_ARCH_SET): Define new macro.
1303 (SH_VALID_BASE_ARCH_SET): Likewise.
1304 (SH_VALID_MMU_ARCH_SET): Likewise.
1305 (SH_VALID_CO_ARCH_SET): Likewise.
1306 (SH_VALID_ARCH_SET): Likewise.
1307 (SH_MERGE_ARCH_SET_VALID): Likewise.
1308 (SH_ARCH_SET_HAS_FPU): Likewise.
1309 (SH_ARCH_SET_HAS_DSP): Likewise.
1310 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1311 (sh_get_arch_from_bfd_mach): Add prototype.
1312 (sh_get_arch_up_from_bfd_mach): Likewise.
1313 (sh_get_bfd_mach_from_arch_set): Likewise.
1314 (sh_merge_bfd_arc): Likewise.
1315
be8c092b
NC		 13162004-05-24 Peter Barada <peter@the-baradas.com>
1317
1318 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1319 into new match_insn_m68k function. Loop over canidate
1320 matches and select first that completely matches.
be8c092b
NC		 1321 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1322 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1323 to verify addressing for MAC/EMAC.
be8c092b
NC		 1324 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1325 reigster halves since 'fpu' and 'spl' look misleading.
1326 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1327 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1328 first, tighten up match masks.
1329 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1330 'size' from special case code in print_insn_m68k to
1331 determine decode size of insns.
1332
a30e9cc4
AM		 13332004-05-19 Alan Modra <amodra@bigpond.net.au>
1334
1335 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1336 well as when -mpower4.
1337
9598fbe5
NC		 13382004-05-13 Nick Clifton <nickc@redhat.com>
1339
1340 * po/fr.po: Updated French translation.
1341
6b6e92f4
NC		 13422004-05-05 Peter Barada <peter@the-baradas.com>
1343
1344 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1345 variants in arch_mask. Only set m68881/68851 for 68k chips.
1346 * m68k-op.c: Switch from ColdFire chips to core variants.
1347
a404d431
AM		 13482004-05-05 Alan Modra <amodra@bigpond.net.au>
1349
a30e9cc4 1350 PR 147.
a404d431
AM		 1351 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1352
f3806e43
BE		 13532004-04-29 Ben Elliston <bje@au.ibm.com>
1354
520ceea4
BE		 1355 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1356 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1357
1f1799d5
KK		 13582004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1359
1360 * sh-dis.c (print_insn_sh): Print the value in constant pool
1361 as a symbol if it looks like a symbol.
1362
fd99574b
NC		 13632004-04-22 Peter Barada <peter@the-baradas.com>
1364
1365 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1366 appropriate ColdFire architectures.
1367 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1368 mask addressing.
1369 Add EMAC instructions, fix MAC instructions. Remove
1370 macmw/macml/msacmw/msacml instructions since mask addressing now
1371 supported.
1372
b4781d44
JJ		 13732004-04-20 Jakub Jelinek <jakub@redhat.com>
1374
1375 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1376 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1377 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1378 macro. Adjust all users.
1379
91809fda 13802004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1381
91809fda
NC		 1382 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1383 separately.
1384
f4453dfa
NC		 13852004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1386
1387 * m32r-asm.c: Regenerate.
1388
9b0de91a
SS		 13892004-03-29 Stan Shebs <shebs@apple.com>
1390
1391 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1392 used.
1393
e20c0b3d
AM		 13942004-03-19 Alan Modra <amodra@bigpond.net.au>
1395
1396 * aclocal.m4: Regenerate.
1397 * config.in: Regenerate.
1398 * configure: Regenerate.
1399 * po/POTFILES.in: Regenerate.
1400 * po/opcodes.pot: Regenerate.
1401
fdd12ef3
AM		 14022004-03-16 Alan Modra <amodra@bigpond.net.au>
1403
1404 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1405 PPC_OPERANDS_GPR_0.
1406 * ppc-opc.c (RA0): Define.
1407 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1408 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1409 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1410
2dc111b3 14112004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1412
1413 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1414
7bfeee7b
AM		 14152004-03-15 Alan Modra <amodra@bigpond.net.au>
1416
1417 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1418
7ffdda93
ML		 14192004-03-12 Michal Ludvig <mludvig@suse.cz>
1420
1421 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1422 (grps): Delete GRPPLOCK entry.
7ffdda93 1423
cc0ec051
AM		 14242004-03-12 Alan Modra <amodra@bigpond.net.au>
1425
1426 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1427 (M, Mp): Use OP_M.
1428 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1429 (GRPPADLCK): Define.
1430 (dis386): Use NOP_Fixup on "nop".
1431 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1432 (twobyte_has_modrm): Set for 0xa7.
1433 (padlock_table): Delete. Move to..
1434 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1435 and clflush.
1436 (print_insn): Revert PADLOCK_SPECIAL code.
1437 (OP_E): Delete sfence, lfence, mfence checks.
1438
4fd61dcb
JJ		 14392004-03-12 Jakub Jelinek <jakub@redhat.com>
1440
1441 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1442 (INVLPG_Fixup): New function.
1443 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1444
0f10071e
ML		 14452004-03-12 Michal Ludvig <mludvig@suse.cz>
1446
1447 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1448 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1449 (padlock_table): New struct with PadLock instructions.
1450 (print_insn): Handle PADLOCK_SPECIAL.
1451
c02908d2
AM		 14522004-03-12 Alan Modra <amodra@bigpond.net.au>
1453
1454 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1455 (OP_E): Twiddle clflush to sfence here.
1456
d5bb7600
NC		 14572004-03-08 Nick Clifton <nickc@redhat.com>
1458
1459 * po/de.po: Updated German translation.
1460
ae51a426
JR		 14612003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1462
1463 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1464 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1465 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1466 accordingly.
1467
676a64f4
RS		 14682004-03-01 Richard Sandiford <rsandifo@redhat.com>
1469
1470 * frv-asm.c: Regenerate.
1471 * frv-desc.c: Regenerate.
1472 * frv-desc.h: Regenerate.
1473 * frv-dis.c: Regenerate.
1474 * frv-ibld.c: Regenerate.
1475 * frv-opc.c: Regenerate.
1476 * frv-opc.h: Regenerate.
1477
c7a48b9a
RS		 14782004-03-01 Richard Sandiford <rsandifo@redhat.com>
1479
1480 * frv-desc.c, frv-opc.c: Regenerate.
1481
8ae0baa2
RS		 14822004-03-01 Richard Sandiford <rsandifo@redhat.com>
1483
1484 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1485
ce11586c
JR		 14862004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1487
1488 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1489 Also correct mistake in the comment.
1490
6a5709a5
JR		 14912004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1492
1493 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1494 ensure that double registers have even numbers.
1495 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1496 that reserved instruction 0xfffd does not decode the same
1497 as 0xfdfd (ftrv).
1498 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1499 REG_N refers to a double register.
1500 Add REG_N_B01 nibble type and use it instead of REG_NM
1501 in ftrv.
1502 Adjust the bit patterns in a few comments.
1503
e5d2b64f 15042004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1505
1506 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1507
1f04b05f
AH		 15082004-02-20 Aldy Hernandez <aldyh@redhat.com>
1509
1510 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1511
2f3b8700
AH		 15122004-02-20 Aldy Hernandez <aldyh@redhat.com>
1513
1514 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1515
f0b26da6 15162004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1517
1518 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1519 mtivor32, mtivor33, mtivor34.
f0b26da6 1520
23d59c56 15212004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1522
1523 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1524
34920d91
NC		 15252004-02-10 Petko Manolov <petkan@nucleusys.com>
1526
1527 * arm-opc.h Maverick accumulator register opcode fixes.
1528
44d86481
BE		 15292004-02-13 Ben Elliston <bje@wasabisystems.com>
1530
1531 * m32r-dis.c: Regenerate.
1532
17707c23
MS		 15332004-01-27 Michael Snyder <msnyder@redhat.com>
1534
1535 * sh-opc.h (sh_table): "fsrra", not "fssra".
1536
fe3a9bc4
NC		 15372004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1538
1539 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1540 contraints.
1541
ff24f124
JJ		 15422004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1543
1544 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1545
a02a862a
AM		 15462004-01-19 Alan Modra <amodra@bigpond.net.au>
1547
1548 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1549 1. Don't print scale factor on AT&T mode when index missing.
1550
d164ea7f
AO		 15512004-01-16 Alexandre Oliva <aoliva@redhat.com>
1552
1553 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1554 when loaded into XR registers.
1555
cb10e79a
RS		 15562004-01-14 Richard Sandiford <rsandifo@redhat.com>
1557
1558 * frv-desc.h: Regenerate.
1559 * frv-desc.c: Regenerate.
1560 * frv-opc.c: Regenerate.
1561
f532f3fa
MS		 15622004-01-13 Michael Snyder <msnyder@redhat.com>
1563
1564 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1565
e45d0630
PB		 15662004-01-09 Paul Brook <paul@codesourcery.com>
1567
1568 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1569 specific opcodes.
1570
3ba7a1aa
DJ		 15712004-01-07 Daniel Jacobowitz <drow@mvista.com>
1572
1573 * Makefile.am (libopcodes_la_DEPENDENCIES)
1574 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1575 comment about the problem.
1576 * Makefile.in: Regenerate.
1577
ba2d3f07
AO		 15782004-01-06 Alexandre Oliva <aoliva@redhat.com>
1579
1580 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1581 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1582 cut&paste errors in shifting/truncating numerical operands.
1583 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1584 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1585 (parse_uslo16): Likewise.
1586 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1587 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1588 (parse_s12): Likewise.
1589 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1590 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1591 (parse_uslo16): Likewise.
1592 (parse_uhi16): Parse gothi and gotfuncdeschi.
1593 (parse_d12): Parse got12 and gotfuncdesc12.
1594 (parse_s12): Likewise.
1595
3ab48931
NC		 15962004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1597
1598 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1599 instruction which looks similar to an 'rla' instruction.
a0bd404e 1600
c9e214e5 1601For older changes see ChangeLog-0203
252b5132
RH		 1602\f
1603Local Variables:
2f6d2f85
NC		 1604mode: change-log
1605left-margin: 8
1606fill-column: 74
252b5132
RH		 1607version-control: never
1608End:
GDB Binutils - Deliverables
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