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ubsan: nios2: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
96f1f604
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
4
8c9b4171
AM		 52019-12-11 Alan Modra <amodra@gmail.com>
6
7 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
8
334175b6
AM		 92019-12-11 Alan Modra <amodra@gmail.com>
10
11 * m68k-dis.c (COERCE32): Cast value first.
12 (NEXTLONG, NEXTULONG): Avoid signed overflow.
13
f8a87c78
AM		 142019-12-11 Alan Modra <amodra@gmail.com>
15
16 * h8300-dis.c (extract_immediate): Avoid signed overflow.
17 (bfd_h8_disassemble): Likewise.
18
159653d8
AM		 192019-12-11 Alan Modra <amodra@gmail.com>
20
21 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
22 past end of operands array.
23
d93bba9e
AM		 242019-12-11 Alan Modra <amodra@gmail.com>
25
26 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
27 overflow when collecting bytes of a number.
28
c202f69e
AM		 292019-12-11 Alan Modra <amodra@gmail.com>
30
31 * cris-dis.c (print_with_operands): Avoid signed integer
32 overflow when collecting bytes of a 32-bit integer.
33
0ef562a4
AM		 342019-12-11 Alan Modra <amodra@gmail.com>
35
36 * cr16-dis.c (EXTRACT, SBM): Rewrite.
37 (cr16_match_opcode): Delete duplicate bcond test.
38
2fd2b153
AM		 392019-12-11 Alan Modra <amodra@gmail.com>
40
41 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
42 (SIGNBIT): New.
43 (MASKBITS, SIGNEXTEND): Rewrite.
44 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
45 unsigned arithmetic, instead assign result of SIGNEXTEND back
46 to x.
47 (fmtconst_val): Use 1u in shift expression.
48
a11db3e9
AM		 492019-12-11 Alan Modra <amodra@gmail.com>
50
51 * arc-dis.c (find_format_from_table): Use ull constant when
52 shifting by up to 32.
53
9d48687b
AM		 542019-12-11 Alan Modra <amodra@gmail.com>
55
56 PR 25270
57 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
58 false when field is zero for sve_size_tsz_bhs.
59
b8e61daa
AM		 602019-12-11 Alan Modra <amodra@gmail.com>
61
62 * epiphany-ibld.c: Regenerate.
63
20135676
AM		 642019-12-10 Alan Modra <amodra@gmail.com>
65
66 PR 24960
67 * disassemble.c (disassemble_free_target): New function.
68
103ebbc3
AM		 692019-12-10 Alan Modra <amodra@gmail.com>
70
71 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
72 * disassemble.c (disassemble_init_for_target): Likewise.
73 * bpf-dis.c: Regenerate.
74 * epiphany-dis.c: Regenerate.
75 * fr30-dis.c: Regenerate.
76 * frv-dis.c: Regenerate.
77 * ip2k-dis.c: Regenerate.
78 * iq2000-dis.c: Regenerate.
79 * lm32-dis.c: Regenerate.
80 * m32c-dis.c: Regenerate.
81 * m32r-dis.c: Regenerate.
82 * mep-dis.c: Regenerate.
83 * mt-dis.c: Regenerate.
84 * or1k-dis.c: Regenerate.
85 * xc16x-dis.c: Regenerate.
86 * xstormy16-dis.c: Regenerate.
87
6f0e0752
AM		 882019-12-10 Alan Modra <amodra@gmail.com>
89
90 * ppc-dis.c (private): Delete variable.
91 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
92 (powerpc_init_dialect): Don't use global private.
93
e7c22a69
AM		 942019-12-10 Alan Modra <amodra@gmail.com>
95
96 * s12z-opc.c: Formatting.
97
0a6aef6b
AM		 982019-12-08 Alan Modra <amodra@gmail.com>
99
100 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
101 registers.
102
2dc4b12f
JB		 1032019-12-05 Jan Beulich <jbeulich@suse.com>
104
105 * aarch64-tbl.h (aarch64_feature_crypto,
106 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
107 CRYPTO_V8_2_INSN): Delete.
108
378fd436
AM		 1092019-12-05 Alan Modra <amodra@gmail.com>
110
111 PR 25249
112 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
113 (struct string_buf): New.
114 (strbuf): New function.
115 (get_field): Use strbuf rather than strdup of local temp.
116 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
117 (get_field_rfsl, get_field_imm15): Likewise.
118 (get_field_rd, get_field_r1, get_field_r2): Update macros.
119 (get_field_special): Likewise. Don't strcpy spr. Formatting.
120 (print_insn_microblaze): Formatting. Init and pass string_buf to
121 get_field functions.
122
0ba59a29
JB		 1232019-12-04 Jan Beulich <jbeulich@suse.com>
124
125 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
126 * i386-tbl.h: Re-generate.
127
77ad8092
JB		 1282019-12-04 Jan Beulich <jbeulich@suse.com>
129
130 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
131
3036c899
JB		 1322019-12-04 Jan Beulich <jbeulich@suse.com>
133
134 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
135 forms.
136 (xbegin): Drop DefaultSize.
137 * i386-tbl.h: Re-generate.
138
8b301fbb
MI		 1392019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
140
141 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
142 Change the coproc CRC conditions to use the extension
143 feature set, second word, base on ARM_EXT2_CRC.
144
6aa385b9
JB		 1452019-11-14 Jan Beulich <jbeulich@suse.com>
146
147 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
148 * i386-tbl.h: Re-generate.
149
0cfa3eb3
JB		 1502019-11-14 Jan Beulich <jbeulich@suse.com>
151
152 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
153 JumpInterSegment, and JumpAbsolute entries.
154 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
155 JUMP_ABSOLUTE): Define.
156 (struct i386_opcode_modifier): Extend jump field to 3 bits.
157 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
158 fields.
159 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
160 JumpInterSegment): Define.
161 * i386-tbl.h: Re-generate.
162
6f2f06be
JB		 1632019-11-14 Jan Beulich <jbeulich@suse.com>
164
165 * i386-gen.c (operand_type_init): Remove
166 OPERAND_TYPE_JUMPABSOLUTE entry.
167 (opcode_modifiers): Add JumpAbsolute entry.
168 (operand_types): Remove JumpAbsolute entry.
169 * i386-opc.h (JumpAbsolute): Move between enums.
170 (struct i386_opcode_modifier): Add jumpabsolute field.
171 (union i386_operand_type): Remove jumpabsolute field.
172 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
173 * i386-init.h, i386-tbl.h: Re-generate.
174
601e8564
JB		 1752019-11-14 Jan Beulich <jbeulich@suse.com>
176
177 * i386-gen.c (opcode_modifiers): Add AnySize entry.
178 (operand_types): Remove AnySize entry.
179 * i386-opc.h (AnySize): Move between enums.
180 (struct i386_opcode_modifier): Add anysize field.
181 (OTUnused): Un-comment.
182 (union i386_operand_type): Remove anysize field.
183 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
184 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
185 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
186 AnySize.
187 * i386-tbl.h: Re-generate.
188
7722d40a
JW		 1892019-11-12 Nelson Chu <nelson.chu@sifive.com>
190
191 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
192 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
193 use the floating point register (FPR).
194
ce760a76
MI		 1952019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
196
197 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
198 cmode 1101.
199 (is_mve_encoding_conflict): Update cmode conflict checks for
200 MVE_VMVN_IMM.
201
51c8edf6
JB		 2022019-11-12 Jan Beulich <jbeulich@suse.com>
203
204 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
205 entry.
206 (operand_types): Remove EsSeg entry.
207 (main): Replace stale use of OTMax.
208 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
209 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
210 (EsSeg): Delete.
211 (OTUnused): Comment out.
212 (union i386_operand_type): Remove esseg field.
213 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
214 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
215 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
216 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
217 * i386-init.h, i386-tbl.h: Re-generate.
218
474da251
JB		 2192019-11-12 Jan Beulich <jbeulich@suse.com>
220
221 * i386-gen.c (operand_instances): Add RegB entry.
222 * i386-opc.h (enum operand_instance): Add RegB.
223 * i386-opc.tbl (RegC, RegD, RegB): Define.
224 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
225 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
226 monitorx, mwaitx): Drop ImmExt and convert encodings
227 accordingly.
228 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
229 (edx, rdx): Add Instance=RegD.
230 (ebx, rbx): Add Instance=RegB.
231 * i386-tbl.h: Re-generate.
232
75e5731b
JB		 2332019-11-12 Jan Beulich <jbeulich@suse.com>
234
235 * i386-gen.c (operand_type_init): Adjust
236 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
237 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
238 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
239 (operand_instances): New.
240 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
241 (output_operand_type): New parameter "instance". Process it.
242 (process_i386_operand_type): New local variable "instance".
243 (main): Adjust static assertions.
244 * i386-opc.h (INSTANCE_WIDTH): Define.
245 (enum operand_instance): New.
246 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
247 (union i386_operand_type): Replace acc, inoutportreg, and
248 shiftcount by instance.
249 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
250 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
251 Add Instance=.
252 * i386-init.h, i386-tbl.h: Re-generate.
253
91802f3c
JB		 2542019-11-11 Jan Beulich <jbeulich@suse.com>
255
256 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
257 smaxp/sminp entries' "tied_operand" field to 2.
258
4f5fc85d
JB		 2592019-11-11 Jan Beulich <jbeulich@suse.com>
260
261 * aarch64-opc.c (operand_general_constraint_met_p): Replace
262 "index" local variable by that of the already existing "num".
263
dc2be329
L		 2642019-11-08 H.J. Lu <hongjiu.lu@intel.com>
265
266 PR gas/25167
267 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
268 * i386-tbl.h: Regenerated.
269
f74a6307
JB		 2702019-11-08 Jan Beulich <jbeulich@suse.com>
271
272 * i386-gen.c (operand_type_init): Add Class= to
273 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
274 OPERAND_TYPE_REGBND entry.
275 (operand_classes): Add RegMask and RegBND entries.
276 (operand_types): Drop RegMask and RegBND entry.
277 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
278 (RegMask, RegBND): Delete.
279 (union i386_operand_type): Remove regmask and regbnd fields.
280 * i386-opc.tbl (RegMask, RegBND): Define.
281 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
282 Class=RegBND.
283 * i386-init.h, i386-tbl.h: Re-generate.
284
3528c362
JB		 2852019-11-08 Jan Beulich <jbeulich@suse.com>
286
287 * i386-gen.c (operand_type_init): Add Class= to
288 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
289 OPERAND_TYPE_REGZMM entries.
290 (operand_classes): Add RegMMX and RegSIMD entries.
291 (operand_types): Drop RegMMX and RegSIMD entries.
292 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
293 (RegMMX, RegSIMD): Delete.
294 (union i386_operand_type): Remove regmmx and regsimd fields.
295 * i386-opc.tbl (RegMMX): Define.
296 (RegXMM, RegYMM, RegZMM): Add Class=.
297 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
298 Class=RegSIMD.
299 * i386-init.h, i386-tbl.h: Re-generate.
300
4a5c67ed
JB		 3012019-11-08 Jan Beulich <jbeulich@suse.com>
302
303 * i386-gen.c (operand_type_init): Add Class= to
304 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
305 entries.
306 (operand_classes): Add RegCR, RegDR, and RegTR entries.
307 (operand_types): Drop Control, Debug, and Test entries.
308 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
309 (Control, Debug, Test): Delete.
310 (union i386_operand_type): Remove control, debug, and test
311 fields.
312 * i386-opc.tbl (Control, Debug, Test): Define.
313 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
314 Class=RegDR, and Test by Class=RegTR.
315 * i386-init.h, i386-tbl.h: Re-generate.
316
00cee14f
JB		 3172019-11-08 Jan Beulich <jbeulich@suse.com>
318
319 * i386-gen.c (operand_type_init): Add Class= to
320 OPERAND_TYPE_SREG entry.
321 (operand_classes): Add SReg entry.
322 (operand_types): Drop SReg entry.
323 * i386-opc.h (enum operand_class): Add SReg.
324 (SReg): Delete.
325 (union i386_operand_type): Remove sreg field.
326 * i386-opc.tbl (SReg): Define.
327 * i386-reg.tbl: Replace SReg by Class=SReg.
328 * i386-init.h, i386-tbl.h: Re-generate.
329
bab6aec1
JB		 3302019-11-08 Jan Beulich <jbeulich@suse.com>
331
332 * i386-gen.c (operand_type_init): Add Class=. New
333 OPERAND_TYPE_ANYIMM entry.
334 (operand_classes): New.
335 (operand_types): Drop Reg entry.
336 (output_operand_type): New parameter "class". Process it.
337 (process_i386_operand_type): New local variable "class".
338 (main): Adjust static assertions.
339 * i386-opc.h (CLASS_WIDTH): Define.
340 (enum operand_class): New.
341 (Reg): Replace by Class. Adjust comment.
342 (union i386_operand_type): Replace reg by class.
343 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
344 Class=.
345 * i386-reg.tbl: Replace Reg by Class=Reg.
346 * i386-init.h: Re-generate.
347
1f4cd317
MM		 3482019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
349
350 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
351 (aarch64_opcode_table): Add data gathering hint mnemonic.
352 * opcodes/aarch64-dis-2.c: Account for new instruction.
353
616ce08e
MM		 3542019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
355
356 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
357
358
8382113f
MM		 3592019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
360
361 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
362 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
363 aarch64_feature_f64mm): New feature sets.
364 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
365 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
366 instructions.
367 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
368 macros.
369 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
370 (OP_SVE_QQQ): New qualifier.
371 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
372 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
373 the movprfx constraint.
374 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
375 (aarch64_opcode_table): Define new instructions smmla,
376 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
377 uzip{1/2}, trn{1/2}.
378 * aarch64-opc.c (operand_general_constraint_met_p): Handle
379 AARCH64_OPND_SVE_ADDR_RI_S4x32.
380 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
381 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
382 Account for new instructions.
383 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
384 S4x32 operand.
385 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
386
aab2c27d
MM		 3872019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3882019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
389
390 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
391 Armv8.6-A.
392 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
393 (neon_opcodes): Add bfloat SIMD instructions.
394 (print_insn_coprocessor): Add new control character %b to print
395 condition code without checking cp_num.
396 (print_insn_neon): Account for BFloat16 instructions that have no
397 special top-byte handling.
398
33593eaf
MM		 3992019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4002019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
401
402 * arm-dis.c (print_insn_coprocessor,
403 print_insn_generic_coprocessor): Create wrapper functions around
404 the implementation of the print_insn_coprocessor control codes.
405 (print_insn_coprocessor_1): Original print_insn_coprocessor
406 function that now takes which array to look at as an argument.
407 (print_insn_arm): Use both print_insn_coprocessor and
408 print_insn_generic_coprocessor.
409 (print_insn_thumb32): As above.
410
df678013
MM		 4112019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4122019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
413
414 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
415 in reglane special case.
416 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
417 aarch64_find_next_opcode): Account for new instructions.
418 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
419 in reglane special case.
420 * aarch64-opc.c (struct operand_qualifier_data): Add data for
421 new AARCH64_OPND_QLF_S_2H qualifier.
422 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
423 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
424 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
425 sets.
426 (BFLOAT_SVE, BFLOAT): New feature set macros.
427 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
428 instructions.
429 (aarch64_opcode_table): Define new instructions bfdot,
430 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
431 bfcvtn2, bfcvt.
432
8ae2d3d9
MM		 4332019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4342019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
435
436 * aarch64-tbl.h (ARMV8_6): New macro.
437
142861df
JB		 4382019-11-07 Jan Beulich <jbeulich@suse.com>
439
440 * i386-dis.c (prefix_table): Add mcommit.
441 (rm_table): Add rdpru.
442 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
443 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
444 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
445 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
446 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
447 * i386-opc.tbl (mcommit, rdpru): New.
448 * i386-init.h, i386-tbl.h: Re-generate.
449
081e283f
JB		 4502019-11-07 Jan Beulich <jbeulich@suse.com>
451
452 * i386-dis.c (OP_Mwait): Drop local variable "names", use
453 "names32" instead.
454 (OP_Monitor): Drop local variable "op1_names", re-purpose
455 "names" for it instead, and replace former "names" uses by
456 "names32" ones.
457
c050c89a
JB		 4582019-11-07 Jan Beulich <jbeulich@suse.com>
459
460 PR/gas 25167
461 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
462 operand-less forms.
463 * opcodes/i386-tbl.h: Re-generate.
464
7abb8d81
JB		 4652019-11-05 Jan Beulich <jbeulich@suse.com>
466
467 * i386-dis.c (OP_Mwaitx): Delete.
468 (prefix_table): Use OP_Mwait for mwaitx entry.
469 (OP_Mwait): Also handle mwaitx.
470
267b8516
JB		 4712019-11-05 Jan Beulich <jbeulich@suse.com>
472
473 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
474 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
475 (prefix_table): Add respective entries.
476 (rm_table): Link to those entries.
477
f8687e93
JB		 4782019-11-05 Jan Beulich <jbeulich@suse.com>
479
480 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
481 (REG_0F1C_P_0_MOD_0): ... this.
482 (REG_0F1E_MOD_3): Rename to ...
483 (REG_0F1E_P_1_MOD_3): ... this.
484 (RM_0F01_REG_5): Rename to ...
485 (RM_0F01_REG_5_MOD_3): ... this.
486 (RM_0F01_REG_7): Rename to ...
487 (RM_0F01_REG_7_MOD_3): ... this.
488 (RM_0F1E_MOD_3_REG_7): Rename to ...
489 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
490 (RM_0FAE_REG_6): Rename to ...
491 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
492 (RM_0FAE_REG_7): Rename to ...
493 (RM_0FAE_REG_7_MOD_3): ... this.
494 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
495 (PREFIX_0F01_REG_5_MOD_0): ... this.
496 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
497 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
498 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
499 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
500 (PREFIX_0FAE_REG_0): Rename to ...
501 (PREFIX_0FAE_REG_0_MOD_3): ... this.
502 (PREFIX_0FAE_REG_1): Rename to ...
503 (PREFIX_0FAE_REG_1_MOD_3): ... this.
504 (PREFIX_0FAE_REG_2): Rename to ...
505 (PREFIX_0FAE_REG_2_MOD_3): ... this.
506 (PREFIX_0FAE_REG_3): Rename to ...
507 (PREFIX_0FAE_REG_3_MOD_3): ... this.
508 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
509 (PREFIX_0FAE_REG_4_MOD_0): ... this.
510 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
511 (PREFIX_0FAE_REG_4_MOD_3): ... this.
512 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
513 (PREFIX_0FAE_REG_5_MOD_0): ... this.
514 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
515 (PREFIX_0FAE_REG_5_MOD_3): ... this.
516 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
517 (PREFIX_0FAE_REG_6_MOD_0): ... this.
518 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
519 (PREFIX_0FAE_REG_6_MOD_3): ... this.
520 (PREFIX_0FAE_REG_7): Rename to ...
521 (PREFIX_0FAE_REG_7_MOD_0): ... this.
522 (PREFIX_MOD_0_0FC3): Rename to ...
523 (PREFIX_0FC3_MOD_0): ... this.
524 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
525 (PREFIX_0FC7_REG_6_MOD_0): ... this.
526 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
527 (PREFIX_0FC7_REG_6_MOD_3): ... this.
528 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
529 (PREFIX_0FC7_REG_7_MOD_3): ... this.
530 (reg_table, prefix_table, mod_table, rm_table): Adjust
531 accordingly.
532
5103274f
NC		 5332019-11-04 Nick Clifton <nickc@redhat.com>
534
535 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
536 of a v850 system register. Move the v850_sreg_names array into
537 this function.
538 (get_v850_reg_name): Likewise for ordinary register names.
539 (get_v850_vreg_name): Likewise for vector register names.
540 (get_v850_cc_name): Likewise for condition codes.
541 * get_v850_float_cc_name): Likewise for floating point condition
542 codes.
543 (get_v850_cacheop_name): Likewise for cache-ops.
544 (get_v850_prefop_name): Likewise for pref-ops.
545 (disassemble): Use the new accessor functions.
546
1820262b
DB		 5472019-10-30 Delia Burduv <delia.burduv@arm.com>
548
549 * aarch64-opc.c (print_immediate_offset_address): Don't print the
550 immediate for the writeback form of ldraa/ldrab if it is 0.
551 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
552 * aarch64-opc-2.c: Regenerated.
553
3cc17af5
JB		 5542019-10-30 Jan Beulich <jbeulich@suse.com>
555
556 * i386-gen.c (operand_type_shorthands): Delete.
557 (operand_type_init): Expand previous shorthands.
558 (set_bitfield_from_shorthand): Rename back to ...
559 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
560 of operand_type_init[].
561 (set_bitfield): Adjust call to the above function.
562 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
563 RegXMM, RegYMM, RegZMM): Define.
564 * i386-reg.tbl: Expand prior shorthands.
565
a2cebd03
JB		 5662019-10-30 Jan Beulich <jbeulich@suse.com>
567
568 * i386-gen.c (output_i386_opcode): Change order of fields
569 emitted to output.
570 * i386-opc.h (struct insn_template): Move operands field.
571 Convert extension_opcode field to unsigned short.
572 * i386-tbl.h: Re-generate.
573
507916b8
JB		 5742019-10-30 Jan Beulich <jbeulich@suse.com>
575
576 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
577 of W.
578 * i386-opc.h (W): Extend comment.
579 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
580 general purpose variants not allowing for byte operands.
581 * i386-tbl.h: Re-generate.
582
efea62b4
NC		 5832019-10-29 Nick Clifton <nickc@redhat.com>
584
585 * tic30-dis.c (print_branch): Correct size of operand array.
586
9adb2591
NC		 5872019-10-29 Nick Clifton <nickc@redhat.com>
588
589 * d30v-dis.c (print_insn): Check that operand index is valid
590 before attempting to access the operands array.
591
993a00a9
NC		 5922019-10-29 Nick Clifton <nickc@redhat.com>
593
594 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
595 locating the bit to be tested.
596
66a66a17
NC		 5972019-10-29 Nick Clifton <nickc@redhat.com>
598
599 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
600 values.
601 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
602 (print_insn_s12z): Check for illegal size values.
603
1ee3542c
NC		 6042019-10-28 Nick Clifton <nickc@redhat.com>
605
606 * csky-dis.c (csky_chars_to_number): Check for a negative
607 count. Use an unsigned integer to construct the return value.
608
bbf9a0b5
NC		 6092019-10-28 Nick Clifton <nickc@redhat.com>
610
611 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
612 operand buffer. Set value to 15 not 13.
613 (get_register_operand): Use OPERAND_BUFFER_LEN.
614 (get_indirect_operand): Likewise.
615 (print_two_operand): Likewise.
616 (print_three_operand): Likewise.
617 (print_oar_insn): Likewise.
618
d1e304bc
NC		 6192019-10-28 Nick Clifton <nickc@redhat.com>
620
621 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
622 (bit_extract_simple): Likewise.
623 (bit_copy): Likewise.
624 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
625 index_offset array are not accessed.
626
dee33451
NC		 6272019-10-28 Nick Clifton <nickc@redhat.com>
628
629 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
630 operand.
631
27cee81d
NC		 6322019-10-25 Nick Clifton <nickc@redhat.com>
633
634 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
635 access to opcodes.op array element.
636
de6d8dc2
NC		 6372019-10-23 Nick Clifton <nickc@redhat.com>
638
639 * rx-dis.c (get_register_name): Fix spelling typo in error
640 message.
641 (get_condition_name, get_flag_name, get_double_register_name)
642 (get_double_register_high_name, get_double_register_low_name)
643 (get_double_control_register_name, get_double_condition_name)
644 (get_opsize_name, get_size_name): Likewise.
645
6207ed28
NC		 6462019-10-22 Nick Clifton <nickc@redhat.com>
647
648 * rx-dis.c (get_size_name): New function. Provides safe
649 access to name array.
650 (get_opsize_name): Likewise.
651 (print_insn_rx): Use the accessor functions.
652
12234dfd
NC		 6532019-10-16 Nick Clifton <nickc@redhat.com>
654
655 * rx-dis.c (get_register_name): New function. Provides safe
656 access to name array.
657 (get_condition_name, get_flag_name, get_double_register_name)
658 (get_double_register_high_name, get_double_register_low_name)
659 (get_double_control_register_name, get_double_condition_name):
660 Likewise.
661 (print_insn_rx): Use the accessor functions.
662
1d378749
NC		 6632019-10-09 Nick Clifton <nickc@redhat.com>
664
665 PR 25041
666 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
667 instructions.
668
d241b910
JB		 6692019-10-07 Jan Beulich <jbeulich@suse.com>
670
671 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
672 (cmpsd): Likewise. Move EsSeg to other operand.
673 * opcodes/i386-tbl.h: Re-generate.
674
f5c5b7c1
AM		 6752019-09-23 Alan Modra <amodra@gmail.com>
676
677 * m68k-dis.c: Include cpu-m68k.h
678
7beeaeb8
AM		 6792019-09-23 Alan Modra <amodra@gmail.com>
680
681 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
682 "elf/mips.h" earlier.
683
3f9aad11
JB		 6842018-09-20 Jan Beulich <jbeulich@suse.com>
685
686 PR gas/25012
687 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
688 with SReg operand.
689 * i386-tbl.h: Re-generate.
690
fd361982
AM		 6912019-09-18 Alan Modra <amodra@gmail.com>
692
693 * arc-ext.c: Update throughout for bfd section macro changes.
694
e0b2a78c
SM		 6952019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
696
697 * Makefile.in: Re-generate.
698 * configure: Re-generate.
699
7e9ad3a3
JW		 7002019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
701
702 * riscv-opc.c (riscv_opcodes): Change subset field
703 to insn_class field for all instructions.
704 (riscv_insn_types): Likewise.
705
bb695960
PB		 7062019-09-16 Phil Blundell <pb@pbcl.net>
707
708 * configure: Regenerated.
709
8063ab7e
MV		 7102019-09-10 Miod Vallat <miod@online.fr>
711
712 PR 24982
713 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
714
60391a25
PB		 7152019-09-09 Phil Blundell <pb@pbcl.net>
716
717 binutils 2.33 branch created.
718
f44b758d
NC		 7192019-09-03 Nick Clifton <nickc@redhat.com>
720
721 PR 24961
722 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
723 greater than zero before indexing via (bufcnt -1).
724
1e4b5e7d
NC		 7252019-09-03 Nick Clifton <nickc@redhat.com>
726
727 PR 24958
728 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
729 (MAX_SPEC_REG_NAME_LEN): Define.
730 (struct mmix_dis_info): Use defined constants for array lengths.
731 (get_reg_name): New function.
732 (get_sprec_reg_name): New function.
733 (print_insn_mmix): Use new functions.
734
c4a23bf8
SP		 7352019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
736
737 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
738 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
739 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
740
a051e2f3
KT		 7412019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
742
743 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
744 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
745 (aarch64_sys_reg_supported_p): Update checks for the above.
746
08132bdd
SP		 7472019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
748
749 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
750 cases MVE_SQRSHRL and MVE_UQRSHLL.
751 (print_insn_mve): Add case for specifier 'k' to check
752 specific bit of the instruction.
753
d88bdcb4
PA		 7542019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
755
756 PR 24854
757 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
758 encountering an unknown machine type.
759 (print_insn_arc): Handle arc_insn_length returning 0. In error
760 cases return -1 rather than calling abort.
761
bc750500
JB		 7622019-08-07 Jan Beulich <jbeulich@suse.com>
763
764 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
765 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
766 IgnoreSize.
767 * i386-tbl.h: Re-generate.
768
23d188c7
BW		 7692019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
770
771 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
772 instructions.
773
c0d6f62f
JW		 7742019-07-30 Mel Chen <mel.chen@sifive.com>
775
776 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
777 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
778
779 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
780 fscsr.
781
0f3f7167
CZ		 7822019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
783
784 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
785 and MPY class instructions.
786 (parse_option): Add nps400 option.
787 (print_arc_disassembler_options): Add nps400 info.
788
7e126ba3
CZ		 7892019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
790
791 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
792 (bspop): Likewise.
793 (modapp): Likewise.
794 * arc-opc.c (RAD_CHK): Add.
795 * arc-tbl.h: Regenerate.
796
a028026d
KT		 7972019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
798
799 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
800 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
801
ac79ff9e
NC		 8022019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
803
804 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
805 instructions as UNPREDICTABLE.
806
231097b0
JM		 8072019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
808
809 * bpf-desc.c: Regenerated.
810
1d942ae9
JB		 8112019-07-17 Jan Beulich <jbeulich@suse.com>
812
813 * i386-gen.c (static_assert): Define.
814 (main): Use it.
815 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
816 (Opcode_Modifier_Num): ... this.
817 (Mem): Delete.
818
dfd69174
JB		 8192019-07-16 Jan Beulich <jbeulich@suse.com>
820
821 * i386-gen.c (operand_types): Move RegMem ...
822 (opcode_modifiers): ... here.
823 * i386-opc.h (RegMem): Move to opcode modifer enum.
824 (union i386_operand_type): Move regmem field ...
825 (struct i386_opcode_modifier): ... here.
826 * i386-opc.tbl (RegMem): Define.
827 (mov, movq): Move RegMem on segment, control, debug, and test
828 register flavors.
829 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
830 to non-SSE2AVX flavor.
831 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
832 Move RegMem on register only flavors. Drop IgnoreSize from
833 legacy encoding flavors.
834 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
835 flavors.
836 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
837 register only flavors.
838 (vmovd): Move RegMem and drop IgnoreSize on register only
839 flavor. Change opcode and operand order to store form.
840 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
841
21df382b
JB		 8422019-07-16 Jan Beulich <jbeulich@suse.com>
843
844 * i386-gen.c (operand_type_init, operand_types): Replace SReg
845 entries.
846 * i386-opc.h (SReg2, SReg3): Replace by ...
847 (SReg): ... this.
848 (union i386_operand_type): Replace sreg fields.
849 * i386-opc.tbl (mov, ): Use SReg.
850 (push, pop): Likewies. Drop i386 and x86-64 specific segment
851 register flavors.
852 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
853 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
854
3719fd55
JM		 8552019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
856
857 * bpf-desc.c: Regenerate.
858 * bpf-opc.c: Likewise.
859 * bpf-opc.h: Likewise.
860
92434a14
JM		 8612019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
862
863 * bpf-desc.c: Regenerate.
864 * bpf-opc.c: Likewise.
865
43dd7626
HPN		 8662019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
867
868 * arm-dis.c (print_insn_coprocessor): Rename index to
869 index_operand.
870
98602811
JW		 8712019-07-05 Kito Cheng <kito.cheng@sifive.com>
872
873 * riscv-opc.c (riscv_insn_types): Add r4 type.
874
875 * riscv-opc.c (riscv_insn_types): Add b and j type.
876
877 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
878 format for sb type and correct s type.
879
01c1ee4a
RS		 8802019-07-02 Richard Sandiford <richard.sandiford@arm.com>
881
882 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
883 SVE FMOV alias of FCPY.
884
83adff69
RS		 8852019-07-02 Richard Sandiford <richard.sandiford@arm.com>
886
887 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
888 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
889
89418844
RS		 8902019-07-02 Richard Sandiford <richard.sandiford@arm.com>
891
892 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
893 registers in an instruction prefixed by MOVPRFX.
894
41be57ca
MM		 8952019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
896
897 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
898 sve_size_13 icode to account for variant behaviour of
899 pmull{t,b}.
900 * aarch64-dis-2.c: Regenerate.
901 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
902 sve_size_13 icode to account for variant behaviour of
903 pmull{t,b}.
904 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
905 (OP_SVE_VVV_Q_D): Add new qualifier.
906 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
907 (struct aarch64_opcode): Split pmull{t,b} into those requiring
908 AES and those not.
909
9d3bf266
JB		 9102019-07-01 Jan Beulich <jbeulich@suse.com>
911
912 * opcodes/i386-gen.c (operand_type_init): Remove
913 OPERAND_TYPE_VEC_IMM4 entry.
914 (operand_types): Remove Vec_Imm4.
915 * opcodes/i386-opc.h (Vec_Imm4): Delete.
916 (union i386_operand_type): Remove vec_imm4.
917 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
918 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
919
c3949f43
JB		 9202019-07-01 Jan Beulich <jbeulich@suse.com>
921
922 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
923 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
924 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
925 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
926 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
927 monitorx, mwaitx): Drop ImmExt from operand-less forms.
928 * i386-tbl.h: Re-generate.
929
5641ec01
JB		 9302019-07-01 Jan Beulich <jbeulich@suse.com>
931
932 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
933 register operands.
934 * i386-tbl.h: Re-generate.
935
79dec6b7
JB		 9362019-07-01 Jan Beulich <jbeulich@suse.com>
937
938 * i386-opc.tbl (C): New.
939 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
940 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
941 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
942 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
943 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
944 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
945 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
946 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
947 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
948 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
949 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
950 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
951 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
952 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
953 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
954 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
955 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
956 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
957 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
958 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
959 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
960 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
961 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
962 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
963 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
964 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
965 flavors.
966 * i386-tbl.h: Re-generate.
967
a0a1771e
JB		 9682019-07-01 Jan Beulich <jbeulich@suse.com>
969
970 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
971 register operands.
972 * i386-tbl.h: Re-generate.
973
cd546e7b
JB		 9742019-07-01 Jan Beulich <jbeulich@suse.com>
975
976 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
977 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
978 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
979 * i386-tbl.h: Re-generate.
980
e3bba3fc
JB		 9812019-07-01 Jan Beulich <jbeulich@suse.com>
982
983 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
984 Disp8MemShift from register only templates.
985 * i386-tbl.h: Re-generate.
986
36cc073e
JB		 9872019-07-01 Jan Beulich <jbeulich@suse.com>
988
989 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
990 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
991 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
992 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
993 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
994 EVEX_W_0F11_P_3_M_1): Delete.
995 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
996 EVEX_W_0F11_P_3): New.
997 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
998 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
999 MOD_EVEX_0F11_PREFIX_3 table entries.
1000 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1001 PREFIX_EVEX_0F11 table entries.
1002 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1003 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1004 EVEX_W_0F11_P_3_M_{0,1} table entries.
1005
219920a7
JB		 10062019-07-01 Jan Beulich <jbeulich@suse.com>
1007
1008 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1009 Delete.
1010
e395f487
L		 10112019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1012
1013 PR binutils/24719
1014 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1015 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1016 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1017 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1018 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1019 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1020 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1021 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1022 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1023 PREFIX_EVEX_0F38C6_REG_6 entries.
1024 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1025 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1026 EVEX_W_0F38C7_R_6_P_2 entries.
1027 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1028 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1029 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1030 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1031 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1032 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1033 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1034
2b7bcc87
JB		 10352019-06-27 Jan Beulich <jbeulich@suse.com>
1036
1037 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1038 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1039 VEX_LEN_0F2D_P_3): Delete.
1040 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1041 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1042 (prefix_table): ... here.
1043
c1dc7af5
JB		 10442019-06-27 Jan Beulich <jbeulich@suse.com>
1045
1046 * i386-dis.c (Iq): Delete.
1047 (Id): New.
1048 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1049 TBM insns.
1050 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1051 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1052 (OP_E_memory): Also honor needindex when deciding whether an
1053 address size prefix needs printing.
1054 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1055
d7560e2d
JW		 10562019-06-26 Jim Wilson <jimw@sifive.com>
1057
1058 PR binutils/24739
1059 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1060 Set info->display_endian to info->endian_code.
1061
2c703856
JB		 10622019-06-25 Jan Beulich <jbeulich@suse.com>
1063
1064 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1065 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1066 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1067 OPERAND_TYPE_ACC64 entries.
1068 * i386-init.h: Re-generate.
1069
54fbadc0
JB		 10702019-06-25 Jan Beulich <jbeulich@suse.com>
1071
1072 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1073 Delete.
1074 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1075 of dqa_mode.
1076 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1077 entries here.
1078 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1079 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1080
a280ab8e
JB		 10812019-06-25 Jan Beulich <jbeulich@suse.com>
1082
1083 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1084 variables.
1085
e1a1babd
JB		 10862019-06-25 Jan Beulich <jbeulich@suse.com>
1087
1088 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1089 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1090 movnti.
d7560e2d 1091 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1092 * i386-tbl.h: Re-generate.
1093
b8364fa7
JB		 10942019-06-25 Jan Beulich <jbeulich@suse.com>
1095
1096 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1097 * i386-tbl.h: Re-generate.
1098
ad692897
L		 10992019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1100
1101 * i386-dis-evex.h: Break into ...
1102 * i386-dis-evex-len.h: New file.
1103 * i386-dis-evex-mod.h: Likewise.
1104 * i386-dis-evex-prefix.h: Likewise.
1105 * i386-dis-evex-reg.h: Likewise.
1106 * i386-dis-evex-w.h: Likewise.
1107 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1108 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1109 i386-dis-evex-mod.h.
1110
f0a6222e
L		 11112019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1112
1113 PR binutils/24700
1114 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1115 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1116 EVEX_W_0F385B_P_2.
1117 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1118 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1119 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1120 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1121 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1122 EVEX_LEN_0F385B_P_2_W_1.
1123 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1124 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1125 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1126 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1127 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1128 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1129 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1130 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1131 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1132 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1133
6e1c90b7
L		 11342019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1135
1136 PR binutils/24691
1137 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1138 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1139 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1140 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1141 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1142 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1143 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1144 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1145 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1146 EVEX_LEN_0F3A43_P_2_W_1.
1147 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1148 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1149 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1150 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1151 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1152 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1153 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1154 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1155 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1156 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1157 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1158 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1159
bcc5a6eb
NC		 11602019-06-14 Nick Clifton <nickc@redhat.com>
1161
1162 * po/fr.po; Updated French translation.
1163
e4c4ac46
SH		 11642019-06-13 Stafford Horne <shorne@gmail.com>
1165
1166 * or1k-asm.c: Regenerated.
1167 * or1k-desc.c: Regenerated.
1168 * or1k-desc.h: Regenerated.
1169 * or1k-dis.c: Regenerated.
1170 * or1k-ibld.c: Regenerated.
1171 * or1k-opc.c: Regenerated.
1172 * or1k-opc.h: Regenerated.
1173 * or1k-opinst.c: Regenerated.
1174
a0e44ef5
PB		 11752019-06-12 Peter Bergner <bergner@linux.ibm.com>
1176
1177 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1178
12efd68d
L		 11792019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1180
1181 PR binutils/24633
1182 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1183 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1184 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1185 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1186 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1187 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1188 EVEX_LEN_0F3A1B_P_2_W_1.
1189 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1190 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1191 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1192 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1193 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1194 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1195 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1196 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1197
63c6fc6c
L		 11982019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1199
1200 PR binutils/24626
1201 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1202 EVEX.vvvv when disassembling VEX and EVEX instructions.
1203 (OP_VEX): Set vex.register_specifier to 0 after readding
1204 vex.register_specifier.
1205 (OP_Vex_2src_1): Likewise.
1206 (OP_Vex_2src_2): Likewise.
1207 (OP_LWP_E): Likewise.
1208 (OP_EX_Vex): Don't check vex.register_specifier.
1209 (OP_XMM_Vex): Likewise.
1210
9186c494
L		 12112019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1212 Lili Cui <lili.cui@intel.com>
1213
1214 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1215 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1216 instructions.
1217 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1218 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1219 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1220 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1221 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1222 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1223 * i386-init.h: Regenerated.
1224 * i386-tbl.h: Likewise.
1225
5d79adc4
L		 12262019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1227 Lili Cui <lili.cui@intel.com>
1228
1229 * doc/c-i386.texi: Document enqcmd.
1230 * testsuite/gas/i386/enqcmd-intel.d: New file.
1231 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1232 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1233 * testsuite/gas/i386/enqcmd.d: Likewise.
1234 * testsuite/gas/i386/enqcmd.s: Likewise.
1235 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1236 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1237 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1238 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1239 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1240 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1241 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1242 and x86-64-enqcmd.
1243
a9d96ab9
AH		 12442019-06-04 Alan Hayward <alan.hayward@arm.com>
1245
1246 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1247
4f6d070a
AM		 12482019-06-03 Alan Modra <amodra@gmail.com>
1249
1250 * ppc-dis.c (prefix_opcd_indices): Correct size.
1251
a2f4b66c
L		 12522019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1253
1254 PR gas/24625
1255 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1256 Disp8ShiftVL.
1257 * i386-tbl.h: Regenerated.
1258
405b5bd8
AM		 12592019-05-24 Alan Modra <amodra@gmail.com>
1260
1261 * po/POTFILES.in: Regenerate.
1262
8acf1435
PB		 12632019-05-24 Peter Bergner <bergner@linux.ibm.com>
1264 Alan Modra <amodra@gmail.com>
1265
1266 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1267 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1268 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1269 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1270 XTOP>): Define and add entries.
1271 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1272 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1273 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1274 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1275
dd7efa79
PB		 12762019-05-24 Peter Bergner <bergner@linux.ibm.com>
1277 Alan Modra <amodra@gmail.com>
1278
1279 * ppc-dis.c (ppc_opts): Add "future" entry.
1280 (PREFIX_OPCD_SEGS): Define.
1281 (prefix_opcd_indices): New array.
1282 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1283 (lookup_prefix): New function.
1284 (print_insn_powerpc): Handle 64-bit prefix instructions.
1285 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1286 (PMRR, POWERXX): Define.
1287 (prefix_opcodes): New instruction table.
1288 (prefix_num_opcodes): New constant.
1289
79472b45
JM		 12902019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1291
1292 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1293 * configure: Regenerated.
1294 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1295 and cpu/bpf.opc.
1296 (HFILES): Add bpf-desc.h and bpf-opc.h.
1297 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1298 bpf-ibld.c and bpf-opc.c.
1299 (BPF_DEPS): Define.
1300 * Makefile.in: Regenerated.
1301 * disassemble.c (ARCH_bpf): Define.
1302 (disassembler): Add case for bfd_arch_bpf.
1303 (disassemble_init_for_target): Likewise.
1304 (enum epbf_isa_attr): Define.
1305 * disassemble.h: extern print_insn_bpf.
1306 * bpf-asm.c: Generated.
1307 * bpf-opc.h: Likewise.
1308 * bpf-opc.c: Likewise.
1309 * bpf-ibld.c: Likewise.
1310 * bpf-dis.c: Likewise.
1311 * bpf-desc.h: Likewise.
1312 * bpf-desc.c: Likewise.
1313
ba6cd17f
SD		 13142019-05-21 Sudakshina Das <sudi.das@arm.com>
1315
1316 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1317 and VMSR with the new operands.
1318
e39c1607
SD		 13192019-05-21 Sudakshina Das <sudi.das@arm.com>
1320
1321 * arm-dis.c (enum mve_instructions): New enum
1322 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1323 and cneg.
1324 (mve_opcodes): New instructions as above.
1325 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1326 csneg and csel.
1327 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1328
23d00a41
SD		 13292019-05-21 Sudakshina Das <sudi.das@arm.com>
1330
1331 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1332 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1333 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1334 uqshl, urshrl and urshr.
1335 (is_mve_okay_in_it): Add new instructions to TRUE list.
1336 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1337 (print_insn_mve): Updated to accept new %j,
1338 %<bitfield>m and %<bitfield>n patterns.
1339
cd4797ee
FS		 13402019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1341
1342 * mips-opc.c (mips_builtin_opcodes): Change source register
1343 constraint for DAUI.
1344
999b073b
NC		 13452019-05-20 Nick Clifton <nickc@redhat.com>
1346
1347 * po/fr.po: Updated French translation.
1348
14b456f2
AV		 13492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1350 Michael Collison <michael.collison@arm.com>
1351
1352 * arm-dis.c (thumb32_opcodes): Add new instructions.
1353 (enum mve_instructions): Likewise.
1354 (enum mve_undefined): Add new reasons.
1355 (is_mve_encoding_conflict): Handle new instructions.
1356 (is_mve_undefined): Likewise.
1357 (is_mve_unpredictable): Likewise.
1358 (print_mve_undefined): Likewise.
1359 (print_mve_size): Likewise.
1360
f49bb598
AV		 13612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1362 Michael Collison <michael.collison@arm.com>
1363
1364 * arm-dis.c (thumb32_opcodes): Add new instructions.
1365 (enum mve_instructions): Likewise.
1366 (is_mve_encoding_conflict): Handle new instructions.
1367 (is_mve_undefined): Likewise.
1368 (is_mve_unpredictable): Likewise.
1369 (print_mve_size): Likewise.
1370
56858bea
AV		 13712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1372 Michael Collison <michael.collison@arm.com>
1373
1374 * arm-dis.c (thumb32_opcodes): Add new instructions.
1375 (enum mve_instructions): Likewise.
1376 (is_mve_encoding_conflict): Likewise.
1377 (is_mve_unpredictable): Likewise.
1378 (print_mve_size): Likewise.
1379
e523f101
AV		 13802019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1381 Michael Collison <michael.collison@arm.com>
1382
1383 * arm-dis.c (thumb32_opcodes): Add new instructions.
1384 (enum mve_instructions): Likewise.
1385 (is_mve_encoding_conflict): Handle new instructions.
1386 (is_mve_undefined): Likewise.
1387 (is_mve_unpredictable): Likewise.
1388 (print_mve_size): Likewise.
1389
66dcaa5d
AV		 13902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1391 Michael Collison <michael.collison@arm.com>
1392
1393 * arm-dis.c (thumb32_opcodes): Add new instructions.
1394 (enum mve_instructions): Likewise.
1395 (is_mve_encoding_conflict): Handle new instructions.
1396 (is_mve_undefined): Likewise.
1397 (is_mve_unpredictable): Likewise.
1398 (print_mve_size): Likewise.
1399 (print_insn_mve): Likewise.
1400
d052b9b7
AV		 14012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1402 Michael Collison <michael.collison@arm.com>
1403
1404 * arm-dis.c (thumb32_opcodes): Add new instructions.
1405 (print_insn_thumb32): Handle new instructions.
1406
ed63aa17
AV		 14072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1408 Michael Collison <michael.collison@arm.com>
1409
1410 * arm-dis.c (enum mve_instructions): Add new instructions.
1411 (enum mve_undefined): Add new reasons.
1412 (is_mve_encoding_conflict): Handle new instructions.
1413 (is_mve_undefined): Likewise.
1414 (is_mve_unpredictable): Likewise.
1415 (print_mve_undefined): Likewise.
1416 (print_mve_size): Likewise.
1417 (print_mve_shift_n): Likewise.
1418 (print_insn_mve): Likewise.
1419
897b9bbc
AV		 14202019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1421 Michael Collison <michael.collison@arm.com>
1422
1423 * arm-dis.c (enum mve_instructions): Add new instructions.
1424 (is_mve_encoding_conflict): Handle new instructions.
1425 (is_mve_unpredictable): Likewise.
1426 (print_mve_rotate): Likewise.
1427 (print_mve_size): Likewise.
1428 (print_insn_mve): Likewise.
1429
1c8f2df8
AV		 14302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1431 Michael Collison <michael.collison@arm.com>
1432
1433 * arm-dis.c (enum mve_instructions): Add new instructions.
1434 (is_mve_encoding_conflict): Handle new instructions.
1435 (is_mve_unpredictable): Likewise.
1436 (print_mve_size): Likewise.
1437 (print_insn_mve): Likewise.
1438
d3b63143
AV		 14392019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1440 Michael Collison <michael.collison@arm.com>
1441
1442 * arm-dis.c (enum mve_instructions): Add new instructions.
1443 (enum mve_undefined): Add new reasons.
1444 (is_mve_encoding_conflict): Handle new instructions.
1445 (is_mve_undefined): Likewise.
1446 (is_mve_unpredictable): Likewise.
1447 (print_mve_undefined): Likewise.
1448 (print_mve_size): Likewise.
1449 (print_insn_mve): Likewise.
1450
14925797
AV		 14512019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1452 Michael Collison <michael.collison@arm.com>
1453
1454 * arm-dis.c (enum mve_instructions): Add new instructions.
1455 (is_mve_encoding_conflict): Handle new instructions.
1456 (is_mve_undefined): Likewise.
1457 (is_mve_unpredictable): Likewise.
1458 (print_mve_size): Likewise.
1459 (print_insn_mve): Likewise.
1460
c507f10b
AV		 14612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1462 Michael Collison <michael.collison@arm.com>
1463
1464 * arm-dis.c (enum mve_instructions): Add new instructions.
1465 (enum mve_unpredictable): Add new reasons.
1466 (enum mve_undefined): Likewise.
1467 (is_mve_okay_in_it): Handle new isntructions.
1468 (is_mve_encoding_conflict): Likewise.
1469 (is_mve_undefined): Likewise.
1470 (is_mve_unpredictable): Likewise.
1471 (print_mve_vmov_index): Likewise.
1472 (print_simd_imm8): Likewise.
1473 (print_mve_undefined): Likewise.
1474 (print_mve_unpredictable): Likewise.
1475 (print_mve_size): Likewise.
1476 (print_insn_mve): Likewise.
1477
bf0b396d
AV		 14782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1479 Michael Collison <michael.collison@arm.com>
1480
1481 * arm-dis.c (enum mve_instructions): Add new instructions.
1482 (enum mve_unpredictable): Add new reasons.
1483 (enum mve_undefined): Likewise.
1484 (is_mve_encoding_conflict): Handle new instructions.
1485 (is_mve_undefined): Likewise.
1486 (is_mve_unpredictable): Likewise.
1487 (print_mve_undefined): Likewise.
1488 (print_mve_unpredictable): Likewise.
1489 (print_mve_rounding_mode): Likewise.
1490 (print_mve_vcvt_size): Likewise.
1491 (print_mve_size): Likewise.
1492 (print_insn_mve): Likewise.
1493
ef1576a1
AV		 14942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1495 Michael Collison <michael.collison@arm.com>
1496
1497 * arm-dis.c (enum mve_instructions): Add new instructions.
1498 (enum mve_unpredictable): Add new reasons.
1499 (enum mve_undefined): Likewise.
1500 (is_mve_undefined): Handle new instructions.
1501 (is_mve_unpredictable): Likewise.
1502 (print_mve_undefined): Likewise.
1503 (print_mve_unpredictable): Likewise.
1504 (print_mve_size): Likewise.
1505 (print_insn_mve): Likewise.
1506
aef6d006
AV		 15072019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1508 Michael Collison <michael.collison@arm.com>
1509
1510 * arm-dis.c (enum mve_instructions): Add new instructions.
1511 (enum mve_undefined): Add new reasons.
1512 (insns): Add new instructions.
1513 (is_mve_encoding_conflict):
1514 (print_mve_vld_str_addr): New print function.
1515 (is_mve_undefined): Handle new instructions.
1516 (is_mve_unpredictable): Likewise.
1517 (print_mve_undefined): Likewise.
1518 (print_mve_size): Likewise.
1519 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1520 (print_insn_mve): Handle new operands.
1521
04d54ace
AV		 15222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1523 Michael Collison <michael.collison@arm.com>
1524
1525 * arm-dis.c (enum mve_instructions): Add new instructions.
1526 (enum mve_unpredictable): Add new reasons.
1527 (is_mve_encoding_conflict): Handle new instructions.
1528 (is_mve_unpredictable): Likewise.
1529 (mve_opcodes): Add new instructions.
1530 (print_mve_unpredictable): Handle new reasons.
1531 (print_mve_register_blocks): New print function.
1532 (print_mve_size): Handle new instructions.
1533 (print_insn_mve): Likewise.
1534
9743db03
AV		 15352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1536 Michael Collison <michael.collison@arm.com>
1537
1538 * arm-dis.c (enum mve_instructions): Add new instructions.
1539 (enum mve_unpredictable): Add new reasons.
1540 (enum mve_undefined): Likewise.
1541 (is_mve_encoding_conflict): Handle new instructions.
1542 (is_mve_undefined): Likewise.
1543 (is_mve_unpredictable): Likewise.
1544 (coprocessor_opcodes): Move NEON VDUP from here...
1545 (neon_opcodes): ... to here.
1546 (mve_opcodes): Add new instructions.
1547 (print_mve_undefined): Handle new reasons.
1548 (print_mve_unpredictable): Likewise.
1549 (print_mve_size): Handle new instructions.
1550 (print_insn_neon): Handle vdup.
1551 (print_insn_mve): Handle new operands.
1552
143275ea
AV		 15532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1554 Michael Collison <michael.collison@arm.com>
1555
1556 * arm-dis.c (enum mve_instructions): Add new instructions.
1557 (enum mve_unpredictable): Add new values.
1558 (mve_opcodes): Add new instructions.
1559 (vec_condnames): New array with vector conditions.
1560 (mve_predicatenames): New array with predicate suffixes.
1561 (mve_vec_sizename): New array with vector sizes.
1562 (enum vpt_pred_state): New enum with vector predication states.
1563 (struct vpt_block): New struct type for vpt blocks.
1564 (vpt_block_state): Global struct to keep track of state.
1565 (mve_extract_pred_mask): New helper function.
1566 (num_instructions_vpt_block): Likewise.
1567 (mark_outside_vpt_block): Likewise.
1568 (mark_inside_vpt_block): Likewise.
1569 (invert_next_predicate_state): Likewise.
1570 (update_next_predicate_state): Likewise.
1571 (update_vpt_block_state): Likewise.
1572 (is_vpt_instruction): Likewise.
1573 (is_mve_encoding_conflict): Add entries for new instructions.
1574 (is_mve_unpredictable): Likewise.
1575 (print_mve_unpredictable): Handle new cases.
1576 (print_instruction_predicate): Likewise.
1577 (print_mve_size): New function.
1578 (print_vec_condition): New function.
1579 (print_insn_mve): Handle vpt blocks and new print operands.
1580
f08d8ce3
AV		 15812019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1582
1583 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1584 8, 14 and 15 for Armv8.1-M Mainline.
1585
73cd51e5
AV		 15862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1587 Michael Collison <michael.collison@arm.com>
1588
1589 * arm-dis.c (enum mve_instructions): New enum.
1590 (enum mve_unpredictable): Likewise.
1591 (enum mve_undefined): Likewise.
1592 (struct mopcode32): New struct.
1593 (is_mve_okay_in_it): New function.
1594 (is_mve_architecture): Likewise.
1595 (arm_decode_field): Likewise.
1596 (arm_decode_field_multiple): Likewise.
1597 (is_mve_encoding_conflict): Likewise.
1598 (is_mve_undefined): Likewise.
1599 (is_mve_unpredictable): Likewise.
1600 (print_mve_undefined): Likewise.
1601 (print_mve_unpredictable): Likewise.
1602 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1603 (print_insn_mve): New function.
1604 (print_insn_thumb32): Handle MVE architecture.
1605 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1606
3076e594
NC		 16072019-05-10 Nick Clifton <nickc@redhat.com>
1608
1609 PR 24538
1610 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1611 end of the table prematurely.
1612
387e7624
FS		 16132019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1614
1615 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1616 macros for R6.
1617
0067be51
AM		 16182019-05-11 Alan Modra <amodra@gmail.com>
1619
1620 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1621 when -Mraw is in effect.
1622
42e6288f
MM		 16232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1624
1625 * aarch64-dis-2.c: Regenerate.
1626 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1627 (OP_SVE_BBB): New variant set.
1628 (OP_SVE_DDDD): New variant set.
1629 (OP_SVE_HHH): New variant set.
1630 (OP_SVE_HHHU): New variant set.
1631 (OP_SVE_SSS): New variant set.
1632 (OP_SVE_SSSU): New variant set.
1633 (OP_SVE_SHH): New variant set.
1634 (OP_SVE_SBBU): New variant set.
1635 (OP_SVE_DSS): New variant set.
1636 (OP_SVE_DHHU): New variant set.
1637 (OP_SVE_VMV_HSD_BHS): New variant set.
1638 (OP_SVE_VVU_HSD_BHS): New variant set.
1639 (OP_SVE_VVVU_SD_BH): New variant set.
1640 (OP_SVE_VVVU_BHSD): New variant set.
1641 (OP_SVE_VVV_QHD_DBS): New variant set.
1642 (OP_SVE_VVV_HSD_BHS): New variant set.
1643 (OP_SVE_VVV_HSD_BHS2): New variant set.
1644 (OP_SVE_VVV_BHS_HSD): New variant set.
1645 (OP_SVE_VV_BHS_HSD): New variant set.
1646 (OP_SVE_VVV_SD): New variant set.
1647 (OP_SVE_VVU_BHS_HSD): New variant set.
1648 (OP_SVE_VZVV_SD): New variant set.
1649 (OP_SVE_VZVV_BH): New variant set.
1650 (OP_SVE_VZV_SD): New variant set.
1651 (aarch64_opcode_table): Add sve2 instructions.
1652
28ed815a
MM		 16532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1654
1655 * aarch64-asm-2.c: Regenerated.
1656 * aarch64-dis-2.c: Regenerated.
1657 * aarch64-opc-2.c: Regenerated.
1658 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1659 for SVE_SHLIMM_UNPRED_22.
1660 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1661 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1662 operand.
1663
fd1dc4a0
MM		 16642019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1665
1666 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1667 sve_size_tsz_bhs iclass encode.
1668 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1669 sve_size_tsz_bhs iclass decode.
1670
31e36ab3
MM		 16712019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1672
1673 * aarch64-asm-2.c: Regenerated.
1674 * aarch64-dis-2.c: Regenerated.
1675 * aarch64-opc-2.c: Regenerated.
1676 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1677 for SVE_Zm4_11_INDEX.
1678 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1679 (fields): Handle SVE_i2h field.
1680 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1681 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1682
1be5f94f
MM		 16832019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1684
1685 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1686 sve_shift_tsz_bhsd iclass encode.
1687 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1688 sve_shift_tsz_bhsd iclass decode.
1689
3c17238b
MM		 16902019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1691
1692 * aarch64-asm-2.c: Regenerated.
1693 * aarch64-dis-2.c: Regenerated.
1694 * aarch64-opc-2.c: Regenerated.
1695 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1696 (aarch64_encode_variant_using_iclass): Handle
1697 sve_shift_tsz_hsd iclass encode.
1698 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1699 sve_shift_tsz_hsd iclass decode.
1700 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1701 for SVE_SHRIMM_UNPRED_22.
1702 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1703 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1704 operand.
1705
cd50a87a
MM		 17062019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1707
1708 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1709 sve_size_013 iclass encode.
1710 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1711 sve_size_013 iclass decode.
1712
3c705960
MM		 17132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1714
1715 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1716 sve_size_bh iclass encode.
1717 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1718 sve_size_bh iclass decode.
1719
0a57e14f
MM		 17202019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1721
1722 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1723 sve_size_sd2 iclass encode.
1724 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1725 sve_size_sd2 iclass decode.
1726 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1727 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1728
c469c864
MM		 17292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1730
1731 * aarch64-asm-2.c: Regenerated.
1732 * aarch64-dis-2.c: Regenerated.
1733 * aarch64-opc-2.c: Regenerated.
1734 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1735 for SVE_ADDR_ZX.
1736 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1737 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1738
116adc27
MM		 17392019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1740
1741 * aarch64-asm-2.c: Regenerated.
1742 * aarch64-dis-2.c: Regenerated.
1743 * aarch64-opc-2.c: Regenerated.
1744 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1745 for SVE_Zm3_11_INDEX.
1746 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1747 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1748 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1749 fields.
1750 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1751
3bd82c86
MM		 17522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1753
1754 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1755 sve_size_hsd2 iclass encode.
1756 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1757 sve_size_hsd2 iclass decode.
1758 * aarch64-opc.c (fields): Handle SVE_size field.
1759 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1760
adccc507
MM		 17612019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1762
1763 * aarch64-asm-2.c: Regenerated.
1764 * aarch64-dis-2.c: Regenerated.
1765 * aarch64-opc-2.c: Regenerated.
1766 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1767 for SVE_IMM_ROT3.
1768 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1769 (fields): Handle SVE_rot3 field.
1770 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1771 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1772
5cd99750
MM		 17732019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1774
1775 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1776 instructions.
1777
7ce2460a
MM		 17782019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1779
1780 * aarch64-tbl.h
1781 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1782 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1783 aarch64_feature_sve2bitperm): New feature sets.
1784 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1785 for feature set addresses.
1786 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1787 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1788
41cee089
FS		 17892019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1790 Faraz Shahbazker <fshahbazker@wavecomp.com>
1791
1792 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1793 argument and set ASE_EVA_R6 appropriately.
1794 (set_default_mips_dis_options): Pass ISA to above.
1795 (parse_mips_dis_option): Likewise.
1796 * mips-opc.c (EVAR6): New macro.
1797 (mips_builtin_opcodes): Add llwpe, scwpe.
1798
b83b4b13
SD		 17992019-05-01 Sudakshina Das <sudi.das@arm.com>
1800
1801 * aarch64-asm-2.c: Regenerated.
1802 * aarch64-dis-2.c: Regenerated.
1803 * aarch64-opc-2.c: Regenerated.
1804 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1805 AARCH64_OPND_TME_UIMM16.
1806 (aarch64_print_operand): Likewise.
1807 * aarch64-tbl.h (QL_IMM_NIL): New.
1808 (TME): New.
1809 (_TME_INSN): New.
1810 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1811
4a90ce95
JD		 18122019-04-29 John Darrington <john@darrington.wattle.id.au>
1813
1814 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1815
a45328b9
AB		 18162019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1817 Faraz Shahbazker <fshahbazker@wavecomp.com>
1818
1819 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1820
d10be0cb
JD		 18212019-04-24 John Darrington <john@darrington.wattle.id.au>
1822
1823 * s12z-opc.h: Add extern "C" bracketing to help
1824 users who wish to use this interface in c++ code.
1825
a679f24e
JD		 18262019-04-24 John Darrington <john@darrington.wattle.id.au>
1827
1828 * s12z-opc.c (bm_decode): Handle bit map operations with the
1829 "reserved0" mode.
1830
32c36c3c
AV		 18312019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1832
1833 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1834 specifier. Add entries for VLDR and VSTR of system registers.
1835 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1836 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1837 of %J and %K format specifier.
1838
efd6b359
AV		 18392019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1840
1841 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1842 Add new entries for VSCCLRM instruction.
1843 (print_insn_coprocessor): Handle new %C format control code.
1844
6b0dd094
AV		 18452019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1846
1847 * arm-dis.c (enum isa): New enum.
1848 (struct sopcode32): New structure.
1849 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1850 set isa field of all current entries to ANY.
1851 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1852 Only match an entry if its isa field allows the current mode.
1853
4b5a202f
AV		 18542019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1855
1856 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1857 CLRM.
1858 (print_insn_thumb32): Add logic to print %n CLRM register list.
1859
60f993ce
AV		 18602019-04-15 Sudakshina Das <sudi.das@arm.com>
1861
1862 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1863 and %Q patterns.
1864
f6b2b12d
AV		 18652019-04-15 Sudakshina Das <sudi.das@arm.com>
1866
1867 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1868 (print_insn_thumb32): Edit the switch case for %Z.
1869
1889da70
AV		 18702019-04-15 Sudakshina Das <sudi.das@arm.com>
1871
1872 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1873
65d1bc05
AV		 18742019-04-15 Sudakshina Das <sudi.das@arm.com>
1875
1876 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1877
1caf72a5
AV		 18782019-04-15 Sudakshina Das <sudi.das@arm.com>
1879
1880 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1881
f1c7f421
AV		 18822019-04-15 Sudakshina Das <sudi.das@arm.com>
1883
1884 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1885 Arm register with r13 and r15 unpredictable.
1886 (thumb32_opcodes): New instructions for bfx and bflx.
1887
4389b29a
AV		 18882019-04-15 Sudakshina Das <sudi.das@arm.com>
1889
1890 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1891
e5d6e09e
AV		 18922019-04-15 Sudakshina Das <sudi.das@arm.com>
1893
1894 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1895
e12437dc
AV		 18962019-04-15 Sudakshina Das <sudi.das@arm.com>
1897
1898 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1899
031254f2
AV		 19002019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1901
1902 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1903
e5a557ac
JD		 19042019-04-12 John Darrington <john@darrington.wattle.id.au>
1905
1906 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1907 "optr". ("operator" is a reserved word in c++).
1908
bd7ceb8d
SD		 19092019-04-11 Sudakshina Das <sudi.das@arm.com>
1910
1911 * aarch64-opc.c (aarch64_print_operand): Add case for
1912 AARCH64_OPND_Rt_SP.
1913 (verify_constraints): Likewise.
1914 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1915 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1916 to accept Rt|SP as first operand.
1917 (AARCH64_OPERANDS): Add new Rt_SP.
1918 * aarch64-asm-2.c: Regenerated.
1919 * aarch64-dis-2.c: Regenerated.
1920 * aarch64-opc-2.c: Regenerated.
1921
e54010f1
SD		 19222019-04-11 Sudakshina Das <sudi.das@arm.com>
1923
1924 * aarch64-asm-2.c: Regenerated.
1925 * aarch64-dis-2.c: Likewise.
1926 * aarch64-opc-2.c: Likewise.
1927 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1928
7e96e219
RS		 19292019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1930
1931 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1932
6f2791d5
L		 19332019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1934
1935 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1936 * i386-init.h: Regenerated.
1937
e392bad3
AM		 19382019-04-07 Alan Modra <amodra@gmail.com>
1939
1940 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1941 op_separator to control printing of spaces, comma and parens
1942 rather than need_comma, need_paren and spaces vars.
1943
dffaa15c
AM		 19442019-04-07 Alan Modra <amodra@gmail.com>
1945
1946 PR 24421
1947 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1948 (print_insn_neon, print_insn_arm): Likewise.
1949
d6aab7a1
XG		 19502019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1951
1952 * i386-dis-evex.h (evex_table): Updated to support BF16
1953 instructions.
1954 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1955 and EVEX_W_0F3872_P_3.
1956 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1957 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1958 * i386-opc.h (enum): Add CpuAVX512_BF16.
1959 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1960 * i386-opc.tbl: Add AVX512 BF16 instructions.
1961 * i386-init.h: Regenerated.
1962 * i386-tbl.h: Likewise.
1963
66e85460
AM		 19642019-04-05 Alan Modra <amodra@gmail.com>
1965
1966 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1967 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1968 to favour printing of "-" branch hint when using the "y" bit.
1969 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1970
c2b1c275
AM		 19712019-04-05 Alan Modra <amodra@gmail.com>
1972
1973 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1974 opcode until first operand is output.
1975
aae9718e
PB		 19762019-04-04 Peter Bergner <bergner@linux.ibm.com>
1977
1978 PR gas/24349
1979 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1980 (valid_bo_post_v2): Add support for 'at' branch hints.
1981 (insert_bo): Only error on branch on ctr.
1982 (get_bo_hint_mask): New function.
1983 (insert_boe): Add new 'branch_taken' formal argument. Add support
1984 for inserting 'at' branch hints.
1985 (extract_boe): Add new 'branch_taken' formal argument. Add support
1986 for extracting 'at' branch hints.
1987 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1988 (BOE): Delete operand.
1989 (BOM, BOP): New operands.
1990 (RM): Update value.
1991 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1992 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1993 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1994 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1995 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1996 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1997 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1998 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1999 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2000 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2001 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2002 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2003 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2004 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2005 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2006 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2007 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2008 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2009 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2010 bttarl+>: New extended mnemonics.
2011
96a86c01
AM		 20122019-03-28 Alan Modra <amodra@gmail.com>
2013
2014 PR 24390
2015 * ppc-opc.c (BTF): Define.
2016 (powerpc_opcodes): Use for mtfsb*.
2017 * ppc-dis.c (print_insn_powerpc): Print fields with both
2018 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2019
796d6298
TC		 20202019-03-25 Tamar Christina <tamar.christina@arm.com>
2021
2022 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2023 (mapping_symbol_for_insn): Implement new algorithm.
2024 (print_insn): Remove duplicate code.
2025
60df3720
TC		 20262019-03-25 Tamar Christina <tamar.christina@arm.com>
2027
2028 * aarch64-dis.c (print_insn_aarch64):
2029 Implement override.
2030
51457761
TC		 20312019-03-25 Tamar Christina <tamar.christina@arm.com>
2032
2033 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2034 order.
2035
53b2f36b
TC		 20362019-03-25 Tamar Christina <tamar.christina@arm.com>
2037
2038 * aarch64-dis.c (last_stop_offset): New.
2039 (print_insn_aarch64): Use stop_offset.
2040
89199bb5
L		 20412019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2042
2043 PR gas/24359
2044 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2045 CPU_ANY_AVX2_FLAGS.
2046 * i386-init.h: Regenerated.
2047
97ed31ae
L		 20482019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2049
2050 PR gas/24348
2051 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2052 vmovdqu16, vmovdqu32 and vmovdqu64.
2053 * i386-tbl.h: Regenerated.
2054
0919bfe9
AK		 20552019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2056
2057 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2058 from vstrszb, vstrszh, and vstrszf.
2059
20602019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2061
2062 * s390-opc.txt: Add instruction descriptions.
2063
21820ebe
JW		 20642019-02-08 Jim Wilson <jimw@sifive.com>
2065
2066 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2067 <bne>: Likewise.
2068
f7dd2fb2
TC		 20692019-02-07 Tamar Christina <tamar.christina@arm.com>
2070
2071 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2072
6456d318
TC		 20732019-02-07 Tamar Christina <tamar.christina@arm.com>
2074
2075 PR binutils/23212
2076 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2077 * aarch64-opc.c (verify_elem_sd): New.
2078 (fields): Add FLD_sz entr.
2079 * aarch64-tbl.h (_SIMD_INSN): New.
2080 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2081 fmulx scalar and vector by element isns.
2082
4a83b610
NC		 20832019-02-07 Nick Clifton <nickc@redhat.com>
2084
2085 * po/sv.po: Updated Swedish translation.
2086
fc60b8c8
AK		 20872019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2088
2089 * s390-mkopc.c (main): Accept arch13 as cpu string.
2090 * s390-opc.c: Add new instruction formats and instruction opcode
2091 masks.
2092 * s390-opc.txt: Add new arch13 instructions.
2093
e10620d3
TC		 20942019-01-25 Sudakshina Das <sudi.das@arm.com>
2095
2096 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2097 (aarch64_opcode): Change encoding for stg, stzg
2098 st2g and st2zg.
2099 * aarch64-asm-2.c: Regenerated.
2100 * aarch64-dis-2.c: Regenerated.
2101 * aarch64-opc-2.c: Regenerated.
2102
20a4ca55
SD		 21032019-01-25 Sudakshina Das <sudi.das@arm.com>
2104
2105 * aarch64-asm-2.c: Regenerated.
2106 * aarch64-dis-2.c: Likewise.
2107 * aarch64-opc-2.c: Likewise.
2108 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2109
550fd7bf
SD		 21102019-01-25 Sudakshina Das <sudi.das@arm.com>
2111 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2112
2113 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2114 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2115 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2116 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2117 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2118 case for ldstgv_indexed.
2119 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2120 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2121 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2122 * aarch64-asm-2.c: Regenerated.
2123 * aarch64-dis-2.c: Regenerated.
2124 * aarch64-opc-2.c: Regenerated.
2125
d9938630
NC		 21262019-01-23 Nick Clifton <nickc@redhat.com>
2127
2128 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2129
375cd423
NC		 21302019-01-21 Nick Clifton <nickc@redhat.com>
2131
2132 * po/de.po: Updated German translation.
2133 * po/uk.po: Updated Ukranian translation.
2134
57299f48
CX		 21352019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2136 * mips-dis.c (mips_arch_choices): Fix typo in
2137 gs464, gs464e and gs264e descriptors.
2138
f48dfe41
NC		 21392019-01-19 Nick Clifton <nickc@redhat.com>
2140
2141 * configure: Regenerate.
2142 * po/opcodes.pot: Regenerate.
2143
f974f26c
NC		 21442018-06-24 Nick Clifton <nickc@redhat.com>
2145
2146 2.32 branch created.
2147
39f286cd
JD		 21482019-01-09 John Darrington <john@darrington.wattle.id.au>
2149
448b8ca8
JD		 2150 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2151 if it is null.
2152 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2153 zero.
2154
3107326d
AP		 21552019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2156
2157 * configure: Regenerate.
2158
7e9ca91e
AM		 21592019-01-07 Alan Modra <amodra@gmail.com>
2160
2161 * configure: Regenerate.
2162 * po/POTFILES.in: Regenerate.
2163
ef1ad42b
JD		 21642019-01-03 John Darrington <john@darrington.wattle.id.au>
2165
2166 * s12z-opc.c: New file.
2167 * s12z-opc.h: New file.
2168 * s12z-dis.c: Removed all code not directly related to display
2169 of instructions. Used the interface provided by the new files
2170 instead.
2171 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2172 * Makefile.in: Regenerate.
ef1ad42b 2173 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2174 * configure: Regenerate.
ef1ad42b 2175
82704155
AM		 21762019-01-01 Alan Modra <amodra@gmail.com>
2177
2178 Update year range in copyright notice of all files.
2179
d5c04e1b 2180For older changes see ChangeLog-2018
3499769a 2181\f
d5c04e1b 2182Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2183
2184Copying and distribution of this file, with or without modification,
2185are permitted in any medium without royalty provided the copyright
2186notice and this notice are preserved.
2187
2188Local Variables:
2189mode: change-log
2190left-margin: 8
2191fill-column: 74
2192version-control: never
2193End:
GDB Binutils - Deliverables
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