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Add new mnemonics for VLE multiple load instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d2e6c9a3
AF		 12017-10-01 Alexander Fedotov <alfedotov@gmail.com>
2
3 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
4 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
5 VLE multimple load/store instructions. Old e_ldm* variants are
6 kept as aliases.
7 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
8
8e43602e
NC		 92017-09-27 Nick Clifton <nickc@redhat.com>
10
11 PR 22179
12 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
13 names for the fmv.x.s and fmv.s.x instructions respectively.
14
58a0b827
NC		 152017-09-26 do <do@nerilex.org>
16
17 PR 22123
18 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
19 be used on CPUs that have emacs support.
20
57a024f4
SDJ		 212017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
22
23 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
24
4ec521f2
KLC		 252017-09-09 Kamil Rytarowski <n54@gmx.com>
26
27 * nds32-asm.c: Rename __BIT() to N32_BIT().
28 * nds32-asm.h: Likewise.
29 * nds32-dis.c: Likewise.
30
4e9ac44a
L		 312017-09-09 H.J. Lu <hongjiu.lu@intel.com>
32
33 * i386-dis.c (last_active_prefix): Removed.
34 (ckprefix): Don't set last_active_prefix.
35 (NOTRACK_Fixup): Don't check last_active_prefix.
36
b55f3386
NC		 372017-08-31 Nick Clifton <nickc@redhat.com>
38
39 * po/fr.po: Updated French translation.
40
59e8523b
JB		 412017-08-31 James Bowman <james.bowman@ftdichip.com>
42
43 * ft32-dis.c (print_insn_ft32): Correct display of non-address
44 fields.
45
74081948
AF		 462017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
47 Edmar Wienskoski <edmar.wienskoski@nxp.com>
48
49 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
50 PPC_OPCODE_EFS2 flag to "e200z4" entry.
51 New entries efs2 and spe2.
52 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
53 (SPE2_OPCD_SEGS): New macro.
54 (spe2_opcd_indices): New.
55 (disassemble_init_powerpc): Handle SPE2 opcodes.
56 (lookup_spe2): New function.
57 (print_insn_powerpc): call lookup_spe2.
58 * ppc-opc.c (insert_evuimm1_ex0): New function.
59 (extract_evuimm1_ex0): Likewise.
60 (insert_evuimm_lt8): Likewise.
61 (extract_evuimm_lt8): Likewise.
62 (insert_off_spe2): Likewise.
63 (extract_off_spe2): Likewise.
64 (insert_Ddd): Likewise.
65 (extract_Ddd): Likewise.
66 (DD): New operand.
67 (EVUIMM_LT8): Likewise.
68 (EVUIMM_LT16): Adjust.
69 (MMMM): New operand.
70 (EVUIMM_1): Likewise.
71 (EVUIMM_1_EX0): Likewise.
72 (EVUIMM_2): Adjust.
73 (NNN): New operand.
74 (VX_OFF_SPE2): Likewise.
75 (BBB): Likewise.
76 (DDD): Likewise.
77 (VX_MASK_DDD): New mask.
78 (HH): New operand.
79 (VX_RA_CONST): New macro.
80 (VX_RA_CONST_MASK): Likewise.
81 (VX_RB_CONST): Likewise.
82 (VX_RB_CONST_MASK): Likewise.
83 (VX_OFF_SPE2_MASK): Likewise.
84 (VX_SPE_CRFD): Likewise.
85 (VX_SPE_CRFD_MASK VX): Likewise.
86 (VX_SPE2_CLR): Likewise.
87 (VX_SPE2_CLR_MASK): Likewise.
88 (VX_SPE2_SPLATB): Likewise.
89 (VX_SPE2_SPLATB_MASK): Likewise.
90 (VX_SPE2_OCTET): Likewise.
91 (VX_SPE2_OCTET_MASK): Likewise.
92 (VX_SPE2_DDHH): Likewise.
93 (VX_SPE2_DDHH_MASK): Likewise.
94 (VX_SPE2_HH): Likewise.
95 (VX_SPE2_HH_MASK): Likewise.
96 (VX_SPE2_EVMAR): Likewise.
97 (VX_SPE2_EVMAR_MASK): Likewise.
98 (PPCSPE2): Likewise.
99 (PPCEFS2): Likewise.
100 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
101 (powerpc_macros): Map old SPE instructions have new names
102 with the same opcodes. Add SPE2 instructions which just are
103 mapped to SPE2.
104 (spe2_opcodes): Add SPE2 opcodes.
105
b80c7270
AM		 1062017-08-23 Alan Modra <amodra@gmail.com>
107
108 * ppc-opc.c: Formatting and comment fixes. Move insert and
109 extract functions earlier, deleting forward declarations.
110 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
111 RA_MASK.
112
67d888f5
PD		 1132017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
114
115 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
116
e3c2f928
AF		 1172017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
118 Edmar Wienskoski <edmar.wienskoski@nxp.com>
119
120 * ppc-opc.c (insert_evuimm2_ex0): New function.
121 (extract_evuimm2_ex0): Likewise.
122 (insert_evuimm4_ex0): Likewise.
123 (extract_evuimm4_ex0): Likewise.
124 (insert_evuimm8_ex0): Likewise.
125 (extract_evuimm8_ex0): Likewise.
126 (insert_evuimm_lt16): Likewise.
127 (extract_evuimm_lt16): Likewise.
128 (insert_rD_rS_even): Likewise.
129 (extract_rD_rS_even): Likewise.
130 (insert_off_lsp): Likewise.
131 (extract_off_lsp): Likewise.
132 (RD_EVEN): New operand.
133 (RS_EVEN): Likewise.
134 (RSQ): Adjust.
135 (EVUIMM_LT16): New operand.
136 (HTM_SI): Adjust.
137 (EVUIMM_2_EX0): New operand.
138 (EVUIMM_4): Adjust.
139 (EVUIMM_4_EX0): New operand.
140 (EVUIMM_8): Adjust.
141 (EVUIMM_8_EX0): New operand.
142 (WS): Adjust.
143 (VX_OFF): New operand.
144 (VX_LSP): New macro.
145 (VX_LSP_MASK): Likewise.
146 (VX_LSP_OFF_MASK): Likewise.
147 (PPC_OPCODE_LSP): Likewise.
148 (vle_opcodes): Add LSP opcodes.
149 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
150
cc4a945a
JW		 1512017-08-09 Jiong Wang <jiong.wang@arm.com>
152
153 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
154 register operands in CRC instructions.
155 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
156 comments.
157
b28b8b5e
L		 1582017-08-07 H.J. Lu <hongjiu.lu@intel.com>
159
160 * disassemble.c (disassembler): Mark big and mach with
161 ATTRIBUTE_UNUSED.
162
e347efc3
MR		 1632017-08-07 Maciej W. Rozycki <macro@imgtec.com>
164
165 * disassemble.c (disassembler): Remove arch/mach/endian
166 assertions.
167
7cbc739c
NC		 1682017-07-25 Nick Clifton <nickc@redhat.com>
169
170 PR 21739
171 * arc-opc.c (insert_rhv2): Use lower case first letter in error
172 message.
173 (insert_r0): Likewise.
174 (insert_r1): Likewise.
175 (insert_r2): Likewise.
176 (insert_r3): Likewise.
177 (insert_sp): Likewise.
178 (insert_gp): Likewise.
179 (insert_pcl): Likewise.
180 (insert_blink): Likewise.
181 (insert_ilink1): Likewise.
182 (insert_ilink2): Likewise.
183 (insert_ras): Likewise.
184 (insert_rbs): Likewise.
185 (insert_rcs): Likewise.
186 (insert_simm3s): Likewise.
187 (insert_rrange): Likewise.
188 (insert_r13el): Likewise.
189 (insert_fpel): Likewise.
190 (insert_blinkel): Likewise.
191 (insert_pclel): Likewise.
192 (insert_nps_bitop_size_2b): Likewise.
193 (insert_nps_imm_offset): Likewise.
194 (insert_nps_imm_entry): Likewise.
195 (insert_nps_size_16bit): Likewise.
196 (insert_nps_##NAME##_pos): Likewise.
197 (insert_nps_##NAME): Likewise.
198 (insert_nps_bitop_ins_ext): Likewise.
199 (insert_nps_##NAME): Likewise.
200 (insert_nps_min_hofs): Likewise.
201 (insert_nps_##NAME): Likewise.
202 (insert_nps_rbdouble_64): Likewise.
203 (insert_nps_misc_imm_offset): Likewise.
204 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
205 option description.
206
7684e580
JW		 2072017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
208 Jiong Wang <jiong.wang@arm.com>
209
210 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
211 correct the print.
212 * aarch64-dis-2.c: Regenerated.
213
47826cdb
AK		 2142017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
215
216 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
217 table.
218
2d2dbad0
NC		 2192017-07-20 Nick Clifton <nickc@redhat.com>
220
221 * po/de.po: Updated German translation.
222
70b448ba 2232017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
224
225 * arc-regs.h (sec_stat): New aux register.
226 (aux_kernel_sp): Likewise.
227 (aux_sec_u_sp): Likewise.
228 (aux_sec_k_sp): Likewise.
229 (sec_vecbase_build): Likewise.
230 (nsc_table_top): Likewise.
231 (nsc_table_base): Likewise.
232 (ersec_stat): Likewise.
233 (aux_sec_except): Likewise.
234
7179e0e6
CZ		 2352017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
236
237 * arc-opc.c (extract_uimm12_20): New function.
238 (UIMM12_20): New operand.
239 (SIMM3_5_S): Adjust.
240 * arc-tbl.h (sjli): Add new instruction.
241
684d5a10
JEM		 2422017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
243 John Eric Martin <John.Martin@emmicro-us.com>
244
245 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
246 (UIMM3_23): Adjust accordingly.
247 * arc-regs.h: Add/correct jli_base register.
248 * arc-tbl.h (jli_s): Likewise.
249
de194d85
YC		 2502017-07-18 Nick Clifton <nickc@redhat.com>
251
252 PR 21775
253 * aarch64-opc.c: Fix spelling typos.
254 * i386-dis.c: Likewise.
255
0f6329bd
RB		 2562017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
257
258 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
259 max_addr_offset and octets variables to size_t.
260
429d795d
AM		 2612017-07-12 Alan Modra <amodra@gmail.com>
262
263 * po/da.po: Update from translationproject.org/latest/opcodes/.
264 * po/de.po: Likewise.
265 * po/es.po: Likewise.
266 * po/fi.po: Likewise.
267 * po/fr.po: Likewise.
268 * po/id.po: Likewise.
269 * po/it.po: Likewise.
270 * po/nl.po: Likewise.
271 * po/pt_BR.po: Likewise.
272 * po/ro.po: Likewise.
273 * po/sv.po: Likewise.
274 * po/tr.po: Likewise.
275 * po/uk.po: Likewise.
276 * po/vi.po: Likewise.
277 * po/zh_CN.po: Likewise.
278
4162bb66
AM		 2792017-07-11 Yao Qi <yao.qi@linaro.org>
280 Alan Modra <amodra@gmail.com>
281
282 * cgen.sh: Mark generated files read-only.
283 * epiphany-asm.c: Regenerate.
284 * epiphany-desc.c: Regenerate.
285 * epiphany-desc.h: Regenerate.
286 * epiphany-dis.c: Regenerate.
287 * epiphany-ibld.c: Regenerate.
288 * epiphany-opc.c: Regenerate.
289 * epiphany-opc.h: Regenerate.
290 * fr30-asm.c: Regenerate.
291 * fr30-desc.c: Regenerate.
292 * fr30-desc.h: Regenerate.
293 * fr30-dis.c: Regenerate.
294 * fr30-ibld.c: Regenerate.
295 * fr30-opc.c: Regenerate.
296 * fr30-opc.h: Regenerate.
297 * frv-asm.c: Regenerate.
298 * frv-desc.c: Regenerate.
299 * frv-desc.h: Regenerate.
300 * frv-dis.c: Regenerate.
301 * frv-ibld.c: Regenerate.
302 * frv-opc.c: Regenerate.
303 * frv-opc.h: Regenerate.
304 * ip2k-asm.c: Regenerate.
305 * ip2k-desc.c: Regenerate.
306 * ip2k-desc.h: Regenerate.
307 * ip2k-dis.c: Regenerate.
308 * ip2k-ibld.c: Regenerate.
309 * ip2k-opc.c: Regenerate.
310 * ip2k-opc.h: Regenerate.
311 * iq2000-asm.c: Regenerate.
312 * iq2000-desc.c: Regenerate.
313 * iq2000-desc.h: Regenerate.
314 * iq2000-dis.c: Regenerate.
315 * iq2000-ibld.c: Regenerate.
316 * iq2000-opc.c: Regenerate.
317 * iq2000-opc.h: Regenerate.
318 * lm32-asm.c: Regenerate.
319 * lm32-desc.c: Regenerate.
320 * lm32-desc.h: Regenerate.
321 * lm32-dis.c: Regenerate.
322 * lm32-ibld.c: Regenerate.
323 * lm32-opc.c: Regenerate.
324 * lm32-opc.h: Regenerate.
325 * lm32-opinst.c: Regenerate.
326 * m32c-asm.c: Regenerate.
327 * m32c-desc.c: Regenerate.
328 * m32c-desc.h: Regenerate.
329 * m32c-dis.c: Regenerate.
330 * m32c-ibld.c: Regenerate.
331 * m32c-opc.c: Regenerate.
332 * m32c-opc.h: Regenerate.
333 * m32r-asm.c: Regenerate.
334 * m32r-desc.c: Regenerate.
335 * m32r-desc.h: Regenerate.
336 * m32r-dis.c: Regenerate.
337 * m32r-ibld.c: Regenerate.
338 * m32r-opc.c: Regenerate.
339 * m32r-opc.h: Regenerate.
340 * m32r-opinst.c: Regenerate.
341 * mep-asm.c: Regenerate.
342 * mep-desc.c: Regenerate.
343 * mep-desc.h: Regenerate.
344 * mep-dis.c: Regenerate.
345 * mep-ibld.c: Regenerate.
346 * mep-opc.c: Regenerate.
347 * mep-opc.h: Regenerate.
348 * mt-asm.c: Regenerate.
349 * mt-desc.c: Regenerate.
350 * mt-desc.h: Regenerate.
351 * mt-dis.c: Regenerate.
352 * mt-ibld.c: Regenerate.
353 * mt-opc.c: Regenerate.
354 * mt-opc.h: Regenerate.
355 * or1k-asm.c: Regenerate.
356 * or1k-desc.c: Regenerate.
357 * or1k-desc.h: Regenerate.
358 * or1k-dis.c: Regenerate.
359 * or1k-ibld.c: Regenerate.
360 * or1k-opc.c: Regenerate.
361 * or1k-opc.h: Regenerate.
362 * or1k-opinst.c: Regenerate.
363 * xc16x-asm.c: Regenerate.
364 * xc16x-desc.c: Regenerate.
365 * xc16x-desc.h: Regenerate.
366 * xc16x-dis.c: Regenerate.
367 * xc16x-ibld.c: Regenerate.
368 * xc16x-opc.c: Regenerate.
369 * xc16x-opc.h: Regenerate.
370 * xstormy16-asm.c: Regenerate.
371 * xstormy16-desc.c: Regenerate.
372 * xstormy16-desc.h: Regenerate.
373 * xstormy16-dis.c: Regenerate.
374 * xstormy16-ibld.c: Regenerate.
375 * xstormy16-opc.c: Regenerate.
376 * xstormy16-opc.h: Regenerate.
377
7639175c
AM		 3782017-07-07 Alan Modra <amodra@gmail.com>
379
380 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
381 * m32c-dis.c: Regenerate.
382 * mep-dis.c: Regenerate.
383
e4bdd679
BP		 3842017-07-05 Borislav Petkov <bp@suse.de>
385
386 * i386-dis.c: Enable ModRM.reg /6 aliases.
387
60c96dbf
RR		 3882017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
389
390 * opcodes/arm-dis.c: Support MVFR2 in disassembly
391 with vmrs and vmsr.
392
0d702cfe
TG		 3932017-07-04 Tristan Gingold <gingold@adacore.com>
394
395 * configure: Regenerate.
396
15e6ed8c
TG		 3972017-07-03 Tristan Gingold <gingold@adacore.com>
398
399 * po/opcodes.pot: Regenerate.
400
b1d3c886
MR		 4012017-06-30 Maciej W. Rozycki <macro@imgtec.com>
402
403 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
404 entries to the MSA ASE instruction block.
405
909b4e3d
MR		 4062017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
407 Maciej W. Rozycki <macro@imgtec.com>
408
409 * micromips-opc.c (XPA, XPAVZ): New macros.
410 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
411 "mthgc0".
412
f5b2fd52
MR		 4132017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
414 Maciej W. Rozycki <macro@imgtec.com>
415
416 * micromips-opc.c (I36): New macro.
417 (micromips_opcodes): Add "eretnc".
418
9785fc2a
MR		 4192017-06-30 Maciej W. Rozycki <macro@imgtec.com>
420 Andrew Bennett <andrew.bennett@imgtec.com>
421
422 * mips-dis.c (mips_calculate_combination_ases): Handle the
423 ASE_XPA_VIRT flag.
424 (parse_mips_ase_option): New function.
425 (parse_mips_dis_option): Factor out ASE option handling to the
426 new function. Call `mips_calculate_combination_ases'.
427 * mips-opc.c (XPAVZ): New macro.
428 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
429 "mfhgc0", "mthc0" and "mthgc0".
430
60804c53
MR		 4312017-06-29 Maciej W. Rozycki <macro@imgtec.com>
432
433 * mips-dis.c (mips_calculate_combination_ases): New function.
434 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
435 calculation to the new function.
436 (set_default_mips_dis_options): Call the new function.
437
2e74f9dd
AK		 4382017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
439
440 * arc-dis.c (parse_disassembler_options): Use
441 FOR_EACH_DISASSEMBLER_OPTION.
442
e1e94c49
AK		 4432017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
444
445 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
446 disassembler option strings.
447 (parse_cpu_option): Likewise.
448
65a55fbb
TC		 4492017-06-28 Tamar Christina <tamar.christina@arm.com>
450
451 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
452 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
453 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
454 (aarch64_feature_dotprod, DOT_INSN): New.
455 (udot, sdot): New.
456 * aarch64-dis-2.c: Regenerated.
457
c604a79a
JW		 4582017-06-28 Jiong Wang <jiong.wang@arm.com>
459
460 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
461
38bf472a
MR		 4622017-06-28 Maciej W. Rozycki <macro@imgtec.com>
463 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 464 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 465
466 * mips-formats.h (INT_BIAS): New macro.
467 (INT_ADJ): Redefine in INT_BIAS terms.
468 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
469 (mips_print_save_restore): New function.
470 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
471 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
472 call.
473 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
474 (print_mips16_insn_arg): Call `mips_print_save_restore' for
475 OP_SAVE_RESTORE_LIST handling, factored out from here.
476 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
477 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
478 (mips_builtin_opcodes): Add "restore" and "save" entries.
479 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
480 (IAMR2): New macro.
481 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
482
9bdfdbf9
AW		 4832017-06-23 Andrew Waterman <andrew@sifive.com>
484
485 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
486 alias; do not mark SLTI instruction as an alias.
487
2234eee6
L		 4882017-06-21 H.J. Lu <hongjiu.lu@intel.com>
489
490 * i386-dis.c (RM_0FAE_REG_5): Removed.
491 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
492 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
493 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
494 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
495 PREFIX_MOD_3_0F01_REG_5_RM_0.
496 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
497 PREFIX_MOD_3_0FAE_REG_5.
498 (mod_table): Update MOD_0FAE_REG_5.
499 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
500 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
501 * i386-tbl.h: Regenerated.
502
c2f76402
L		 5032017-06-21 H.J. Lu <hongjiu.lu@intel.com>
504
505 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
506 * i386-opc.tbl: Likewise.
507 * i386-tbl.h: Regenerated.
508
9fef80d6
L		 5092017-06-21 H.J. Lu <hongjiu.lu@intel.com>
510
511 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
512 and "jmp{&|}".
513 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
514 prefix.
515
0f6d864d
NC		 5162017-06-19 Nick Clifton <nickc@redhat.com>
517
518 PR binutils/21614
519 * score-dis.c (score_opcodes): Add sentinel.
520
e197589b
AM		 5212017-06-16 Alan Modra <amodra@gmail.com>
522
523 * rx-decode.c: Regenerate.
524
0d96e4df
L		 5252017-06-15 H.J. Lu <hongjiu.lu@intel.com>
526
527 PR binutils/21594
528 * i386-dis.c (OP_E_register): Check valid bnd register.
529 (OP_G): Likewise.
530
cd3ea7c6
NC		 5312017-06-15 Nick Clifton <nickc@redhat.com>
532
533 PR binutils/21595
534 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
535 range value.
536
63323b5b
NC		 5372017-06-15 Nick Clifton <nickc@redhat.com>
538
539 PR binutils/21588
540 * rl78-decode.opc (OP_BUF_LEN): Define.
541 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
542 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
543 array.
544 * rl78-decode.c: Regenerate.
545
08c7881b
NC		 5462017-06-15 Nick Clifton <nickc@redhat.com>
547
548 PR binutils/21586
549 * bfin-dis.c (gregs): Clip index to prevent overflow.
550 (regs): Likewise.
551 (regs_lo): Likewise.
552 (regs_hi): Likewise.
553
e64519d1
NC		 5542017-06-14 Nick Clifton <nickc@redhat.com>
555
556 PR binutils/21576
557 * score7-dis.c (score_opcodes): Add sentinel.
558
6394c606
YQ		 5592017-06-14 Yao Qi <yao.qi@linaro.org>
560
561 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
562 * arm-dis.c: Likewise.
563 * ia64-dis.c: Likewise.
564 * mips-dis.c: Likewise.
565 * spu-dis.c: Likewise.
566 * disassemble.h (print_insn_aarch64): New declaration, moved from
567 include/dis-asm.h.
568 (print_insn_big_arm, print_insn_big_mips): Likewise.
569 (print_insn_i386, print_insn_ia64): Likewise.
570 (print_insn_little_arm, print_insn_little_mips): Likewise.
571
db5fa770
NC		 5722017-06-14 Nick Clifton <nickc@redhat.com>
573
574 PR binutils/21587
575 * rx-decode.opc: Include libiberty.h
576 (GET_SCALE): New macro - validates access to SCALE array.
577 (GET_PSCALE): New macro - validates access to PSCALE array.
578 (DIs, SIs, S2Is, rx_disp): Use new macros.
579 * rx-decode.c: Regenerate.
580
05c966f3
AV		 5812017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
582
583 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
584
10045478
AK		 5852017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
586
587 * arc-dis.c (enforced_isa_mask): Declare.
588 (cpu_types): Likewise.
589 (parse_cpu_option): New function.
590 (parse_disassembler_options): Use it.
591 (print_insn_arc): Use enforced_isa_mask.
592 (print_arc_disassembler_options): Document new options.
593
88c1242d
YQ		 5942017-05-24 Yao Qi <yao.qi@linaro.org>
595
596 * alpha-dis.c: Include disassemble.h, don't include
597 dis-asm.h.
598 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
599 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
600 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
601 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
602 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
603 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
604 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
605 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
606 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
607 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
608 * moxie-dis.c, msp430-dis.c, mt-dis.c:
609 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
610 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
611 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
612 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
613 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
614 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
615 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
616 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
617 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
618 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
619 * z80-dis.c, z8k-dis.c: Likewise.
620 * disassemble.h: New file.
621
ab20fa4a
YQ		 6222017-05-24 Yao Qi <yao.qi@linaro.org>
623
624 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
625 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
626
003ca0fd
YQ		 6272017-05-24 Yao Qi <yao.qi@linaro.org>
628
629 * disassemble.c (disassembler): Add arguments a, big and mach.
630 Use them.
631
04ef582a
L		 6322017-05-22 H.J. Lu <hongjiu.lu@intel.com>
633
634 * i386-dis.c (NOTRACK_Fixup): New.
635 (NOTRACK): Likewise.
636 (NOTRACK_PREFIX): Likewise.
637 (last_active_prefix): Likewise.
638 (reg_table): Use NOTRACK on indirect call and jmp.
639 (ckprefix): Set last_active_prefix.
640 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
641 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
642 * i386-opc.h (NoTrackPrefixOk): New.
643 (i386_opcode_modifier): Add notrackprefixok.
644 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
645 Add notrack.
646 * i386-tbl.h: Regenerated.
647
64517994
JM		 6482017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
649
650 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
651 (X_IMM2): Define.
652 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
653 bfd_mach_sparc_v9m8.
654 (print_insn_sparc): Handle new operand types.
655 * sparc-opc.c (MASK_M8): Define.
656 (v6): Add MASK_M8.
657 (v6notlet): Likewise.
658 (v7): Likewise.
659 (v8): Likewise.
660 (v9): Likewise.
661 (v9a): Likewise.
662 (v9b): Likewise.
663 (v9c): Likewise.
664 (v9d): Likewise.
665 (v9e): Likewise.
666 (v9v): Likewise.
667 (v9m): Likewise.
668 (v9andleon): Likewise.
669 (m8): Define.
670 (HWS_VM8): Define.
671 (HWS2_VM8): Likewise.
672 (sparc_opcode_archs): Add entry for "m8".
673 (sparc_opcodes): Add OSA2017 and M8 instructions
674 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
675 fpx{ll,ra,rl}64x,
676 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
677 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
678 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
679 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
680 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
681 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
682 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
683 ASI_CORE_SELECT_COMMIT_NHT.
684
535b785f
AM		 6852017-05-18 Alan Modra <amodra@gmail.com>
686
687 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
688 * aarch64-dis.c: Likewise.
689 * aarch64-gen.c: Likewise.
690 * aarch64-opc.c: Likewise.
691
25499ac7
MR		 6922017-05-15 Maciej W. Rozycki <macro@imgtec.com>
693 Matthew Fortune <matthew.fortune@imgtec.com>
694
695 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
696 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
697 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
698 (print_insn_arg) <OP_REG28>: Add handler.
699 (validate_insn_args) <OP_REG28>: Handle.
700 (print_mips16_insn_arg): Handle MIPS16 instructions that require
701 32-bit encoding and 9-bit immediates.
702 (print_insn_mips16): Handle MIPS16 instructions that require
703 32-bit encoding and MFC0/MTC0 operand decoding.
704 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
705 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
706 (RD_C0, WR_C0, E2, E2MT): New macros.
707 (mips16_opcodes): Add entries for MIPS16e2 instructions:
708 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
709 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
710 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
711 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
712 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
713 instructions, "swl", "swr", "sync" and its "sync_acquire",
714 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
715 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
716 regular/extended entries for original MIPS16 ISA revision
717 instructions whose extended forms are subdecoded in the MIPS16e2
718 ISA revision: "li", "sll" and "srl".
719
fdfb4752
MR		 7202017-05-15 Maciej W. Rozycki <macro@imgtec.com>
721
722 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
723 reference in CP0 move operand decoding.
724
a4f89915
MR		 7252017-05-12 Maciej W. Rozycki <macro@imgtec.com>
726
727 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
728 type to hexadecimal.
729 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
730
99e2d67a
MR		 7312017-05-11 Maciej W. Rozycki <macro@imgtec.com>
732
733 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
734 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
735 "sync_rmb" and "sync_wmb" as aliases.
736 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
737 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
738
53a346d8
CZ		 7392017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
740
741 * arc-dis.c (parse_option): Update quarkse_em option..
742 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
743 QUARKSE1.
744 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
745
f91d48de
KC		 7462017-05-03 Kito Cheng <kito.cheng@gmail.com>
747
748 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
749
43e379d7
MC		 7502017-05-01 Michael Clark <michaeljclark@mac.com>
751
752 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
753 register.
754
a4ddc54e
MR		 7552017-05-02 Maciej W. Rozycki <macro@imgtec.com>
756
757 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
758 and branches and not synthetic data instructions.
759
fe50e98c
BE		 7602017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
761
762 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
763
126124cc
CZ		 7642017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
765
766 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
767 * arc-opc.c (insert_r13el): New function.
768 (R13_EL): Define.
769 * arc-tbl.h: Add new enter/leave variants.
770
be6a24d8
CZ		 7712017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
772
773 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
774
0348fd79
MR		 7752017-04-25 Maciej W. Rozycki <macro@imgtec.com>
776
777 * mips-dis.c (print_mips_disassembler_options): Add
778 `no-aliases'.
779
6e3d1f07
MR		 7802017-04-25 Maciej W. Rozycki <macro@imgtec.com>
781
782 * mips16-opc.c (AL): New macro.
783 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
784 of "ld" and "lw" as aliases.
785
957f6b39
TC		 7862017-04-24 Tamar Christina <tamar.christina@arm.com>
787
788 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
789 arguments.
790
a8cc8a54
AM		 7912017-04-22 Alexander Fedotov <alfedotov@gmail.com>
792 Alan Modra <amodra@gmail.com>
793
794 * ppc-opc.c (ELEV): Define.
795 (vle_opcodes): Add se_rfgi and e_sc.
796 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
797 for E200Z4.
798
3ab87b68
JM		 7992017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
800
801 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
802
792f174f
NC		 8032017-04-21 Nick Clifton <nickc@redhat.com>
804
805 PR binutils/21380
806 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
807 LD3R and LD4R.
808
42742084
AM		 8092017-04-13 Alan Modra <amodra@gmail.com>
810
811 * epiphany-desc.c: Regenerate.
812 * fr30-desc.c: Regenerate.
813 * frv-desc.c: Regenerate.
814 * ip2k-desc.c: Regenerate.
815 * iq2000-desc.c: Regenerate.
816 * lm32-desc.c: Regenerate.
817 * m32c-desc.c: Regenerate.
818 * m32r-desc.c: Regenerate.
819 * mep-desc.c: Regenerate.
820 * mt-desc.c: Regenerate.
821 * or1k-desc.c: Regenerate.
822 * xc16x-desc.c: Regenerate.
823 * xstormy16-desc.c: Regenerate.
824
9a85b496
AM		 8252017-04-11 Alan Modra <amodra@gmail.com>
826
ef85eab0 827 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 828 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
829 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 830 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
831 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 832 (PPCVSX2): Define as PPC_OPCODE_POWER8.
833 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 834 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 835 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 836
62adc510
AM		 8372017-04-10 Alan Modra <amodra@gmail.com>
838
839 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
840 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
841 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
842 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
843
aa808707
PC		 8442017-04-09 Pip Cet <pipcet@gmail.com>
845
846 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
847 appropriate floating-point precision directly.
848
ac8f0f72
AM		 8492017-04-07 Alan Modra <amodra@gmail.com>
850
851 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
852 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
853 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
854 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
855 vector instructions with E6500 not PPCVEC2.
856
62ecb94c
PC		 8572017-04-06 Pip Cet <pipcet@gmail.com>
858
859 * Makefile.am: Add wasm32-dis.c.
860 * configure.ac: Add wasm32-dis.c to wasm32 target.
861 * disassemble.c: Add wasm32 disassembler code.
862 * wasm32-dis.c: New file.
863 * Makefile.in: Regenerate.
864 * configure: Regenerate.
865 * po/POTFILES.in: Regenerate.
866 * po/opcodes.pot: Regenerate.
867
f995bbe8
PA		 8682017-04-05 Pedro Alves <palves@redhat.com>
869
870 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
871 * arm-dis.c (parse_arm_disassembler_options): Constify.
872 * ppc-dis.c (powerpc_init_dialect): Constify local.
873 * vax-dis.c (parse_disassembler_options): Constify.
874
b5292032
PD		 8752017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
876
877 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
878 RISCV_GP_SYMBOL.
879
f96bd6c2
PC		 8802017-03-30 Pip Cet <pipcet@gmail.com>
881
882 * configure.ac: Add (empty) bfd_wasm32_arch target.
883 * configure: Regenerate
884 * po/opcodes.pot: Regenerate.
885
f7c514a3
JM		 8862017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
887
888 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
889 OSA2015.
890 * opcodes/sparc-opc.c (asi_table): New ASIs.
891
52be03fd
AM		 8922017-03-29 Alan Modra <amodra@gmail.com>
893
894 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
895 "raw" option.
896 (lookup_powerpc): Don't special case -1 dialect. Handle
897 PPC_OPCODE_RAW.
898 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
899 lookup_powerpc call, pass it on second.
900
9b753937
AM		 9012017-03-27 Alan Modra <amodra@gmail.com>
902
903 PR 21303
904 * ppc-dis.c (struct ppc_mopt): Comment.
905 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
906
c0c31e91
RZ		 9072017-03-27 Rinat Zelig <rinat@mellanox.com>
908
909 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
910 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
911 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
912 (insert_nps_misc_imm_offset): New function.
913 (extract_nps_misc imm_offset): New function.
914 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
915 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
916
2253c8f0
AK		 9172017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
918
919 * s390-mkopc.c (main): Remove vx2 check.
920 * s390-opc.txt: Remove vx2 instruction flags.
921
645d3342
RZ		 9222017-03-21 Rinat Zelig <rinat@mellanox.com>
923
924 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
925 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
926 (insert_nps_imm_offset): New function.
927 (extract_nps_imm_offset): New function.
928 (insert_nps_imm_entry): New function.
929 (extract_nps_imm_entry): New function.
930
4b94dd2d
AM		 9312017-03-17 Alan Modra <amodra@gmail.com>
932
933 PR 21248
934 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
935 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
936 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
937
b416fe87
KC		 9382017-03-14 Kito Cheng <kito.cheng@gmail.com>
939
940 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
941 <c.andi>: Likewise.
942 <c.addiw> Likewise.
943
03b039a5
KC		 9442017-03-14 Kito Cheng <kito.cheng@gmail.com>
945
946 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
947
2c232b83
AW		 9482017-03-13 Andrew Waterman <andrew@sifive.com>
949
950 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
951 <srl> Likewise.
952 <srai> Likewise.
953 <sra> Likewise.
954
86fa6981
L		 9552017-03-09 H.J. Lu <hongjiu.lu@intel.com>
956
957 * i386-gen.c (opcode_modifiers): Replace S with Load.
958 * i386-opc.h (S): Removed.
959 (Load): New.
960 (i386_opcode_modifier): Replace s with load.
961 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
962 and {evex}. Replace S with Load.
963 * i386-tbl.h: Regenerated.
964
c1fe188b
L		 9652017-03-09 H.J. Lu <hongjiu.lu@intel.com>
966
967 * i386-opc.tbl: Use CpuCET on rdsspq.
968 * i386-tbl.h: Regenerated.
969
4b8b687e
PB		 9702017-03-08 Peter Bergner <bergner@vnet.ibm.com>
971
972 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
973 <vsx>: Do not use PPC_OPCODE_VSX3;
974
1437d063
PB		 9752017-03-08 Peter Bergner <bergner@vnet.ibm.com>
976
977 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
978
603555e5
L		 9792017-03-06 H.J. Lu <hongjiu.lu@intel.com>
980
981 * i386-dis.c (REG_0F1E_MOD_3): New enum.
982 (MOD_0F1E_PREFIX_1): Likewise.
983 (MOD_0F38F5_PREFIX_2): Likewise.
984 (MOD_0F38F6_PREFIX_0): Likewise.
985 (RM_0F1E_MOD_3_REG_7): Likewise.
986 (PREFIX_MOD_0_0F01_REG_5): Likewise.
987 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
988 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
989 (PREFIX_0F1E): Likewise.
990 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
991 (PREFIX_0F38F5): Likewise.
992 (dis386_twobyte): Use PREFIX_0F1E.
993 (reg_table): Add REG_0F1E_MOD_3.
994 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
995 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
996 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
997 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
998 (three_byte_table): Use PREFIX_0F38F5.
999 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1000 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1001 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1002 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1003 PREFIX_MOD_3_0F01_REG_5_RM_2.
1004 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1005 (cpu_flags): Add CpuCET.
1006 * i386-opc.h (CpuCET): New enum.
1007 (CpuUnused): Commented out.
1008 (i386_cpu_flags): Add cpucet.
1009 * i386-opc.tbl: Add Intel CET instructions.
1010 * i386-init.h: Regenerated.
1011 * i386-tbl.h: Likewise.
1012
73f07bff
AM		 10132017-03-06 Alan Modra <amodra@gmail.com>
1014
1015 PR 21124
1016 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1017 (extract_raq, extract_ras, extract_rbx): New functions.
1018 (powerpc_operands): Use opposite corresponding insert function.
1019 (Q_MASK): Define.
1020 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1021 register restriction.
1022
65b48a81
PB		 10232017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1024
1025 * disassemble.c Include "safe-ctype.h".
1026 (disassemble_init_for_target): Handle s390 init.
1027 (remove_whitespace_and_extra_commas): New function.
1028 (disassembler_options_cmp): Likewise.
1029 * arm-dis.c: Include "libiberty.h".
1030 (NUM_ELEM): Delete.
1031 (regnames): Use long disassembler style names.
1032 Add force-thumb and no-force-thumb options.
1033 (NUM_ARM_REGNAMES): Rename from this...
1034 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1035 (get_arm_regname_num_options): Delete.
1036 (set_arm_regname_option): Likewise.
1037 (get_arm_regnames): Likewise.
1038 (parse_disassembler_options): Likewise.
1039 (parse_arm_disassembler_option): Rename from this...
1040 (parse_arm_disassembler_options): ...to this. Make static.
1041 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1042 (print_insn): Use parse_arm_disassembler_options.
1043 (disassembler_options_arm): New function.
1044 (print_arm_disassembler_options): Handle updated regnames.
1045 * ppc-dis.c: Include "libiberty.h".
1046 (ppc_opts): Add "32" and "64" entries.
1047 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1048 (powerpc_init_dialect): Add break to switch statement.
1049 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1050 (disassembler_options_powerpc): New function.
1051 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1052 Remove printing of "32" and "64".
1053 * s390-dis.c: Include "libiberty.h".
1054 (init_flag): Remove unneeded variable.
1055 (struct s390_options_t): New structure type.
1056 (options): New structure.
1057 (init_disasm): Rename from this...
1058 (disassemble_init_s390): ...to this. Add initializations for
1059 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1060 (print_insn_s390): Delete call to init_disasm.
1061 (disassembler_options_s390): New function.
1062 (print_s390_disassembler_options): Print using information from
1063 struct 'options'.
1064 * po/opcodes.pot: Regenerate.
1065
15c7c1d8
JB		 10662017-02-28 Jan Beulich <jbeulich@suse.com>
1067
1068 * i386-dis.c (PCMPESTR_Fixup): New.
1069 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1070 (prefix_table): Use PCMPESTR_Fixup.
1071 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1072 PCMPESTR_Fixup.
1073 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1074 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1075 Split 64-bit and non-64-bit variants.
1076 * opcodes/i386-tbl.h: Re-generate.
1077
582e12bf
RS		 10782017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1079
1080 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1081 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1082 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1083 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1084 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1085 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1086 (OP_SVE_V_HSD): New macros.
1087 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1088 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1089 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1090 (aarch64_opcode_table): Add new SVE instructions.
1091 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1092 for rotation operands. Add new SVE operands.
1093 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1094 (ins_sve_quad_index): Likewise.
1095 (ins_imm_rotate): Split into...
1096 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1097 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1098 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1099 functions.
1100 (aarch64_ins_sve_addr_ri_s4): New function.
1101 (aarch64_ins_sve_quad_index): Likewise.
1102 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1103 * aarch64-asm-2.c: Regenerate.
1104 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1105 (ext_sve_quad_index): Likewise.
1106 (ext_imm_rotate): Split into...
1107 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1108 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1109 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1110 functions.
1111 (aarch64_ext_sve_addr_ri_s4): New function.
1112 (aarch64_ext_sve_quad_index): Likewise.
1113 (aarch64_ext_sve_index): Allow quad indices.
1114 (do_misc_decoding): Likewise.
1115 * aarch64-dis-2.c: Regenerate.
1116 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1117 aarch64_field_kinds.
1118 (OPD_F_OD_MASK): Widen by one bit.
1119 (OPD_F_NO_ZR): Bump accordingly.
1120 (get_operand_field_width): New function.
1121 * aarch64-opc.c (fields): Add new SVE fields.
1122 (operand_general_constraint_met_p): Handle new SVE operands.
1123 (aarch64_print_operand): Likewise.
1124 * aarch64-opc-2.c: Regenerate.
1125
f482d304
RS		 11262017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1127
1128 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1129 (aarch64_feature_compnum): ...this.
1130 (SIMD_V8_3): Replace with...
1131 (COMPNUM): ...this.
1132 (CNUM_INSN): New macro.
1133 (aarch64_opcode_table): Use it for the complex number instructions.
1134
7db2c588
JB		 11352017-02-24 Jan Beulich <jbeulich@suse.com>
1136
1137 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1138
1e9d41d4
SL		 11392017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1140
1141 Add support for associating SPARC ASIs with an architecture level.
1142 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1143 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1144 decoding of SPARC ASIs.
1145
53c4d625
JB		 11462017-02-23 Jan Beulich <jbeulich@suse.com>
1147
1148 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1149 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1150
11648de5
JB		 11512017-02-21 Jan Beulich <jbeulich@suse.com>
1152
1153 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1154 1 (instead of to itself). Correct typo.
1155
f98d33be
AW		 11562017-02-14 Andrew Waterman <andrew@sifive.com>
1157
1158 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1159 pseudoinstructions.
1160
773fb663
RS		 11612017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1162
1163 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1164 (aarch64_sys_reg_supported_p): Handle them.
1165
cc07cda6
CZ		 11662017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1167
1168 * arc-opc.c (UIMM6_20R): Define.
1169 (SIMM12_20): Use above.
1170 (SIMM12_20R): Define.
1171 (SIMM3_5_S): Use above.
1172 (UIMM7_A32_11R_S): Define.
1173 (UIMM7_9_S): Use above.
1174 (UIMM3_13R_S): Define.
1175 (SIMM11_A32_7_S): Use above.
1176 (SIMM9_8R): Define.
1177 (UIMM10_A32_8_S): Use above.
1178 (UIMM8_8R_S): Define.
1179 (W6): Use above.
1180 (arc_relax_opcodes): Use all above defines.
1181
66a5a740
VG		 11822017-02-15 Vineet Gupta <vgupta@synopsys.com>
1183
1184 * arc-regs.h: Distinguish some of the registers different on
1185 ARC700 and HS38 cpus.
1186
7e0de605
AM		 11872017-02-14 Alan Modra <amodra@gmail.com>
1188
1189 PR 21118
1190 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1191 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1192
54064fdb
AM		 11932017-02-11 Stafford Horne <shorne@gmail.com>
1194 Alan Modra <amodra@gmail.com>
1195
1196 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1197 Use insn_bytes_value and insn_int_value directly instead. Don't
1198 free allocated memory until function exit.
1199
dce75bf9
NP		 12002017-02-10 Nicholas Piggin <npiggin@gmail.com>
1201
1202 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1203
1b7e3d2f
NC		 12042017-02-03 Nick Clifton <nickc@redhat.com>
1205
1206 PR 21096
1207 * aarch64-opc.c (print_register_list): Ensure that the register
1208 list index will fir into the tb buffer.
1209 (print_register_offset_address): Likewise.
1210 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1211
8ec5cf65
AD		 12122017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1213
1214 PR 21056
1215 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1216 instructions when the previous fetch packet ends with a 32-bit
1217 instruction.
1218
a1aa5e81
DD		 12192017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1220
1221 * pru-opc.c: Remove vague reference to a future GDB port.
1222
add3afb2
NC		 12232017-01-20 Nick Clifton <nickc@redhat.com>
1224
1225 * po/ga.po: Updated Irish translation.
1226
c13a63b0
SN		 12272017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1228
1229 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1230
9608051a
YQ		 12312017-01-13 Yao Qi <yao.qi@linaro.org>
1232
1233 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1234 if FETCH_DATA returns 0.
1235 (m68k_scan_mask): Likewise.
1236 (print_insn_m68k): Update code to handle -1 return value.
1237
f622ea96
YQ		 12382017-01-13 Yao Qi <yao.qi@linaro.org>
1239
1240 * m68k-dis.c (enum print_insn_arg_error): New.
1241 (NEXTBYTE): Replace -3 with
1242 PRINT_INSN_ARG_MEMORY_ERROR.
1243 (NEXTULONG): Likewise.
1244 (NEXTSINGLE): Likewise.
1245 (NEXTDOUBLE): Likewise.
1246 (NEXTDOUBLE): Likewise.
1247 (NEXTPACKED): Likewise.
1248 (FETCH_ARG): Likewise.
1249 (FETCH_DATA): Update comments.
1250 (print_insn_arg): Update comments. Replace magic numbers with
1251 enum.
1252 (match_insn_m68k): Likewise.
1253
620214f7
IT		 12542017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1255
1256 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1257 * i386-dis-evex.h (evex_table): Updated.
1258 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1259 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1260 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1261 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1262 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1263 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1264 * i386-init.h: Regenerate.
1265 * i386-tbl.h: Ditto.
1266
d95014a2
YQ		 12672017-01-12 Yao Qi <yao.qi@linaro.org>
1268
1269 * msp430-dis.c (msp430_singleoperand): Return -1 if
1270 msp430dis_opcode_signed returns false.
1271 (msp430_doubleoperand): Likewise.
1272 (msp430_branchinstr): Return -1 if
1273 msp430dis_opcode_unsigned returns false.
1274 (msp430x_calla_instr): Likewise.
1275 (print_insn_msp430): Likewise.
1276
0ae60c3e
NC		 12772017-01-05 Nick Clifton <nickc@redhat.com>
1278
1279 PR 20946
1280 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1281 could not be matched.
1282 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1283 NULL.
1284
d74d4880
SN		 12852017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1286
1287 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1288 (aarch64_opcode_table): Use RCPC_INSN.
1289
cc917fd9
KC		 12902017-01-03 Kito Cheng <kito.cheng@gmail.com>
1291
1292 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1293 extension.
1294 * riscv-opcodes/all-opcodes: Likewise.
1295
b52d3cfc
DP		 12962017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1297
1298 * riscv-dis.c (print_insn_args): Add fall through comment.
1299
f90c58d5
NC		 13002017-01-03 Nick Clifton <nickc@redhat.com>
1301
1302 * po/sr.po: New Serbian translation.
1303 * configure.ac (ALL_LINGUAS): Add sr.
1304 * configure: Regenerate.
1305
f47b0d4a
AM		 13062017-01-02 Alan Modra <amodra@gmail.com>
1307
1308 * epiphany-desc.h: Regenerate.
1309 * epiphany-opc.h: Regenerate.
1310 * fr30-desc.h: Regenerate.
1311 * fr30-opc.h: Regenerate.
1312 * frv-desc.h: Regenerate.
1313 * frv-opc.h: Regenerate.
1314 * ip2k-desc.h: Regenerate.
1315 * ip2k-opc.h: Regenerate.
1316 * iq2000-desc.h: Regenerate.
1317 * iq2000-opc.h: Regenerate.
1318 * lm32-desc.h: Regenerate.
1319 * lm32-opc.h: Regenerate.
1320 * m32c-desc.h: Regenerate.
1321 * m32c-opc.h: Regenerate.
1322 * m32r-desc.h: Regenerate.
1323 * m32r-opc.h: Regenerate.
1324 * mep-desc.h: Regenerate.
1325 * mep-opc.h: Regenerate.
1326 * mt-desc.h: Regenerate.
1327 * mt-opc.h: Regenerate.
1328 * or1k-desc.h: Regenerate.
1329 * or1k-opc.h: Regenerate.
1330 * xc16x-desc.h: Regenerate.
1331 * xc16x-opc.h: Regenerate.
1332 * xstormy16-desc.h: Regenerate.
1333 * xstormy16-opc.h: Regenerate.
1334
2571583a
AM		 13352017-01-02 Alan Modra <amodra@gmail.com>
1336
1337 Update year range in copyright notice of all files.
1338
5c1ad6b5 1339For older changes see ChangeLog-2016
3499769a 1340\f
5c1ad6b5 1341Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1342
1343Copying and distribution of this file, with or without modification,
1344are permitted in any medium without royalty provided the copyright
1345notice and this notice are preserved.
1346
1347Local Variables:
1348mode: change-log
1349left-margin: 8
1350fill-column: 74
1351version-control: never
1352End:
GDB Binutils - Deliverables
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