[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>

	* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.

2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c: Add comment accidentally removed by old commit.
	(MTMSRD_L): Delete.

2015-06-04  Nick Clifton  <nickc@redhat.com>

	PR 18474
	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (arm_opcodes): Add "setpan".
	(thumb_opcodes): Add "setpan".

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	macros.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_rdma): New.
	(RDMA): New.
	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_lor): New.
	(LOR): New.
	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	"stllrb", "stllrh".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-tbl.h: Regenerate.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.

2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (IH) New define.
	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	<tlbie>: Add RS operand for POWER7.
	<slbia>: Add IH operand for POWER6.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.

2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.

2015-04-30  DJ Delorie  <dj@redhat.com>

	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

2015-04-29  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_requirement): Removed.
	(print_insn): Don't set prefix_requirement.  Check
	dp->prefix_requirement instead of prefix_requirement.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	(PREFIX_MANDATORY_REPNZ): Likewise.
	(PREFIX_MANDATORY_DATA): Likewise.
	(PREFIX_MANDATORY_ADDR): Likewise.
	(PREFIX_MANDATORY_LOCK): Likewise.
	(PREFIX_MANDATORY): Likewise.
	(PREFIX_UD_SHIFT): Set to 8
	(PREFIX_UD_REPZ): Updated.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
	(PREFIX_IGNORED_SHIFT): New.
	(PREFIX_IGNORED_REPZ): Likewise.
	(PREFIX_IGNORED_REPNZ): Likewise.
	(PREFIX_IGNORED_DATA): Likewise.
	(PREFIX_IGNORED_ADDR): Likewise.
	(PREFIX_IGNORED_LOCK): Likewise.
	(PREFIX_OPCODE): Likewise.
	(PREFIX_IGNORED): Likewise.
	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	(three_byte_table): Likewise.
	(mod_table): Likewise.
	(mandatory_prefix): Renamed to ...
	(prefix_requirement): This.
	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	Update PREFIX_90 entry.
	(get_valid_dis386): Check prefix_requirement to see if a prefix
	should be ignored.
	(print_insn): Replace mandatory_prefix with prefix_requirement.

2015-04-15  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	use it for ssat and ssat16.
	(print_insn_thumb32): Add handle case for 'D' control code.

2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	Fill prefix_requirement field.
	(struct dis386): Add prefix_requirement field.
	(dis386): Fill prefix_requirement field.
	(dis386_twobyte): Ditto.
	(twobyte_has_mandatory_prefix_: Remove.
	(reg_table): Fill prefix_requirement field.
	(prefix_table): Ditto.
	(x86_64_table): Ditto.
	(three_byte_table): Ditto.
	(xop_table): Ditto.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(bad_opcode): Ditto.
	(print_insn): Use prefix_requirement.
	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	(float_reg): Ditto.

2015-03-30  Mike Frysinger  <vapier@gentoo.org>

	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.

2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	powerpc_opcd_indices and vle_opcd_indices once.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c (powerpc_opcodes): Add slbfee.

2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.

2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>

	* i386-dis.c (rm_table): Add clzero.
	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	Add CPU_CLZERO_FLAGS.
	(cpu_flags): Add CpuCLZERO.
	* i386-opc.h: Add CpuCLZERO.
	* i386-opc.tbl: Add clzero.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2015-03-03  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>

	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

2015-02-23  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.

2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".

2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.

2015-01-28  James Bowman  <james.bowman@ftdichip.com>

	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* nds32-asm.c (keyword_sr): Add new system registers.

2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.

2015-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2014
\f
Copyright (C) 2015 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
bdfa8b95 MW	1	2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
	2
	3	* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
	4
24b4cf66 SN	5	2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
	6
	7	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
	8
99a2c561 PB	9	2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
	10
	11	* ppc-opc.c: Add comment accidentally removed by old commit.
	12	(MTMSRD_L): Delete.
	13
13be46a2 NC	14	2015-06-04 Nick Clifton <nickc@redhat.com>
	15
	16	PR 18474
	17	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
	18
ddfded2f MW	19	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	20
	21	* arm-dis.c (arm_opcodes): Add "setpan".
	22	(thumb_opcodes): Add "setpan".
	23
1af1dd51 MW	24	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	25
	26	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	27	macros.
	28
9e1f0fa7 MW	29	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	30
	31	* aarch64-tbl.h (aarch64_feature_rdma): New.
	32	(RDMA): New.
	33	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	34	* aarch64-asm-2.c: Regenerate.
	35	* aarch64-dis-2.c: Regenerate.
	36	* aarch64-opc-2.c: Regenerate.
	37
290806fd MW	38	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	39
	40	* aarch64-tbl.h (aarch64_feature_lor): New.
	41	(LOR): New.
	42	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	43	"stllrb", "stllrh".
	44	* aarch64-asm-2.c: Regenerate.
	45	* aarch64-dis-2.c: Regenerate.
	46	* aarch64-opc-2.c: Regenerate.
	47
f21cce2c MW	48	2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
	49
	50	* aarch64-opc.c (F_ARCHEXT): New.
	51	(aarch64_sys_regs): Add "pan".
	52	(aarch64_sys_reg_supported_p): New.
	53	(aarch64_pstatefields): Add "pan".
	54	(aarch64_pstatefield_supported_p): New.
	55
d194d186 JB	56	2015-06-01 Jan Beulich <jbeulich@suse.com>
	57
	58	* i386-tbl.h: Regenerate.
	59
3a8547d2 JB	60	2015-06-01 Jan Beulich <jbeulich@suse.com>
	61
	62	* i386-dis.c (print_insn): Swap rounding mode specifier and
	63	general purpose register in Intel mode.
	64
015c54d5 JB	65	2015-06-01 Jan Beulich <jbeulich@suse.com>
	66
	67	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	68	* i386-tbl.h: Regenerate.
	69
071f0063 L	70	2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
	71
	72	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	73	* i386-init.h: Regenerated.
	74
5db04b09 L	75	2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
	76
	77	PR binutis/18386
	78	* i386-dis.c: Add comments for '@'.
	79	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	80	(enum x86_64_isa): New.
	81	(isa64): Likewise.
	82	(print_i386_disassembler_options): Add amd64 and intel64.
	83	(print_insn): Handle amd64 and intel64.
	84	(putop): Handle '@'.
	85	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	86	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	87	* i386-opc.h (AMD64): New.
	88	(CpuIntel64): Likewise.
	89	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	90	* i386-opc.tbl: Add direct call/jmp with Disp16\|Disp32 for AMD64.
	91	Mark direct call/jmp without Disp16\|Disp32 as Intel64.
	92	* i386-init.h: Regenerated.
	93	* i386-tbl.h: Likewise.
	94
4bc0608a PB	95	2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
	96
	97	* ppc-opc.c (IH) New define.
	98	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	99	<tlbie>: Add RS operand for POWER7.
	100	<slbia>: Add IH operand for POWER6.
	101
70cead07 L	102	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	103
	104	* opcodes/i386-opc.tbl (call): Remove Disp16\|Disp32 from 64-bit
	105	direct branch.
	106	(jmp): Likewise.
	107	* i386-tbl.h: Regenerated.
	108
7b6d09fb L	109	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	110
	111	* configure.ac: Support bfd_iamcu_arch.
	112	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	113	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	114	CPU_IAMCU_COMPAT_FLAGS.
	115	(cpu_flags): Add CpuIAMCU.
	116	* i386-opc.h (CpuIAMCU): New.
	117	(i386_cpu_flags): Add cpuiamcu.
	118	* configure: Regenerated.
	119	* i386-init.h: Likewise.
	120	* i386-tbl.h: Likewise.
	121
31955f99 L	122	2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
	123
	124	PR binutis/18386
	125	* i386-dis.c (X86_64_E8): New.
	126	(X86_64_E9): Likewise.
	127	Update comments on 'T', 'U', 'V'. Add comments for '^'.
	128	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	129	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	130	(mod_table): Replace {T\|} with ^ on Jcall/Jmp.
	131	(putop): Handle '^'.
	132	(OP_J): Ignore the operand size prefix in 64-bit. Don't check
	133	REX_W.
	134
0952813b DD	135	2015-04-30 DJ Delorie <dj@redhat.com>
	136
	137	* disassemble.c (disassembler): Choose suitable disassembler based
	138	on E_ABI.
	139	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
	140	it to decode mul/div insns.
	141	* rl78-decode.c: Regenerate.
	142	* rl78-dis.c (print_insn_rl78): Rename to...
	143	(print_insn_rl78_common): ...this, take ISA parameter.
	144	(print_insn_rl78): New.
	145	(print_insn_rl78_g10): New.
	146	(print_insn_rl78_g13): New.
	147	(print_insn_rl78_g14): New.
	148	(rl78_get_disassembler): New.
	149
f9d3ecaa NC	150	2015-04-29 Nick Clifton <nickc@redhat.com>
	151
	152	* po/fr.po: Updated French translation.
	153
4fff86c5 PB	154	2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
	155
	156	* ppc-opc.c (DCBT_EO): New define.
	157	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	158	<lharx>: Likewise.
	159	<stbcx.>: Likewise.
	160	<sthcx.>: Likewise.
	161	<waitrsv>: Do not enable for POWER7 and later.
	162	<waitimpl>: Likewise.
	163	<dcbt>: Default to the two operand form of the instruction for all
	164	"old" cpus. For "new" cpus, use the operand ordering that matches
	165	whether the cpu is server or embedded.
	166	<dcbtst>: Likewise.
	167
3b78cfe1 AK	168	2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	169
	170	* s390-opc.c: New instruction type VV0UU2.
	171	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	172	and WFC.
	173
04d824a4 JB	174	2015-04-23 Jan Beulich <jbeulich@suse.com>
	175
	176	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	177	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	178	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	179	(vfpclasspd, vfpclassps): Add %XZ.
	180
09708981 L	181	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	182
	183	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	184	(PREFIX_UD_REPZ): Likewise.
	185	(PREFIX_UD_REPNZ): Likewise.
	186	(PREFIX_UD_DATA): Likewise.
	187	(PREFIX_UD_ADDR): Likewise.
	188	(PREFIX_UD_LOCK): Likewise.
	189
3888916d L	190	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	191
	192	* i386-dis.c (prefix_requirement): Removed.
	193	(print_insn): Don't set prefix_requirement. Check
	194	dp->prefix_requirement instead of prefix_requirement.
	195
f24bcbaa L	196	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	197
	198	PR binutils/17898
	199	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	200	(PREFIX_MOD_0_0FC7_REG_6): This.
	201	(PREFIX_MOD_3_0FC7_REG_6): New.
	202	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	203	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	204	PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
	205	PREFIX_MOD_3_0FC7_REG_7.
	206	(mod_table): Replace PREFIX_0FC7_REG_6 with
	207	PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
	208	PREFIX_MOD_3_0FC7_REG_7.
	209
507bd325 L	210	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	211
	212	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	213	(PREFIX_MANDATORY_REPNZ): Likewise.
	214	(PREFIX_MANDATORY_DATA): Likewise.
	215	(PREFIX_MANDATORY_ADDR): Likewise.
	216	(PREFIX_MANDATORY_LOCK): Likewise.
	217	(PREFIX_MANDATORY): Likewise.
	218	(PREFIX_UD_SHIFT): Set to 8
	219	(PREFIX_UD_REPZ): Updated.
	220	(PREFIX_UD_REPNZ): Likewise.
	221	(PREFIX_UD_DATA): Likewise.
	222	(PREFIX_UD_ADDR): Likewise.
	223	(PREFIX_UD_LOCK): Likewise.
	224	(PREFIX_IGNORED_SHIFT): New.
	225	(PREFIX_IGNORED_REPZ): Likewise.
	226	(PREFIX_IGNORED_REPNZ): Likewise.
	227	(PREFIX_IGNORED_DATA): Likewise.
	228	(PREFIX_IGNORED_ADDR): Likewise.
	229	(PREFIX_IGNORED_LOCK): Likewise.
	230	(PREFIX_OPCODE): Likewise.
	231	(PREFIX_IGNORED): Likewise.
	232	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	233	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	234	(three_byte_table): Likewise.
	235	(mod_table): Likewise.
	236	(mandatory_prefix): Renamed to ...
	237	(prefix_requirement): This.
	238	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	239	Update PREFIX_90 entry.
	240	(get_valid_dis386): Check prefix_requirement to see if a prefix
	241	should be ignored.
	242	(print_insn): Replace mandatory_prefix with prefix_requirement.
	243
f0fba320 RL	244	2015-04-15 Renlin Li <renlin.li@arm.com>
	245
	246	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	247	use it for ssat and ssat16.
	248	(print_insn_thumb32): Add handle case for 'D' control code.
	249
bf890a93 IT	250	2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
	251	H.J. Lu <hongjiu.lu@intel.com>
	252
	253	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	254	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	255	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	256	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	257	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	258	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	259	Fill prefix_requirement field.
	260	(struct dis386): Add prefix_requirement field.
	261	(dis386): Fill prefix_requirement field.
	262	(dis386_twobyte): Ditto.
	263	(twobyte_has_mandatory_prefix_: Remove.
	264	(reg_table): Fill prefix_requirement field.
	265	(prefix_table): Ditto.
	266	(x86_64_table): Ditto.
	267	(three_byte_table): Ditto.
	268	(xop_table): Ditto.
	269	(vex_table): Ditto.
	270	(vex_len_table): Ditto.
	271	(vex_w_table): Ditto.
	272	(mod_table): Ditto.
	273	(bad_opcode): Ditto.
	274	(print_insn): Use prefix_requirement.
	275	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	276	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	277	(float_reg): Ditto.
	278
2f783c1f MF	279	2015-03-30 Mike Frysinger <vapier@gentoo.org>
	280
	281	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
	282
b9d94d62 L	283	2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
	284
	285	* Makefile.in: Regenerated.
	286
27c49e9a AB	287	2015-03-25 Anton Blanchard <anton@samba.org>
	288
	289	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	290	powerpc_opcd_indices and vle_opcd_indices once.
	291
c4e676f1 AB	292	2015-03-25 Anton Blanchard <anton@samba.org>
	293
	294	* ppc-opc.c (powerpc_opcodes): Add slbfee.
	295
823d2571 TG	296	2015-03-24 Terry Guo <terry.guo@arm.com>
	297
	298	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	299	(opcode16): Likewise.
	300	(coprocessor_opcodes): Replace bit with feature struct.
	301	(neon_opcodes): Likewise.
	302	(arm_opcodes): Likewise.
	303	(thumb_opcodes): Likewise.
	304	(thumb32_opcodes): Likewise.
	305	(print_insn_coprocessor): Likewise.
	306	(print_insn_arm): Likewise.
	307	(select_arm_features): Follow new feature struct.
	308
029f3522 GG	309	2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
	310
	311	* i386-dis.c (rm_table): Add clzero.
	312	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	313	Add CPU_CLZERO_FLAGS.
	314	(cpu_flags): Add CpuCLZERO.
	315	* i386-opc.h: Add CpuCLZERO.
	316	* i386-opc.tbl: Add clzero.
	317	* i386-init.h: Re-generated.
	318	* i386-tbl.h: Re-generated.
	319
6914869a AB	320	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	321
	322	* mips-opc.c (decode_mips_operand): Fix constraint issues
	323	with u and y operands.
	324
21e20815 AB	325	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	326
	327	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
	328
6b1d7593 AK	329	2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	330
	331	* s390-opc.c: Add new IBM z13 instructions.
	332	* s390-opc.txt: Likewise.
	333
c8f89a34 JW	334	2015-03-10 Renlin Li <renlin.li@arm.com>
	335
	336	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	337	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	338	related alias.
	339	* aarch64-asm-2.c: Regenerate.
	340	* aarch64-dis-2.c: Likewise.
	341	* aarch64-opc-2.c: Likewise.
	342
d8282f0e JW	343	2015-03-03 Jiong Wang <jiong.wang@arm.com>
	344
	345	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
	346
ac994365 OE	347	2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
	348
	349	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	350	arch_sh_up.
	351	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	352	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
	353
fd63f640 V	354	2015-02-23 Vinay <Vinay.G@kpit.com>
	355
	356	* rl78-decode.opc (MOV): Added space between two operands for
	357	'mov' instruction in index addressing mode.
	358	* rl78-decode.c: Regenerate.
	359
f63c1776 PA	360	2015-02-19 Pedro Alves <palves@redhat.com>
	361
	362	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
	363
07774fcc PA	364	2015-02-10 Pedro Alves <palves@redhat.com>
	365	Tom Tromey <tromey@redhat.com>
	366
	367	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	368	microblaze_and, microblaze_xor.
	369	* microblaze-opc.h (opcodes): Adjust.
	370
3f8107ab AM	371	2015-01-28 James Bowman <james.bowman@ftdichip.com>
	372
	373	* Makefile.am: Add FT32 files.
	374	* configure.ac: Handle FT32.
	375	* disassemble.c (disassembler): Call print_insn_ft32.
	376	* ft32-dis.c: New file.
	377	* ft32-opc.c: New file.
	378	* Makefile.in: Regenerate.
	379	* configure: Regenerate.
	380	* po/POTFILES.in: Regenerate.
	381
e5fe4957 KLC	382	2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
	383
	384	* nds32-asm.c (keyword_sr): Add new system registers.
	385
1e2e8c52 AK	386	2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	387
	388	* s390-dis.c (s390_extract_operand): Support vector register
	389	operands.
	390	(s390_print_insn_with_opcode): Support new operands types and add
	391	new handling of optional operands.
	392	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	393	and include opcode/s390.h instead.
	394	(struct op_struct): New field `flags'.
	395	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	396	(dumpTable): Dump flags.
	397	(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
	398	string.
	399	* s390-opc.c: Add new operands types, instruction formats, and
	400	instruction masks.
	401	(s390_opformats): Add new formats for .insn.
	402	* s390-opc.txt: Add new instructions.
	403
b90efa5b	404	2015-01-01 Alan Modra <amodra@gmail.com>
bffb6004	405
b90efa5b	406	Update year range in copyright notice of all files.
bffb6004	407
b90efa5b	408	For older changes see ChangeLog-2014
252b5132	409	\f
b90efa5b	410	Copyright (C) 2015 Free Software Foundation, Inc.
752937aa NC	411
	412	Copying and distribution of this file, with or without modification,
	413	are permitted in any medium without royalty provided the copyright
	414	notice and this notice are preserved.
	415
252b5132	416	Local Variables:
2f6d2f85 NC	417	mode: change-log
	418	left-margin: 8
	419	fill-column: 74
252b5132 RH	420	version-control: never
252b5132 RH	421	End: