[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2020-02-10  H.J. Lu  <hongjiu.lu@intel.com>

	PR gas/25516
	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	with ISA64.
	* i386-opc.h (AMD64): Removed.
	(Intel64): Likewose.
	(AMD64): New.
	(INTEL64): Likewise.
	(INTEL64ONLY): Likewise.
	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	* i386-opc.tbl (Amd64): New.
	(Intel64): Likewise.
	(Intel64Only): Likewise.
	Replace AMD64 with Amd64.  Update sysenter/sysenter with
	Cpu64 and Intel64Only.  Remove AMD64 from sysenter/sysenter.
	* i386-tbl.h: Regenerated.

2020-02-07  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25469
	* z80-dis.c: Add support for GBZ80 opcodes.

2020-02-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.

2020-02-03  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-02-01  Alan Modra  <amodra@gmail.com>

	* frv-ibld.c: Regenerate.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	(OP_E_memory): Replace xmm_mdq_mode case label by
	vex_scalar_w_dq_mode one.
	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.

2020-01-31  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	(intel_operand_size): Drop vex_w_dq_mode case label.

2020-01-31  Richard Sandiford  <richard.sandiford@arm.com>

	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-30  Jose E. Marchesi  <jose.marchesi@oracle.com>

	* bpf-opc.c: Regenerate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	(dis386): Use them to replace C2/C3 table entries.
	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	* i386-tbl.h: Re-generate.

2020-01-30  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	forms.
	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-30  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_dp): Make unsigned.

2020-01-27  H.J. Lu  <hongjiu.lu@intel.com>
	    Jan Beulich  <jbeulich@suse.com>

	PR binutils/25445
	* i386-dis.c (MOVSXD_Fixup): New function.
	(movsxd_mode): New enum.
	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	(intel_operand_size): Handle movsxd_mode.
	(OP_E_register): Likewise.
	(OP_G): Likewise.
	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	register on movsxd.  Add movsxd with 16-bit destination register
	for AMD64 and Intel64 ISAs.
	* i386-tbl.h: Regenerated.

2020-01-27  Tamar Christina  <tamar.christina@arm.com>

	PR 25403
	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	* aarch64-asm-2.c: Regenerate
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (sysret): Drop DefaultSize.
	* i386-tbl.h: Re-generate.

2020-01-21  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	Dword.
	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	* i386-tbl.h: Re-generate.

2020-01-20  Nick Clifton  <nickc@redhat.com>

	* po/de.po: Updated German translation.
	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	* po/uk.po: Updated Ukranian translation.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* hppa-dis.c (fput_const): Remove useless cast.

2020-01-20  Alan Modra  <amodra@gmail.com>

	* arm-dis.c (print_insn_arm): Wrap 'T' value.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	* configure: Regenerate.
	* po/opcodes.pot: Regenerate.

2020-01-18  Nick Clifton  <nickc@redhat.com>

	Binutils 2.34 branch created.

2020-01-17  Christian Biesinger  <cbiesinger@google.com>

	* opintl.h: Fix spelling error (seperate).

2020-01-17  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Add {vex} pseudo prefix.
	* i386-tbl.h: Regenerated.

2020-01-16  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	PR 25376
	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	(neon_opcodes): Likewise.
	(select_arm_features): Make sure we enable MVE bits when selecting
	armv8.1-m.main.  Make sure we do not enable MVE bits when not selecting
	any architecture.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: Drop stale comment from XOP section.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	(extractps): Add VexWIG to SSE2AVX forms.
	* i386-tbl.h: Re-generate.

2020-01-16  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	Size64 from and use VexW1 on SSE2AVX forms.
	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	* i386-tbl.h: Re-generate.

2020-01-15  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_version): Make unsigned long.
	(optab, optab_special, registernames): New file scope vars.
	(tic4x_print_register): Set up registernames rather than
	malloc'd registertable.
	(tic4x_disassemble): Delete optable and optable_special.  Use
	optab and optab_special instead.  Throw away old optab,
	optab_special and registernames when info->mach changes.

2020-01-14  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25377
	* z80-dis.c (suffix): Use .db instruction to generate double
	prefix.

2020-01-14  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c (unpack_instr): Formatting.  Cast unsigned short
	values to unsigned before shifting.

2020-01-13  Thomas Troeger  <tstroege@gmx.de>

	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	flow instructions.
	(print_insn_thumb16, print_insn_thumb32): Likewise.
	(print_insn): Initialize the insn info.
	* i386-dis.c (print_insn): Initialize the insn info fields, and
	detect jumps.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

	* arc-opc.c (C_NE): Make it required.

2012-01-13  Claudiu Zissulescu <claziss@gmail.com>

        * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	reserved register name.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* wasm32-dis.c (print_insn_wasm32): Localise variables.  Store
	result of wasm_read_leb128 in a uint64_t and check that bits
	are not lost when copying to other locals.  Use uint32_t for
	most locals.  Use PRId64 when printing int64_t.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c: Formatting.
	* score7-dis.c: Formatting.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* score-dis.c (print_insn_score48): Use unsigned variables for
	unsigned values.  Don't left shift negative values.
	(print_insn_score32): Likewise.
	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* tic4x-dis.c (tic4x_print_register): Remove dead code.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* fr30-ibld.c: Regenerate.

2020-01-13  Alan Modra  <amodra@gmail.com>

	* xgate-dis.c (print_insn): Don't left shift signed value.
	(ripBits): Formatting, use 1u.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	* tilegx-opc.c (parse_insn_tilegx): Likewise.  Delete raw_opval.

2020-01-10  Alan Modra  <amodra@gmail.com>

	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	and XRREG value earlier to avoid a shift with negative exponent.
	* m10200-dis.c (disassemble): Similarly.

2020-01-09  Nick Clifton  <nickc@redhat.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use correct cast.

2020-01-03  Sergey Belyashov  <sergey.belyashov@gmail.com>

	PR 25224
	* z80-dis.c (ld_ii_ii): Use character constant when checking
	opcode byte value.

2020-01-09  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (SEP_Fixup): New.
	(SEP): Define.
	(dis386_twobyte): Use it for sysenter/sysexit.
	(enum x86_64_isa): Change amd64 enumerator to value 1.
	(OP_J): Compare isa64 against intel64 instead of amd64.
	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	forms.
	* i386-tbl.h: Re-generate.

2020-01-08  Alan Modra  <amodra@gmail.com>

	* z8k-dis.c: Include libiberty.h
	(instr_data_s): Make max_fetched unsigned.
	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	Don't exceed byte_info bounds.
	(output_instr): Make num_bytes unsigned.
	(unpack_instr): Likewise for nibl_count and loop.
	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	idx unsigned.
	* z8k-opc.h: Regenerate.

2020-01-07  Shahab Vahedi  <shahab@synopsys.com>

	* arc-tbl.h (llock): Use 'LLOCK' as class.
	(llockd): Likewise.
	(scond): Use 'SCOND' as class.
	(scondd): Likewise.
	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	(scondd): Likewise.

2020-01-06  Alan Modra  <amodra@gmail.com>

	* m32c-ibld.c: Regenerate.

2020-01-06  Alan Modra  <amodra@gmail.com>

	PR 25344
	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	Peek at next byte to prevent recursion on repeated prefix bytes.
	Ensure uninitialised "mybuf" is not accessed.
	(print_insn_z80): Don't zero n_fetch and n_used here,..
	(print_insn_z80_buf): ..do it here instead.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* m32r-ibld.c: Regenerate.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* crx-dis.c (match_opcode): Avoid shift left of signed value.

2020-01-04  Alan Modra  <amodra@gmail.com>

	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Use
	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
	forms of SUDOT and USDOT.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
	uzip{1,2}.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-03  Jan Beulich  <jbeulich@suse.com>

	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
	FMMLA encoding.
	* opcodes/aarch64-dis-2.c: Re-generate.

2020-01-02  Sergey Belyashov  <sergey.belyashov@gmail.com>

	* z80-dis.c: Add support for eZ80 and Z80 instructions.

2020-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2019
\f
Copyright (C) 2020 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
4b5aaf5f L	1	2020-02-10 H.J. Lu <hongjiu.lu@intel.com>
	2
	3	PR gas/25516
	4	* i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
	5	with ISA64.
	6	* i386-opc.h (AMD64): Removed.
	7	(Intel64): Likewose.
	8	(AMD64): New.
	9	(INTEL64): Likewise.
	10	(INTEL64ONLY): Likewise.
	11	(i386_opcode_modifier): Replace amd64 and intel64 with isa64.
	12	* i386-opc.tbl (Amd64): New.
	13	(Intel64): Likewise.
	14	(Intel64Only): Likewise.
	15	Replace AMD64 with Amd64. Update sysenter/sysenter with
	16	Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
	17	* i386-tbl.h: Regenerated.
	18
9fc0b501 SB	19	2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
	20
	21	PR 25469
	22	* z80-dis.c: Add support for GBZ80 opcodes.
	23
c5d7be0c AM	24	2020-02-04 Alan Modra <amodra@gmail.com>
	25
	26	* d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
	27
44e4546f AM	28	2020-02-03 Alan Modra <amodra@gmail.com>
	29
	30	* m32c-ibld.c: Regenerate.
	31
b2b1453a AM	32	2020-02-01 Alan Modra <amodra@gmail.com>
	33
	34	* frv-ibld.c: Regenerate.
	35
4102be5c JB	36	2020-01-31 Jan Beulich <jbeulich@suse.com>
	37
	38	* i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
	39	(intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
	40	(OP_E_memory): Replace xmm_mdq_mode case label by
	41	vex_scalar_w_dq_mode one.
	42	* i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
	43
825bd36c JB	44	2020-01-31 Jan Beulich <jbeulich@suse.com>
	45
	46	* i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
	47	(vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
	48	vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
	49	(intel_operand_size): Drop vex_w_dq_mode case label.
	50
c3036ed0 RS	51	2020-01-31 Richard Sandiford <richard.sandiford@arm.com>
	52
	53	* aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
	54	Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
	55
0c115f84 AM	56	2020-01-30 Alan Modra <amodra@gmail.com>
	57
	58	* m32c-ibld.c: Regenerate.
	59
bd434cc4 JM	60	2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
	61
	62	* bpf-opc.c: Regenerate.
	63
aeab2b26 JB	64	2020-01-30 Jan Beulich <jbeulich@suse.com>
	65
	66	* i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
	67	(dis386): Use them to replace C2/C3 table entries.
	68	(x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
	69	* i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
	70	ones. Use Size64 instead of DefaultSize on Intel64 ones.
	71	* i386-tbl.h: Re-generate.
	72
62b3f548 JB	73	2020-01-30 Jan Beulich <jbeulich@suse.com>
	74
	75	* i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
	76	forms.
	77	(fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
	78	DefaultSize.
	79	* i386-tbl.h: Re-generate.
	80
1bd8ae10 AM	81	2020-01-30 Alan Modra <amodra@gmail.com>
	82
	83	* tic4x-dis.c (tic4x_dp): Make unsigned.
	84
bc31405e L	85	2020-01-27 H.J. Lu <hongjiu.lu@intel.com>
	86	Jan Beulich <jbeulich@suse.com>
	87
	88	PR binutils/25445
	89	* i386-dis.c (MOVSXD_Fixup): New function.
	90	(movsxd_mode): New enum.
	91	(x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
	92	(intel_operand_size): Handle movsxd_mode.
	93	(OP_E_register): Likewise.
	94	(OP_G): Likewise.
	95	* i386-opc.tbl: Remove Rex64 and allow 32-bit destination
	96	register on movsxd. Add movsxd with 16-bit destination register
	97	for AMD64 and Intel64 ISAs.
	98	* i386-tbl.h: Regenerated.
	99
7568c93b TC	100	2020-01-27 Tamar Christina <tamar.christina@arm.com>
	101
	102	PR 25403
	103	* aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
	104	* aarch64-asm-2.c: Regenerate
	105	* aarch64-dis-2.c: Likewise.
	106	* aarch64-opc-2.c: Likewise.
	107
c006a730 JB	108	2020-01-21 Jan Beulich <jbeulich@suse.com>
	109
	110	* i386-opc.tbl (sysret): Drop DefaultSize.
	111	* i386-tbl.h: Re-generate.
	112
c906a69a JB	113	2020-01-21 Jan Beulich <jbeulich@suse.com>
	114
	115	* i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
	116	Dword.
	117	(vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
	118	* i386-tbl.h: Re-generate.
	119
26916852 NC	120	2020-01-20 Nick Clifton <nickc@redhat.com>
	121
	122	* po/de.po: Updated German translation.
	123	* po/pt_BR.po: Updated Brazilian Portuguese translation.
	124	* po/uk.po: Updated Ukranian translation.
	125
4d6cbb64 AM	126	2020-01-20 Alan Modra <amodra@gmail.com>
	127
	128	* hppa-dis.c (fput_const): Remove useless cast.
	129
2bddb71a AM	130	2020-01-20 Alan Modra <amodra@gmail.com>
	131
	132	* arm-dis.c (print_insn_arm): Wrap 'T' value.
	133
1b1bb2c6 NC	134	2020-01-18 Nick Clifton <nickc@redhat.com>
	135
	136	* configure: Regenerate.
	137	* po/opcodes.pot: Regenerate.
	138
ae774686 NC	139	2020-01-18 Nick Clifton <nickc@redhat.com>
	140
	141	Binutils 2.34 branch created.
	142
07f1f3aa CB	143	2020-01-17 Christian Biesinger <cbiesinger@google.com>
	144
	145	* opintl.h: Fix spelling error (seperate).
	146
42e04b36 L	147	2020-01-17 H.J. Lu <hongjiu.lu@intel.com>
	148
	149	* i386-opc.tbl: Add {vex} pseudo prefix.
	150	* i386-tbl.h: Regenerated.
	151
2da2eaf4 AV	152	2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
	153
	154	PR 25376
	155	* opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
	156	(neon_opcodes): Likewise.
	157	(select_arm_features): Make sure we enable MVE bits when selecting
	158	armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
	159	any architecture.
	160
d0849eed JB	161	2020-01-16 Jan Beulich <jbeulich@suse.com>
	162
	163	* i386-opc.tbl: Drop stale comment from XOP section.
	164
9cf70a44 JB	165	2020-01-16 Jan Beulich <jbeulich@suse.com>
	166
	167	* i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
	168	(extractps): Add VexWIG to SSE2AVX forms.
	169	* i386-tbl.h: Re-generate.
	170
4814632e JB	171	2020-01-16 Jan Beulich <jbeulich@suse.com>
	172
	173	* i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
	174	Size64 from and use VexW1 on SSE2AVX forms.
	175	(vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
	176	VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
	177	* i386-tbl.h: Re-generate.
	178
aad09917 AM	179	2020-01-15 Alan Modra <amodra@gmail.com>
	180
	181	* tic4x-dis.c (tic4x_version): Make unsigned long.
	182	(optab, optab_special, registernames): New file scope vars.
	183	(tic4x_print_register): Set up registernames rather than
	184	malloc'd registertable.
	185	(tic4x_disassemble): Delete optable and optable_special. Use
	186	optab and optab_special instead. Throw away old optab,
	187	optab_special and registernames when info->mach changes.
	188
7a6bf3be SB	189	2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
	190
	191	PR 25377
	192	* z80-dis.c (suffix): Use .db instruction to generate double
	193	prefix.
	194
ca1eaac0 AM	195	2020-01-14 Alan Modra <amodra@gmail.com>
	196
	197	* z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
	198	values to unsigned before shifting.
	199
1d67fe3b TT	200	2020-01-13 Thomas Troeger <tstroege@gmx.de>
	201
	202	* arm-dis.c (print_insn_arm): Fill in insn info fields for control
	203	flow instructions.
	204	(print_insn_thumb16, print_insn_thumb32): Likewise.
	205	(print_insn): Initialize the insn info.
	206	* i386-dis.c (print_insn): Initialize the insn info fields, and
	207	detect jumps.
	208
5e4f7e05 CZ	209	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	210
	211	* arc-opc.c (C_NE): Make it required.
	212
b9fe6b8a CZ	213	2012-01-13 Claudiu Zissulescu <claziss@gmail.com>
	214
	215	* opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
	216	reserved register name.
	217
90dee485 AM	218	2020-01-13 Alan Modra <amodra@gmail.com>
	219
	220	* ns32k-dis.c (Is_gen): Use strchr, add 'f'.
	221	(print_insn_ns32k): Adjust ioffset for 'f' index_offset.
	222
febda64f AM	223	2020-01-13 Alan Modra <amodra@gmail.com>
	224
	225	* wasm32-dis.c (print_insn_wasm32): Localise variables. Store
	226	result of wasm_read_leb128 in a uint64_t and check that bits
	227	are not lost when copying to other locals. Use uint32_t for
	228	most locals. Use PRId64 when printing int64_t.
	229
df08b588 AM	230	2020-01-13 Alan Modra <amodra@gmail.com>
	231
	232	* score-dis.c: Formatting.
	233	* score7-dis.c: Formatting.
	234
b2c759ce AM	235	2020-01-13 Alan Modra <amodra@gmail.com>
	236
	237	* score-dis.c (print_insn_score48): Use unsigned variables for
	238	unsigned values. Don't left shift negative values.
	239	(print_insn_score32): Likewise.
	240	* score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
	241
5496abe1 AM	242	2020-01-13 Alan Modra <amodra@gmail.com>
	243
	244	* tic4x-dis.c (tic4x_print_register): Remove dead code.
	245
202e762b AM	246	2020-01-13 Alan Modra <amodra@gmail.com>
	247
	248	* fr30-ibld.c: Regenerate.
	249
7ef412cf AM	250	2020-01-13 Alan Modra <amodra@gmail.com>
	251
	252	* xgate-dis.c (print_insn): Don't left shift signed value.
	253	(ripBits): Formatting, use 1u.
	254
7f578b95 AM	255	2020-01-10 Alan Modra <amodra@gmail.com>
	256
	257	* tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
	258	* tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
	259
441af85b AM	260	2020-01-10 Alan Modra <amodra@gmail.com>
	261
	262	* m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
	263	and XRREG value earlier to avoid a shift with negative exponent.
	264	* m10200-dis.c (disassemble): Similarly.
	265
bce58db4 NC	266	2020-01-09 Nick Clifton <nickc@redhat.com>
	267
	268	PR 25224
	269	* z80-dis.c (ld_ii_ii): Use correct cast.
	270
40c75bc8 SB	271	2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
	272
	273	PR 25224
	274	* z80-dis.c (ld_ii_ii): Use character constant when checking
	275	opcode byte value.
	276
d835a58b JB	277	2020-01-09 Jan Beulich <jbeulich@suse.com>
	278
	279	* i386-dis.c (SEP_Fixup): New.
	280	(SEP): Define.
	281	(dis386_twobyte): Use it for sysenter/sysexit.
	282	(enum x86_64_isa): Change amd64 enumerator to value 1.
	283	(OP_J): Compare isa64 against intel64 instead of amd64.
	284	* i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
	285	forms.
	286	* i386-tbl.h: Re-generate.
	287
030a2e78 AM	288	2020-01-08 Alan Modra <amodra@gmail.com>
	289
	290	* z8k-dis.c: Include libiberty.h
	291	(instr_data_s): Make max_fetched unsigned.
	292	(z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
	293	Don't exceed byte_info bounds.
	294	(output_instr): Make num_bytes unsigned.
	295	(unpack_instr): Likewise for nibl_count and loop.
	296	* z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
	297	idx unsigned.
	298	* z8k-opc.h: Regenerate.
	299
bb82aefe SV	300	2020-01-07 Shahab Vahedi <shahab@synopsys.com>
	301
	302	* arc-tbl.h (llock): Use 'LLOCK' as class.
	303	(llockd): Likewise.
	304	(scond): Use 'SCOND' as class.
	305	(scondd): Likewise.
	306	(llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
	307	(scondd): Likewise.
	308
cc6aa1a6 AM	309	2020-01-06 Alan Modra <amodra@gmail.com>
	310
	311	* m32c-ibld.c: Regenerate.
	312
660e62b1 AM	313	2020-01-06 Alan Modra <amodra@gmail.com>
	314
	315	PR 25344
	316	* z80-dis.c (suffix): Don't use a local struct buffer copy.
	317	Peek at next byte to prevent recursion on repeated prefix bytes.
	318	Ensure uninitialised "mybuf" is not accessed.
	319	(print_insn_z80): Don't zero n_fetch and n_used here,..
	320	(print_insn_z80_buf): ..do it here instead.
	321
c9ae58fe AM	322	2020-01-04 Alan Modra <amodra@gmail.com>
	323
	324	* m32r-ibld.c: Regenerate.
	325
5f57d4ec AM	326	2020-01-04 Alan Modra <amodra@gmail.com>
	327
	328	* cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
	329
2c5c1196 AM	330	2020-01-04 Alan Modra <amodra@gmail.com>
	331
	332	* crx-dis.c (match_opcode): Avoid shift left of signed value.
	333
2e98c6c5 AM	334	2020-01-04 Alan Modra <amodra@gmail.com>
	335
	336	* d30v-dis.c (print_insn): Avoid signed overflow in left shift.
	337
567dfba2 JB	338	2020-01-03 Jan Beulich <jbeulich@suse.com>
567dfba2 JB	339
5437a02a JB	340	* aarch64-tbl.h (aarch64_opcode_table): Use
	341	SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
	342
	343	2020-01-03 Jan Beulich <jbeulich@suse.com>
	344
	345	* aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2 JB	346	forms of SUDOT and USDOT.
567dfba2 JB	347
8c45011a JB	348	2020-01-03 Jan Beulich <jbeulich@suse.com>
8c45011a JB	349
5437a02a	350	* aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a JB	351	uzip{1,2}.
	352	* opcodes/aarch64-dis-2.c: Re-generate.
	353
f4950f76 JB	354	2020-01-03 Jan Beulich <jbeulich@suse.com>
f4950f76 JB	355
5437a02a	356	* aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76 JB	357	FMMLA encoding.
	358	* opcodes/aarch64-dis-2.c: Re-generate.
	359
6655dba2 SB	360	2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
	361
	362	* z80-dis.c: Add support for eZ80 and Z80 instructions.
	363
b14ce8bf AM	364	2020-01-01 Alan Modra <amodra@gmail.com>
	365
	366	Update year range in copyright notice of all files.
	367
0b114740	368	For older changes see ChangeLog-2019
3499769a	369	\f
0b114740	370	Copyright (C) 2020 Free Software Foundation, Inc.
3499769a AM	371
	372	Copying and distribution of this file, with or without modification,
	373	are permitted in any medium without royalty provided the copyright
	374	notice and this notice are preserved.
	375
	376	Local Variables:
	377	mode: change-log
	378	left-margin: 8
	379	fill-column: 74
	380	version-control: never
	381	End: