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ubsan: xtensa: left shift cannot be represented in type 'int'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b8e61daa
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * epiphany-ibld.c: Regenerate.
4
20135676
AM		 52019-12-10 Alan Modra <amodra@gmail.com>
6
7 PR 24960
8 * disassemble.c (disassemble_free_target): New function.
9
103ebbc3
AM		 102019-12-10 Alan Modra <amodra@gmail.com>
11
12 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
13 * disassemble.c (disassemble_init_for_target): Likewise.
14 * bpf-dis.c: Regenerate.
15 * epiphany-dis.c: Regenerate.
16 * fr30-dis.c: Regenerate.
17 * frv-dis.c: Regenerate.
18 * ip2k-dis.c: Regenerate.
19 * iq2000-dis.c: Regenerate.
20 * lm32-dis.c: Regenerate.
21 * m32c-dis.c: Regenerate.
22 * m32r-dis.c: Regenerate.
23 * mep-dis.c: Regenerate.
24 * mt-dis.c: Regenerate.
25 * or1k-dis.c: Regenerate.
26 * xc16x-dis.c: Regenerate.
27 * xstormy16-dis.c: Regenerate.
28
6f0e0752
AM		 292019-12-10 Alan Modra <amodra@gmail.com>
30
31 * ppc-dis.c (private): Delete variable.
32 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
33 (powerpc_init_dialect): Don't use global private.
34
e7c22a69
AM		 352019-12-10 Alan Modra <amodra@gmail.com>
36
37 * s12z-opc.c: Formatting.
38
0a6aef6b
AM		 392019-12-08 Alan Modra <amodra@gmail.com>
40
41 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
42 registers.
43
2dc4b12f
JB		 442019-12-05 Jan Beulich <jbeulich@suse.com>
45
46 * aarch64-tbl.h (aarch64_feature_crypto,
47 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
48 CRYPTO_V8_2_INSN): Delete.
49
378fd436
AM		 502019-12-05 Alan Modra <amodra@gmail.com>
51
52 PR 25249
53 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
54 (struct string_buf): New.
55 (strbuf): New function.
56 (get_field): Use strbuf rather than strdup of local temp.
57 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
58 (get_field_rfsl, get_field_imm15): Likewise.
59 (get_field_rd, get_field_r1, get_field_r2): Update macros.
60 (get_field_special): Likewise. Don't strcpy spr. Formatting.
61 (print_insn_microblaze): Formatting. Init and pass string_buf to
62 get_field functions.
63
0ba59a29
JB		 642019-12-04 Jan Beulich <jbeulich@suse.com>
65
66 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
67 * i386-tbl.h: Re-generate.
68
77ad8092
JB		 692019-12-04 Jan Beulich <jbeulich@suse.com>
70
71 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
72
3036c899
JB		 732019-12-04 Jan Beulich <jbeulich@suse.com>
74
75 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
76 forms.
77 (xbegin): Drop DefaultSize.
78 * i386-tbl.h: Re-generate.
79
8b301fbb
MI		 802019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
81
82 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
83 Change the coproc CRC conditions to use the extension
84 feature set, second word, base on ARM_EXT2_CRC.
85
6aa385b9
JB		 862019-11-14 Jan Beulich <jbeulich@suse.com>
87
88 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
89 * i386-tbl.h: Re-generate.
90
0cfa3eb3
JB		 912019-11-14 Jan Beulich <jbeulich@suse.com>
92
93 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
94 JumpInterSegment, and JumpAbsolute entries.
95 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
96 JUMP_ABSOLUTE): Define.
97 (struct i386_opcode_modifier): Extend jump field to 3 bits.
98 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
99 fields.
100 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
101 JumpInterSegment): Define.
102 * i386-tbl.h: Re-generate.
103
6f2f06be
JB		 1042019-11-14 Jan Beulich <jbeulich@suse.com>
105
106 * i386-gen.c (operand_type_init): Remove
107 OPERAND_TYPE_JUMPABSOLUTE entry.
108 (opcode_modifiers): Add JumpAbsolute entry.
109 (operand_types): Remove JumpAbsolute entry.
110 * i386-opc.h (JumpAbsolute): Move between enums.
111 (struct i386_opcode_modifier): Add jumpabsolute field.
112 (union i386_operand_type): Remove jumpabsolute field.
113 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
114 * i386-init.h, i386-tbl.h: Re-generate.
115
601e8564
JB		 1162019-11-14 Jan Beulich <jbeulich@suse.com>
117
118 * i386-gen.c (opcode_modifiers): Add AnySize entry.
119 (operand_types): Remove AnySize entry.
120 * i386-opc.h (AnySize): Move between enums.
121 (struct i386_opcode_modifier): Add anysize field.
122 (OTUnused): Un-comment.
123 (union i386_operand_type): Remove anysize field.
124 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
125 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
126 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
127 AnySize.
128 * i386-tbl.h: Re-generate.
129
7722d40a
JW		 1302019-11-12 Nelson Chu <nelson.chu@sifive.com>
131
132 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
133 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
134 use the floating point register (FPR).
135
ce760a76
MI		 1362019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
137
138 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
139 cmode 1101.
140 (is_mve_encoding_conflict): Update cmode conflict checks for
141 MVE_VMVN_IMM.
142
51c8edf6
JB		 1432019-11-12 Jan Beulich <jbeulich@suse.com>
144
145 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
146 entry.
147 (operand_types): Remove EsSeg entry.
148 (main): Replace stale use of OTMax.
149 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
150 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
151 (EsSeg): Delete.
152 (OTUnused): Comment out.
153 (union i386_operand_type): Remove esseg field.
154 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
155 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
156 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
157 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
158 * i386-init.h, i386-tbl.h: Re-generate.
159
474da251
JB		 1602019-11-12 Jan Beulich <jbeulich@suse.com>
161
162 * i386-gen.c (operand_instances): Add RegB entry.
163 * i386-opc.h (enum operand_instance): Add RegB.
164 * i386-opc.tbl (RegC, RegD, RegB): Define.
165 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
166 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
167 monitorx, mwaitx): Drop ImmExt and convert encodings
168 accordingly.
169 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
170 (edx, rdx): Add Instance=RegD.
171 (ebx, rbx): Add Instance=RegB.
172 * i386-tbl.h: Re-generate.
173
75e5731b
JB		 1742019-11-12 Jan Beulich <jbeulich@suse.com>
175
176 * i386-gen.c (operand_type_init): Adjust
177 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
178 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
179 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
180 (operand_instances): New.
181 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
182 (output_operand_type): New parameter "instance". Process it.
183 (process_i386_operand_type): New local variable "instance".
184 (main): Adjust static assertions.
185 * i386-opc.h (INSTANCE_WIDTH): Define.
186 (enum operand_instance): New.
187 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
188 (union i386_operand_type): Replace acc, inoutportreg, and
189 shiftcount by instance.
190 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
191 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
192 Add Instance=.
193 * i386-init.h, i386-tbl.h: Re-generate.
194
91802f3c
JB		 1952019-11-11 Jan Beulich <jbeulich@suse.com>
196
197 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
198 smaxp/sminp entries' "tied_operand" field to 2.
199
4f5fc85d
JB		 2002019-11-11 Jan Beulich <jbeulich@suse.com>
201
202 * aarch64-opc.c (operand_general_constraint_met_p): Replace
203 "index" local variable by that of the already existing "num".
204
dc2be329
L		 2052019-11-08 H.J. Lu <hongjiu.lu@intel.com>
206
207 PR gas/25167
208 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
209 * i386-tbl.h: Regenerated.
210
f74a6307
JB		 2112019-11-08 Jan Beulich <jbeulich@suse.com>
212
213 * i386-gen.c (operand_type_init): Add Class= to
214 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
215 OPERAND_TYPE_REGBND entry.
216 (operand_classes): Add RegMask and RegBND entries.
217 (operand_types): Drop RegMask and RegBND entry.
218 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
219 (RegMask, RegBND): Delete.
220 (union i386_operand_type): Remove regmask and regbnd fields.
221 * i386-opc.tbl (RegMask, RegBND): Define.
222 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
223 Class=RegBND.
224 * i386-init.h, i386-tbl.h: Re-generate.
225
3528c362
JB		 2262019-11-08 Jan Beulich <jbeulich@suse.com>
227
228 * i386-gen.c (operand_type_init): Add Class= to
229 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
230 OPERAND_TYPE_REGZMM entries.
231 (operand_classes): Add RegMMX and RegSIMD entries.
232 (operand_types): Drop RegMMX and RegSIMD entries.
233 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
234 (RegMMX, RegSIMD): Delete.
235 (union i386_operand_type): Remove regmmx and regsimd fields.
236 * i386-opc.tbl (RegMMX): Define.
237 (RegXMM, RegYMM, RegZMM): Add Class=.
238 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
239 Class=RegSIMD.
240 * i386-init.h, i386-tbl.h: Re-generate.
241
4a5c67ed
JB		 2422019-11-08 Jan Beulich <jbeulich@suse.com>
243
244 * i386-gen.c (operand_type_init): Add Class= to
245 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
246 entries.
247 (operand_classes): Add RegCR, RegDR, and RegTR entries.
248 (operand_types): Drop Control, Debug, and Test entries.
249 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
250 (Control, Debug, Test): Delete.
251 (union i386_operand_type): Remove control, debug, and test
252 fields.
253 * i386-opc.tbl (Control, Debug, Test): Define.
254 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
255 Class=RegDR, and Test by Class=RegTR.
256 * i386-init.h, i386-tbl.h: Re-generate.
257
00cee14f
JB		 2582019-11-08 Jan Beulich <jbeulich@suse.com>
259
260 * i386-gen.c (operand_type_init): Add Class= to
261 OPERAND_TYPE_SREG entry.
262 (operand_classes): Add SReg entry.
263 (operand_types): Drop SReg entry.
264 * i386-opc.h (enum operand_class): Add SReg.
265 (SReg): Delete.
266 (union i386_operand_type): Remove sreg field.
267 * i386-opc.tbl (SReg): Define.
268 * i386-reg.tbl: Replace SReg by Class=SReg.
269 * i386-init.h, i386-tbl.h: Re-generate.
270
bab6aec1
JB		 2712019-11-08 Jan Beulich <jbeulich@suse.com>
272
273 * i386-gen.c (operand_type_init): Add Class=. New
274 OPERAND_TYPE_ANYIMM entry.
275 (operand_classes): New.
276 (operand_types): Drop Reg entry.
277 (output_operand_type): New parameter "class". Process it.
278 (process_i386_operand_type): New local variable "class".
279 (main): Adjust static assertions.
280 * i386-opc.h (CLASS_WIDTH): Define.
281 (enum operand_class): New.
282 (Reg): Replace by Class. Adjust comment.
283 (union i386_operand_type): Replace reg by class.
284 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
285 Class=.
286 * i386-reg.tbl: Replace Reg by Class=Reg.
287 * i386-init.h: Re-generate.
288
1f4cd317
MM		 2892019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
290
291 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
292 (aarch64_opcode_table): Add data gathering hint mnemonic.
293 * opcodes/aarch64-dis-2.c: Account for new instruction.
294
616ce08e
MM		 2952019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
296
297 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
298
299
8382113f
MM		 3002019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
301
302 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
303 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
304 aarch64_feature_f64mm): New feature sets.
305 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
306 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
307 instructions.
308 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
309 macros.
310 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
311 (OP_SVE_QQQ): New qualifier.
312 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
313 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
314 the movprfx constraint.
315 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
316 (aarch64_opcode_table): Define new instructions smmla,
317 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
318 uzip{1/2}, trn{1/2}.
319 * aarch64-opc.c (operand_general_constraint_met_p): Handle
320 AARCH64_OPND_SVE_ADDR_RI_S4x32.
321 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
322 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
323 Account for new instructions.
324 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
325 S4x32 operand.
326 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
327
aab2c27d
MM		 3282019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3292019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
330
331 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
332 Armv8.6-A.
333 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
334 (neon_opcodes): Add bfloat SIMD instructions.
335 (print_insn_coprocessor): Add new control character %b to print
336 condition code without checking cp_num.
337 (print_insn_neon): Account for BFloat16 instructions that have no
338 special top-byte handling.
339
33593eaf
MM		 3402019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3412019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
342
343 * arm-dis.c (print_insn_coprocessor,
344 print_insn_generic_coprocessor): Create wrapper functions around
345 the implementation of the print_insn_coprocessor control codes.
346 (print_insn_coprocessor_1): Original print_insn_coprocessor
347 function that now takes which array to look at as an argument.
348 (print_insn_arm): Use both print_insn_coprocessor and
349 print_insn_generic_coprocessor.
350 (print_insn_thumb32): As above.
351
df678013
MM		 3522019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3532019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
354
355 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
356 in reglane special case.
357 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
358 aarch64_find_next_opcode): Account for new instructions.
359 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
360 in reglane special case.
361 * aarch64-opc.c (struct operand_qualifier_data): Add data for
362 new AARCH64_OPND_QLF_S_2H qualifier.
363 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
364 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
365 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
366 sets.
367 (BFLOAT_SVE, BFLOAT): New feature set macros.
368 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
369 instructions.
370 (aarch64_opcode_table): Define new instructions bfdot,
371 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
372 bfcvtn2, bfcvt.
373
8ae2d3d9
MM		 3742019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3752019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
376
377 * aarch64-tbl.h (ARMV8_6): New macro.
378
142861df
JB		 3792019-11-07 Jan Beulich <jbeulich@suse.com>
380
381 * i386-dis.c (prefix_table): Add mcommit.
382 (rm_table): Add rdpru.
383 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
384 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
385 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
386 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
387 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
388 * i386-opc.tbl (mcommit, rdpru): New.
389 * i386-init.h, i386-tbl.h: Re-generate.
390
081e283f
JB		 3912019-11-07 Jan Beulich <jbeulich@suse.com>
392
393 * i386-dis.c (OP_Mwait): Drop local variable "names", use
394 "names32" instead.
395 (OP_Monitor): Drop local variable "op1_names", re-purpose
396 "names" for it instead, and replace former "names" uses by
397 "names32" ones.
398
c050c89a
JB		 3992019-11-07 Jan Beulich <jbeulich@suse.com>
400
401 PR/gas 25167
402 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
403 operand-less forms.
404 * opcodes/i386-tbl.h: Re-generate.
405
7abb8d81
JB		 4062019-11-05 Jan Beulich <jbeulich@suse.com>
407
408 * i386-dis.c (OP_Mwaitx): Delete.
409 (prefix_table): Use OP_Mwait for mwaitx entry.
410 (OP_Mwait): Also handle mwaitx.
411
267b8516
JB		 4122019-11-05 Jan Beulich <jbeulich@suse.com>
413
414 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
415 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
416 (prefix_table): Add respective entries.
417 (rm_table): Link to those entries.
418
f8687e93
JB		 4192019-11-05 Jan Beulich <jbeulich@suse.com>
420
421 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
422 (REG_0F1C_P_0_MOD_0): ... this.
423 (REG_0F1E_MOD_3): Rename to ...
424 (REG_0F1E_P_1_MOD_3): ... this.
425 (RM_0F01_REG_5): Rename to ...
426 (RM_0F01_REG_5_MOD_3): ... this.
427 (RM_0F01_REG_7): Rename to ...
428 (RM_0F01_REG_7_MOD_3): ... this.
429 (RM_0F1E_MOD_3_REG_7): Rename to ...
430 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
431 (RM_0FAE_REG_6): Rename to ...
432 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
433 (RM_0FAE_REG_7): Rename to ...
434 (RM_0FAE_REG_7_MOD_3): ... this.
435 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
436 (PREFIX_0F01_REG_5_MOD_0): ... this.
437 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
438 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
439 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
440 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
441 (PREFIX_0FAE_REG_0): Rename to ...
442 (PREFIX_0FAE_REG_0_MOD_3): ... this.
443 (PREFIX_0FAE_REG_1): Rename to ...
444 (PREFIX_0FAE_REG_1_MOD_3): ... this.
445 (PREFIX_0FAE_REG_2): Rename to ...
446 (PREFIX_0FAE_REG_2_MOD_3): ... this.
447 (PREFIX_0FAE_REG_3): Rename to ...
448 (PREFIX_0FAE_REG_3_MOD_3): ... this.
449 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
450 (PREFIX_0FAE_REG_4_MOD_0): ... this.
451 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
452 (PREFIX_0FAE_REG_4_MOD_3): ... this.
453 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
454 (PREFIX_0FAE_REG_5_MOD_0): ... this.
455 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
456 (PREFIX_0FAE_REG_5_MOD_3): ... this.
457 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
458 (PREFIX_0FAE_REG_6_MOD_0): ... this.
459 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
460 (PREFIX_0FAE_REG_6_MOD_3): ... this.
461 (PREFIX_0FAE_REG_7): Rename to ...
462 (PREFIX_0FAE_REG_7_MOD_0): ... this.
463 (PREFIX_MOD_0_0FC3): Rename to ...
464 (PREFIX_0FC3_MOD_0): ... this.
465 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
466 (PREFIX_0FC7_REG_6_MOD_0): ... this.
467 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
468 (PREFIX_0FC7_REG_6_MOD_3): ... this.
469 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
470 (PREFIX_0FC7_REG_7_MOD_3): ... this.
471 (reg_table, prefix_table, mod_table, rm_table): Adjust
472 accordingly.
473
5103274f
NC		 4742019-11-04 Nick Clifton <nickc@redhat.com>
475
476 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
477 of a v850 system register. Move the v850_sreg_names array into
478 this function.
479 (get_v850_reg_name): Likewise for ordinary register names.
480 (get_v850_vreg_name): Likewise for vector register names.
481 (get_v850_cc_name): Likewise for condition codes.
482 * get_v850_float_cc_name): Likewise for floating point condition
483 codes.
484 (get_v850_cacheop_name): Likewise for cache-ops.
485 (get_v850_prefop_name): Likewise for pref-ops.
486 (disassemble): Use the new accessor functions.
487
1820262b
DB		 4882019-10-30 Delia Burduv <delia.burduv@arm.com>
489
490 * aarch64-opc.c (print_immediate_offset_address): Don't print the
491 immediate for the writeback form of ldraa/ldrab if it is 0.
492 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
493 * aarch64-opc-2.c: Regenerated.
494
3cc17af5
JB		 4952019-10-30 Jan Beulich <jbeulich@suse.com>
496
497 * i386-gen.c (operand_type_shorthands): Delete.
498 (operand_type_init): Expand previous shorthands.
499 (set_bitfield_from_shorthand): Rename back to ...
500 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
501 of operand_type_init[].
502 (set_bitfield): Adjust call to the above function.
503 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
504 RegXMM, RegYMM, RegZMM): Define.
505 * i386-reg.tbl: Expand prior shorthands.
506
a2cebd03
JB		 5072019-10-30 Jan Beulich <jbeulich@suse.com>
508
509 * i386-gen.c (output_i386_opcode): Change order of fields
510 emitted to output.
511 * i386-opc.h (struct insn_template): Move operands field.
512 Convert extension_opcode field to unsigned short.
513 * i386-tbl.h: Re-generate.
514
507916b8
JB		 5152019-10-30 Jan Beulich <jbeulich@suse.com>
516
517 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
518 of W.
519 * i386-opc.h (W): Extend comment.
520 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
521 general purpose variants not allowing for byte operands.
522 * i386-tbl.h: Re-generate.
523
efea62b4
NC		 5242019-10-29 Nick Clifton <nickc@redhat.com>
525
526 * tic30-dis.c (print_branch): Correct size of operand array.
527
9adb2591
NC		 5282019-10-29 Nick Clifton <nickc@redhat.com>
529
530 * d30v-dis.c (print_insn): Check that operand index is valid
531 before attempting to access the operands array.
532
993a00a9
NC		 5332019-10-29 Nick Clifton <nickc@redhat.com>
534
535 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
536 locating the bit to be tested.
537
66a66a17
NC		 5382019-10-29 Nick Clifton <nickc@redhat.com>
539
540 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
541 values.
542 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
543 (print_insn_s12z): Check for illegal size values.
544
1ee3542c
NC		 5452019-10-28 Nick Clifton <nickc@redhat.com>
546
547 * csky-dis.c (csky_chars_to_number): Check for a negative
548 count. Use an unsigned integer to construct the return value.
549
bbf9a0b5
NC		 5502019-10-28 Nick Clifton <nickc@redhat.com>
551
552 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
553 operand buffer. Set value to 15 not 13.
554 (get_register_operand): Use OPERAND_BUFFER_LEN.
555 (get_indirect_operand): Likewise.
556 (print_two_operand): Likewise.
557 (print_three_operand): Likewise.
558 (print_oar_insn): Likewise.
559
d1e304bc
NC		 5602019-10-28 Nick Clifton <nickc@redhat.com>
561
562 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
563 (bit_extract_simple): Likewise.
564 (bit_copy): Likewise.
565 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
566 index_offset array are not accessed.
567
dee33451
NC		 5682019-10-28 Nick Clifton <nickc@redhat.com>
569
570 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
571 operand.
572
27cee81d
NC		 5732019-10-25 Nick Clifton <nickc@redhat.com>
574
575 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
576 access to opcodes.op array element.
577
de6d8dc2
NC		 5782019-10-23 Nick Clifton <nickc@redhat.com>
579
580 * rx-dis.c (get_register_name): Fix spelling typo in error
581 message.
582 (get_condition_name, get_flag_name, get_double_register_name)
583 (get_double_register_high_name, get_double_register_low_name)
584 (get_double_control_register_name, get_double_condition_name)
585 (get_opsize_name, get_size_name): Likewise.
586
6207ed28
NC		 5872019-10-22 Nick Clifton <nickc@redhat.com>
588
589 * rx-dis.c (get_size_name): New function. Provides safe
590 access to name array.
591 (get_opsize_name): Likewise.
592 (print_insn_rx): Use the accessor functions.
593
12234dfd
NC		 5942019-10-16 Nick Clifton <nickc@redhat.com>
595
596 * rx-dis.c (get_register_name): New function. Provides safe
597 access to name array.
598 (get_condition_name, get_flag_name, get_double_register_name)
599 (get_double_register_high_name, get_double_register_low_name)
600 (get_double_control_register_name, get_double_condition_name):
601 Likewise.
602 (print_insn_rx): Use the accessor functions.
603
1d378749
NC		 6042019-10-09 Nick Clifton <nickc@redhat.com>
605
606 PR 25041
607 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
608 instructions.
609
d241b910
JB		 6102019-10-07 Jan Beulich <jbeulich@suse.com>
611
612 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
613 (cmpsd): Likewise. Move EsSeg to other operand.
614 * opcodes/i386-tbl.h: Re-generate.
615
f5c5b7c1
AM		 6162019-09-23 Alan Modra <amodra@gmail.com>
617
618 * m68k-dis.c: Include cpu-m68k.h
619
7beeaeb8
AM		 6202019-09-23 Alan Modra <amodra@gmail.com>
621
622 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
623 "elf/mips.h" earlier.
624
3f9aad11
JB		 6252018-09-20 Jan Beulich <jbeulich@suse.com>
626
627 PR gas/25012
628 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
629 with SReg operand.
630 * i386-tbl.h: Re-generate.
631
fd361982
AM		 6322019-09-18 Alan Modra <amodra@gmail.com>
633
634 * arc-ext.c: Update throughout for bfd section macro changes.
635
e0b2a78c
SM		 6362019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
637
638 * Makefile.in: Re-generate.
639 * configure: Re-generate.
640
7e9ad3a3
JW		 6412019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
642
643 * riscv-opc.c (riscv_opcodes): Change subset field
644 to insn_class field for all instructions.
645 (riscv_insn_types): Likewise.
646
bb695960
PB		 6472019-09-16 Phil Blundell <pb@pbcl.net>
648
649 * configure: Regenerated.
650
8063ab7e
MV		 6512019-09-10 Miod Vallat <miod@online.fr>
652
653 PR 24982
654 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
655
60391a25
PB		 6562019-09-09 Phil Blundell <pb@pbcl.net>
657
658 binutils 2.33 branch created.
659
f44b758d
NC		 6602019-09-03 Nick Clifton <nickc@redhat.com>
661
662 PR 24961
663 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
664 greater than zero before indexing via (bufcnt -1).
665
1e4b5e7d
NC		 6662019-09-03 Nick Clifton <nickc@redhat.com>
667
668 PR 24958
669 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
670 (MAX_SPEC_REG_NAME_LEN): Define.
671 (struct mmix_dis_info): Use defined constants for array lengths.
672 (get_reg_name): New function.
673 (get_sprec_reg_name): New function.
674 (print_insn_mmix): Use new functions.
675
c4a23bf8
SP		 6762019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
677
678 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
679 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
680 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
681
a051e2f3
KT		 6822019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
683
684 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
685 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
686 (aarch64_sys_reg_supported_p): Update checks for the above.
687
08132bdd
SP		 6882019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
689
690 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
691 cases MVE_SQRSHRL and MVE_UQRSHLL.
692 (print_insn_mve): Add case for specifier 'k' to check
693 specific bit of the instruction.
694
d88bdcb4
PA		 6952019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
696
697 PR 24854
698 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
699 encountering an unknown machine type.
700 (print_insn_arc): Handle arc_insn_length returning 0. In error
701 cases return -1 rather than calling abort.
702
bc750500
JB		 7032019-08-07 Jan Beulich <jbeulich@suse.com>
704
705 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
706 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
707 IgnoreSize.
708 * i386-tbl.h: Re-generate.
709
23d188c7
BW		 7102019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
711
712 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
713 instructions.
714
c0d6f62f
JW		 7152019-07-30 Mel Chen <mel.chen@sifive.com>
716
717 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
718 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
719
720 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
721 fscsr.
722
0f3f7167
CZ		 7232019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
724
725 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
726 and MPY class instructions.
727 (parse_option): Add nps400 option.
728 (print_arc_disassembler_options): Add nps400 info.
729
7e126ba3
CZ		 7302019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
731
732 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
733 (bspop): Likewise.
734 (modapp): Likewise.
735 * arc-opc.c (RAD_CHK): Add.
736 * arc-tbl.h: Regenerate.
737
a028026d
KT		 7382019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
739
740 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
741 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
742
ac79ff9e
NC		 7432019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
744
745 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
746 instructions as UNPREDICTABLE.
747
231097b0
JM		 7482019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
749
750 * bpf-desc.c: Regenerated.
751
1d942ae9
JB		 7522019-07-17 Jan Beulich <jbeulich@suse.com>
753
754 * i386-gen.c (static_assert): Define.
755 (main): Use it.
756 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
757 (Opcode_Modifier_Num): ... this.
758 (Mem): Delete.
759
dfd69174
JB		 7602019-07-16 Jan Beulich <jbeulich@suse.com>
761
762 * i386-gen.c (operand_types): Move RegMem ...
763 (opcode_modifiers): ... here.
764 * i386-opc.h (RegMem): Move to opcode modifer enum.
765 (union i386_operand_type): Move regmem field ...
766 (struct i386_opcode_modifier): ... here.
767 * i386-opc.tbl (RegMem): Define.
768 (mov, movq): Move RegMem on segment, control, debug, and test
769 register flavors.
770 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
771 to non-SSE2AVX flavor.
772 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
773 Move RegMem on register only flavors. Drop IgnoreSize from
774 legacy encoding flavors.
775 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
776 flavors.
777 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
778 register only flavors.
779 (vmovd): Move RegMem and drop IgnoreSize on register only
780 flavor. Change opcode and operand order to store form.
781 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
782
21df382b
JB		 7832019-07-16 Jan Beulich <jbeulich@suse.com>
784
785 * i386-gen.c (operand_type_init, operand_types): Replace SReg
786 entries.
787 * i386-opc.h (SReg2, SReg3): Replace by ...
788 (SReg): ... this.
789 (union i386_operand_type): Replace sreg fields.
790 * i386-opc.tbl (mov, ): Use SReg.
791 (push, pop): Likewies. Drop i386 and x86-64 specific segment
792 register flavors.
793 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
794 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
795
3719fd55
JM		 7962019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
797
798 * bpf-desc.c: Regenerate.
799 * bpf-opc.c: Likewise.
800 * bpf-opc.h: Likewise.
801
92434a14
JM		 8022019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
803
804 * bpf-desc.c: Regenerate.
805 * bpf-opc.c: Likewise.
806
43dd7626
HPN		 8072019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
808
809 * arm-dis.c (print_insn_coprocessor): Rename index to
810 index_operand.
811
98602811
JW		 8122019-07-05 Kito Cheng <kito.cheng@sifive.com>
813
814 * riscv-opc.c (riscv_insn_types): Add r4 type.
815
816 * riscv-opc.c (riscv_insn_types): Add b and j type.
817
818 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
819 format for sb type and correct s type.
820
01c1ee4a
RS		 8212019-07-02 Richard Sandiford <richard.sandiford@arm.com>
822
823 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
824 SVE FMOV alias of FCPY.
825
83adff69
RS		 8262019-07-02 Richard Sandiford <richard.sandiford@arm.com>
827
828 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
829 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
830
89418844
RS		 8312019-07-02 Richard Sandiford <richard.sandiford@arm.com>
832
833 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
834 registers in an instruction prefixed by MOVPRFX.
835
41be57ca
MM		 8362019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
837
838 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
839 sve_size_13 icode to account for variant behaviour of
840 pmull{t,b}.
841 * aarch64-dis-2.c: Regenerate.
842 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
843 sve_size_13 icode to account for variant behaviour of
844 pmull{t,b}.
845 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
846 (OP_SVE_VVV_Q_D): Add new qualifier.
847 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
848 (struct aarch64_opcode): Split pmull{t,b} into those requiring
849 AES and those not.
850
9d3bf266
JB		 8512019-07-01 Jan Beulich <jbeulich@suse.com>
852
853 * opcodes/i386-gen.c (operand_type_init): Remove
854 OPERAND_TYPE_VEC_IMM4 entry.
855 (operand_types): Remove Vec_Imm4.
856 * opcodes/i386-opc.h (Vec_Imm4): Delete.
857 (union i386_operand_type): Remove vec_imm4.
858 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
859 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
860
c3949f43
JB		 8612019-07-01 Jan Beulich <jbeulich@suse.com>
862
863 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
864 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
865 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
866 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
867 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
868 monitorx, mwaitx): Drop ImmExt from operand-less forms.
869 * i386-tbl.h: Re-generate.
870
5641ec01
JB		 8712019-07-01 Jan Beulich <jbeulich@suse.com>
872
873 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
874 register operands.
875 * i386-tbl.h: Re-generate.
876
79dec6b7
JB		 8772019-07-01 Jan Beulich <jbeulich@suse.com>
878
879 * i386-opc.tbl (C): New.
880 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
881 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
882 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
883 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
884 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
885 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
886 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
887 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
888 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
889 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
890 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
891 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
892 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
893 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
894 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
895 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
896 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
897 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
898 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
899 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
900 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
901 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
902 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
903 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
904 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
905 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
906 flavors.
907 * i386-tbl.h: Re-generate.
908
a0a1771e
JB		 9092019-07-01 Jan Beulich <jbeulich@suse.com>
910
911 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
912 register operands.
913 * i386-tbl.h: Re-generate.
914
cd546e7b
JB		 9152019-07-01 Jan Beulich <jbeulich@suse.com>
916
917 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
918 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
919 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
920 * i386-tbl.h: Re-generate.
921
e3bba3fc
JB		 9222019-07-01 Jan Beulich <jbeulich@suse.com>
923
924 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
925 Disp8MemShift from register only templates.
926 * i386-tbl.h: Re-generate.
927
36cc073e
JB		 9282019-07-01 Jan Beulich <jbeulich@suse.com>
929
930 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
931 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
932 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
933 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
934 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
935 EVEX_W_0F11_P_3_M_1): Delete.
936 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
937 EVEX_W_0F11_P_3): New.
938 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
939 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
940 MOD_EVEX_0F11_PREFIX_3 table entries.
941 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
942 PREFIX_EVEX_0F11 table entries.
943 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
944 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
945 EVEX_W_0F11_P_3_M_{0,1} table entries.
946
219920a7
JB		 9472019-07-01 Jan Beulich <jbeulich@suse.com>
948
949 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
950 Delete.
951
e395f487
L		 9522019-06-27 H.J. Lu <hongjiu.lu@intel.com>
953
954 PR binutils/24719
955 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
956 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
957 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
958 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
959 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
960 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
961 EVEX_LEN_0F38C7_R_6_P_2_W_1.
962 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
963 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
964 PREFIX_EVEX_0F38C6_REG_6 entries.
965 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
966 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
967 EVEX_W_0F38C7_R_6_P_2 entries.
968 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
969 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
970 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
971 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
972 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
973 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
974 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
975
2b7bcc87
JB		 9762019-06-27 Jan Beulich <jbeulich@suse.com>
977
978 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
979 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
980 VEX_LEN_0F2D_P_3): Delete.
981 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
982 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
983 (prefix_table): ... here.
984
c1dc7af5
JB		 9852019-06-27 Jan Beulich <jbeulich@suse.com>
986
987 * i386-dis.c (Iq): Delete.
988 (Id): New.
989 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
990 TBM insns.
991 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
992 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
993 (OP_E_memory): Also honor needindex when deciding whether an
994 address size prefix needs printing.
995 (OP_I): Remove handling of q_mode. Add handling of d_mode.
996
d7560e2d
JW		 9972019-06-26 Jim Wilson <jimw@sifive.com>
998
999 PR binutils/24739
1000 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1001 Set info->display_endian to info->endian_code.
1002
2c703856
JB		 10032019-06-25 Jan Beulich <jbeulich@suse.com>
1004
1005 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1006 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1007 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1008 OPERAND_TYPE_ACC64 entries.
1009 * i386-init.h: Re-generate.
1010
54fbadc0
JB		 10112019-06-25 Jan Beulich <jbeulich@suse.com>
1012
1013 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1014 Delete.
1015 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1016 of dqa_mode.
1017 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1018 entries here.
1019 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1020 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1021
a280ab8e
JB		 10222019-06-25 Jan Beulich <jbeulich@suse.com>
1023
1024 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1025 variables.
1026
e1a1babd
JB		 10272019-06-25 Jan Beulich <jbeulich@suse.com>
1028
1029 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1030 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1031 movnti.
d7560e2d 1032 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1033 * i386-tbl.h: Re-generate.
1034
b8364fa7
JB		 10352019-06-25 Jan Beulich <jbeulich@suse.com>
1036
1037 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1038 * i386-tbl.h: Re-generate.
1039
ad692897
L		 10402019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1041
1042 * i386-dis-evex.h: Break into ...
1043 * i386-dis-evex-len.h: New file.
1044 * i386-dis-evex-mod.h: Likewise.
1045 * i386-dis-evex-prefix.h: Likewise.
1046 * i386-dis-evex-reg.h: Likewise.
1047 * i386-dis-evex-w.h: Likewise.
1048 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1049 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1050 i386-dis-evex-mod.h.
1051
f0a6222e
L		 10522019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1053
1054 PR binutils/24700
1055 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1056 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1057 EVEX_W_0F385B_P_2.
1058 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1059 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1060 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1061 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1062 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1063 EVEX_LEN_0F385B_P_2_W_1.
1064 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1065 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1066 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1067 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1068 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1069 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1070 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1071 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1072 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1073 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1074
6e1c90b7
L		 10752019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1076
1077 PR binutils/24691
1078 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1079 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1080 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1081 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1082 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1083 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1084 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1085 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1086 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1087 EVEX_LEN_0F3A43_P_2_W_1.
1088 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1089 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1090 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1091 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1092 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1093 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1094 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1095 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1096 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1097 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1098 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1099 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1100
bcc5a6eb
NC		 11012019-06-14 Nick Clifton <nickc@redhat.com>
1102
1103 * po/fr.po; Updated French translation.
1104
e4c4ac46
SH		 11052019-06-13 Stafford Horne <shorne@gmail.com>
1106
1107 * or1k-asm.c: Regenerated.
1108 * or1k-desc.c: Regenerated.
1109 * or1k-desc.h: Regenerated.
1110 * or1k-dis.c: Regenerated.
1111 * or1k-ibld.c: Regenerated.
1112 * or1k-opc.c: Regenerated.
1113 * or1k-opc.h: Regenerated.
1114 * or1k-opinst.c: Regenerated.
1115
a0e44ef5
PB		 11162019-06-12 Peter Bergner <bergner@linux.ibm.com>
1117
1118 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1119
12efd68d
L		 11202019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1121
1122 PR binutils/24633
1123 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1124 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1125 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1126 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1127 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1128 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1129 EVEX_LEN_0F3A1B_P_2_W_1.
1130 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1131 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1132 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1133 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1134 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1135 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1136 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1137 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1138
63c6fc6c
L		 11392019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1140
1141 PR binutils/24626
1142 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1143 EVEX.vvvv when disassembling VEX and EVEX instructions.
1144 (OP_VEX): Set vex.register_specifier to 0 after readding
1145 vex.register_specifier.
1146 (OP_Vex_2src_1): Likewise.
1147 (OP_Vex_2src_2): Likewise.
1148 (OP_LWP_E): Likewise.
1149 (OP_EX_Vex): Don't check vex.register_specifier.
1150 (OP_XMM_Vex): Likewise.
1151
9186c494
L		 11522019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1153 Lili Cui <lili.cui@intel.com>
1154
1155 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1156 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1157 instructions.
1158 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1159 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1160 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1161 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1162 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1163 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1164 * i386-init.h: Regenerated.
1165 * i386-tbl.h: Likewise.
1166
5d79adc4
L		 11672019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1168 Lili Cui <lili.cui@intel.com>
1169
1170 * doc/c-i386.texi: Document enqcmd.
1171 * testsuite/gas/i386/enqcmd-intel.d: New file.
1172 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1173 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1174 * testsuite/gas/i386/enqcmd.d: Likewise.
1175 * testsuite/gas/i386/enqcmd.s: Likewise.
1176 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1177 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1178 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1179 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1180 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1181 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1182 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1183 and x86-64-enqcmd.
1184
a9d96ab9
AH		 11852019-06-04 Alan Hayward <alan.hayward@arm.com>
1186
1187 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1188
4f6d070a
AM		 11892019-06-03 Alan Modra <amodra@gmail.com>
1190
1191 * ppc-dis.c (prefix_opcd_indices): Correct size.
1192
a2f4b66c
L		 11932019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1194
1195 PR gas/24625
1196 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1197 Disp8ShiftVL.
1198 * i386-tbl.h: Regenerated.
1199
405b5bd8
AM		 12002019-05-24 Alan Modra <amodra@gmail.com>
1201
1202 * po/POTFILES.in: Regenerate.
1203
8acf1435
PB		 12042019-05-24 Peter Bergner <bergner@linux.ibm.com>
1205 Alan Modra <amodra@gmail.com>
1206
1207 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1208 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1209 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1210 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1211 XTOP>): Define and add entries.
1212 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1213 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1214 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1215 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1216
dd7efa79
PB		 12172019-05-24 Peter Bergner <bergner@linux.ibm.com>
1218 Alan Modra <amodra@gmail.com>
1219
1220 * ppc-dis.c (ppc_opts): Add "future" entry.
1221 (PREFIX_OPCD_SEGS): Define.
1222 (prefix_opcd_indices): New array.
1223 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1224 (lookup_prefix): New function.
1225 (print_insn_powerpc): Handle 64-bit prefix instructions.
1226 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1227 (PMRR, POWERXX): Define.
1228 (prefix_opcodes): New instruction table.
1229 (prefix_num_opcodes): New constant.
1230
79472b45
JM		 12312019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1232
1233 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1234 * configure: Regenerated.
1235 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1236 and cpu/bpf.opc.
1237 (HFILES): Add bpf-desc.h and bpf-opc.h.
1238 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1239 bpf-ibld.c and bpf-opc.c.
1240 (BPF_DEPS): Define.
1241 * Makefile.in: Regenerated.
1242 * disassemble.c (ARCH_bpf): Define.
1243 (disassembler): Add case for bfd_arch_bpf.
1244 (disassemble_init_for_target): Likewise.
1245 (enum epbf_isa_attr): Define.
1246 * disassemble.h: extern print_insn_bpf.
1247 * bpf-asm.c: Generated.
1248 * bpf-opc.h: Likewise.
1249 * bpf-opc.c: Likewise.
1250 * bpf-ibld.c: Likewise.
1251 * bpf-dis.c: Likewise.
1252 * bpf-desc.h: Likewise.
1253 * bpf-desc.c: Likewise.
1254
ba6cd17f
SD		 12552019-05-21 Sudakshina Das <sudi.das@arm.com>
1256
1257 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1258 and VMSR with the new operands.
1259
e39c1607
SD		 12602019-05-21 Sudakshina Das <sudi.das@arm.com>
1261
1262 * arm-dis.c (enum mve_instructions): New enum
1263 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1264 and cneg.
1265 (mve_opcodes): New instructions as above.
1266 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1267 csneg and csel.
1268 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1269
23d00a41
SD		 12702019-05-21 Sudakshina Das <sudi.das@arm.com>
1271
1272 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1273 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1274 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1275 uqshl, urshrl and urshr.
1276 (is_mve_okay_in_it): Add new instructions to TRUE list.
1277 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1278 (print_insn_mve): Updated to accept new %j,
1279 %<bitfield>m and %<bitfield>n patterns.
1280
cd4797ee
FS		 12812019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1282
1283 * mips-opc.c (mips_builtin_opcodes): Change source register
1284 constraint for DAUI.
1285
999b073b
NC		 12862019-05-20 Nick Clifton <nickc@redhat.com>
1287
1288 * po/fr.po: Updated French translation.
1289
14b456f2
AV		 12902019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1291 Michael Collison <michael.collison@arm.com>
1292
1293 * arm-dis.c (thumb32_opcodes): Add new instructions.
1294 (enum mve_instructions): Likewise.
1295 (enum mve_undefined): Add new reasons.
1296 (is_mve_encoding_conflict): Handle new instructions.
1297 (is_mve_undefined): Likewise.
1298 (is_mve_unpredictable): Likewise.
1299 (print_mve_undefined): Likewise.
1300 (print_mve_size): Likewise.
1301
f49bb598
AV		 13022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1303 Michael Collison <michael.collison@arm.com>
1304
1305 * arm-dis.c (thumb32_opcodes): Add new instructions.
1306 (enum mve_instructions): Likewise.
1307 (is_mve_encoding_conflict): Handle new instructions.
1308 (is_mve_undefined): Likewise.
1309 (is_mve_unpredictable): Likewise.
1310 (print_mve_size): Likewise.
1311
56858bea
AV		 13122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1313 Michael Collison <michael.collison@arm.com>
1314
1315 * arm-dis.c (thumb32_opcodes): Add new instructions.
1316 (enum mve_instructions): Likewise.
1317 (is_mve_encoding_conflict): Likewise.
1318 (is_mve_unpredictable): Likewise.
1319 (print_mve_size): Likewise.
1320
e523f101
AV		 13212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1322 Michael Collison <michael.collison@arm.com>
1323
1324 * arm-dis.c (thumb32_opcodes): Add new instructions.
1325 (enum mve_instructions): Likewise.
1326 (is_mve_encoding_conflict): Handle new instructions.
1327 (is_mve_undefined): Likewise.
1328 (is_mve_unpredictable): Likewise.
1329 (print_mve_size): Likewise.
1330
66dcaa5d
AV		 13312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1332 Michael Collison <michael.collison@arm.com>
1333
1334 * arm-dis.c (thumb32_opcodes): Add new instructions.
1335 (enum mve_instructions): Likewise.
1336 (is_mve_encoding_conflict): Handle new instructions.
1337 (is_mve_undefined): Likewise.
1338 (is_mve_unpredictable): Likewise.
1339 (print_mve_size): Likewise.
1340 (print_insn_mve): Likewise.
1341
d052b9b7
AV		 13422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1343 Michael Collison <michael.collison@arm.com>
1344
1345 * arm-dis.c (thumb32_opcodes): Add new instructions.
1346 (print_insn_thumb32): Handle new instructions.
1347
ed63aa17
AV		 13482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1349 Michael Collison <michael.collison@arm.com>
1350
1351 * arm-dis.c (enum mve_instructions): Add new instructions.
1352 (enum mve_undefined): Add new reasons.
1353 (is_mve_encoding_conflict): Handle new instructions.
1354 (is_mve_undefined): Likewise.
1355 (is_mve_unpredictable): Likewise.
1356 (print_mve_undefined): Likewise.
1357 (print_mve_size): Likewise.
1358 (print_mve_shift_n): Likewise.
1359 (print_insn_mve): Likewise.
1360
897b9bbc
AV		 13612019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1362 Michael Collison <michael.collison@arm.com>
1363
1364 * arm-dis.c (enum mve_instructions): Add new instructions.
1365 (is_mve_encoding_conflict): Handle new instructions.
1366 (is_mve_unpredictable): Likewise.
1367 (print_mve_rotate): Likewise.
1368 (print_mve_size): Likewise.
1369 (print_insn_mve): Likewise.
1370
1c8f2df8
AV		 13712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1372 Michael Collison <michael.collison@arm.com>
1373
1374 * arm-dis.c (enum mve_instructions): Add new instructions.
1375 (is_mve_encoding_conflict): Handle new instructions.
1376 (is_mve_unpredictable): Likewise.
1377 (print_mve_size): Likewise.
1378 (print_insn_mve): Likewise.
1379
d3b63143
AV		 13802019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1381 Michael Collison <michael.collison@arm.com>
1382
1383 * arm-dis.c (enum mve_instructions): Add new instructions.
1384 (enum mve_undefined): Add new reasons.
1385 (is_mve_encoding_conflict): Handle new instructions.
1386 (is_mve_undefined): Likewise.
1387 (is_mve_unpredictable): Likewise.
1388 (print_mve_undefined): Likewise.
1389 (print_mve_size): Likewise.
1390 (print_insn_mve): Likewise.
1391
14925797
AV		 13922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1393 Michael Collison <michael.collison@arm.com>
1394
1395 * arm-dis.c (enum mve_instructions): Add new instructions.
1396 (is_mve_encoding_conflict): Handle new instructions.
1397 (is_mve_undefined): Likewise.
1398 (is_mve_unpredictable): Likewise.
1399 (print_mve_size): Likewise.
1400 (print_insn_mve): Likewise.
1401
c507f10b
AV		 14022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1403 Michael Collison <michael.collison@arm.com>
1404
1405 * arm-dis.c (enum mve_instructions): Add new instructions.
1406 (enum mve_unpredictable): Add new reasons.
1407 (enum mve_undefined): Likewise.
1408 (is_mve_okay_in_it): Handle new isntructions.
1409 (is_mve_encoding_conflict): Likewise.
1410 (is_mve_undefined): Likewise.
1411 (is_mve_unpredictable): Likewise.
1412 (print_mve_vmov_index): Likewise.
1413 (print_simd_imm8): Likewise.
1414 (print_mve_undefined): Likewise.
1415 (print_mve_unpredictable): Likewise.
1416 (print_mve_size): Likewise.
1417 (print_insn_mve): Likewise.
1418
bf0b396d
AV		 14192019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1420 Michael Collison <michael.collison@arm.com>
1421
1422 * arm-dis.c (enum mve_instructions): Add new instructions.
1423 (enum mve_unpredictable): Add new reasons.
1424 (enum mve_undefined): Likewise.
1425 (is_mve_encoding_conflict): Handle new instructions.
1426 (is_mve_undefined): Likewise.
1427 (is_mve_unpredictable): Likewise.
1428 (print_mve_undefined): Likewise.
1429 (print_mve_unpredictable): Likewise.
1430 (print_mve_rounding_mode): Likewise.
1431 (print_mve_vcvt_size): Likewise.
1432 (print_mve_size): Likewise.
1433 (print_insn_mve): Likewise.
1434
ef1576a1
AV		 14352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1436 Michael Collison <michael.collison@arm.com>
1437
1438 * arm-dis.c (enum mve_instructions): Add new instructions.
1439 (enum mve_unpredictable): Add new reasons.
1440 (enum mve_undefined): Likewise.
1441 (is_mve_undefined): Handle new instructions.
1442 (is_mve_unpredictable): Likewise.
1443 (print_mve_undefined): Likewise.
1444 (print_mve_unpredictable): Likewise.
1445 (print_mve_size): Likewise.
1446 (print_insn_mve): Likewise.
1447
aef6d006
AV		 14482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1449 Michael Collison <michael.collison@arm.com>
1450
1451 * arm-dis.c (enum mve_instructions): Add new instructions.
1452 (enum mve_undefined): Add new reasons.
1453 (insns): Add new instructions.
1454 (is_mve_encoding_conflict):
1455 (print_mve_vld_str_addr): New print function.
1456 (is_mve_undefined): Handle new instructions.
1457 (is_mve_unpredictable): Likewise.
1458 (print_mve_undefined): Likewise.
1459 (print_mve_size): Likewise.
1460 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1461 (print_insn_mve): Handle new operands.
1462
04d54ace
AV		 14632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1464 Michael Collison <michael.collison@arm.com>
1465
1466 * arm-dis.c (enum mve_instructions): Add new instructions.
1467 (enum mve_unpredictable): Add new reasons.
1468 (is_mve_encoding_conflict): Handle new instructions.
1469 (is_mve_unpredictable): Likewise.
1470 (mve_opcodes): Add new instructions.
1471 (print_mve_unpredictable): Handle new reasons.
1472 (print_mve_register_blocks): New print function.
1473 (print_mve_size): Handle new instructions.
1474 (print_insn_mve): Likewise.
1475
9743db03
AV		 14762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1477 Michael Collison <michael.collison@arm.com>
1478
1479 * arm-dis.c (enum mve_instructions): Add new instructions.
1480 (enum mve_unpredictable): Add new reasons.
1481 (enum mve_undefined): Likewise.
1482 (is_mve_encoding_conflict): Handle new instructions.
1483 (is_mve_undefined): Likewise.
1484 (is_mve_unpredictable): Likewise.
1485 (coprocessor_opcodes): Move NEON VDUP from here...
1486 (neon_opcodes): ... to here.
1487 (mve_opcodes): Add new instructions.
1488 (print_mve_undefined): Handle new reasons.
1489 (print_mve_unpredictable): Likewise.
1490 (print_mve_size): Handle new instructions.
1491 (print_insn_neon): Handle vdup.
1492 (print_insn_mve): Handle new operands.
1493
143275ea
AV		 14942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1495 Michael Collison <michael.collison@arm.com>
1496
1497 * arm-dis.c (enum mve_instructions): Add new instructions.
1498 (enum mve_unpredictable): Add new values.
1499 (mve_opcodes): Add new instructions.
1500 (vec_condnames): New array with vector conditions.
1501 (mve_predicatenames): New array with predicate suffixes.
1502 (mve_vec_sizename): New array with vector sizes.
1503 (enum vpt_pred_state): New enum with vector predication states.
1504 (struct vpt_block): New struct type for vpt blocks.
1505 (vpt_block_state): Global struct to keep track of state.
1506 (mve_extract_pred_mask): New helper function.
1507 (num_instructions_vpt_block): Likewise.
1508 (mark_outside_vpt_block): Likewise.
1509 (mark_inside_vpt_block): Likewise.
1510 (invert_next_predicate_state): Likewise.
1511 (update_next_predicate_state): Likewise.
1512 (update_vpt_block_state): Likewise.
1513 (is_vpt_instruction): Likewise.
1514 (is_mve_encoding_conflict): Add entries for new instructions.
1515 (is_mve_unpredictable): Likewise.
1516 (print_mve_unpredictable): Handle new cases.
1517 (print_instruction_predicate): Likewise.
1518 (print_mve_size): New function.
1519 (print_vec_condition): New function.
1520 (print_insn_mve): Handle vpt blocks and new print operands.
1521
f08d8ce3
AV		 15222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1523
1524 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1525 8, 14 and 15 for Armv8.1-M Mainline.
1526
73cd51e5
AV		 15272019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1528 Michael Collison <michael.collison@arm.com>
1529
1530 * arm-dis.c (enum mve_instructions): New enum.
1531 (enum mve_unpredictable): Likewise.
1532 (enum mve_undefined): Likewise.
1533 (struct mopcode32): New struct.
1534 (is_mve_okay_in_it): New function.
1535 (is_mve_architecture): Likewise.
1536 (arm_decode_field): Likewise.
1537 (arm_decode_field_multiple): Likewise.
1538 (is_mve_encoding_conflict): Likewise.
1539 (is_mve_undefined): Likewise.
1540 (is_mve_unpredictable): Likewise.
1541 (print_mve_undefined): Likewise.
1542 (print_mve_unpredictable): Likewise.
1543 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1544 (print_insn_mve): New function.
1545 (print_insn_thumb32): Handle MVE architecture.
1546 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1547
3076e594
NC		 15482019-05-10 Nick Clifton <nickc@redhat.com>
1549
1550 PR 24538
1551 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1552 end of the table prematurely.
1553
387e7624
FS		 15542019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1555
1556 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1557 macros for R6.
1558
0067be51
AM		 15592019-05-11 Alan Modra <amodra@gmail.com>
1560
1561 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1562 when -Mraw is in effect.
1563
42e6288f
MM		 15642019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1565
1566 * aarch64-dis-2.c: Regenerate.
1567 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1568 (OP_SVE_BBB): New variant set.
1569 (OP_SVE_DDDD): New variant set.
1570 (OP_SVE_HHH): New variant set.
1571 (OP_SVE_HHHU): New variant set.
1572 (OP_SVE_SSS): New variant set.
1573 (OP_SVE_SSSU): New variant set.
1574 (OP_SVE_SHH): New variant set.
1575 (OP_SVE_SBBU): New variant set.
1576 (OP_SVE_DSS): New variant set.
1577 (OP_SVE_DHHU): New variant set.
1578 (OP_SVE_VMV_HSD_BHS): New variant set.
1579 (OP_SVE_VVU_HSD_BHS): New variant set.
1580 (OP_SVE_VVVU_SD_BH): New variant set.
1581 (OP_SVE_VVVU_BHSD): New variant set.
1582 (OP_SVE_VVV_QHD_DBS): New variant set.
1583 (OP_SVE_VVV_HSD_BHS): New variant set.
1584 (OP_SVE_VVV_HSD_BHS2): New variant set.
1585 (OP_SVE_VVV_BHS_HSD): New variant set.
1586 (OP_SVE_VV_BHS_HSD): New variant set.
1587 (OP_SVE_VVV_SD): New variant set.
1588 (OP_SVE_VVU_BHS_HSD): New variant set.
1589 (OP_SVE_VZVV_SD): New variant set.
1590 (OP_SVE_VZVV_BH): New variant set.
1591 (OP_SVE_VZV_SD): New variant set.
1592 (aarch64_opcode_table): Add sve2 instructions.
1593
28ed815a
MM		 15942019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1595
1596 * aarch64-asm-2.c: Regenerated.
1597 * aarch64-dis-2.c: Regenerated.
1598 * aarch64-opc-2.c: Regenerated.
1599 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1600 for SVE_SHLIMM_UNPRED_22.
1601 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1602 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1603 operand.
1604
fd1dc4a0
MM		 16052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1606
1607 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1608 sve_size_tsz_bhs iclass encode.
1609 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1610 sve_size_tsz_bhs iclass decode.
1611
31e36ab3
MM		 16122019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1613
1614 * aarch64-asm-2.c: Regenerated.
1615 * aarch64-dis-2.c: Regenerated.
1616 * aarch64-opc-2.c: Regenerated.
1617 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1618 for SVE_Zm4_11_INDEX.
1619 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1620 (fields): Handle SVE_i2h field.
1621 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1622 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1623
1be5f94f
MM		 16242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1625
1626 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1627 sve_shift_tsz_bhsd iclass encode.
1628 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1629 sve_shift_tsz_bhsd iclass decode.
1630
3c17238b
MM		 16312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1632
1633 * aarch64-asm-2.c: Regenerated.
1634 * aarch64-dis-2.c: Regenerated.
1635 * aarch64-opc-2.c: Regenerated.
1636 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1637 (aarch64_encode_variant_using_iclass): Handle
1638 sve_shift_tsz_hsd iclass encode.
1639 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1640 sve_shift_tsz_hsd iclass decode.
1641 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1642 for SVE_SHRIMM_UNPRED_22.
1643 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1644 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1645 operand.
1646
cd50a87a
MM		 16472019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1648
1649 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1650 sve_size_013 iclass encode.
1651 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1652 sve_size_013 iclass decode.
1653
3c705960
MM		 16542019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1655
1656 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1657 sve_size_bh iclass encode.
1658 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1659 sve_size_bh iclass decode.
1660
0a57e14f
MM		 16612019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1662
1663 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1664 sve_size_sd2 iclass encode.
1665 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1666 sve_size_sd2 iclass decode.
1667 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1668 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1669
c469c864
MM		 16702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1671
1672 * aarch64-asm-2.c: Regenerated.
1673 * aarch64-dis-2.c: Regenerated.
1674 * aarch64-opc-2.c: Regenerated.
1675 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1676 for SVE_ADDR_ZX.
1677 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1678 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1679
116adc27
MM		 16802019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1681
1682 * aarch64-asm-2.c: Regenerated.
1683 * aarch64-dis-2.c: Regenerated.
1684 * aarch64-opc-2.c: Regenerated.
1685 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1686 for SVE_Zm3_11_INDEX.
1687 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1688 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1689 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1690 fields.
1691 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1692
3bd82c86
MM		 16932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1694
1695 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1696 sve_size_hsd2 iclass encode.
1697 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1698 sve_size_hsd2 iclass decode.
1699 * aarch64-opc.c (fields): Handle SVE_size field.
1700 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1701
adccc507
MM		 17022019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1703
1704 * aarch64-asm-2.c: Regenerated.
1705 * aarch64-dis-2.c: Regenerated.
1706 * aarch64-opc-2.c: Regenerated.
1707 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1708 for SVE_IMM_ROT3.
1709 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1710 (fields): Handle SVE_rot3 field.
1711 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1712 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1713
5cd99750
MM		 17142019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1715
1716 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1717 instructions.
1718
7ce2460a
MM		 17192019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1720
1721 * aarch64-tbl.h
1722 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1723 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1724 aarch64_feature_sve2bitperm): New feature sets.
1725 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1726 for feature set addresses.
1727 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1728 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1729
41cee089
FS		 17302019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1731 Faraz Shahbazker <fshahbazker@wavecomp.com>
1732
1733 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1734 argument and set ASE_EVA_R6 appropriately.
1735 (set_default_mips_dis_options): Pass ISA to above.
1736 (parse_mips_dis_option): Likewise.
1737 * mips-opc.c (EVAR6): New macro.
1738 (mips_builtin_opcodes): Add llwpe, scwpe.
1739
b83b4b13
SD		 17402019-05-01 Sudakshina Das <sudi.das@arm.com>
1741
1742 * aarch64-asm-2.c: Regenerated.
1743 * aarch64-dis-2.c: Regenerated.
1744 * aarch64-opc-2.c: Regenerated.
1745 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1746 AARCH64_OPND_TME_UIMM16.
1747 (aarch64_print_operand): Likewise.
1748 * aarch64-tbl.h (QL_IMM_NIL): New.
1749 (TME): New.
1750 (_TME_INSN): New.
1751 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1752
4a90ce95
JD		 17532019-04-29 John Darrington <john@darrington.wattle.id.au>
1754
1755 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1756
a45328b9
AB		 17572019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1758 Faraz Shahbazker <fshahbazker@wavecomp.com>
1759
1760 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1761
d10be0cb
JD		 17622019-04-24 John Darrington <john@darrington.wattle.id.au>
1763
1764 * s12z-opc.h: Add extern "C" bracketing to help
1765 users who wish to use this interface in c++ code.
1766
a679f24e
JD		 17672019-04-24 John Darrington <john@darrington.wattle.id.au>
1768
1769 * s12z-opc.c (bm_decode): Handle bit map operations with the
1770 "reserved0" mode.
1771
32c36c3c
AV		 17722019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1773
1774 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1775 specifier. Add entries for VLDR and VSTR of system registers.
1776 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1777 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1778 of %J and %K format specifier.
1779
efd6b359
AV		 17802019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1781
1782 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1783 Add new entries for VSCCLRM instruction.
1784 (print_insn_coprocessor): Handle new %C format control code.
1785
6b0dd094
AV		 17862019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1787
1788 * arm-dis.c (enum isa): New enum.
1789 (struct sopcode32): New structure.
1790 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1791 set isa field of all current entries to ANY.
1792 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1793 Only match an entry if its isa field allows the current mode.
1794
4b5a202f
AV		 17952019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1796
1797 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1798 CLRM.
1799 (print_insn_thumb32): Add logic to print %n CLRM register list.
1800
60f993ce
AV		 18012019-04-15 Sudakshina Das <sudi.das@arm.com>
1802
1803 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1804 and %Q patterns.
1805
f6b2b12d
AV		 18062019-04-15 Sudakshina Das <sudi.das@arm.com>
1807
1808 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1809 (print_insn_thumb32): Edit the switch case for %Z.
1810
1889da70
AV		 18112019-04-15 Sudakshina Das <sudi.das@arm.com>
1812
1813 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1814
65d1bc05
AV		 18152019-04-15 Sudakshina Das <sudi.das@arm.com>
1816
1817 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1818
1caf72a5
AV		 18192019-04-15 Sudakshina Das <sudi.das@arm.com>
1820
1821 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1822
f1c7f421
AV		 18232019-04-15 Sudakshina Das <sudi.das@arm.com>
1824
1825 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1826 Arm register with r13 and r15 unpredictable.
1827 (thumb32_opcodes): New instructions for bfx and bflx.
1828
4389b29a
AV		 18292019-04-15 Sudakshina Das <sudi.das@arm.com>
1830
1831 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1832
e5d6e09e
AV		 18332019-04-15 Sudakshina Das <sudi.das@arm.com>
1834
1835 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1836
e12437dc
AV		 18372019-04-15 Sudakshina Das <sudi.das@arm.com>
1838
1839 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1840
031254f2
AV		 18412019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1842
1843 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1844
e5a557ac
JD		 18452019-04-12 John Darrington <john@darrington.wattle.id.au>
1846
1847 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1848 "optr". ("operator" is a reserved word in c++).
1849
bd7ceb8d
SD		 18502019-04-11 Sudakshina Das <sudi.das@arm.com>
1851
1852 * aarch64-opc.c (aarch64_print_operand): Add case for
1853 AARCH64_OPND_Rt_SP.
1854 (verify_constraints): Likewise.
1855 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1856 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1857 to accept Rt|SP as first operand.
1858 (AARCH64_OPERANDS): Add new Rt_SP.
1859 * aarch64-asm-2.c: Regenerated.
1860 * aarch64-dis-2.c: Regenerated.
1861 * aarch64-opc-2.c: Regenerated.
1862
e54010f1
SD		 18632019-04-11 Sudakshina Das <sudi.das@arm.com>
1864
1865 * aarch64-asm-2.c: Regenerated.
1866 * aarch64-dis-2.c: Likewise.
1867 * aarch64-opc-2.c: Likewise.
1868 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1869
7e96e219
RS		 18702019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1871
1872 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1873
6f2791d5
L		 18742019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1875
1876 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1877 * i386-init.h: Regenerated.
1878
e392bad3
AM		 18792019-04-07 Alan Modra <amodra@gmail.com>
1880
1881 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1882 op_separator to control printing of spaces, comma and parens
1883 rather than need_comma, need_paren and spaces vars.
1884
dffaa15c
AM		 18852019-04-07 Alan Modra <amodra@gmail.com>
1886
1887 PR 24421
1888 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1889 (print_insn_neon, print_insn_arm): Likewise.
1890
d6aab7a1
XG		 18912019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1892
1893 * i386-dis-evex.h (evex_table): Updated to support BF16
1894 instructions.
1895 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1896 and EVEX_W_0F3872_P_3.
1897 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1898 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1899 * i386-opc.h (enum): Add CpuAVX512_BF16.
1900 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1901 * i386-opc.tbl: Add AVX512 BF16 instructions.
1902 * i386-init.h: Regenerated.
1903 * i386-tbl.h: Likewise.
1904
66e85460
AM		 19052019-04-05 Alan Modra <amodra@gmail.com>
1906
1907 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1908 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1909 to favour printing of "-" branch hint when using the "y" bit.
1910 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1911
c2b1c275
AM		 19122019-04-05 Alan Modra <amodra@gmail.com>
1913
1914 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1915 opcode until first operand is output.
1916
aae9718e
PB		 19172019-04-04 Peter Bergner <bergner@linux.ibm.com>
1918
1919 PR gas/24349
1920 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1921 (valid_bo_post_v2): Add support for 'at' branch hints.
1922 (insert_bo): Only error on branch on ctr.
1923 (get_bo_hint_mask): New function.
1924 (insert_boe): Add new 'branch_taken' formal argument. Add support
1925 for inserting 'at' branch hints.
1926 (extract_boe): Add new 'branch_taken' formal argument. Add support
1927 for extracting 'at' branch hints.
1928 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1929 (BOE): Delete operand.
1930 (BOM, BOP): New operands.
1931 (RM): Update value.
1932 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1933 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1934 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1935 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1936 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1937 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1938 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1939 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1940 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1941 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1942 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1943 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1944 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1945 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1946 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1947 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1948 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1949 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1950 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1951 bttarl+>: New extended mnemonics.
1952
96a86c01
AM		 19532019-03-28 Alan Modra <amodra@gmail.com>
1954
1955 PR 24390
1956 * ppc-opc.c (BTF): Define.
1957 (powerpc_opcodes): Use for mtfsb*.
1958 * ppc-dis.c (print_insn_powerpc): Print fields with both
1959 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1960
796d6298
TC		 19612019-03-25 Tamar Christina <tamar.christina@arm.com>
1962
1963 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1964 (mapping_symbol_for_insn): Implement new algorithm.
1965 (print_insn): Remove duplicate code.
1966
60df3720
TC		 19672019-03-25 Tamar Christina <tamar.christina@arm.com>
1968
1969 * aarch64-dis.c (print_insn_aarch64):
1970 Implement override.
1971
51457761
TC		 19722019-03-25 Tamar Christina <tamar.christina@arm.com>
1973
1974 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1975 order.
1976
53b2f36b
TC		 19772019-03-25 Tamar Christina <tamar.christina@arm.com>
1978
1979 * aarch64-dis.c (last_stop_offset): New.
1980 (print_insn_aarch64): Use stop_offset.
1981
89199bb5
L		 19822019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1983
1984 PR gas/24359
1985 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1986 CPU_ANY_AVX2_FLAGS.
1987 * i386-init.h: Regenerated.
1988
97ed31ae
L		 19892019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1990
1991 PR gas/24348
1992 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1993 vmovdqu16, vmovdqu32 and vmovdqu64.
1994 * i386-tbl.h: Regenerated.
1995
0919bfe9
AK		 19962019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1997
1998 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1999 from vstrszb, vstrszh, and vstrszf.
2000
20012019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2002
2003 * s390-opc.txt: Add instruction descriptions.
2004
21820ebe
JW		 20052019-02-08 Jim Wilson <jimw@sifive.com>
2006
2007 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2008 <bne>: Likewise.
2009
f7dd2fb2
TC		 20102019-02-07 Tamar Christina <tamar.christina@arm.com>
2011
2012 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2013
6456d318
TC		 20142019-02-07 Tamar Christina <tamar.christina@arm.com>
2015
2016 PR binutils/23212
2017 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2018 * aarch64-opc.c (verify_elem_sd): New.
2019 (fields): Add FLD_sz entr.
2020 * aarch64-tbl.h (_SIMD_INSN): New.
2021 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2022 fmulx scalar and vector by element isns.
2023
4a83b610
NC		 20242019-02-07 Nick Clifton <nickc@redhat.com>
2025
2026 * po/sv.po: Updated Swedish translation.
2027
fc60b8c8
AK		 20282019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2029
2030 * s390-mkopc.c (main): Accept arch13 as cpu string.
2031 * s390-opc.c: Add new instruction formats and instruction opcode
2032 masks.
2033 * s390-opc.txt: Add new arch13 instructions.
2034
e10620d3
TC		 20352019-01-25 Sudakshina Das <sudi.das@arm.com>
2036
2037 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2038 (aarch64_opcode): Change encoding for stg, stzg
2039 st2g and st2zg.
2040 * aarch64-asm-2.c: Regenerated.
2041 * aarch64-dis-2.c: Regenerated.
2042 * aarch64-opc-2.c: Regenerated.
2043
20a4ca55
SD		 20442019-01-25 Sudakshina Das <sudi.das@arm.com>
2045
2046 * aarch64-asm-2.c: Regenerated.
2047 * aarch64-dis-2.c: Likewise.
2048 * aarch64-opc-2.c: Likewise.
2049 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2050
550fd7bf
SD		 20512019-01-25 Sudakshina Das <sudi.das@arm.com>
2052 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2053
2054 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2055 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2056 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2057 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2058 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2059 case for ldstgv_indexed.
2060 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2061 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2062 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2063 * aarch64-asm-2.c: Regenerated.
2064 * aarch64-dis-2.c: Regenerated.
2065 * aarch64-opc-2.c: Regenerated.
2066
d9938630
NC		 20672019-01-23 Nick Clifton <nickc@redhat.com>
2068
2069 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2070
375cd423
NC		 20712019-01-21 Nick Clifton <nickc@redhat.com>
2072
2073 * po/de.po: Updated German translation.
2074 * po/uk.po: Updated Ukranian translation.
2075
57299f48
CX		 20762019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2077 * mips-dis.c (mips_arch_choices): Fix typo in
2078 gs464, gs464e and gs264e descriptors.
2079
f48dfe41
NC		 20802019-01-19 Nick Clifton <nickc@redhat.com>
2081
2082 * configure: Regenerate.
2083 * po/opcodes.pot: Regenerate.
2084
f974f26c
NC		 20852018-06-24 Nick Clifton <nickc@redhat.com>
2086
2087 2.32 branch created.
2088
39f286cd
JD		 20892019-01-09 John Darrington <john@darrington.wattle.id.au>
2090
448b8ca8
JD		 2091 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2092 if it is null.
2093 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2094 zero.
2095
3107326d
AP		 20962019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2097
2098 * configure: Regenerate.
2099
7e9ca91e
AM		 21002019-01-07 Alan Modra <amodra@gmail.com>
2101
2102 * configure: Regenerate.
2103 * po/POTFILES.in: Regenerate.
2104
ef1ad42b
JD		 21052019-01-03 John Darrington <john@darrington.wattle.id.au>
2106
2107 * s12z-opc.c: New file.
2108 * s12z-opc.h: New file.
2109 * s12z-dis.c: Removed all code not directly related to display
2110 of instructions. Used the interface provided by the new files
2111 instead.
2112 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2113 * Makefile.in: Regenerate.
ef1ad42b 2114 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2115 * configure: Regenerate.
ef1ad42b 2116
82704155
AM		 21172019-01-01 Alan Modra <amodra@gmail.com>
2118
2119 Update year range in copyright notice of all files.
2120
d5c04e1b 2121For older changes see ChangeLog-2018
3499769a 2122\f
d5c04e1b 2123Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2124
2125Copying and distribution of this file, with or without modification,
2126are permitted in any medium without royalty provided the copyright
2127notice and this notice are preserved.
2128
2129Local Variables:
2130mode: change-log
2131left-margin: 8
2132fill-column: 74
2133version-control: never
2134End:
GDB Binutils - Deliverables
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