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i386: Set ELF_MAXPAGESIZE to 0x1000 for VxWorks
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
957f6b39
TC		 12017-04-24 Tamar Christina <tamar.christina@arm.com>
2
3 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
4 arguments.
5
a8cc8a54
AM		 62017-04-22 Alexander Fedotov <alfedotov@gmail.com>
7 Alan Modra <amodra@gmail.com>
8
9 * ppc-opc.c (ELEV): Define.
10 (vle_opcodes): Add se_rfgi and e_sc.
11 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
12 for E200Z4.
13
3ab87b68
JM		 142017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
15
16 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
17
792f174f
NC		 182017-04-21 Nick Clifton <nickc@redhat.com>
19
20 PR binutils/21380
21 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
22 LD3R and LD4R.
23
42742084
AM		 242017-04-13 Alan Modra <amodra@gmail.com>
25
26 * epiphany-desc.c: Regenerate.
27 * fr30-desc.c: Regenerate.
28 * frv-desc.c: Regenerate.
29 * ip2k-desc.c: Regenerate.
30 * iq2000-desc.c: Regenerate.
31 * lm32-desc.c: Regenerate.
32 * m32c-desc.c: Regenerate.
33 * m32r-desc.c: Regenerate.
34 * mep-desc.c: Regenerate.
35 * mt-desc.c: Regenerate.
36 * or1k-desc.c: Regenerate.
37 * xc16x-desc.c: Regenerate.
38 * xstormy16-desc.c: Regenerate.
39
9a85b496
AM		 402017-04-11 Alan Modra <amodra@gmail.com>
41
ef85eab0 42 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 43 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
44 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 45 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
46 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 47 (PPCVSX2): Define as PPC_OPCODE_POWER8.
48 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 49 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 50 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 51
62adc510
AM		 522017-04-10 Alan Modra <amodra@gmail.com>
53
54 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
55 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
56 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
57 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
58
aa808707
PC		 592017-04-09 Pip Cet <pipcet@gmail.com>
60
61 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
62 appropriate floating-point precision directly.
63
ac8f0f72
AM		 642017-04-07 Alan Modra <amodra@gmail.com>
65
66 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
67 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
68 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
69 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
70 vector instructions with E6500 not PPCVEC2.
71
62ecb94c
PC		 722017-04-06 Pip Cet <pipcet@gmail.com>
73
74 * Makefile.am: Add wasm32-dis.c.
75 * configure.ac: Add wasm32-dis.c to wasm32 target.
76 * disassemble.c: Add wasm32 disassembler code.
77 * wasm32-dis.c: New file.
78 * Makefile.in: Regenerate.
79 * configure: Regenerate.
80 * po/POTFILES.in: Regenerate.
81 * po/opcodes.pot: Regenerate.
82
f995bbe8
PA		 832017-04-05 Pedro Alves <palves@redhat.com>
84
85 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
86 * arm-dis.c (parse_arm_disassembler_options): Constify.
87 * ppc-dis.c (powerpc_init_dialect): Constify local.
88 * vax-dis.c (parse_disassembler_options): Constify.
89
b5292032
PD		 902017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
91
92 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
93 RISCV_GP_SYMBOL.
94
f96bd6c2
PC		 952017-03-30 Pip Cet <pipcet@gmail.com>
96
97 * configure.ac: Add (empty) bfd_wasm32_arch target.
98 * configure: Regenerate
99 * po/opcodes.pot: Regenerate.
100
f7c514a3
JM		 1012017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
102
103 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
104 OSA2015.
105 * opcodes/sparc-opc.c (asi_table): New ASIs.
106
52be03fd
AM		 1072017-03-29 Alan Modra <amodra@gmail.com>
108
109 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
110 "raw" option.
111 (lookup_powerpc): Don't special case -1 dialect. Handle
112 PPC_OPCODE_RAW.
113 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
114 lookup_powerpc call, pass it on second.
115
9b753937
AM		 1162017-03-27 Alan Modra <amodra@gmail.com>
117
118 PR 21303
119 * ppc-dis.c (struct ppc_mopt): Comment.
120 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
121
c0c31e91
RZ		 1222017-03-27 Rinat Zelig <rinat@mellanox.com>
123
124 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
125 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
126 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
127 (insert_nps_misc_imm_offset): New function.
128 (extract_nps_misc imm_offset): New function.
129 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
130 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
131
2253c8f0
AK		 1322017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
133
134 * s390-mkopc.c (main): Remove vx2 check.
135 * s390-opc.txt: Remove vx2 instruction flags.
136
645d3342
RZ		 1372017-03-21 Rinat Zelig <rinat@mellanox.com>
138
139 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
140 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
141 (insert_nps_imm_offset): New function.
142 (extract_nps_imm_offset): New function.
143 (insert_nps_imm_entry): New function.
144 (extract_nps_imm_entry): New function.
145
4b94dd2d
AM		 1462017-03-17 Alan Modra <amodra@gmail.com>
147
148 PR 21248
149 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
150 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
151 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
152
b416fe87
KC		 1532017-03-14 Kito Cheng <kito.cheng@gmail.com>
154
155 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
156 <c.andi>: Likewise.
157 <c.addiw> Likewise.
158
03b039a5
KC		 1592017-03-14 Kito Cheng <kito.cheng@gmail.com>
160
161 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
162
2c232b83
AW		 1632017-03-13 Andrew Waterman <andrew@sifive.com>
164
165 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
166 <srl> Likewise.
167 <srai> Likewise.
168 <sra> Likewise.
169
86fa6981
L		 1702017-03-09 H.J. Lu <hongjiu.lu@intel.com>
171
172 * i386-gen.c (opcode_modifiers): Replace S with Load.
173 * i386-opc.h (S): Removed.
174 (Load): New.
175 (i386_opcode_modifier): Replace s with load.
176 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
177 and {evex}. Replace S with Load.
178 * i386-tbl.h: Regenerated.
179
c1fe188b
L		 1802017-03-09 H.J. Lu <hongjiu.lu@intel.com>
181
182 * i386-opc.tbl: Use CpuCET on rdsspq.
183 * i386-tbl.h: Regenerated.
184
4b8b687e
PB		 1852017-03-08 Peter Bergner <bergner@vnet.ibm.com>
186
187 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
188 <vsx>: Do not use PPC_OPCODE_VSX3;
189
1437d063
PB		 1902017-03-08 Peter Bergner <bergner@vnet.ibm.com>
191
192 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
193
603555e5
L		 1942017-03-06 H.J. Lu <hongjiu.lu@intel.com>
195
196 * i386-dis.c (REG_0F1E_MOD_3): New enum.
197 (MOD_0F1E_PREFIX_1): Likewise.
198 (MOD_0F38F5_PREFIX_2): Likewise.
199 (MOD_0F38F6_PREFIX_0): Likewise.
200 (RM_0F1E_MOD_3_REG_7): Likewise.
201 (PREFIX_MOD_0_0F01_REG_5): Likewise.
202 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
203 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
204 (PREFIX_0F1E): Likewise.
205 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
206 (PREFIX_0F38F5): Likewise.
207 (dis386_twobyte): Use PREFIX_0F1E.
208 (reg_table): Add REG_0F1E_MOD_3.
209 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
210 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
211 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
212 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
213 (three_byte_table): Use PREFIX_0F38F5.
214 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
215 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
216 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
217 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
218 PREFIX_MOD_3_0F01_REG_5_RM_2.
219 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
220 (cpu_flags): Add CpuCET.
221 * i386-opc.h (CpuCET): New enum.
222 (CpuUnused): Commented out.
223 (i386_cpu_flags): Add cpucet.
224 * i386-opc.tbl: Add Intel CET instructions.
225 * i386-init.h: Regenerated.
226 * i386-tbl.h: Likewise.
227
73f07bff
AM		 2282017-03-06 Alan Modra <amodra@gmail.com>
229
230 PR 21124
231 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
232 (extract_raq, extract_ras, extract_rbx): New functions.
233 (powerpc_operands): Use opposite corresponding insert function.
234 (Q_MASK): Define.
235 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
236 register restriction.
237
65b48a81
PB		 2382017-02-28 Peter Bergner <bergner@vnet.ibm.com>
239
240 * disassemble.c Include "safe-ctype.h".
241 (disassemble_init_for_target): Handle s390 init.
242 (remove_whitespace_and_extra_commas): New function.
243 (disassembler_options_cmp): Likewise.
244 * arm-dis.c: Include "libiberty.h".
245 (NUM_ELEM): Delete.
246 (regnames): Use long disassembler style names.
247 Add force-thumb and no-force-thumb options.
248 (NUM_ARM_REGNAMES): Rename from this...
249 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
250 (get_arm_regname_num_options): Delete.
251 (set_arm_regname_option): Likewise.
252 (get_arm_regnames): Likewise.
253 (parse_disassembler_options): Likewise.
254 (parse_arm_disassembler_option): Rename from this...
255 (parse_arm_disassembler_options): ...to this. Make static.
256 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
257 (print_insn): Use parse_arm_disassembler_options.
258 (disassembler_options_arm): New function.
259 (print_arm_disassembler_options): Handle updated regnames.
260 * ppc-dis.c: Include "libiberty.h".
261 (ppc_opts): Add "32" and "64" entries.
262 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
263 (powerpc_init_dialect): Add break to switch statement.
264 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
265 (disassembler_options_powerpc): New function.
266 (print_ppc_disassembler_options): Use ARRAY_SIZE.
267 Remove printing of "32" and "64".
268 * s390-dis.c: Include "libiberty.h".
269 (init_flag): Remove unneeded variable.
270 (struct s390_options_t): New structure type.
271 (options): New structure.
272 (init_disasm): Rename from this...
273 (disassemble_init_s390): ...to this. Add initializations for
274 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
275 (print_insn_s390): Delete call to init_disasm.
276 (disassembler_options_s390): New function.
277 (print_s390_disassembler_options): Print using information from
278 struct 'options'.
279 * po/opcodes.pot: Regenerate.
280
15c7c1d8
JB		 2812017-02-28 Jan Beulich <jbeulich@suse.com>
282
283 * i386-dis.c (PCMPESTR_Fixup): New.
284 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
285 (prefix_table): Use PCMPESTR_Fixup.
286 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
287 PCMPESTR_Fixup.
288 (vex_w_table): Delete VPCMPESTR{I,M} entries.
289 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
290 Split 64-bit and non-64-bit variants.
291 * opcodes/i386-tbl.h: Re-generate.
292
582e12bf
RS		 2932017-02-24 Richard Sandiford <richard.sandiford@arm.com>
294
295 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
296 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
297 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
298 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
299 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
300 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
301 (OP_SVE_V_HSD): New macros.
302 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
303 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
304 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
305 (aarch64_opcode_table): Add new SVE instructions.
306 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
307 for rotation operands. Add new SVE operands.
308 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
309 (ins_sve_quad_index): Likewise.
310 (ins_imm_rotate): Split into...
311 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
312 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
313 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
314 functions.
315 (aarch64_ins_sve_addr_ri_s4): New function.
316 (aarch64_ins_sve_quad_index): Likewise.
317 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
318 * aarch64-asm-2.c: Regenerate.
319 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
320 (ext_sve_quad_index): Likewise.
321 (ext_imm_rotate): Split into...
322 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
323 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
324 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
325 functions.
326 (aarch64_ext_sve_addr_ri_s4): New function.
327 (aarch64_ext_sve_quad_index): Likewise.
328 (aarch64_ext_sve_index): Allow quad indices.
329 (do_misc_decoding): Likewise.
330 * aarch64-dis-2.c: Regenerate.
331 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
332 aarch64_field_kinds.
333 (OPD_F_OD_MASK): Widen by one bit.
334 (OPD_F_NO_ZR): Bump accordingly.
335 (get_operand_field_width): New function.
336 * aarch64-opc.c (fields): Add new SVE fields.
337 (operand_general_constraint_met_p): Handle new SVE operands.
338 (aarch64_print_operand): Likewise.
339 * aarch64-opc-2.c: Regenerate.
340
f482d304
RS		 3412017-02-24 Richard Sandiford <richard.sandiford@arm.com>
342
343 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
344 (aarch64_feature_compnum): ...this.
345 (SIMD_V8_3): Replace with...
346 (COMPNUM): ...this.
347 (CNUM_INSN): New macro.
348 (aarch64_opcode_table): Use it for the complex number instructions.
349
7db2c588
JB		 3502017-02-24 Jan Beulich <jbeulich@suse.com>
351
352 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
353
1e9d41d4
SL		 3542017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
355
356 Add support for associating SPARC ASIs with an architecture level.
357 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
358 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
359 decoding of SPARC ASIs.
360
53c4d625
JB		 3612017-02-23 Jan Beulich <jbeulich@suse.com>
362
363 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
364 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
365
11648de5
JB		 3662017-02-21 Jan Beulich <jbeulich@suse.com>
367
368 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
369 1 (instead of to itself). Correct typo.
370
f98d33be
AW		 3712017-02-14 Andrew Waterman <andrew@sifive.com>
372
373 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
374 pseudoinstructions.
375
773fb663
RS		 3762017-02-15 Richard Sandiford <richard.sandiford@arm.com>
377
378 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
379 (aarch64_sys_reg_supported_p): Handle them.
380
cc07cda6
CZ		 3812017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
382
383 * arc-opc.c (UIMM6_20R): Define.
384 (SIMM12_20): Use above.
385 (SIMM12_20R): Define.
386 (SIMM3_5_S): Use above.
387 (UIMM7_A32_11R_S): Define.
388 (UIMM7_9_S): Use above.
389 (UIMM3_13R_S): Define.
390 (SIMM11_A32_7_S): Use above.
391 (SIMM9_8R): Define.
392 (UIMM10_A32_8_S): Use above.
393 (UIMM8_8R_S): Define.
394 (W6): Use above.
395 (arc_relax_opcodes): Use all above defines.
396
66a5a740
VG		 3972017-02-15 Vineet Gupta <vgupta@synopsys.com>
398
399 * arc-regs.h: Distinguish some of the registers different on
400 ARC700 and HS38 cpus.
401
7e0de605
AM		 4022017-02-14 Alan Modra <amodra@gmail.com>
403
404 PR 21118
405 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
406 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
407
54064fdb
AM		 4082017-02-11 Stafford Horne <shorne@gmail.com>
409 Alan Modra <amodra@gmail.com>
410
411 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
412 Use insn_bytes_value and insn_int_value directly instead. Don't
413 free allocated memory until function exit.
414
dce75bf9
NP		 4152017-02-10 Nicholas Piggin <npiggin@gmail.com>
416
417 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
418
1b7e3d2f
NC		 4192017-02-03 Nick Clifton <nickc@redhat.com>
420
421 PR 21096
422 * aarch64-opc.c (print_register_list): Ensure that the register
423 list index will fir into the tb buffer.
424 (print_register_offset_address): Likewise.
425 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
426
8ec5cf65
AD		 4272017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
428
429 PR 21056
430 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
431 instructions when the previous fetch packet ends with a 32-bit
432 instruction.
433
a1aa5e81
DD		 4342017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
435
436 * pru-opc.c: Remove vague reference to a future GDB port.
437
add3afb2
NC		 4382017-01-20 Nick Clifton <nickc@redhat.com>
439
440 * po/ga.po: Updated Irish translation.
441
c13a63b0
SN		 4422017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
443
444 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
445
9608051a
YQ		 4462017-01-13 Yao Qi <yao.qi@linaro.org>
447
448 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
449 if FETCH_DATA returns 0.
450 (m68k_scan_mask): Likewise.
451 (print_insn_m68k): Update code to handle -1 return value.
452
f622ea96
YQ		 4532017-01-13 Yao Qi <yao.qi@linaro.org>
454
455 * m68k-dis.c (enum print_insn_arg_error): New.
456 (NEXTBYTE): Replace -3 with
457 PRINT_INSN_ARG_MEMORY_ERROR.
458 (NEXTULONG): Likewise.
459 (NEXTSINGLE): Likewise.
460 (NEXTDOUBLE): Likewise.
461 (NEXTDOUBLE): Likewise.
462 (NEXTPACKED): Likewise.
463 (FETCH_ARG): Likewise.
464 (FETCH_DATA): Update comments.
465 (print_insn_arg): Update comments. Replace magic numbers with
466 enum.
467 (match_insn_m68k): Likewise.
468
620214f7
IT		 4692017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
470
471 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
472 * i386-dis-evex.h (evex_table): Updated.
473 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
474 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
475 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
476 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
477 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
478 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
479 * i386-init.h: Regenerate.
480 * i386-tbl.h: Ditto.
481
d95014a2
YQ		 4822017-01-12 Yao Qi <yao.qi@linaro.org>
483
484 * msp430-dis.c (msp430_singleoperand): Return -1 if
485 msp430dis_opcode_signed returns false.
486 (msp430_doubleoperand): Likewise.
487 (msp430_branchinstr): Return -1 if
488 msp430dis_opcode_unsigned returns false.
489 (msp430x_calla_instr): Likewise.
490 (print_insn_msp430): Likewise.
491
0ae60c3e
NC		 4922017-01-05 Nick Clifton <nickc@redhat.com>
493
494 PR 20946
495 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
496 could not be matched.
497 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
498 NULL.
499
d74d4880
SN		 5002017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
501
502 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
503 (aarch64_opcode_table): Use RCPC_INSN.
504
cc917fd9
KC		 5052017-01-03 Kito Cheng <kito.cheng@gmail.com>
506
507 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
508 extension.
509 * riscv-opcodes/all-opcodes: Likewise.
510
b52d3cfc
DP		 5112017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
512
513 * riscv-dis.c (print_insn_args): Add fall through comment.
514
f90c58d5
NC		 5152017-01-03 Nick Clifton <nickc@redhat.com>
516
517 * po/sr.po: New Serbian translation.
518 * configure.ac (ALL_LINGUAS): Add sr.
519 * configure: Regenerate.
520
f47b0d4a
AM		 5212017-01-02 Alan Modra <amodra@gmail.com>
522
523 * epiphany-desc.h: Regenerate.
524 * epiphany-opc.h: Regenerate.
525 * fr30-desc.h: Regenerate.
526 * fr30-opc.h: Regenerate.
527 * frv-desc.h: Regenerate.
528 * frv-opc.h: Regenerate.
529 * ip2k-desc.h: Regenerate.
530 * ip2k-opc.h: Regenerate.
531 * iq2000-desc.h: Regenerate.
532 * iq2000-opc.h: Regenerate.
533 * lm32-desc.h: Regenerate.
534 * lm32-opc.h: Regenerate.
535 * m32c-desc.h: Regenerate.
536 * m32c-opc.h: Regenerate.
537 * m32r-desc.h: Regenerate.
538 * m32r-opc.h: Regenerate.
539 * mep-desc.h: Regenerate.
540 * mep-opc.h: Regenerate.
541 * mt-desc.h: Regenerate.
542 * mt-opc.h: Regenerate.
543 * or1k-desc.h: Regenerate.
544 * or1k-opc.h: Regenerate.
545 * xc16x-desc.h: Regenerate.
546 * xc16x-opc.h: Regenerate.
547 * xstormy16-desc.h: Regenerate.
548 * xstormy16-opc.h: Regenerate.
549
2571583a
AM		 5502017-01-02 Alan Modra <amodra@gmail.com>
551
552 Update year range in copyright notice of all files.
553
5c1ad6b5 554For older changes see ChangeLog-2016
3499769a 555\f
5c1ad6b5 556Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 557
558Copying and distribution of this file, with or without modification,
559are permitted in any medium without royalty provided the copyright
560notice and this notice are preserved.
561
562Local Variables:
563mode: change-log
564left-margin: 8
565fill-column: 74
566version-control: never
567End:
GDB Binutils - Deliverables
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