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cpu,opcodes,gas: fix arguments to ldabs and ldind eBPF instructions
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
92434a14
JM		 12019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
2
3 * bpf-desc.c: Regenerate.
4 * bpf-opc.c: Likewise.
5
43dd7626
HPN		 62019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
7
8 * arm-dis.c (print_insn_coprocessor): Rename index to
9 index_operand.
10
98602811
JW		 112019-07-05 Kito Cheng <kito.cheng@sifive.com>
12
13 * riscv-opc.c (riscv_insn_types): Add r4 type.
14
15 * riscv-opc.c (riscv_insn_types): Add b and j type.
16
17 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
18 format for sb type and correct s type.
19
01c1ee4a
RS		 202019-07-02 Richard Sandiford <richard.sandiford@arm.com>
21
22 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
23 SVE FMOV alias of FCPY.
24
83adff69
RS		 252019-07-02 Richard Sandiford <richard.sandiford@arm.com>
26
27 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
28 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
29
89418844
RS		 302019-07-02 Richard Sandiford <richard.sandiford@arm.com>
31
32 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
33 registers in an instruction prefixed by MOVPRFX.
34
41be57ca
MM		 352019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
36
37 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
38 sve_size_13 icode to account for variant behaviour of
39 pmull{t,b}.
40 * aarch64-dis-2.c: Regenerate.
41 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
42 sve_size_13 icode to account for variant behaviour of
43 pmull{t,b}.
44 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
45 (OP_SVE_VVV_Q_D): Add new qualifier.
46 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
47 (struct aarch64_opcode): Split pmull{t,b} into those requiring
48 AES and those not.
49
9d3bf266
JB		 502019-07-01 Jan Beulich <jbeulich@suse.com>
51
52 * opcodes/i386-gen.c (operand_type_init): Remove
53 OPERAND_TYPE_VEC_IMM4 entry.
54 (operand_types): Remove Vec_Imm4.
55 * opcodes/i386-opc.h (Vec_Imm4): Delete.
56 (union i386_operand_type): Remove vec_imm4.
57 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
58 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
59
c3949f43
JB		 602019-07-01 Jan Beulich <jbeulich@suse.com>
61
62 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
63 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
64 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
65 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
66 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
67 monitorx, mwaitx): Drop ImmExt from operand-less forms.
68 * i386-tbl.h: Re-generate.
69
5641ec01
JB		 702019-07-01 Jan Beulich <jbeulich@suse.com>
71
72 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
73 register operands.
74 * i386-tbl.h: Re-generate.
75
79dec6b7
JB		 762019-07-01 Jan Beulich <jbeulich@suse.com>
77
78 * i386-opc.tbl (C): New.
79 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
80 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
81 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
82 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
83 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
84 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
85 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
86 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
87 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
88 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
89 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
90 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
91 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
92 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
93 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
94 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
95 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
96 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
97 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
98 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
99 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
100 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
101 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
102 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
103 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
104 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
105 flavors.
106 * i386-tbl.h: Re-generate.
107
a0a1771e
JB		 1082019-07-01 Jan Beulich <jbeulich@suse.com>
109
110 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
111 register operands.
112 * i386-tbl.h: Re-generate.
113
cd546e7b
JB		 1142019-07-01 Jan Beulich <jbeulich@suse.com>
115
116 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
117 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
118 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
119 * i386-tbl.h: Re-generate.
120
e3bba3fc
JB		 1212019-07-01 Jan Beulich <jbeulich@suse.com>
122
123 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
124 Disp8MemShift from register only templates.
125 * i386-tbl.h: Re-generate.
126
36cc073e
JB		 1272019-07-01 Jan Beulich <jbeulich@suse.com>
128
129 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
130 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
131 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
132 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
133 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
134 EVEX_W_0F11_P_3_M_1): Delete.
135 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
136 EVEX_W_0F11_P_3): New.
137 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
138 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
139 MOD_EVEX_0F11_PREFIX_3 table entries.
140 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
141 PREFIX_EVEX_0F11 table entries.
142 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
143 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
144 EVEX_W_0F11_P_3_M_{0,1} table entries.
145
219920a7
JB		 1462019-07-01 Jan Beulich <jbeulich@suse.com>
147
148 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
149 Delete.
150
e395f487
L		 1512019-06-27 H.J. Lu <hongjiu.lu@intel.com>
152
153 PR binutils/24719
154 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
155 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
156 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
157 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
158 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
159 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
160 EVEX_LEN_0F38C7_R_6_P_2_W_1.
161 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
162 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
163 PREFIX_EVEX_0F38C6_REG_6 entries.
164 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
165 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
166 EVEX_W_0F38C7_R_6_P_2 entries.
167 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
168 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
169 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
170 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
171 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
172 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
173 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
174
2b7bcc87
JB		 1752019-06-27 Jan Beulich <jbeulich@suse.com>
176
177 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
178 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
179 VEX_LEN_0F2D_P_3): Delete.
180 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
181 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
182 (prefix_table): ... here.
183
c1dc7af5
JB		 1842019-06-27 Jan Beulich <jbeulich@suse.com>
185
186 * i386-dis.c (Iq): Delete.
187 (Id): New.
188 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
189 TBM insns.
190 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
191 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
192 (OP_E_memory): Also honor needindex when deciding whether an
193 address size prefix needs printing.
194 (OP_I): Remove handling of q_mode. Add handling of d_mode.
195
d7560e2d
JW		 1962019-06-26 Jim Wilson <jimw@sifive.com>
197
198 PR binutils/24739
199 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
200 Set info->display_endian to info->endian_code.
201
2c703856
JB		 2022019-06-25 Jan Beulich <jbeulich@suse.com>
203
204 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
205 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
206 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
207 OPERAND_TYPE_ACC64 entries.
208 * i386-init.h: Re-generate.
209
54fbadc0
JB		 2102019-06-25 Jan Beulich <jbeulich@suse.com>
211
212 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
213 Delete.
214 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
215 of dqa_mode.
216 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
217 entries here.
218 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
219 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
220
a280ab8e
JB		 2212019-06-25 Jan Beulich <jbeulich@suse.com>
222
223 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
224 variables.
225
e1a1babd
JB		 2262019-06-25 Jan Beulich <jbeulich@suse.com>
227
228 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
229 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
230 movnti.
d7560e2d 231 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 232 * i386-tbl.h: Re-generate.
233
b8364fa7
JB		 2342019-06-25 Jan Beulich <jbeulich@suse.com>
235
236 * i386-opc.tbl (and): Mark Imm8S form for optimization.
237 * i386-tbl.h: Re-generate.
238
ad692897
L		 2392019-06-21 H.J. Lu <hongjiu.lu@intel.com>
240
241 * i386-dis-evex.h: Break into ...
242 * i386-dis-evex-len.h: New file.
243 * i386-dis-evex-mod.h: Likewise.
244 * i386-dis-evex-prefix.h: Likewise.
245 * i386-dis-evex-reg.h: Likewise.
246 * i386-dis-evex-w.h: Likewise.
247 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
248 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
249 i386-dis-evex-mod.h.
250
f0a6222e
L		 2512019-06-19 H.J. Lu <hongjiu.lu@intel.com>
252
253 PR binutils/24700
254 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
255 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
256 EVEX_W_0F385B_P_2.
257 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
258 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
259 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
260 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
261 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
262 EVEX_LEN_0F385B_P_2_W_1.
263 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
264 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
265 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
266 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
267 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
268 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
269 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
270 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
271 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
272 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
273
6e1c90b7
L		 2742019-06-17 H.J. Lu <hongjiu.lu@intel.com>
275
276 PR binutils/24691
277 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
278 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
279 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
280 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
281 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
282 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
283 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
284 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
285 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
286 EVEX_LEN_0F3A43_P_2_W_1.
287 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
288 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
289 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
290 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
291 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
292 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
293 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
294 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
295 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
296 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
297 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
298 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
299
bcc5a6eb
NC		 3002019-06-14 Nick Clifton <nickc@redhat.com>
301
302 * po/fr.po; Updated French translation.
303
e4c4ac46
SH		 3042019-06-13 Stafford Horne <shorne@gmail.com>
305
306 * or1k-asm.c: Regenerated.
307 * or1k-desc.c: Regenerated.
308 * or1k-desc.h: Regenerated.
309 * or1k-dis.c: Regenerated.
310 * or1k-ibld.c: Regenerated.
311 * or1k-opc.c: Regenerated.
312 * or1k-opc.h: Regenerated.
313 * or1k-opinst.c: Regenerated.
314
a0e44ef5
PB		 3152019-06-12 Peter Bergner <bergner@linux.ibm.com>
316
317 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
318
12efd68d
L		 3192019-06-05 H.J. Lu <hongjiu.lu@intel.com>
320
321 PR binutils/24633
322 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
323 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
324 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
325 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
326 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
327 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
328 EVEX_LEN_0F3A1B_P_2_W_1.
329 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
330 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
331 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
332 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
333 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
334 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
335 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
336 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
337
63c6fc6c
L		 3382019-06-04 H.J. Lu <hongjiu.lu@intel.com>
339
340 PR binutils/24626
341 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
342 EVEX.vvvv when disassembling VEX and EVEX instructions.
343 (OP_VEX): Set vex.register_specifier to 0 after readding
344 vex.register_specifier.
345 (OP_Vex_2src_1): Likewise.
346 (OP_Vex_2src_2): Likewise.
347 (OP_LWP_E): Likewise.
348 (OP_EX_Vex): Don't check vex.register_specifier.
349 (OP_XMM_Vex): Likewise.
350
9186c494
L		 3512019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
352 Lili Cui <lili.cui@intel.com>
353
354 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
355 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
356 instructions.
357 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
358 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
359 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
360 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
361 (i386_cpu_flags): Add cpuavx512_vp2intersect.
362 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
363 * i386-init.h: Regenerated.
364 * i386-tbl.h: Likewise.
365
5d79adc4
L		 3662019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
367 Lili Cui <lili.cui@intel.com>
368
369 * doc/c-i386.texi: Document enqcmd.
370 * testsuite/gas/i386/enqcmd-intel.d: New file.
371 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
372 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
373 * testsuite/gas/i386/enqcmd.d: Likewise.
374 * testsuite/gas/i386/enqcmd.s: Likewise.
375 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
376 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
377 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
378 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
379 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
380 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
381 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
382 and x86-64-enqcmd.
383
a9d96ab9
AH		 3842019-06-04 Alan Hayward <alan.hayward@arm.com>
385
386 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
387
4f6d070a
AM		 3882019-06-03 Alan Modra <amodra@gmail.com>
389
390 * ppc-dis.c (prefix_opcd_indices): Correct size.
391
a2f4b66c
L		 3922019-05-28 H.J. Lu <hongjiu.lu@intel.com>
393
394 PR gas/24625
395 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
396 Disp8ShiftVL.
397 * i386-tbl.h: Regenerated.
398
405b5bd8
AM		 3992019-05-24 Alan Modra <amodra@gmail.com>
400
401 * po/POTFILES.in: Regenerate.
402
8acf1435
PB		 4032019-05-24 Peter Bergner <bergner@linux.ibm.com>
404 Alan Modra <amodra@gmail.com>
405
406 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
407 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
408 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
409 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
410 XTOP>): Define and add entries.
411 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
412 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
413 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
414 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
415
dd7efa79
PB		 4162019-05-24 Peter Bergner <bergner@linux.ibm.com>
417 Alan Modra <amodra@gmail.com>
418
419 * ppc-dis.c (ppc_opts): Add "future" entry.
420 (PREFIX_OPCD_SEGS): Define.
421 (prefix_opcd_indices): New array.
422 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
423 (lookup_prefix): New function.
424 (print_insn_powerpc): Handle 64-bit prefix instructions.
425 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
426 (PMRR, POWERXX): Define.
427 (prefix_opcodes): New instruction table.
428 (prefix_num_opcodes): New constant.
429
79472b45
JM		 4302019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
431
432 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
433 * configure: Regenerated.
434 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
435 and cpu/bpf.opc.
436 (HFILES): Add bpf-desc.h and bpf-opc.h.
437 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
438 bpf-ibld.c and bpf-opc.c.
439 (BPF_DEPS): Define.
440 * Makefile.in: Regenerated.
441 * disassemble.c (ARCH_bpf): Define.
442 (disassembler): Add case for bfd_arch_bpf.
443 (disassemble_init_for_target): Likewise.
444 (enum epbf_isa_attr): Define.
445 * disassemble.h: extern print_insn_bpf.
446 * bpf-asm.c: Generated.
447 * bpf-opc.h: Likewise.
448 * bpf-opc.c: Likewise.
449 * bpf-ibld.c: Likewise.
450 * bpf-dis.c: Likewise.
451 * bpf-desc.h: Likewise.
452 * bpf-desc.c: Likewise.
453
ba6cd17f
SD		 4542019-05-21 Sudakshina Das <sudi.das@arm.com>
455
456 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
457 and VMSR with the new operands.
458
e39c1607
SD		 4592019-05-21 Sudakshina Das <sudi.das@arm.com>
460
461 * arm-dis.c (enum mve_instructions): New enum
462 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
463 and cneg.
464 (mve_opcodes): New instructions as above.
465 (is_mve_encoding_conflict): Add cases for csinc, csinv,
466 csneg and csel.
467 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
468
23d00a41
SD		 4692019-05-21 Sudakshina Das <sudi.das@arm.com>
470
471 * arm-dis.c (emun mve_instructions): Updated for new instructions.
472 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
473 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
474 uqshl, urshrl and urshr.
475 (is_mve_okay_in_it): Add new instructions to TRUE list.
476 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
477 (print_insn_mve): Updated to accept new %j,
478 %<bitfield>m and %<bitfield>n patterns.
479
cd4797ee
FS		 4802019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
481
482 * mips-opc.c (mips_builtin_opcodes): Change source register
483 constraint for DAUI.
484
999b073b
NC		 4852019-05-20 Nick Clifton <nickc@redhat.com>
486
487 * po/fr.po: Updated French translation.
488
14b456f2
AV		 4892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
490 Michael Collison <michael.collison@arm.com>
491
492 * arm-dis.c (thumb32_opcodes): Add new instructions.
493 (enum mve_instructions): Likewise.
494 (enum mve_undefined): Add new reasons.
495 (is_mve_encoding_conflict): Handle new instructions.
496 (is_mve_undefined): Likewise.
497 (is_mve_unpredictable): Likewise.
498 (print_mve_undefined): Likewise.
499 (print_mve_size): Likewise.
500
f49bb598
AV		 5012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
502 Michael Collison <michael.collison@arm.com>
503
504 * arm-dis.c (thumb32_opcodes): Add new instructions.
505 (enum mve_instructions): Likewise.
506 (is_mve_encoding_conflict): Handle new instructions.
507 (is_mve_undefined): Likewise.
508 (is_mve_unpredictable): Likewise.
509 (print_mve_size): Likewise.
510
56858bea
AV		 5112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
512 Michael Collison <michael.collison@arm.com>
513
514 * arm-dis.c (thumb32_opcodes): Add new instructions.
515 (enum mve_instructions): Likewise.
516 (is_mve_encoding_conflict): Likewise.
517 (is_mve_unpredictable): Likewise.
518 (print_mve_size): Likewise.
519
e523f101
AV		 5202019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
521 Michael Collison <michael.collison@arm.com>
522
523 * arm-dis.c (thumb32_opcodes): Add new instructions.
524 (enum mve_instructions): Likewise.
525 (is_mve_encoding_conflict): Handle new instructions.
526 (is_mve_undefined): Likewise.
527 (is_mve_unpredictable): Likewise.
528 (print_mve_size): Likewise.
529
66dcaa5d
AV		 5302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
531 Michael Collison <michael.collison@arm.com>
532
533 * arm-dis.c (thumb32_opcodes): Add new instructions.
534 (enum mve_instructions): Likewise.
535 (is_mve_encoding_conflict): Handle new instructions.
536 (is_mve_undefined): Likewise.
537 (is_mve_unpredictable): Likewise.
538 (print_mve_size): Likewise.
539 (print_insn_mve): Likewise.
540
d052b9b7
AV		 5412019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
542 Michael Collison <michael.collison@arm.com>
543
544 * arm-dis.c (thumb32_opcodes): Add new instructions.
545 (print_insn_thumb32): Handle new instructions.
546
ed63aa17
AV		 5472019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
548 Michael Collison <michael.collison@arm.com>
549
550 * arm-dis.c (enum mve_instructions): Add new instructions.
551 (enum mve_undefined): Add new reasons.
552 (is_mve_encoding_conflict): Handle new instructions.
553 (is_mve_undefined): Likewise.
554 (is_mve_unpredictable): Likewise.
555 (print_mve_undefined): Likewise.
556 (print_mve_size): Likewise.
557 (print_mve_shift_n): Likewise.
558 (print_insn_mve): Likewise.
559
897b9bbc
AV		 5602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
561 Michael Collison <michael.collison@arm.com>
562
563 * arm-dis.c (enum mve_instructions): Add new instructions.
564 (is_mve_encoding_conflict): Handle new instructions.
565 (is_mve_unpredictable): Likewise.
566 (print_mve_rotate): Likewise.
567 (print_mve_size): Likewise.
568 (print_insn_mve): Likewise.
569
1c8f2df8
AV		 5702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
571 Michael Collison <michael.collison@arm.com>
572
573 * arm-dis.c (enum mve_instructions): Add new instructions.
574 (is_mve_encoding_conflict): Handle new instructions.
575 (is_mve_unpredictable): Likewise.
576 (print_mve_size): Likewise.
577 (print_insn_mve): Likewise.
578
d3b63143
AV		 5792019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
580 Michael Collison <michael.collison@arm.com>
581
582 * arm-dis.c (enum mve_instructions): Add new instructions.
583 (enum mve_undefined): Add new reasons.
584 (is_mve_encoding_conflict): Handle new instructions.
585 (is_mve_undefined): Likewise.
586 (is_mve_unpredictable): Likewise.
587 (print_mve_undefined): Likewise.
588 (print_mve_size): Likewise.
589 (print_insn_mve): Likewise.
590
14925797
AV		 5912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
592 Michael Collison <michael.collison@arm.com>
593
594 * arm-dis.c (enum mve_instructions): Add new instructions.
595 (is_mve_encoding_conflict): Handle new instructions.
596 (is_mve_undefined): Likewise.
597 (is_mve_unpredictable): Likewise.
598 (print_mve_size): Likewise.
599 (print_insn_mve): Likewise.
600
c507f10b
AV		 6012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
602 Michael Collison <michael.collison@arm.com>
603
604 * arm-dis.c (enum mve_instructions): Add new instructions.
605 (enum mve_unpredictable): Add new reasons.
606 (enum mve_undefined): Likewise.
607 (is_mve_okay_in_it): Handle new isntructions.
608 (is_mve_encoding_conflict): Likewise.
609 (is_mve_undefined): Likewise.
610 (is_mve_unpredictable): Likewise.
611 (print_mve_vmov_index): Likewise.
612 (print_simd_imm8): Likewise.
613 (print_mve_undefined): Likewise.
614 (print_mve_unpredictable): Likewise.
615 (print_mve_size): Likewise.
616 (print_insn_mve): Likewise.
617
bf0b396d
AV		 6182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
619 Michael Collison <michael.collison@arm.com>
620
621 * arm-dis.c (enum mve_instructions): Add new instructions.
622 (enum mve_unpredictable): Add new reasons.
623 (enum mve_undefined): Likewise.
624 (is_mve_encoding_conflict): Handle new instructions.
625 (is_mve_undefined): Likewise.
626 (is_mve_unpredictable): Likewise.
627 (print_mve_undefined): Likewise.
628 (print_mve_unpredictable): Likewise.
629 (print_mve_rounding_mode): Likewise.
630 (print_mve_vcvt_size): Likewise.
631 (print_mve_size): Likewise.
632 (print_insn_mve): Likewise.
633
ef1576a1
AV		 6342019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
635 Michael Collison <michael.collison@arm.com>
636
637 * arm-dis.c (enum mve_instructions): Add new instructions.
638 (enum mve_unpredictable): Add new reasons.
639 (enum mve_undefined): Likewise.
640 (is_mve_undefined): Handle new instructions.
641 (is_mve_unpredictable): Likewise.
642 (print_mve_undefined): Likewise.
643 (print_mve_unpredictable): Likewise.
644 (print_mve_size): Likewise.
645 (print_insn_mve): Likewise.
646
aef6d006
AV		 6472019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
648 Michael Collison <michael.collison@arm.com>
649
650 * arm-dis.c (enum mve_instructions): Add new instructions.
651 (enum mve_undefined): Add new reasons.
652 (insns): Add new instructions.
653 (is_mve_encoding_conflict):
654 (print_mve_vld_str_addr): New print function.
655 (is_mve_undefined): Handle new instructions.
656 (is_mve_unpredictable): Likewise.
657 (print_mve_undefined): Likewise.
658 (print_mve_size): Likewise.
659 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
660 (print_insn_mve): Handle new operands.
661
04d54ace
AV		 6622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
663 Michael Collison <michael.collison@arm.com>
664
665 * arm-dis.c (enum mve_instructions): Add new instructions.
666 (enum mve_unpredictable): Add new reasons.
667 (is_mve_encoding_conflict): Handle new instructions.
668 (is_mve_unpredictable): Likewise.
669 (mve_opcodes): Add new instructions.
670 (print_mve_unpredictable): Handle new reasons.
671 (print_mve_register_blocks): New print function.
672 (print_mve_size): Handle new instructions.
673 (print_insn_mve): Likewise.
674
9743db03
AV		 6752019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
676 Michael Collison <michael.collison@arm.com>
677
678 * arm-dis.c (enum mve_instructions): Add new instructions.
679 (enum mve_unpredictable): Add new reasons.
680 (enum mve_undefined): Likewise.
681 (is_mve_encoding_conflict): Handle new instructions.
682 (is_mve_undefined): Likewise.
683 (is_mve_unpredictable): Likewise.
684 (coprocessor_opcodes): Move NEON VDUP from here...
685 (neon_opcodes): ... to here.
686 (mve_opcodes): Add new instructions.
687 (print_mve_undefined): Handle new reasons.
688 (print_mve_unpredictable): Likewise.
689 (print_mve_size): Handle new instructions.
690 (print_insn_neon): Handle vdup.
691 (print_insn_mve): Handle new operands.
692
143275ea
AV		 6932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
694 Michael Collison <michael.collison@arm.com>
695
696 * arm-dis.c (enum mve_instructions): Add new instructions.
697 (enum mve_unpredictable): Add new values.
698 (mve_opcodes): Add new instructions.
699 (vec_condnames): New array with vector conditions.
700 (mve_predicatenames): New array with predicate suffixes.
701 (mve_vec_sizename): New array with vector sizes.
702 (enum vpt_pred_state): New enum with vector predication states.
703 (struct vpt_block): New struct type for vpt blocks.
704 (vpt_block_state): Global struct to keep track of state.
705 (mve_extract_pred_mask): New helper function.
706 (num_instructions_vpt_block): Likewise.
707 (mark_outside_vpt_block): Likewise.
708 (mark_inside_vpt_block): Likewise.
709 (invert_next_predicate_state): Likewise.
710 (update_next_predicate_state): Likewise.
711 (update_vpt_block_state): Likewise.
712 (is_vpt_instruction): Likewise.
713 (is_mve_encoding_conflict): Add entries for new instructions.
714 (is_mve_unpredictable): Likewise.
715 (print_mve_unpredictable): Handle new cases.
716 (print_instruction_predicate): Likewise.
717 (print_mve_size): New function.
718 (print_vec_condition): New function.
719 (print_insn_mve): Handle vpt blocks and new print operands.
720
f08d8ce3
AV		 7212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
722
723 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
724 8, 14 and 15 for Armv8.1-M Mainline.
725
73cd51e5
AV		 7262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
727 Michael Collison <michael.collison@arm.com>
728
729 * arm-dis.c (enum mve_instructions): New enum.
730 (enum mve_unpredictable): Likewise.
731 (enum mve_undefined): Likewise.
732 (struct mopcode32): New struct.
733 (is_mve_okay_in_it): New function.
734 (is_mve_architecture): Likewise.
735 (arm_decode_field): Likewise.
736 (arm_decode_field_multiple): Likewise.
737 (is_mve_encoding_conflict): Likewise.
738 (is_mve_undefined): Likewise.
739 (is_mve_unpredictable): Likewise.
740 (print_mve_undefined): Likewise.
741 (print_mve_unpredictable): Likewise.
742 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
743 (print_insn_mve): New function.
744 (print_insn_thumb32): Handle MVE architecture.
745 (select_arm_features): Force thumb for Armv8.1-m Mainline.
746
3076e594
NC		 7472019-05-10 Nick Clifton <nickc@redhat.com>
748
749 PR 24538
750 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
751 end of the table prematurely.
752
387e7624
FS		 7532019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
754
755 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
756 macros for R6.
757
0067be51
AM		 7582019-05-11 Alan Modra <amodra@gmail.com>
759
760 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
761 when -Mraw is in effect.
762
42e6288f
MM		 7632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
764
765 * aarch64-dis-2.c: Regenerate.
766 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
767 (OP_SVE_BBB): New variant set.
768 (OP_SVE_DDDD): New variant set.
769 (OP_SVE_HHH): New variant set.
770 (OP_SVE_HHHU): New variant set.
771 (OP_SVE_SSS): New variant set.
772 (OP_SVE_SSSU): New variant set.
773 (OP_SVE_SHH): New variant set.
774 (OP_SVE_SBBU): New variant set.
775 (OP_SVE_DSS): New variant set.
776 (OP_SVE_DHHU): New variant set.
777 (OP_SVE_VMV_HSD_BHS): New variant set.
778 (OP_SVE_VVU_HSD_BHS): New variant set.
779 (OP_SVE_VVVU_SD_BH): New variant set.
780 (OP_SVE_VVVU_BHSD): New variant set.
781 (OP_SVE_VVV_QHD_DBS): New variant set.
782 (OP_SVE_VVV_HSD_BHS): New variant set.
783 (OP_SVE_VVV_HSD_BHS2): New variant set.
784 (OP_SVE_VVV_BHS_HSD): New variant set.
785 (OP_SVE_VV_BHS_HSD): New variant set.
786 (OP_SVE_VVV_SD): New variant set.
787 (OP_SVE_VVU_BHS_HSD): New variant set.
788 (OP_SVE_VZVV_SD): New variant set.
789 (OP_SVE_VZVV_BH): New variant set.
790 (OP_SVE_VZV_SD): New variant set.
791 (aarch64_opcode_table): Add sve2 instructions.
792
28ed815a
MM		 7932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
794
795 * aarch64-asm-2.c: Regenerated.
796 * aarch64-dis-2.c: Regenerated.
797 * aarch64-opc-2.c: Regenerated.
798 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
799 for SVE_SHLIMM_UNPRED_22.
800 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
801 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
802 operand.
803
fd1dc4a0
MM		 8042019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
805
806 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
807 sve_size_tsz_bhs iclass encode.
808 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
809 sve_size_tsz_bhs iclass decode.
810
31e36ab3
MM		 8112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
812
813 * aarch64-asm-2.c: Regenerated.
814 * aarch64-dis-2.c: Regenerated.
815 * aarch64-opc-2.c: Regenerated.
816 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
817 for SVE_Zm4_11_INDEX.
818 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
819 (fields): Handle SVE_i2h field.
820 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
821 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
822
1be5f94f
MM		 8232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
824
825 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
826 sve_shift_tsz_bhsd iclass encode.
827 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
828 sve_shift_tsz_bhsd iclass decode.
829
3c17238b
MM		 8302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
831
832 * aarch64-asm-2.c: Regenerated.
833 * aarch64-dis-2.c: Regenerated.
834 * aarch64-opc-2.c: Regenerated.
835 * aarch64-asm.c (aarch64_ins_sve_shrimm):
836 (aarch64_encode_variant_using_iclass): Handle
837 sve_shift_tsz_hsd iclass encode.
838 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
839 sve_shift_tsz_hsd iclass decode.
840 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
841 for SVE_SHRIMM_UNPRED_22.
842 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
843 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
844 operand.
845
cd50a87a
MM		 8462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
847
848 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
849 sve_size_013 iclass encode.
850 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
851 sve_size_013 iclass decode.
852
3c705960
MM		 8532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
854
855 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
856 sve_size_bh iclass encode.
857 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
858 sve_size_bh iclass decode.
859
0a57e14f
MM		 8602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
861
862 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
863 sve_size_sd2 iclass encode.
864 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
865 sve_size_sd2 iclass decode.
866 * aarch64-opc.c (fields): Handle SVE_sz2 field.
867 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
868
c469c864
MM		 8692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
870
871 * aarch64-asm-2.c: Regenerated.
872 * aarch64-dis-2.c: Regenerated.
873 * aarch64-opc-2.c: Regenerated.
874 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
875 for SVE_ADDR_ZX.
876 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
877 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
878
116adc27
MM		 8792019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
880
881 * aarch64-asm-2.c: Regenerated.
882 * aarch64-dis-2.c: Regenerated.
883 * aarch64-opc-2.c: Regenerated.
884 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
885 for SVE_Zm3_11_INDEX.
886 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
887 (fields): Handle SVE_i3l and SVE_i3h2 fields.
888 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
889 fields.
890 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
891
3bd82c86
MM		 8922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
893
894 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
895 sve_size_hsd2 iclass encode.
896 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
897 sve_size_hsd2 iclass decode.
898 * aarch64-opc.c (fields): Handle SVE_size field.
899 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
900
adccc507
MM		 9012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
902
903 * aarch64-asm-2.c: Regenerated.
904 * aarch64-dis-2.c: Regenerated.
905 * aarch64-opc-2.c: Regenerated.
906 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
907 for SVE_IMM_ROT3.
908 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
909 (fields): Handle SVE_rot3 field.
910 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
911 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
912
5cd99750
MM		 9132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
914
915 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
916 instructions.
917
7ce2460a
MM		 9182019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
919
920 * aarch64-tbl.h
921 (aarch64_feature_sve2, aarch64_feature_sve2aes,
922 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
923 aarch64_feature_sve2bitperm): New feature sets.
924 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
925 for feature set addresses.
926 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
927 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
928
41cee089
FS		 9292019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
930 Faraz Shahbazker <fshahbazker@wavecomp.com>
931
932 * mips-dis.c (mips_calculate_combination_ases): Add ISA
933 argument and set ASE_EVA_R6 appropriately.
934 (set_default_mips_dis_options): Pass ISA to above.
935 (parse_mips_dis_option): Likewise.
936 * mips-opc.c (EVAR6): New macro.
937 (mips_builtin_opcodes): Add llwpe, scwpe.
938
b83b4b13
SD		 9392019-05-01 Sudakshina Das <sudi.das@arm.com>
940
941 * aarch64-asm-2.c: Regenerated.
942 * aarch64-dis-2.c: Regenerated.
943 * aarch64-opc-2.c: Regenerated.
944 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
945 AARCH64_OPND_TME_UIMM16.
946 (aarch64_print_operand): Likewise.
947 * aarch64-tbl.h (QL_IMM_NIL): New.
948 (TME): New.
949 (_TME_INSN): New.
950 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
951
4a90ce95
JD		 9522019-04-29 John Darrington <john@darrington.wattle.id.au>
953
954 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
955
a45328b9
AB		 9562019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
957 Faraz Shahbazker <fshahbazker@wavecomp.com>
958
959 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
960
d10be0cb
JD		 9612019-04-24 John Darrington <john@darrington.wattle.id.au>
962
963 * s12z-opc.h: Add extern "C" bracketing to help
964 users who wish to use this interface in c++ code.
965
a679f24e
JD		 9662019-04-24 John Darrington <john@darrington.wattle.id.au>
967
968 * s12z-opc.c (bm_decode): Handle bit map operations with the
969 "reserved0" mode.
970
32c36c3c
AV		 9712019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
972
973 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
974 specifier. Add entries for VLDR and VSTR of system registers.
975 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
976 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
977 of %J and %K format specifier.
978
efd6b359
AV		 9792019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
980
981 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
982 Add new entries for VSCCLRM instruction.
983 (print_insn_coprocessor): Handle new %C format control code.
984
6b0dd094
AV		 9852019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
986
987 * arm-dis.c (enum isa): New enum.
988 (struct sopcode32): New structure.
989 (coprocessor_opcodes): change type of entries to struct sopcode32 and
990 set isa field of all current entries to ANY.
991 (print_insn_coprocessor): Change type of insn to struct sopcode32.
992 Only match an entry if its isa field allows the current mode.
993
4b5a202f
AV		 9942019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
995
996 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
997 CLRM.
998 (print_insn_thumb32): Add logic to print %n CLRM register list.
999
60f993ce
AV		 10002019-04-15 Sudakshina Das <sudi.das@arm.com>
1001
1002 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1003 and %Q patterns.
1004
f6b2b12d
AV		 10052019-04-15 Sudakshina Das <sudi.das@arm.com>
1006
1007 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1008 (print_insn_thumb32): Edit the switch case for %Z.
1009
1889da70
AV		 10102019-04-15 Sudakshina Das <sudi.das@arm.com>
1011
1012 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1013
65d1bc05
AV		 10142019-04-15 Sudakshina Das <sudi.das@arm.com>
1015
1016 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1017
1caf72a5
AV		 10182019-04-15 Sudakshina Das <sudi.das@arm.com>
1019
1020 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1021
f1c7f421
AV		 10222019-04-15 Sudakshina Das <sudi.das@arm.com>
1023
1024 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1025 Arm register with r13 and r15 unpredictable.
1026 (thumb32_opcodes): New instructions for bfx and bflx.
1027
4389b29a
AV		 10282019-04-15 Sudakshina Das <sudi.das@arm.com>
1029
1030 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1031
e5d6e09e
AV		 10322019-04-15 Sudakshina Das <sudi.das@arm.com>
1033
1034 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1035
e12437dc
AV		 10362019-04-15 Sudakshina Das <sudi.das@arm.com>
1037
1038 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1039
031254f2
AV		 10402019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1041
1042 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1043
e5a557ac
JD		 10442019-04-12 John Darrington <john@darrington.wattle.id.au>
1045
1046 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1047 "optr". ("operator" is a reserved word in c++).
1048
bd7ceb8d
SD		 10492019-04-11 Sudakshina Das <sudi.das@arm.com>
1050
1051 * aarch64-opc.c (aarch64_print_operand): Add case for
1052 AARCH64_OPND_Rt_SP.
1053 (verify_constraints): Likewise.
1054 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1055 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1056 to accept Rt|SP as first operand.
1057 (AARCH64_OPERANDS): Add new Rt_SP.
1058 * aarch64-asm-2.c: Regenerated.
1059 * aarch64-dis-2.c: Regenerated.
1060 * aarch64-opc-2.c: Regenerated.
1061
e54010f1
SD		 10622019-04-11 Sudakshina Das <sudi.das@arm.com>
1063
1064 * aarch64-asm-2.c: Regenerated.
1065 * aarch64-dis-2.c: Likewise.
1066 * aarch64-opc-2.c: Likewise.
1067 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1068
7e96e219
RS		 10692019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1070
1071 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1072
6f2791d5
L		 10732019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1074
1075 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1076 * i386-init.h: Regenerated.
1077
e392bad3
AM		 10782019-04-07 Alan Modra <amodra@gmail.com>
1079
1080 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1081 op_separator to control printing of spaces, comma and parens
1082 rather than need_comma, need_paren and spaces vars.
1083
dffaa15c
AM		 10842019-04-07 Alan Modra <amodra@gmail.com>
1085
1086 PR 24421
1087 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1088 (print_insn_neon, print_insn_arm): Likewise.
1089
d6aab7a1
XG		 10902019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1091
1092 * i386-dis-evex.h (evex_table): Updated to support BF16
1093 instructions.
1094 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1095 and EVEX_W_0F3872_P_3.
1096 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1097 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1098 * i386-opc.h (enum): Add CpuAVX512_BF16.
1099 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1100 * i386-opc.tbl: Add AVX512 BF16 instructions.
1101 * i386-init.h: Regenerated.
1102 * i386-tbl.h: Likewise.
1103
66e85460
AM		 11042019-04-05 Alan Modra <amodra@gmail.com>
1105
1106 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1107 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1108 to favour printing of "-" branch hint when using the "y" bit.
1109 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1110
c2b1c275
AM		 11112019-04-05 Alan Modra <amodra@gmail.com>
1112
1113 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1114 opcode until first operand is output.
1115
aae9718e
PB		 11162019-04-04 Peter Bergner <bergner@linux.ibm.com>
1117
1118 PR gas/24349
1119 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1120 (valid_bo_post_v2): Add support for 'at' branch hints.
1121 (insert_bo): Only error on branch on ctr.
1122 (get_bo_hint_mask): New function.
1123 (insert_boe): Add new 'branch_taken' formal argument. Add support
1124 for inserting 'at' branch hints.
1125 (extract_boe): Add new 'branch_taken' formal argument. Add support
1126 for extracting 'at' branch hints.
1127 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1128 (BOE): Delete operand.
1129 (BOM, BOP): New operands.
1130 (RM): Update value.
1131 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1132 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1133 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1134 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1135 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1136 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1137 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1138 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1139 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1140 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1141 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1142 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1143 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1144 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1145 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1146 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1147 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1148 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1149 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1150 bttarl+>: New extended mnemonics.
1151
96a86c01
AM		 11522019-03-28 Alan Modra <amodra@gmail.com>
1153
1154 PR 24390
1155 * ppc-opc.c (BTF): Define.
1156 (powerpc_opcodes): Use for mtfsb*.
1157 * ppc-dis.c (print_insn_powerpc): Print fields with both
1158 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1159
796d6298
TC		 11602019-03-25 Tamar Christina <tamar.christina@arm.com>
1161
1162 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1163 (mapping_symbol_for_insn): Implement new algorithm.
1164 (print_insn): Remove duplicate code.
1165
60df3720
TC		 11662019-03-25 Tamar Christina <tamar.christina@arm.com>
1167
1168 * aarch64-dis.c (print_insn_aarch64):
1169 Implement override.
1170
51457761
TC		 11712019-03-25 Tamar Christina <tamar.christina@arm.com>
1172
1173 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1174 order.
1175
53b2f36b
TC		 11762019-03-25 Tamar Christina <tamar.christina@arm.com>
1177
1178 * aarch64-dis.c (last_stop_offset): New.
1179 (print_insn_aarch64): Use stop_offset.
1180
89199bb5
L		 11812019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1182
1183 PR gas/24359
1184 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1185 CPU_ANY_AVX2_FLAGS.
1186 * i386-init.h: Regenerated.
1187
97ed31ae
L		 11882019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1189
1190 PR gas/24348
1191 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1192 vmovdqu16, vmovdqu32 and vmovdqu64.
1193 * i386-tbl.h: Regenerated.
1194
0919bfe9
AK		 11952019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1196
1197 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1198 from vstrszb, vstrszh, and vstrszf.
1199
12002019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1201
1202 * s390-opc.txt: Add instruction descriptions.
1203
21820ebe
JW		 12042019-02-08 Jim Wilson <jimw@sifive.com>
1205
1206 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1207 <bne>: Likewise.
1208
f7dd2fb2
TC		 12092019-02-07 Tamar Christina <tamar.christina@arm.com>
1210
1211 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1212
6456d318
TC		 12132019-02-07 Tamar Christina <tamar.christina@arm.com>
1214
1215 PR binutils/23212
1216 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1217 * aarch64-opc.c (verify_elem_sd): New.
1218 (fields): Add FLD_sz entr.
1219 * aarch64-tbl.h (_SIMD_INSN): New.
1220 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1221 fmulx scalar and vector by element isns.
1222
4a83b610
NC		 12232019-02-07 Nick Clifton <nickc@redhat.com>
1224
1225 * po/sv.po: Updated Swedish translation.
1226
fc60b8c8
AK		 12272019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1228
1229 * s390-mkopc.c (main): Accept arch13 as cpu string.
1230 * s390-opc.c: Add new instruction formats and instruction opcode
1231 masks.
1232 * s390-opc.txt: Add new arch13 instructions.
1233
e10620d3
TC		 12342019-01-25 Sudakshina Das <sudi.das@arm.com>
1235
1236 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1237 (aarch64_opcode): Change encoding for stg, stzg
1238 st2g and st2zg.
1239 * aarch64-asm-2.c: Regenerated.
1240 * aarch64-dis-2.c: Regenerated.
1241 * aarch64-opc-2.c: Regenerated.
1242
20a4ca55
SD		 12432019-01-25 Sudakshina Das <sudi.das@arm.com>
1244
1245 * aarch64-asm-2.c: Regenerated.
1246 * aarch64-dis-2.c: Likewise.
1247 * aarch64-opc-2.c: Likewise.
1248 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1249
550fd7bf
SD		 12502019-01-25 Sudakshina Das <sudi.das@arm.com>
1251 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1252
1253 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1254 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1255 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1256 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1257 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1258 case for ldstgv_indexed.
1259 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1260 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1261 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1262 * aarch64-asm-2.c: Regenerated.
1263 * aarch64-dis-2.c: Regenerated.
1264 * aarch64-opc-2.c: Regenerated.
1265
d9938630
NC		 12662019-01-23 Nick Clifton <nickc@redhat.com>
1267
1268 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1269
375cd423
NC		 12702019-01-21 Nick Clifton <nickc@redhat.com>
1271
1272 * po/de.po: Updated German translation.
1273 * po/uk.po: Updated Ukranian translation.
1274
57299f48
CX		 12752019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1276 * mips-dis.c (mips_arch_choices): Fix typo in
1277 gs464, gs464e and gs264e descriptors.
1278
f48dfe41
NC		 12792019-01-19 Nick Clifton <nickc@redhat.com>
1280
1281 * configure: Regenerate.
1282 * po/opcodes.pot: Regenerate.
1283
f974f26c
NC		 12842018-06-24 Nick Clifton <nickc@redhat.com>
1285
1286 2.32 branch created.
1287
39f286cd
JD		 12882019-01-09 John Darrington <john@darrington.wattle.id.au>
1289
448b8ca8
JD		 1290 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1291 if it is null.
1292 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1293 zero.
1294
3107326d
AP		 12952019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1296
1297 * configure: Regenerate.
1298
7e9ca91e
AM		 12992019-01-07 Alan Modra <amodra@gmail.com>
1300
1301 * configure: Regenerate.
1302 * po/POTFILES.in: Regenerate.
1303
ef1ad42b
JD		 13042019-01-03 John Darrington <john@darrington.wattle.id.au>
1305
1306 * s12z-opc.c: New file.
1307 * s12z-opc.h: New file.
1308 * s12z-dis.c: Removed all code not directly related to display
1309 of instructions. Used the interface provided by the new files
1310 instead.
1311 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1312 * Makefile.in: Regenerate.
ef1ad42b 1313 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1314 * configure: Regenerate.
ef1ad42b 1315
82704155
AM		 13162019-01-01 Alan Modra <amodra@gmail.com>
1317
1318 Update year range in copyright notice of all files.
1319
d5c04e1b 1320For older changes see ChangeLog-2018
3499769a 1321\f
d5c04e1b 1322Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1323
1324Copying and distribution of this file, with or without modification,
1325are permitted in any medium without royalty provided the copyright
1326notice and this notice are preserved.
1327
1328Local Variables:
1329mode: change-log
1330left-margin: 8
1331fill-column: 74
1332version-control: never
1333End:
GDB Binutils - Deliverables
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