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Revert "Add support for AArch64 trace unit registers."
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a203d9b7
YZ		 12013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
2
3 Revert
4
5 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
6
7 * aarch64-opc.c (CPENT): New define.
8 (F_READONLY, F_WRITEONLY): Likewise.
9 (aarch64_sys_regs): Add trace unit registers.
10 (aarch64_sys_reg_readonly_p): New function.
11 (aarch64_sys_reg_writeonly_p): Ditto.
12
75468c93
YZ		 132013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
14
15 * aarch64-opc.c (CPENT): New define.
16 (F_READONLY, F_WRITEONLY): Likewise.
17 (aarch64_sys_regs): Add trace unit registers.
18 (aarch64_sys_reg_readonly_p): New function.
19 (aarch64_sys_reg_writeonly_p): Ditto.
20
caeba11c
MR		 212013-11-15 Maciej W. Rozycki <macro@codesourcery.com>
22
23 * mips-opc.c (mips_builtin_opcodes): Add RD_2 to "mfcr" and
24 "mtcr".
25
b83a9376
CM		 262013-11-11 Catherine Moore <clm@codesourcery.com>
27
28 * mips-dis.c (print_insn_mips): Use
29 INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
30 (print_insn_micromips): Likewise.
31 * mips-opc.c (LDD): Remove.
32 (CLD): Include INSN_LOAD_MEMORY.
33 (LM): New.
34 (mips_builtin_opcodes): Use LM instead of LDD.
35 Add LM to load instructions.
36
d56da83e
L		 372013-11-08 H.J. Lu <hongjiu.lu@intel.com>
38
39 PR gas/16140
40 * i386-gen.c (cpu_flag_init): Remove CpuNop from CPU_K6_2_FLAGS.
41 * i386-init.h: Regenerated.
42
49eec193
YZ		 432013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
44
45 * aarch64-opc.c (F_DEPRECATED): New macro.
46 (aarch64_sys_regs): Update; flag "spsr_svc" and "spsr_hyp" with
47 F_DEPRECATED.
48 (aarch64_print_operand): Call aarch64_sys_reg_deprecated_p on
49 AARCH64_OPND_SYSREG.
50
68a64283
YZ		 512013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
52
53 * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
54 (convert_from_csel): Likewise.
55 * aarch64-opc.c (operand_general_constraint_met_p): Handle
56 AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
57 (aarch64_print_operand): Handle AARCH64_OPND_COND1.
58 * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
59 COND for cinc, cset, cinv, csetm and cneg.
60 (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
61 * aarch64-asm-2.c: Re-generated.
62 * aarch64-dis-2.c: Ditto.
63 * aarch64-opc-2.c: Ditto.
64
4e50d5f8
YZ		 652013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
66
67 * aarch64-opc.c (set_syntax_error): New function.
68 (operand_general_constraint_met_p): Replace set_other_error
69 with set_syntax_error.
70
7d4a7d10
AA		 712013-10-30 Andreas Arnez <arnez@linux.vnet.ibm.com>
72
73 * s390-dis.c (init_disasm): Default to full 'zarch' opcode
74 availability even for 31-bit programs.
75
85181173
RR		 762013-10-15 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
77
78 * arm-dis.c (neon_opcodes): Adjust print string for vshll.
79
4edbb8e3
CF		 802013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
81
82 * micromips-opc.c (decode_micromips_operand): Add +T, +U, +V, +W,
83 +d, +e, +h, +k, +l, +n, +o, +u, +v, +w, +x,
84 +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
85 (MSA): New define.
86 (MSA64): New define.
87 (micromips_opcodes): Add MSA instructions.
88 * mips-dis.c (msa_control_names): New array.
89 (mips_abi_choice): Add ASE_MSA to mips32r2.
90 Remove ASE_MDMX from mips64r2.
91 Add ASE_MSA and ASE_MSA64 to mips64r2.
92 (parse_mips_dis_option): Handle -Mmsa.
93 (print_reg): Handle cases for OP_REG_MSA and OP_REG_MSA_CTRL.
94 (print_insn_arg): Handle cases for OP_IMM_INDEX and OP_REG_INDEX.
95 (print_mips_disassembler_options): Print -Mmsa.
96 * mips-opc.c (decode_mips_operand): Add +T, +U, +V, +W, +d, +e, +h, +k,
97 +l, +n, +o, +u, +v, +w, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
98 (MSA): New define.
99 (MSA64): New define.
100 (mips_builtin_op): Add MSA instructions.
101
ae335a4e
SL		 1022013-10-13 Sandra Loosemore <sandra@codesourcery.com>
103
104 * nios2-opc.c (nios2_builtin_reg): Use "sstatus" rather than "ba"
105 as the primary name of r30.
106
6c75cc62
L		 1072013-10-12 Jan Beulich <jbeulich@suse.com>
108
109 * i386-dis.c (intel_operand_size): Move v_bnd_mode alongside the
110 default case.
111 (OP_E_register): Move v_bnd_mode alongside m_mode.
112 * i386-opc.tbl (bndcl, bndcu, bndcn): Split 32- and 64-bit variants.
113 Drop Reg16 and Disp16. Add NoRex64.
114 (bndmk, bndmov, bndldx, bndstx): Drop Disp16.
115 * i386-tbl.h: Re-generate.
116
0e1c2434
SK		 1172013-10-10 Sean Keys <skeys@ipdatasys.com>
118
119 * xgate-opc.c (xgate_opcode): Remove short_hand field from opcode
120 table.
121 * xgate-dis.c (print_insn): Refactor to work with table change.
122
7903e530
RM		 1232013-10-10 Roland McGrath <mcgrathr@google.com>
124
9ce09ba2
RM		 125 * i386-dis.c (oappend_maybe_intel): New function.
126 (OP_ST, OP_STi, append_seg, OP_I, OP_I64, OP_sI, OP_ESreg): Use it.
127 (OP_C, OP_T, CMP_Fixup, OP_EX_VexImmW): Likewise.
128 (VCMP_Fixup, VPCMP_Fixup, PCLMUL_Fixup): Likewise.
129
2b4e983c
RM		 130 * cr16-opc.c (REG): Cast NAME to 'reg' enum type to suppress
131 possible compiler warnings when the union's initializer is
132 actually meant for the 'preg' enum typed member.
133 * crx-opc.c (REG): Likewise.
134
7903e530
RM		 135 * v850-dis.c (v850_cacheop_codes, v850_prefop_codes):
136 Remove duplicate const qualifier.
137
79e0e31d
JB		 1382013-10-08 Jan Beulich <jbeulich@suse.com>
139
140 * i386-opc.tbl (invlpg): Use Anysize instead of Unspecified.
141 (clflush): Use Anysize instead of Byte|Unspecified.
142 (prefetch*): Likewise.
143 * i386-tbl.h: Re-generate.
144
45099dfa
CF		 1452013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
146
147 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
148
916fae91
L		 1492013-09-30 H.J. Lu <hongjiu.lu@intel.com>
150
151 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
152 * i386-init.h: Regenerated.
153
c7b0bd56
SE		 1542013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
155
156 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
157 * i386-init.h: Regenerated.
158
cc9afea3
AM		 1592013-09-20 Alan Modra <amodra@gmail.com>
160
161 * configure: Regenerate.
162
e3f9e852
RS		 1632013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
164
165 * s390-opc.txt (clih): Make the immediate unsigned.
166
74db7efb
NC		 1672013-09-04 Roland McGrath <mcgrathr@google.com>
168
169 PR gas/15914
170 * arm-dis.c (arm_opcodes): Add udf.
171 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
172 (thumb32_opcodes): Add udf.w.
173 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
174
c8094e01
AK		 1752013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
176
177 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
178 For the load fp integer instructions only the suppression flag was
179 new with z196 version.
180
7e105031
NC		 1812013-08-28 Nick Clifton <nickc@redhat.com>
182
183 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
184 immediate is not suitable for the 32-bit ABI.
185
fb6f3895
MR		 1862013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
187
188 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
189 replacing NODS.
190
9aff4b7a
NC		 1912013-08-23 Yuri Chornoivan <yurchor@ukr.net>
192
193 PR binutils/15834
194 * aarch64-asm.c: Fix typos.
195 * aarch64-dis.c: Likewise.
196 * msp430-dis.c: Likewise.
197
5e0dc5ba
RS		 1982013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
199
200 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
201 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
202 Use +H rather than +C for the real "dext".
203 * mips-opc.c (mips_builtin_opcodes): Likewise.
204
0f35dbc4
RS		 2052013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
206
207 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
208 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
209 and OPTIONAL_MAPPED_REG.
210 * mips-opc.c (decode_mips_operand): Likewise.
211 * mips16-opc.c (decode_mips16_operand): Likewise.
212 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
213
79ceb7cb
L		 2142013-08-19 H.J. Lu <hongjiu.lu@intel.com>
215
216 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
217 (PREFIX_EVEX_0F3A3F): Likewise.
218 * i386-dis-evex.h (evex_table): Updated.
219
ee5734f0
RS		 2202013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
221
222 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
223 VCLIPW.
224
d6787ef9
EB		 2252013-08-05 Eric Botcazou <ebotcazou@adacore.com>
226 Konrad Eisele <konrad@gaisler.com>
227
228 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
229 bfd_mach_sparc.
230 * sparc-opc.c (MASK_LEON): Define.
231 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
232 (letandleon): New macro.
233 (v9andleon): Likewise.
234 (sparc_opc): Add leon.
235 (umac): Enable for letandleon.
236 (smac): Likewise.
237 (casa): Enable for v9andleon.
238 (cas): Likewise.
239 (casl): Likewise.
240
14daeee3
RS		 2412013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
242 Richard Sandiford <rdsandiford@googlemail.com>
243
244 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
245 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
246 (print_vu0_channel): New function.
247 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
248 (print_insn_args): Handle '#'.
249 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
250 * mips-opc.c (mips_vu0_channel_mask): New constant.
251 (decode_mips_operand): Handle new VU0 operand types.
252 (VU0, VU0CH): New macros.
253 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
254 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
255 Use "+6" rather than "G" for QMFC2 and QMTC2.
256
3ccad066
RS		 2572013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
258
259 * mips-formats.h (PCREL): Reorder parameters and update the definition
260 to match new mips_pcrel_operand layout.
261 (JUMP, JALX, BRANCH): Update accordingly.
262 * mips16-opc.c (decode_mips16_operand): Likewise.
263
df34fbcc
RS		 2642013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
265
266 * micromips-opc.c (WR_s): Delete.
267
fc76e730
RS		 2682013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
269
270 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
271 New macros.
272 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
273 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
274 (mips_builtin_opcodes): Use the new position-based read-write flags
275 instead of field-based ones. Use UDI for "udi..." instructions.
276 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
277 New macros.
278 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
279 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
280 (WR_SP, RD_16): New macros.
281 (RD_SP): Redefine as an INSN2_* flag.
282 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
283 (mips16_opcodes): Use the new position-based read-write flags
284 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
285 pinfo2 field.
286 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
287 New macros.
288 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
289 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
290 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
291 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
292 (micromips_opcodes): Use the new position-based read-write flags
293 instead of field-based ones.
294 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
295 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
296 of field-based flags.
297
26545944
RS		 2982013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
299
300 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
301 (WR_SP): Replace with...
302 (MOD_SP): ...this.
303 (mips16_opcodes): Update accordingly.
304 * mips-dis.c (print_insn_mips16): Likewise.
305
a8d92fc6
RS		 3062013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
307
308 * mips16-opc.c (mips16_opcodes): Reformat.
309
6a819047
RS		 3102013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
311
312 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
313 for operands that are hard-coded to $0.
314 * micromips-opc.c (micromips_opcodes): Likewise.
315
344c74a6
RS		 3162013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
317
318 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
319 for the single-operand forms of JALR and JALR.HB.
320 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
321 and JALRS.HB.
322
41989114
RS		 3232013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
324
325 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
326 instructions. Fix them to use WR_MACC instead of WR_CC and
327 add missing RD_MACCs.
328
6d075bce
RS		 3292013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
330
331 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
332
4f6ffcd3
PB		 3332013-07-29 Peter Bergner <bergner@vnet.ibm.com>
334
335 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
336
43234a1e
L		 3372013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
338 Alexander Ivchenko <alexander.ivchenko@intel.com>
339 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
340 Sergey Lega <sergey.s.lega@intel.com>
341 Anna Tikhonova <anna.tikhonova@intel.com>
342 Ilya Tocar <ilya.tocar@intel.com>
343 Andrey Turetskiy <andrey.turetskiy@intel.com>
344 Ilya Verbin <ilya.verbin@intel.com>
345 Kirill Yukhin <kirill.yukhin@intel.com>
346 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
347
348 * i386-dis-evex.h: New.
349 * i386-dis.c (OP_Rounding): New.
350 (VPCMP_Fixup): New.
351 (OP_Mask): New.
352 (Rdq): New.
353 (XMxmmq): New.
354 (EXdScalarS): New.
355 (EXymm): New.
356 (EXEvexHalfBcstXmmq): New.
357 (EXxmm_mdq): New.
358 (EXEvexXGscat): New.
359 (EXEvexXNoBcst): New.
360 (VPCMP): New.
361 (EXxEVexR): New.
362 (EXxEVexS): New.
363 (XMask): New.
364 (MaskG): New.
365 (MaskE): New.
366 (MaskR): New.
367 (MaskVex): New.
368 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
369 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
370 evex_rounding_mode, evex_sae_mode, mask_mode.
371 (USE_EVEX_TABLE): New.
372 (EVEX_TABLE): New.
373 (EVEX enum): New.
374 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
375 REG_EVEX_0F38C7.
376 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
377 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
378 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
379 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
380 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
381 MOD_EVEX_0F38C7_REG_6.
382 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
383 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
384 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
385 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
386 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
387 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
388 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
389 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
390 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
391 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
392 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
393 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
394 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
395 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
396 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
397 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
398 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
399 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
400 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
401 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
402 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
403 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
404 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
405 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
406 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
407 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
408 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
409 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
410 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
411 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
412 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
413 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
414 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
415 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
416 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
417 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
418 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
419 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
420 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
421 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
422 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
423 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
424 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
425 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
426 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
427 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
428 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
429 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
430 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
431 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
432 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
433 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
434 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
435 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
436 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
437 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
438 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
439 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
440 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
441 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
442 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
443 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
444 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
445 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
446 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
447 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
448 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
449 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
450 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
451 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
452 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
453 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
454 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
455 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
456 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
457 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
458 PREFIX_EVEX_0F3A55.
459 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
460 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
461 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
462 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
463 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
464 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
465 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
466 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
467 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
468 VEX_W_0F3A32_P_2_LEN_0.
469 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
470 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
471 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
472 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
473 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
474 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
475 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
476 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
477 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
478 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
479 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
480 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
481 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
482 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
483 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
484 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
485 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
486 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
487 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
488 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
489 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
490 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
491 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
492 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
493 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
494 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
495 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
496 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
497 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
498 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
499 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
500 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
501 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
502 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
503 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
504 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
505 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
506 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
507 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
508 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
509 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
510 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
511 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
512 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
513 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
514 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
515 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
516 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
517 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
518 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
519 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
520 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
521 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
522 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
523 (struct vex): Add fields evex, r, v, mask_register_specifier,
524 zeroing, ll, b.
525 (intel_names_xmm): Add upper 16 registers.
526 (att_names_xmm): Ditto.
527 (intel_names_ymm): Ditto.
528 (att_names_ymm): Ditto.
529 (names_zmm): New.
530 (intel_names_zmm): Ditto.
531 (att_names_zmm): Ditto.
532 (names_mask): Ditto.
533 (intel_names_mask): Ditto.
534 (att_names_mask): Ditto.
535 (names_rounding): Ditto.
536 (names_broadcast): Ditto.
537 (x86_64_table): Add escape to evex-table.
538 (reg_table): Include reg_table evex-entries from
539 i386-dis-evex.h. Fix prefetchwt1 instruction.
540 (prefix_table): Add entries for new instructions.
541 (vex_table): Ditto.
542 (vex_len_table): Ditto.
543 (vex_w_table): Ditto.
544 (mod_table): Ditto.
545 (get_valid_dis386): Properly handle new instructions.
546 (print_insn): Handle zmm and mask registers, print mask operand.
547 (intel_operand_size): Support EVEX, new modes and sizes.
548 (OP_E_register): Handle new modes.
549 (OP_E_memory): Ditto.
550 (OP_G): Ditto.
551 (OP_XMM): Ditto.
552 (OP_EX): Ditto.
553 (OP_VEX): Ditto.
554 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
555 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
556 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
557 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
558 CpuAVX512PF and CpuVREX.
559 (operand_type_init): Add OPERAND_TYPE_REGZMM,
560 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
561 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
562 StaticRounding, SAE, Disp8MemShift, NoDefMask.
563 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
564 * i386-init.h: Regenerate.
565 * i386-opc.h (CpuAVX512F): New.
566 (CpuAVX512CD): New.
567 (CpuAVX512ER): New.
568 (CpuAVX512PF): New.
569 (CpuVREX): New.
570 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
571 cpuavx512pf and cpuvrex fields.
572 (VecSIB): Add VecSIB512.
573 (EVex): New.
574 (Masking): New.
575 (VecESize): New.
576 (Broadcast): New.
577 (StaticRounding): New.
578 (SAE): New.
579 (Disp8MemShift): New.
580 (NoDefMask): New.
581 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
582 staticrounding, sae, disp8memshift and nodefmask.
583 (RegZMM): New.
584 (Zmmword): Ditto.
585 (Vec_Disp8): Ditto.
586 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
587 fields.
588 (RegVRex): New.
589 * i386-opc.tbl: Add AVX512 instructions.
590 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
591 registers, mask registers.
592 * i386-tbl.h: Regenerate.
593
1d2db237
RS		 5942013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
595
596 PR gas/15220
597 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
598 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
599
a0046408
L		 6002013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
601
602 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
603 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
604 PREFIX_0F3ACC.
605 (prefix_table): Updated.
606 (three_byte_table): Likewise.
607 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
608 (cpu_flags): Add CpuSHA.
609 (i386_cpu_flags): Add cpusha.
610 * i386-init.h: Regenerate.
611 * i386-opc.h (CpuSHA): New.
612 (CpuUnused): Restored.
613 (i386_cpu_flags): Add cpusha.
614 * i386-opc.tbl: Add SHA instructions.
615 * i386-tbl.h: Regenerate.
616
7e8b059b
L		 6172013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
618 Kirill Yukhin <kirill.yukhin@intel.com>
619 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
620
621 * i386-dis.c (BND_Fixup): New.
622 (Ebnd): New.
623 (Ev_bnd): New.
624 (Gbnd): New.
625 (BND): New.
626 (v_bnd_mode): New.
627 (bnd_mode): New.
c623f86c
L		 628 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
629 MOD_0F1B_PREFIX_1.
630 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 631 (dis tables): Replace XX with BND for near branch and call
632 instructions.
633 (prefix_table): Add new entries.
634 (mod_table): Likewise.
635 (names_bnd): New.
636 (intel_names_bnd): New.
637 (att_names_bnd): New.
638 (BND_PREFIX): New.
639 (prefix_name): Handle BND_PREFIX.
640 (print_insn): Initialize names_bnd.
641 (intel_operand_size): Handle new modes.
642 (OP_E_register): Likewise.
643 (OP_E_memory): Likewise.
644 (OP_G): Likewise.
645 * i386-gen.c (cpu_flag_init): Add CpuMPX.
646 (cpu_flags): Add CpuMPX.
647 (operand_type_init): Add RegBND.
648 (opcode_modifiers): Add BNDPrefixOk.
649 (operand_types): Add RegBND.
650 * i386-init.h: Regenerate.
651 * i386-opc.h (CpuMPX): New.
652 (CpuUnused): Comment out.
653 (i386_cpu_flags): Add cpumpx.
654 (BNDPrefixOk): New.
655 (i386_opcode_modifier): Add bndprefixok.
656 (RegBND): New.
657 (i386_operand_type): Add regbnd.
658 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
659 Add MPX instructions and bnd prefix.
660 * i386-reg.tbl: Add bnd0-bnd3 registers.
661 * i386-tbl.h: Regenerate.
662
b56e23fb
RS		 6632013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
664
665 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
666 ATTRIBUTE_UNUSED.
667
e7ae278d
RS		 6682013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
669
670 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
671 special rules.
672 * Makefile.in: Regenerate.
673 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
674 all fields. Reformat.
675
c3c07478
RS		 6762013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
677
678 * mips16-opc.c: Include mips-formats.h.
679 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
680 static arrays.
681 (decode_mips16_operand): New function.
682 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
683 (print_insn_arg): Handle OP_ENTRY_EXIT list.
684 Abort for OP_SAVE_RESTORE_LIST.
685 (print_mips16_insn_arg): Change interface. Use mips_operand
686 structures. Delete GET_OP_S. Move GET_OP definition to...
687 (print_insn_mips16): ...here. Call init_print_arg_state.
688 Update the call to print_mips16_insn_arg.
689
ab902481
RS		 6902013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
691
692 * mips-formats.h: New file.
693 * mips-opc.c: Include mips-formats.h.
694 (reg_0_map): New static array.
695 (decode_mips_operand): New function.
696 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
697 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
698 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
699 (int_c_map): New static arrays.
700 (decode_micromips_operand): New function.
701 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
702 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
703 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
704 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
705 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
706 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
707 (micromips_imm_b_map, micromips_imm_c_map): Delete.
708 (print_reg): New function.
709 (mips_print_arg_state): New structure.
710 (init_print_arg_state, print_insn_arg): New functions.
711 (print_insn_args): Change interface and use mips_operand structures.
712 Delete GET_OP_S. Move GET_OP definition to...
713 (print_insn_mips): ...here. Update the call to print_insn_args.
714 (print_insn_micromips): Use print_insn_args.
715
cc537e56
RS		 7162013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
717
718 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
719 in macros.
720
7a5f87ce
RS		 7212013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
722
723 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
724 ADDA.S, MULA.S and SUBA.S.
725
41741fa4
L		 7262013-07-08 H.J. Lu <hongjiu.lu@intel.com>
727
728 PR gas/13572
729 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
730 * i386-tbl.h: Regenerated.
731
f2ae14a1
RS		 7322013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
733
734 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
735 and SD A(B) macros up.
736 * micromips-opc.c (micromips_opcodes): Likewise.
737
04c9d415
RS		 7382013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
739
740 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
741 instructions.
742
5c324c16
RS		 7432013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
744
745 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
746 MDMX-like instructions.
747 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
748 printing "Q" operands for INSN_5400 instructions.
749
23e69e47
RS		 7502013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
751
752 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
753 "+S" for "cins".
754 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
755 Combine cases.
756
27c5c572
RS		 7572013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
758
759 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
760 "jalx".
761 * mips16-opc.c (mips16_opcodes): Likewise.
762 * micromips-opc.c (micromips_opcodes): Likewise.
763 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
764 (print_insn_mips16): Handle "+i".
765 (print_insn_micromips): Likewise. Conditionally preserve the
766 ISA bit for "a" but not for "+i".
767
e76ff5ab
RS		 7682013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
769
770 * micromips-opc.c (WR_mhi): Rename to..
771 (WR_mh): ...this.
772 (micromips_opcodes): Update "movep" entry accordingly. Replace
773 "mh,mi" with "mh".
774 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
775 (micromips_to_32_reg_h_map1): ...this.
776 (micromips_to_32_reg_i_map): Rename to...
777 (micromips_to_32_reg_h_map2): ...this.
778 (print_micromips_insn): Remove "mi" case. Print both registers
779 in the pair for "mh".
780
fa7616a4
RS		 7812013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
782
783 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
784 * micromips-opc.c (micromips_opcodes): Likewise.
785 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
786 and "+T" handling. Check for a "0" suffix when deciding whether to
787 use coprocessor 0 names. In that case, also check for ",H" selectors.
788
fb798c50
AK		 7892013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
790
791 * s390-opc.c (J12_12, J24_24): New macros.
792 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
793 (MASK_MII_UPI): Rename to MASK_MII_UPP.
794 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
795
58ae08f2
AM		 7962013-07-04 Alan Modra <amodra@gmail.com>
797
798 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
799
b5e04c2b
NC		 8002013-06-26 Nick Clifton <nickc@redhat.com>
801
802 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
803 field when checking for type 2 nop.
804 * rx-decode.c: Regenerate.
805
833794fc
MR		 8062013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
807
808 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
809 and "movep" macros.
810
1bbce132
MR		 8112013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
812
813 * mips-dis.c (is_mips16_plt_tail): New function.
814 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
815 word.
816 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
817
34c911a4
NC		 8182013-06-21 DJ Delorie <dj@redhat.com>
819
820 * msp430-decode.opc: New.
821 * msp430-decode.c: New/generated.
822 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
823 (MAINTAINER_CLEANFILES): Likewise.
824 Add rule to build msp430-decode.c frommsp430decode.opc
825 using the opc2c program.
826 * Makefile.in: Regenerate.
827 * configure.in: Add msp430-decode.lo to msp430 architecture files.
828 * configure: Regenerate.
829
b9eead84
YZ		 8302013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
831
832 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
833 (SYMTAB_AVAILABLE): Removed.
834 (#include "elf/aarch64.h): Ditto.
835
7f3c4072
CM		 8362013-06-17 Catherine Moore <clm@codesourcery.com>
837 Maciej W. Rozycki <macro@codesourcery.com>
838 Chao-Ying Fu <fu@mips.com>
839
840 * micromips-opc.c (EVA): Define.
841 (TLBINV): Define.
842 (micromips_opcodes): Add EVA opcodes.
843 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
844 (print_insn_args): Handle EVA offsets.
845 (print_insn_micromips): Likewise.
846 * mips-opc.c (EVA): Define.
847 (TLBINV): Define.
848 (mips_builtin_opcodes): Add EVA opcodes.
849
de40ceb6
AM		 8502013-06-17 Alan Modra <amodra@gmail.com>
851
852 * Makefile.am (mips-opc.lo): Add rules to create automatic
853 dependency files. Pass archdefs.
854 (micromips-opc.lo, mips16-opc.lo): Likewise.
855 * Makefile.in: Regenerate.
856
3531d549
DD		 8572013-06-14 DJ Delorie <dj@redhat.com>
858
859 * rx-decode.opc (rx_decode_opcode): Bit operations on
860 registers are 32-bit operations, not 8-bit operations.
861 * rx-decode.c: Regenerate.
862
ba92f7fb
CF		 8632013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
864
865 * micromips-opc.c (IVIRT): New define.
866 (IVIRT64): New define.
867 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
868 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
869
870 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
871 dmtgc0 to print cp0 names.
872
9daf7bab
SL		 8732013-06-09 Sandra Loosemore <sandra@codesourcery.com>
874
875 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
876 argument.
877
d301a56b
RS		 8782013-06-08 Catherine Moore <clm@codesourcery.com>
879 Richard Sandiford <rdsandiford@googlemail.com>
880
881 * micromips-opc.c (D32, D33, MC): Update definitions.
882 (micromips_opcodes): Initialize ase field.
883 * mips-dis.c (mips_arch_choice): Add ase field.
884 (mips_arch_choices): Initialize ase field.
885 (set_default_mips_dis_options): Declare and setup mips_ase.
886 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
887 MT32, MC): Update definitions.
888 (mips_builtin_opcodes): Initialize ase field.
889
a3dcb6c5
RS		 8902013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
891
892 * s390-opc.txt (flogr): Require a register pair destination.
893
6cf1d90c
AK		 8942013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
895
896 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
897 instruction format.
898
c77c0862
RS		 8992013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
900
901 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
902
c0637f3a
PB		 9032013-05-20 Peter Bergner <bergner@vnet.ibm.com>
904
905 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
906 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
907 XLS_MASK, PPCVSX2): New defines.
908 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
909 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
910 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
911 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
912 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
913 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
914 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
915 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
916 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
917 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
918 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
919 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
920 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
921 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
922 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
923 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
924 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
925 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
926 <lxvx, stxvx>: New extended mnemonics.
927
4934fdaf
AM		 9282013-05-17 Alan Modra <amodra@gmail.com>
929
930 * ia64-raw.tbl: Replace non-ASCII char.
931 * ia64-waw.tbl: Likewise.
932 * ia64-asmtab.c: Regenerate.
933
6091d651
SE		 9342013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
935
936 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
937 * i386-init.h: Regenerated.
938
d2865ed3
YZ		 9392013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
940
941 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
942 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
943 check from [0, 255] to [-128, 255].
944
b015e599
AP		 9452013-05-09 Andrew Pinski <apinski@cavium.com>
946
947 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
948 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
949 (parse_mips_dis_option): Handle the virt option.
950 (print_insn_args): Handle "+J".
951 (print_mips_disassembler_options): Print out message about virt64.
952 * mips-opc.c (IVIRT): New define.
953 (IVIRT64): New define.
954 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
955 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
956 Move rfe to the bottom as it conflicts with tlbgp.
957
9f0682fe
AM		 9582013-05-09 Alan Modra <amodra@gmail.com>
959
960 * ppc-opc.c (extract_vlesi): Properly sign extend.
961 (extract_vlensi): Likewise. Comment reason for setting invalid.
962
13761a11
NC		 9632013-05-02 Nick Clifton <nickc@redhat.com>
964
965 * msp430-dis.c: Add support for MSP430X instructions.
966
e3031850
SL		 9672013-04-24 Sandra Loosemore <sandra@codesourcery.com>
968
969 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
970 to "eccinj".
971
17310e56
NC		 9722013-04-17 Wei-chen Wang <cole945@gmail.com>
973
974 PR binutils/15369
975 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
976 of CGEN_CPU_ENDIAN.
977 (hash_insns_list): Likewise.
978
731df338
JK		 9792013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
980
981 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
982 warning workaround.
983
5f77db52
JB		 9842013-04-08 Jan Beulich <jbeulich@suse.com>
985
986 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
987 * i386-tbl.h: Re-generate.
988
0afd1215
DM		 9892013-04-06 David S. Miller <davem@davemloft.net>
990
991 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
992 of an opcode, prefer the one with F_PREFERRED set.
993 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
994 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
995 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
996 mark existing mnenomics as aliases. Add "cc" suffix to edge
997 instructions generating condition codes, mark existing mnenomics
998 as aliases. Add "fp" prefix to VIS compare instructions, mark
999 existing mnenomics as aliases.
1000
41702d50
NC		 10012013-04-03 Nick Clifton <nickc@redhat.com>
1002
1003 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
1004 destination address by subtracting the operand from the current
1005 address.
1006 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
1007 a positive value in the insn.
1008 (extract_u16_loop): Do not negate the returned value.
1009 (D16_LOOP): Add V850_INVERSE_PCREL flag.
1010
1011 (ceilf.sw): Remove duplicate entry.
1012 (cvtf.hs): New entry.
1013 (cvtf.sh): Likewise.
1014 (fmaf.s): Likewise.
1015 (fmsf.s): Likewise.
1016 (fnmaf.s): Likewise.
1017 (fnmsf.s): Likewise.
1018 (maddf.s): Restrict to E3V5 architectures.
1019 (msubf.s): Likewise.
1020 (nmaddf.s): Likewise.
1021 (nmsubf.s): Likewise.
1022
55cf16e1
L		 10232013-03-27 H.J. Lu <hongjiu.lu@intel.com>
1024
1025 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
1026 check address mode.
1027 (print_insn): Pass sizeflag to get_sib.
1028
51dcdd4d
NC		 10292013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
1030
1031 PR binutils/15068
1032 * tic6x-dis.c: Add support for displaying 16-bit insns.
1033
795b8e6b
NC		 10342013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
1035
1036 PR gas/15095
1037 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
1038 individual msb and lsb halves in src1 & src2 fields. Discard the
1039 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
1040 follow what Ti SDK does in that case as any value in the src1
1041 field yields the same output with SDK disassembler.
1042
314d60dd
ME		 10432013-03-12 Michael Eager <eager@eagercon.com>
1044
795b8e6b 1045 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 1046
dad60f8e
SL		 10472013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1048
1049 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
1050
f5cb796a
SL		 10512013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1052
1053 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
1054
21fde85c
SL		 10552013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
1056
1057 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
1058
dd5181d5
KT		 10592013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1060
1061 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
1062 (thumb32_opcodes): Likewise.
1063 (print_insn_thumb32): Handle 'S' control char.
1064
87a8d6cb
NC		 10652013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
1066
1067 * lm32-desc.c: Regenerate.
1068
99dce992
L		 10692013-03-01 H.J. Lu <hongjiu.lu@intel.com>
1070
1071 * i386-reg.tbl (riz): Add RegRex64.
1072 * i386-tbl.h: Regenerated.
1073
e60bb1dd
YZ		 10742013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
1075
1076 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
1077 (aarch64_feature_crc): New static.
1078 (CRC): New macro.
1079 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
1080 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
1081 * aarch64-asm-2.c: Re-generate.
1082 * aarch64-dis-2.c: Ditto.
1083 * aarch64-opc-2.c: Ditto.
1084
c7570fcd
AM		 10852013-02-27 Alan Modra <amodra@gmail.com>
1086
1087 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
1088 * rl78-decode.c: Regenerate.
1089
151fa98f
NC		 10902013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
1091
1092 * rl78-decode.opc: Fix encoding of DIVWU insn.
1093 * rl78-decode.c: Regenerate.
1094
5c111e37
L		 10952013-02-19 H.J. Lu <hongjiu.lu@intel.com>
1096
1097 PR gas/15159
1098 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
1099
1100 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
1101 (cpu_flags): Add CpuSMAP.
1102
1103 * i386-opc.h (CpuSMAP): New.
1104 (i386_cpu_flags): Add cpusmap.
1105
1106 * i386-opc.tbl: Add clac and stac.
1107
1108 * i386-init.h: Regenerated.
1109 * i386-tbl.h: Likewise.
1110
9d1df426
NC		 11112013-02-15 Markos Chandras <markos.chandras@imgtec.com>
1112
1113 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
1114 which also makes the disassembler output be in little
1115 endian like it should be.
1116
a1ccaec9
YZ		 11172013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
1118
1119 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
1120 fields to NULL.
1121 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
1122
ef068ef4 11232013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 1124
1125 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
1126 section disassembled.
1127
6fe6ded9
RE		 11282013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1129
1130 * arm-dis.c: Update strht pattern.
1131
0aa27725
RS		 11322013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
1133
1134 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
1135 single-float. Disable ll, lld, sc and scd for EE. Disable the
1136 trunc.w.s macro for EE.
1137
36591ba1
SL		 11382013-02-06 Sandra Loosemore <sandra@codesourcery.com>
1139 Andrew Jenner <andrew@codesourcery.com>
1140
1141 Based on patches from Altera Corporation.
1142
1143 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1144 nios2-opc.c.
1145 * Makefile.in: Regenerated.
1146 * configure.in: Add case for bfd_nios2_arch.
1147 * configure: Regenerated.
1148 * disassemble.c (ARCH_nios2): Define.
1149 (disassembler): Add case for bfd_arch_nios2.
1150 * nios2-dis.c: New file.
1151 * nios2-opc.c: New file.
1152
545093a4
AM		 11532013-02-04 Alan Modra <amodra@gmail.com>
1154
1155 * po/POTFILES.in: Regenerate.
1156 * rl78-decode.c: Regenerate.
1157 * rx-decode.c: Regenerate.
1158
e30181a5
YZ		 11592013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1160
1161 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1162 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1163 * aarch64-asm.c (convert_xtl_to_shll): New function.
1164 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1165 calling convert_xtl_to_shll.
1166 * aarch64-dis.c (convert_shll_to_xtl): New function.
1167 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1168 calling convert_shll_to_xtl.
1169 * aarch64-gen.c: Update copyright year.
1170 * aarch64-asm-2.c: Re-generate.
1171 * aarch64-dis-2.c: Re-generate.
1172 * aarch64-opc-2.c: Re-generate.
1173
78c8d46c
NC		 11742013-01-24 Nick Clifton <nickc@redhat.com>
1175
1176 * v850-dis.c: Add support for e3v5 architecture.
1177 * v850-opc.c: Likewise.
1178
f5555712
YZ		 11792013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1180
1181 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1182 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1183 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1184 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1185 alignment check; change to call set_sft_amount_out_of_range_error
1186 instead of set_imm_out_of_range_error.
1187 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1188 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1189 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1190 SIMD_IMM_SFT.
1191
2f81ff92
L		 11922013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1193
1194 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1195
1196 * i386-init.h: Regenerated.
1197 * i386-tbl.h: Likewise.
1198
dd42f060
NC		 11992013-01-15 Nick Clifton <nickc@redhat.com>
1200
1201 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1202 values.
1203 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1204
a4533ed8
NC		 12052013-01-14 Will Newton <will.newton@imgtec.com>
1206
1207 * metag-dis.c (REG_WIDTH): Increase to 64.
1208
5817ffd1
PB		 12092013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1210
1211 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1212 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1213 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1214 (SH6): Update.
1215 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1216 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1217 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1218 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1219
a3c62988
NC		 12202013-01-10 Will Newton <will.newton@imgtec.com>
1221
1222 * Makefile.am: Add Meta.
1223 * configure.in: Add Meta.
1224 * disassemble.c: Add Meta support.
1225 * metag-dis.c: New file.
1226 * Makefile.in: Regenerate.
1227 * configure: Regenerate.
1228
73335eae
NC		 12292013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1230
1231 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1232 (match_opcode): Rename to cr16_match_opcode.
1233
e407c74b
NC		 12342013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1235
1236 * mips-dis.c: Add names for CP0 registers of r5900.
1237 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1238 instructions sq and lq.
1239 Add support for MIPS r5900 CPU.
1240 Add support for 128 bit MMI (Multimedia Instructions).
1241 Add support for EE instructions (Emotion Engine).
1242 Disable unsupported floating point instructions (64 bit and
1243 undefined compare operations).
1244 Enable instructions of MIPS ISA IV which are supported by r5900.
1245 Disable 64 bit co processor instructions.
1246 Disable 64 bit multiplication and division instructions.
1247 Disable instructions for co-processor 2 and 3, because these are
1248 not supported (preparation for later VU0 support (Vector Unit)).
1249 Disable cvt.w.s because this behaves like trunc.w.s and the
1250 correct execution can't be ensured on r5900.
1251 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1252 will confuse less developers and compilers.
1253
a32c3ff8
NC		 12542013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1255
fb098a1e
YZ		 1256 * aarch64-opc.c (aarch64_print_operand): Change to print
1257 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1258 in comment.
1259 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1260 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1261 OP_MOV_IMM_WIDE.
1262
12632013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1264
1265 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1266 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1267
62658407
L		 12682013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1269
1270 * i386-gen.c (process_copyright): Update copyright year to 2013.
1271
bab4becb 12722013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1273
bab4becb
NC		 1274 * cr16-dis.c (match_opcode,make_instruction): Remove static
1275 declaration.
1276 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1277 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1278
bab4becb 1279For older changes see ChangeLog-2012
252b5132 1280\f
bab4becb 1281Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1282
1283Copying and distribution of this file, with or without modification,
1284are permitted in any medium without royalty provided the copyright
1285notice and this notice are preserved.
1286
252b5132 1287Local Variables:
2f6d2f85
NC		 1288mode: change-log
1289left-margin: 8
1290fill-column: 74
252b5132
RH		 1291version-control: never
1292End:
GDB Binutils - Deliverables
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