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bb2a1453
AS		 12020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2
3 PR 25848
4 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
5 cmpi only on m68020up and cpu32.
6
c2e5c986
SD		 72020-04-20 Sudakshina Das <sudi.das@arm.com>
8
9 * aarch64-asm.c (aarch64_ins_none): New.
10 * aarch64-asm.h (ins_none): New declaration.
11 * aarch64-dis.c (aarch64_ext_none): New.
12 * aarch64-dis.h (ext_none): New declaration.
13 * aarch64-opc.c (aarch64_print_operand): Update case for
14 AARCH64_OPND_BARRIER_PSB.
15 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
16 (AARCH64_OPERANDS): Update inserter/extracter for
17 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
18 * aarch64-asm-2.c: Regenerated.
19 * aarch64-dis-2.c: Regenerated.
20 * aarch64-opc-2.c: Regenerated.
21
8a6e1d1d
SD		 222020-04-20 Sudakshina Das <sudi.das@arm.com>
23
24 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
25 (aarch64_feature_ras, RAS): Likewise.
26 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
27 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
28 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
29 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
30 * aarch64-asm-2.c: Regenerated.
31 * aarch64-dis-2.c: Regenerated.
32 * aarch64-opc-2.c: Regenerated.
33
e409955d
FS		 342020-04-17 Fredrik Strupe <fredrik@strupe.net>
35
36 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
37 (print_insn_neon): Support disassembly of conditional
38 instructions.
39
c54a9b56
DF		 402020-02-16 David Faust <david.faust@oracle.com>
41
42 * bpf-desc.c: Regenerate.
43 * bpf-desc.h: Likewise.
44 * bpf-opc.c: Regenerate.
45 * bpf-opc.h: Likewise.
46
bb651e8b
CL		 472020-04-07 Lili Cui <lili.cui@intel.com>
48
49 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
50 (prefix_table): New instructions (see prefixes above).
51 (rm_table): Likewise
52 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
53 CPU_ANY_TSXLDTRK_FLAGS.
54 (cpu_flags): Add CpuTSXLDTRK.
55 * i386-opc.h (enum): Add CpuTSXLDTRK.
56 (i386_cpu_flags): Add cputsxldtrk.
57 * i386-opc.tbl: Add XSUSPLDTRK insns.
58 * i386-init.h: Regenerate.
59 * i386-tbl.h: Likewise.
60
4b27d27c
L		 612020-04-02 Lili Cui <lili.cui@intel.com>
62
63 * i386-dis.c (prefix_table): New instructions serialize.
64 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
65 CPU_ANY_SERIALIZE_FLAGS.
66 (cpu_flags): Add CpuSERIALIZE.
67 * i386-opc.h (enum): Add CpuSERIALIZE.
68 (i386_cpu_flags): Add cpuserialize.
69 * i386-opc.tbl: Add SERIALIZE insns.
70 * i386-init.h: Regenerate.
71 * i386-tbl.h: Likewise.
72
832a5807
AM		 732020-03-26 Alan Modra <amodra@gmail.com>
74
75 * disassemble.h (opcodes_assert): Declare.
76 (OPCODES_ASSERT): Define.
77 * disassemble.c: Don't include assert.h. Include opintl.h.
78 (opcodes_assert): New function.
79 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
80 (bfd_h8_disassemble): Reduce size of data array. Correctly
81 calculate maxlen. Omit insn decoding when insn length exceeds
82 maxlen. Exit from nibble loop when looking for E, before
83 accessing next data byte. Move processing of E outside loop.
84 Replace tests of maxlen in loop with assertions.
85
4c4addbe
AM		 862020-03-26 Alan Modra <amodra@gmail.com>
87
88 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
89
a18cd0ca
AM		 902020-03-25 Alan Modra <amodra@gmail.com>
91
92 * z80-dis.c (suffix): Init mybuf.
93
57cb32b3
AM		 942020-03-22 Alan Modra <amodra@gmail.com>
95
96 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
97 successflly read from section.
98
beea5cc1
AM		 992020-03-22 Alan Modra <amodra@gmail.com>
100
101 * arc-dis.c (find_format): Use ISO C string concatenation rather
102 than line continuation within a string. Don't access needs_limm
103 before testing opcode != NULL.
104
03704c77
AM		 1052020-03-22 Alan Modra <amodra@gmail.com>
106
107 * ns32k-dis.c (print_insn_arg): Update comment.
108 (print_insn_ns32k): Reduce size of index_offset array, and
109 initialize, passing -1 to print_insn_arg for args that are not
110 an index. Don't exit arg loop early. Abort on bad arg number.
111
d1023b5d
AM		 1122020-03-22 Alan Modra <amodra@gmail.com>
113
114 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
115 * s12z-opc.c: Formatting.
116 (operands_f): Return an int.
117 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
118 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
119 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
120 (exg_sex_discrim): Likewise.
121 (create_immediate_operand, create_bitfield_operand),
122 (create_register_operand_with_size, create_register_all_operand),
123 (create_register_all16_operand, create_simple_memory_operand),
124 (create_memory_operand, create_memory_auto_operand): Don't
125 segfault on malloc failure.
126 (z_ext24_decode): Return an int status, negative on fail, zero
127 on success.
128 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
129 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
130 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
131 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
132 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
133 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
134 (loop_primitive_decode, shift_decode, psh_pul_decode),
135 (bit_field_decode): Similarly.
136 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
137 to return value, update callers.
138 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
139 Don't segfault on NULL operand.
140 (decode_operation): Return OP_INVALID on first fail.
141 (decode_s12z): Check all reads, returning -1 on fail.
142
340f3ac8
AM		 1432020-03-20 Alan Modra <amodra@gmail.com>
144
145 * metag-dis.c (print_insn_metag): Don't ignore status from
146 read_memory_func.
147
fe90ae8a
AM		 1482020-03-20 Alan Modra <amodra@gmail.com>
149
150 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
151 Initialize parts of buffer not written when handling a possible
152 2-byte insn at end of section. Don't attempt decoding of such
153 an insn by the 4-byte machinery.
154
833d919c
AM		 1552020-03-20 Alan Modra <amodra@gmail.com>
156
157 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
158 partially filled buffer. Prevent lookup of 4-byte insns when
159 only VLE 2-byte insns are possible due to section size. Print
160 ".word" rather than ".long" for 2-byte leftovers.
161
327ef784
NC		 1622020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
163
164 PR 25641
165 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
166
1673df32
JB		 1672020-03-13 Jan Beulich <jbeulich@suse.com>
168
169 * i386-dis.c (X86_64_0D): Rename to ...
170 (X86_64_0E): ... this.
171
384f3689
L		 1722020-03-09 H.J. Lu <hongjiu.lu@intel.com>
173
174 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
175 * Makefile.in: Regenerated.
176
865e2027
JB		 1772020-03-09 Jan Beulich <jbeulich@suse.com>
178
179 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
180 3-operand pseudos.
181 * i386-tbl.h: Re-generate.
182
2f13234b
JB		 1832020-03-09 Jan Beulich <jbeulich@suse.com>
184
185 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
186 vprot*, vpsha*, and vpshl*.
187 * i386-tbl.h: Re-generate.
188
3fabc179
JB		 1892020-03-09 Jan Beulich <jbeulich@suse.com>
190
191 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
192 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
193 * i386-tbl.h: Re-generate.
194
3677e4c1
JB		 1952020-03-09 Jan Beulich <jbeulich@suse.com>
196
197 * i386-gen.c (set_bitfield): Ignore zero-length field names.
198 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
199 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
200 * i386-tbl.h: Re-generate.
201
4c4898e8
JB		 2022020-03-09 Jan Beulich <jbeulich@suse.com>
203
204 * i386-gen.c (struct template_arg, struct template_instance,
205 struct template_param, struct template, templates,
206 parse_template, expand_templates): New.
207 (process_i386_opcodes): Various local variables moved to
208 expand_templates. Call parse_template and expand_templates.
209 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
210 * i386-tbl.h: Re-generate.
211
bc49bfd8
JB		 2122020-03-06 Jan Beulich <jbeulich@suse.com>
213
214 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
215 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
216 register and memory source templates. Replace VexW= by VexW*
217 where applicable.
218 * i386-tbl.h: Re-generate.
219
4873e243
JB		 2202020-03-06 Jan Beulich <jbeulich@suse.com>
221
222 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
223 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
224 * i386-tbl.h: Re-generate.
225
672a349b
JB		 2262020-03-06 Jan Beulich <jbeulich@suse.com>
227
228 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
229 * i386-tbl.h: Re-generate.
230
4ed21b58
JB		 2312020-03-06 Jan Beulich <jbeulich@suse.com>
232
233 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
234 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
235 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
236 VexW0 on SSE2AVX variants.
237 (vmovq): Drop NoRex64 from XMM/XMM variants.
238 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
239 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
240 applicable use VexW0.
241 * i386-tbl.h: Re-generate.
242
643bb870
JB		 2432020-03-06 Jan Beulich <jbeulich@suse.com>
244
245 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
246 * i386-opc.h (Rex64): Delete.
247 (struct i386_opcode_modifier): Remove rex64 field.
248 * i386-opc.tbl (crc32): Drop Rex64.
249 Replace Rex64 with Size64 everywhere else.
250 * i386-tbl.h: Re-generate.
251
a23b33b3
JB		 2522020-03-06 Jan Beulich <jbeulich@suse.com>
253
254 * i386-dis.c (OP_E_memory): Exclude recording of used address
255 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
256 addressed memory operands for MPX insns.
257
a0497384
JB		 2582020-03-06 Jan Beulich <jbeulich@suse.com>
259
260 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
261 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
262 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
263 (ptwrite): Split into non-64-bit and 64-bit forms.
264 * i386-tbl.h: Re-generate.
265
b630c145
JB		 2662020-03-06 Jan Beulich <jbeulich@suse.com>
267
268 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
269 template.
270 * i386-tbl.h: Re-generate.
271
a847e322
JB		 2722020-03-04 Jan Beulich <jbeulich@suse.com>
273
274 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
275 (prefix_table): Move vmmcall here. Add vmgexit.
276 (rm_table): Replace vmmcall entry by prefix_table[] escape.
277 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
278 (cpu_flags): Add CpuSEV_ES entry.
279 * i386-opc.h (CpuSEV_ES): New.
280 (union i386_cpu_flags): Add cpusev_es field.
281 * i386-opc.tbl (vmgexit): New.
282 * i386-init.h, i386-tbl.h: Re-generate.
283
3cd7f3e3
L		 2842020-03-03 H.J. Lu <hongjiu.lu@intel.com>
285
286 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
287 with MnemonicSize.
288 * i386-opc.h (IGNORESIZE): New.
289 (DEFAULTSIZE): Likewise.
290 (IgnoreSize): Removed.
291 (DefaultSize): Likewise.
292 (MnemonicSize): New.
293 (i386_opcode_modifier): Replace ignoresize/defaultsize with
294 mnemonicsize.
295 * i386-opc.tbl (IgnoreSize): New.
296 (DefaultSize): Likewise.
297 * i386-tbl.h: Regenerated.
298
b8ba1385
SB		 2992020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
300
301 PR 25627
302 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
303 instructions.
304
10d97a0f
L		 3052020-03-03 H.J. Lu <hongjiu.lu@intel.com>
306
307 PR gas/25622
308 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
309 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
310 * i386-tbl.h: Regenerated.
311
dc1e8a47
AM		 3122020-02-26 Alan Modra <amodra@gmail.com>
313
314 * aarch64-asm.c: Indent labels correctly.
315 * aarch64-dis.c: Likewise.
316 * aarch64-gen.c: Likewise.
317 * aarch64-opc.c: Likewise.
318 * alpha-dis.c: Likewise.
319 * i386-dis.c: Likewise.
320 * nds32-asm.c: Likewise.
321 * nfp-dis.c: Likewise.
322 * visium-dis.c: Likewise.
323
265b4673
CZ		 3242020-02-25 Claudiu Zissulescu <claziss@gmail.com>
325
326 * arc-regs.h (int_vector_base): Make it available for all ARC
327 CPUs.
328
bd0cf5a6
NC		 3292020-02-20 Nelson Chu <nelson.chu@sifive.com>
330
331 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
332 changed.
333
fa164239
JW		 3342020-02-19 Nelson Chu <nelson.chu@sifive.com>
335
336 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
337 c.mv/c.li if rs1 is zero.
338
272a84b1
L		 3392020-02-17 H.J. Lu <hongjiu.lu@intel.com>
340
341 * i386-gen.c (cpu_flag_init): Replace CpuABM with
342 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
343 CPU_POPCNT_FLAGS.
344 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
345 * i386-opc.h (CpuABM): Removed.
346 (CpuPOPCNT): New.
347 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
348 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
349 popcnt. Remove CpuABM from lzcnt.
350 * i386-init.h: Regenerated.
351 * i386-tbl.h: Likewise.
352
1f730c46
JB		 3532020-02-17 Jan Beulich <jbeulich@suse.com>
354
355 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
356 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
357 VexW1 instead of open-coding them.
358 * i386-tbl.h: Re-generate.
359
c8f8eebc
JB		 3602020-02-17 Jan Beulich <jbeulich@suse.com>
361
362 * i386-opc.tbl (AddrPrefixOpReg): Define.
363 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
364 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
365 templates. Drop NoRex64.
366 * i386-tbl.h: Re-generate.
367
b9915cbc
JB		 3682020-02-17 Jan Beulich <jbeulich@suse.com>
369
370 PR gas/6518
371 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
372 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
373 into Intel syntax instance (with Unpsecified) and AT&T one
374 (without).
375 (vcvtneps2bf16): Likewise, along with folding the two so far
376 separate ones.
377 * i386-tbl.h: Re-generate.
378
ce504911
L		 3792020-02-16 H.J. Lu <hongjiu.lu@intel.com>
380
381 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
382 CPU_ANY_SSE4A_FLAGS.
383
dabec65d
AM		 3842020-02-17 Alan Modra <amodra@gmail.com>
385
386 * i386-gen.c (cpu_flag_init): Correct last change.
387
af5c13b0
L		 3882020-02-16 H.J. Lu <hongjiu.lu@intel.com>
389
390 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
391 CPU_ANY_SSE4_FLAGS.
392
6867aac0
L		 3932020-02-14 H.J. Lu <hongjiu.lu@intel.com>
394
395 * i386-opc.tbl (movsx): Remove Intel syntax comments.
396 (movzx): Likewise.
397
65fca059
JB		 3982020-02-14 Jan Beulich <jbeulich@suse.com>
399
400 PR gas/25438
401 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
402 destination for Cpu64-only variant.
403 (movzx): Fold patterns.
404 * i386-tbl.h: Re-generate.
405
7deea9aa
JB		 4062020-02-13 Jan Beulich <jbeulich@suse.com>
407
408 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
409 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
410 CPU_ANY_SSE4_FLAGS entry.
411 * i386-init.h: Re-generate.
412
6c0946d0
JB		 4132020-02-12 Jan Beulich <jbeulich@suse.com>
414
415 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
416 with Unspecified, making the present one AT&T syntax only.
417 * i386-tbl.h: Re-generate.
418
ddb56fe6
JB		 4192020-02-12 Jan Beulich <jbeulich@suse.com>
420
421 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
422 * i386-tbl.h: Re-generate.
423
5990e377
JB		 4242020-02-12 Jan Beulich <jbeulich@suse.com>
425
426 PR gas/24546
427 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
428 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
429 Amd64 and Intel64 templates.
430 (call, jmp): Likewise for far indirect variants. Dro
431 Unspecified.
432 * i386-tbl.h: Re-generate.
433
50128d0c
JB		 4342020-02-11 Jan Beulich <jbeulich@suse.com>
435
436 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
437 * i386-opc.h (ShortForm): Delete.
438 (struct i386_opcode_modifier): Remove shortform field.
439 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
440 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
441 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
442 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
443 Drop ShortForm.
444 * i386-tbl.h: Re-generate.
445
1e05b5c4
JB		 4462020-02-11 Jan Beulich <jbeulich@suse.com>
447
448 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
449 fucompi): Drop ShortForm from operand-less templates.
450 * i386-tbl.h: Re-generate.
451
2f5dd314
AM		 4522020-02-11 Alan Modra <amodra@gmail.com>
453
454 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
455 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
456 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
457 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
458 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
459
5aae9ae9
MM		 4602020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
461
462 * arm-dis.c (print_insn_cde): Define 'V' parse character.
463 (cde_opcodes): Add VCX* instructions.
464
4934a27c
MM		 4652020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
466 Matthew Malcomson <matthew.malcomson@arm.com>
467
468 * arm-dis.c (struct cdeopcode32): New.
469 (CDE_OPCODE): New macro.
470 (cde_opcodes): New disassembly table.
471 (regnames): New option to table.
472 (cde_coprocs): New global variable.
473 (print_insn_cde): New
474 (print_insn_thumb32): Use print_insn_cde.
475 (parse_arm_disassembler_options): Parse coprocN args.
476
4b5aaf5f
L		 4772020-02-10 H.J. Lu <hongjiu.lu@intel.com>
478
479 PR gas/25516
480 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
481 with ISA64.
482 * i386-opc.h (AMD64): Removed.
483 (Intel64): Likewose.
484 (AMD64): New.
485 (INTEL64): Likewise.
486 (INTEL64ONLY): Likewise.
487 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
488 * i386-opc.tbl (Amd64): New.
489 (Intel64): Likewise.
490 (Intel64Only): Likewise.
491 Replace AMD64 with Amd64. Update sysenter/sysenter with
492 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
493 * i386-tbl.h: Regenerated.
494
9fc0b501
SB		 4952020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
496
497 PR 25469
498 * z80-dis.c: Add support for GBZ80 opcodes.
499
c5d7be0c
AM		 5002020-02-04 Alan Modra <amodra@gmail.com>
501
502 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
503
44e4546f
AM		 5042020-02-03 Alan Modra <amodra@gmail.com>
505
506 * m32c-ibld.c: Regenerate.
507
b2b1453a
AM		 5082020-02-01 Alan Modra <amodra@gmail.com>
509
510 * frv-ibld.c: Regenerate.
511
4102be5c
JB		 5122020-01-31 Jan Beulich <jbeulich@suse.com>
513
514 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
515 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
516 (OP_E_memory): Replace xmm_mdq_mode case label by
517 vex_scalar_w_dq_mode one.
518 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
519
825bd36c
JB		 5202020-01-31 Jan Beulich <jbeulich@suse.com>
521
522 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
523 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
524 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
525 (intel_operand_size): Drop vex_w_dq_mode case label.
526
c3036ed0
RS		 5272020-01-31 Richard Sandiford <richard.sandiford@arm.com>
528
529 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
530 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
531
0c115f84
AM		 5322020-01-30 Alan Modra <amodra@gmail.com>
533
534 * m32c-ibld.c: Regenerate.
535
bd434cc4
JM		 5362020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
537
538 * bpf-opc.c: Regenerate.
539
aeab2b26
JB		 5402020-01-30 Jan Beulich <jbeulich@suse.com>
541
542 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
543 (dis386): Use them to replace C2/C3 table entries.
544 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
545 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
546 ones. Use Size64 instead of DefaultSize on Intel64 ones.
547 * i386-tbl.h: Re-generate.
548
62b3f548
JB		 5492020-01-30 Jan Beulich <jbeulich@suse.com>
550
551 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
552 forms.
553 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
554 DefaultSize.
555 * i386-tbl.h: Re-generate.
556
1bd8ae10
AM		 5572020-01-30 Alan Modra <amodra@gmail.com>
558
559 * tic4x-dis.c (tic4x_dp): Make unsigned.
560
bc31405e
L		 5612020-01-27 H.J. Lu <hongjiu.lu@intel.com>
562 Jan Beulich <jbeulich@suse.com>
563
564 PR binutils/25445
565 * i386-dis.c (MOVSXD_Fixup): New function.
566 (movsxd_mode): New enum.
567 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
568 (intel_operand_size): Handle movsxd_mode.
569 (OP_E_register): Likewise.
570 (OP_G): Likewise.
571 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
572 register on movsxd. Add movsxd with 16-bit destination register
573 for AMD64 and Intel64 ISAs.
574 * i386-tbl.h: Regenerated.
575
7568c93b
TC		 5762020-01-27 Tamar Christina <tamar.christina@arm.com>
577
578 PR 25403
579 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
580 * aarch64-asm-2.c: Regenerate
581 * aarch64-dis-2.c: Likewise.
582 * aarch64-opc-2.c: Likewise.
583
c006a730
JB		 5842020-01-21 Jan Beulich <jbeulich@suse.com>
585
586 * i386-opc.tbl (sysret): Drop DefaultSize.
587 * i386-tbl.h: Re-generate.
588
c906a69a
JB		 5892020-01-21 Jan Beulich <jbeulich@suse.com>
590
591 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
592 Dword.
593 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
594 * i386-tbl.h: Re-generate.
595
26916852
NC		 5962020-01-20 Nick Clifton <nickc@redhat.com>
597
598 * po/de.po: Updated German translation.
599 * po/pt_BR.po: Updated Brazilian Portuguese translation.
600 * po/uk.po: Updated Ukranian translation.
601
4d6cbb64
AM		 6022020-01-20 Alan Modra <amodra@gmail.com>
603
604 * hppa-dis.c (fput_const): Remove useless cast.
605
2bddb71a
AM		 6062020-01-20 Alan Modra <amodra@gmail.com>
607
608 * arm-dis.c (print_insn_arm): Wrap 'T' value.
609
1b1bb2c6
NC		 6102020-01-18 Nick Clifton <nickc@redhat.com>
611
612 * configure: Regenerate.
613 * po/opcodes.pot: Regenerate.
614
ae774686
NC		 6152020-01-18 Nick Clifton <nickc@redhat.com>
616
617 Binutils 2.34 branch created.
618
07f1f3aa
CB		 6192020-01-17 Christian Biesinger <cbiesinger@google.com>
620
621 * opintl.h: Fix spelling error (seperate).
622
42e04b36
L		 6232020-01-17 H.J. Lu <hongjiu.lu@intel.com>
624
625 * i386-opc.tbl: Add {vex} pseudo prefix.
626 * i386-tbl.h: Regenerated.
627
2da2eaf4
AV		 6282020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
629
630 PR 25376
631 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
632 (neon_opcodes): Likewise.
633 (select_arm_features): Make sure we enable MVE bits when selecting
634 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
635 any architecture.
636
d0849eed
JB		 6372020-01-16 Jan Beulich <jbeulich@suse.com>
638
639 * i386-opc.tbl: Drop stale comment from XOP section.
640
9cf70a44
JB		 6412020-01-16 Jan Beulich <jbeulich@suse.com>
642
643 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
644 (extractps): Add VexWIG to SSE2AVX forms.
645 * i386-tbl.h: Re-generate.
646
4814632e
JB		 6472020-01-16 Jan Beulich <jbeulich@suse.com>
648
649 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
650 Size64 from and use VexW1 on SSE2AVX forms.
651 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
652 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
653 * i386-tbl.h: Re-generate.
654
aad09917
AM		 6552020-01-15 Alan Modra <amodra@gmail.com>
656
657 * tic4x-dis.c (tic4x_version): Make unsigned long.
658 (optab, optab_special, registernames): New file scope vars.
659 (tic4x_print_register): Set up registernames rather than
660 malloc'd registertable.
661 (tic4x_disassemble): Delete optable and optable_special. Use
662 optab and optab_special instead. Throw away old optab,
663 optab_special and registernames when info->mach changes.
664
7a6bf3be
SB		 6652020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
666
667 PR 25377
668 * z80-dis.c (suffix): Use .db instruction to generate double
669 prefix.
670
ca1eaac0
AM		 6712020-01-14 Alan Modra <amodra@gmail.com>
672
673 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
674 values to unsigned before shifting.
675
1d67fe3b
TT		 6762020-01-13 Thomas Troeger <tstroege@gmx.de>
677
678 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
679 flow instructions.
680 (print_insn_thumb16, print_insn_thumb32): Likewise.
681 (print_insn): Initialize the insn info.
682 * i386-dis.c (print_insn): Initialize the insn info fields, and
683 detect jumps.
684
5e4f7e05
CZ		 6852012-01-13 Claudiu Zissulescu <claziss@gmail.com>
686
687 * arc-opc.c (C_NE): Make it required.
688
b9fe6b8a
CZ		 6892012-01-13 Claudiu Zissulescu <claziss@gmail.com>
690
691 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
692 reserved register name.
693
90dee485
AM		 6942020-01-13 Alan Modra <amodra@gmail.com>
695
696 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
697 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
698
febda64f
AM		 6992020-01-13 Alan Modra <amodra@gmail.com>
700
701 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
702 result of wasm_read_leb128 in a uint64_t and check that bits
703 are not lost when copying to other locals. Use uint32_t for
704 most locals. Use PRId64 when printing int64_t.
705
df08b588
AM		 7062020-01-13 Alan Modra <amodra@gmail.com>
707
708 * score-dis.c: Formatting.
709 * score7-dis.c: Formatting.
710
b2c759ce
AM		 7112020-01-13 Alan Modra <amodra@gmail.com>
712
713 * score-dis.c (print_insn_score48): Use unsigned variables for
714 unsigned values. Don't left shift negative values.
715 (print_insn_score32): Likewise.
716 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
717
5496abe1
AM		 7182020-01-13 Alan Modra <amodra@gmail.com>
719
720 * tic4x-dis.c (tic4x_print_register): Remove dead code.
721
202e762b
AM		 7222020-01-13 Alan Modra <amodra@gmail.com>
723
724 * fr30-ibld.c: Regenerate.
725
7ef412cf
AM		 7262020-01-13 Alan Modra <amodra@gmail.com>
727
728 * xgate-dis.c (print_insn): Don't left shift signed value.
729 (ripBits): Formatting, use 1u.
730
7f578b95
AM		 7312020-01-10 Alan Modra <amodra@gmail.com>
732
733 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
734 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
735
441af85b
AM		 7362020-01-10 Alan Modra <amodra@gmail.com>
737
738 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
739 and XRREG value earlier to avoid a shift with negative exponent.
740 * m10200-dis.c (disassemble): Similarly.
741
bce58db4
NC		 7422020-01-09 Nick Clifton <nickc@redhat.com>
743
744 PR 25224
745 * z80-dis.c (ld_ii_ii): Use correct cast.
746
40c75bc8
SB		 7472020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
748
749 PR 25224
750 * z80-dis.c (ld_ii_ii): Use character constant when checking
751 opcode byte value.
752
d835a58b
JB		 7532020-01-09 Jan Beulich <jbeulich@suse.com>
754
755 * i386-dis.c (SEP_Fixup): New.
756 (SEP): Define.
757 (dis386_twobyte): Use it for sysenter/sysexit.
758 (enum x86_64_isa): Change amd64 enumerator to value 1.
759 (OP_J): Compare isa64 against intel64 instead of amd64.
760 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
761 forms.
762 * i386-tbl.h: Re-generate.
763
030a2e78
AM		 7642020-01-08 Alan Modra <amodra@gmail.com>
765
766 * z8k-dis.c: Include libiberty.h
767 (instr_data_s): Make max_fetched unsigned.
768 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
769 Don't exceed byte_info bounds.
770 (output_instr): Make num_bytes unsigned.
771 (unpack_instr): Likewise for nibl_count and loop.
772 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
773 idx unsigned.
774 * z8k-opc.h: Regenerate.
775
bb82aefe
SV		 7762020-01-07 Shahab Vahedi <shahab@synopsys.com>
777
778 * arc-tbl.h (llock): Use 'LLOCK' as class.
779 (llockd): Likewise.
780 (scond): Use 'SCOND' as class.
781 (scondd): Likewise.
782 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
783 (scondd): Likewise.
784
cc6aa1a6
AM		 7852020-01-06 Alan Modra <amodra@gmail.com>
786
787 * m32c-ibld.c: Regenerate.
788
660e62b1
AM		 7892020-01-06 Alan Modra <amodra@gmail.com>
790
791 PR 25344
792 * z80-dis.c (suffix): Don't use a local struct buffer copy.
793 Peek at next byte to prevent recursion on repeated prefix bytes.
794 Ensure uninitialised "mybuf" is not accessed.
795 (print_insn_z80): Don't zero n_fetch and n_used here,..
796 (print_insn_z80_buf): ..do it here instead.
797
c9ae58fe
AM		 7982020-01-04 Alan Modra <amodra@gmail.com>
799
800 * m32r-ibld.c: Regenerate.
801
5f57d4ec
AM		 8022020-01-04 Alan Modra <amodra@gmail.com>
803
804 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
805
2c5c1196
AM		 8062020-01-04 Alan Modra <amodra@gmail.com>
807
808 * crx-dis.c (match_opcode): Avoid shift left of signed value.
809
2e98c6c5
AM		 8102020-01-04 Alan Modra <amodra@gmail.com>
811
812 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
813
567dfba2
JB		 8142020-01-03 Jan Beulich <jbeulich@suse.com>
815
5437a02a
JB		 816 * aarch64-tbl.h (aarch64_opcode_table): Use
817 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
818
8192020-01-03 Jan Beulich <jbeulich@suse.com>
820
821 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 822 forms of SUDOT and USDOT.
823
8c45011a
JB		 8242020-01-03 Jan Beulich <jbeulich@suse.com>
825
5437a02a 826 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 827 uzip{1,2}.
828 * opcodes/aarch64-dis-2.c: Re-generate.
829
f4950f76
JB		 8302020-01-03 Jan Beulich <jbeulich@suse.com>
831
5437a02a 832 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 833 FMMLA encoding.
834 * opcodes/aarch64-dis-2.c: Re-generate.
835
6655dba2
SB		 8362020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
837
838 * z80-dis.c: Add support for eZ80 and Z80 instructions.
839
b14ce8bf
AM		 8402020-01-01 Alan Modra <amodra@gmail.com>
841
842 Update year range in copyright notice of all files.
843
0b114740 844For older changes see ChangeLog-2019
3499769a 845\f
0b114740 846Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 847
848Copying and distribution of this file, with or without modification,
849are permitted in any medium without royalty provided the copyright
850notice and this notice are preserved.
851
852Local Variables:
853mode: change-log
854left-margin: 8
855fill-column: 74
856version-control: never
857End:
GDB Binutils - Deliverables
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