Commit | Line | Data |
---|---|---|
1f730c46 JB |
1 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
2 | ||
3 | * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss): | |
4 | Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/ | |
5 | VexW1 instead of open-coding them. | |
6 | * i386-tbl.h: Re-generate. | |
7 | ||
c8f8eebc JB |
8 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
9 | ||
10 | * i386-opc.tbl (AddrPrefixOpReg): Define. | |
11 | (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx, | |
12 | umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64 | |
13 | templates. Drop NoRex64. | |
14 | * i386-tbl.h: Re-generate. | |
15 | ||
b9915cbc JB |
16 | 2020-02-17 Jan Beulich <jbeulich@suse.com> |
17 | ||
18 | PR gas/6518 | |
19 | * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq, | |
20 | vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms | |
21 | into Intel syntax instance (with Unpsecified) and AT&T one | |
22 | (without). | |
23 | (vcvtneps2bf16): Likewise, along with folding the two so far | |
24 | separate ones. | |
25 | * i386-tbl.h: Re-generate. | |
26 | ||
ce504911 L |
27 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
28 | ||
29 | * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from | |
30 | CPU_ANY_SSE4A_FLAGS. | |
31 | ||
dabec65d AM |
32 | 2020-02-17 Alan Modra <amodra@gmail.com> |
33 | ||
34 | * i386-gen.c (cpu_flag_init): Correct last change. | |
35 | ||
af5c13b0 L |
36 | 2020-02-16 H.J. Lu <hongjiu.lu@intel.com> |
37 | ||
38 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove | |
39 | CPU_ANY_SSE4_FLAGS. | |
40 | ||
6867aac0 L |
41 | 2020-02-14 H.J. Lu <hongjiu.lu@intel.com> |
42 | ||
43 | * i386-opc.tbl (movsx): Remove Intel syntax comments. | |
44 | (movzx): Likewise. | |
45 | ||
65fca059 JB |
46 | 2020-02-14 Jan Beulich <jbeulich@suse.com> |
47 | ||
48 | PR gas/25438 | |
49 | * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as | |
50 | destination for Cpu64-only variant. | |
51 | (movzx): Fold patterns. | |
52 | * i386-tbl.h: Re-generate. | |
53 | ||
7deea9aa JB |
54 | 2020-02-13 Jan Beulich <jbeulich@suse.com> |
55 | ||
56 | * i386-gen.c (cpu_flag_init): Move CpuSSE4a from | |
57 | CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add | |
58 | CPU_ANY_SSE4_FLAGS entry. | |
59 | * i386-init.h: Re-generate. | |
60 | ||
6c0946d0 JB |
61 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
62 | ||
63 | * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form | |
64 | with Unspecified, making the present one AT&T syntax only. | |
65 | * i386-tbl.h: Re-generate. | |
66 | ||
ddb56fe6 JB |
67 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
68 | ||
69 | * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants. | |
70 | * i386-tbl.h: Re-generate. | |
71 | ||
5990e377 JB |
72 | 2020-02-12 Jan Beulich <jbeulich@suse.com> |
73 | ||
74 | PR gas/24546 | |
75 | * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode. | |
76 | * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into | |
77 | Amd64 and Intel64 templates. | |
78 | (call, jmp): Likewise for far indirect variants. Dro | |
79 | Unspecified. | |
80 | * i386-tbl.h: Re-generate. | |
81 | ||
50128d0c JB |
82 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
83 | ||
84 | * i386-gen.c (opcode_modifiers): Remove ShortForm entry. | |
85 | * i386-opc.h (ShortForm): Delete. | |
86 | (struct i386_opcode_modifier): Remove shortform field. | |
87 | * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld, | |
88 | fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub, | |
89 | fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp, | |
90 | ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq): | |
91 | Drop ShortForm. | |
92 | * i386-tbl.h: Re-generate. | |
93 | ||
1e05b5c4 JB |
94 | 2020-02-11 Jan Beulich <jbeulich@suse.com> |
95 | ||
96 | * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip, | |
97 | fucompi): Drop ShortForm from operand-less templates. | |
98 | * i386-tbl.h: Re-generate. | |
99 | ||
2f5dd314 AM |
100 | 2020-02-11 Alan Modra <amodra@gmail.com> |
101 | ||
102 | * cgen-ibld.in (extract_normal): Set *valuep on all return paths. | |
103 | * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c, | |
104 | * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c, | |
105 | * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c, | |
106 | * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate. | |
107 | ||
5aae9ae9 MM |
108 | 2020-02-10 Matthew Malcomson <matthew.malcomson@arm.com> |
109 | ||
110 | * arm-dis.c (print_insn_cde): Define 'V' parse character. | |
111 | (cde_opcodes): Add VCX* instructions. | |
112 | ||
4934a27c MM |
113 | 2020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com> |
114 | Matthew Malcomson <matthew.malcomson@arm.com> | |
115 | ||
116 | * arm-dis.c (struct cdeopcode32): New. | |
117 | (CDE_OPCODE): New macro. | |
118 | (cde_opcodes): New disassembly table. | |
119 | (regnames): New option to table. | |
120 | (cde_coprocs): New global variable. | |
121 | (print_insn_cde): New | |
122 | (print_insn_thumb32): Use print_insn_cde. | |
123 | (parse_arm_disassembler_options): Parse coprocN args. | |
124 | ||
4b5aaf5f L |
125 | 2020-02-10 H.J. Lu <hongjiu.lu@intel.com> |
126 | ||
127 | PR gas/25516 | |
128 | * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64 | |
129 | with ISA64. | |
130 | * i386-opc.h (AMD64): Removed. | |
131 | (Intel64): Likewose. | |
132 | (AMD64): New. | |
133 | (INTEL64): Likewise. | |
134 | (INTEL64ONLY): Likewise. | |
135 | (i386_opcode_modifier): Replace amd64 and intel64 with isa64. | |
136 | * i386-opc.tbl (Amd64): New. | |
137 | (Intel64): Likewise. | |
138 | (Intel64Only): Likewise. | |
139 | Replace AMD64 with Amd64. Update sysenter/sysenter with | |
140 | Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter. | |
141 | * i386-tbl.h: Regenerated. | |
142 | ||
9fc0b501 SB |
143 | 2020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com> |
144 | ||
145 | PR 25469 | |
146 | * z80-dis.c: Add support for GBZ80 opcodes. | |
147 | ||
c5d7be0c AM |
148 | 2020-02-04 Alan Modra <amodra@gmail.com> |
149 | ||
150 | * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned. | |
151 | ||
44e4546f AM |
152 | 2020-02-03 Alan Modra <amodra@gmail.com> |
153 | ||
154 | * m32c-ibld.c: Regenerate. | |
155 | ||
b2b1453a AM |
156 | 2020-02-01 Alan Modra <amodra@gmail.com> |
157 | ||
158 | * frv-ibld.c: Regenerate. | |
159 | ||
4102be5c JB |
160 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
161 | ||
162 | * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete. | |
163 | (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label. | |
164 | (OP_E_memory): Replace xmm_mdq_mode case label by | |
165 | vex_scalar_w_dq_mode one. | |
166 | * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar. | |
167 | ||
825bd36c JB |
168 | 2020-01-31 Jan Beulich <jbeulich@suse.com> |
169 | ||
170 | * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete. | |
171 | (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode, | |
172 | vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments. | |
173 | (intel_operand_size): Drop vex_w_dq_mode case label. | |
174 | ||
c3036ed0 RS |
175 | 2020-01-31 Richard Sandiford <richard.sandiford@arm.com> |
176 | ||
177 | * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt. | |
178 | Remove C_SCAN_MOVPRFX for SVE bfcvtnt. | |
179 | ||
0c115f84 AM |
180 | 2020-01-30 Alan Modra <amodra@gmail.com> |
181 | ||
182 | * m32c-ibld.c: Regenerate. | |
183 | ||
bd434cc4 JM |
184 | 2020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com> |
185 | ||
186 | * bpf-opc.c: Regenerate. | |
187 | ||
aeab2b26 JB |
188 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
189 | ||
190 | * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators. | |
191 | (dis386): Use them to replace C2/C3 table entries. | |
192 | (x86_64_table): Add X86_64_C2 and X86_64_C3 entries. | |
193 | * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64 | |
194 | ones. Use Size64 instead of DefaultSize on Intel64 ones. | |
195 | * i386-tbl.h: Re-generate. | |
196 | ||
62b3f548 JB |
197 | 2020-01-30 Jan Beulich <jbeulich@suse.com> |
198 | ||
199 | * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword | |
200 | forms. | |
201 | (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop | |
202 | DefaultSize. | |
203 | * i386-tbl.h: Re-generate. | |
204 | ||
1bd8ae10 AM |
205 | 2020-01-30 Alan Modra <amodra@gmail.com> |
206 | ||
207 | * tic4x-dis.c (tic4x_dp): Make unsigned. | |
208 | ||
bc31405e L |
209 | 2020-01-27 H.J. Lu <hongjiu.lu@intel.com> |
210 | Jan Beulich <jbeulich@suse.com> | |
211 | ||
212 | PR binutils/25445 | |
213 | * i386-dis.c (MOVSXD_Fixup): New function. | |
214 | (movsxd_mode): New enum. | |
215 | (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd. | |
216 | (intel_operand_size): Handle movsxd_mode. | |
217 | (OP_E_register): Likewise. | |
218 | (OP_G): Likewise. | |
219 | * i386-opc.tbl: Remove Rex64 and allow 32-bit destination | |
220 | register on movsxd. Add movsxd with 16-bit destination register | |
221 | for AMD64 and Intel64 ISAs. | |
222 | * i386-tbl.h: Regenerated. | |
223 | ||
7568c93b TC |
224 | 2020-01-27 Tamar Christina <tamar.christina@arm.com> |
225 | ||
226 | PR 25403 | |
227 | * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv. | |
228 | * aarch64-asm-2.c: Regenerate | |
229 | * aarch64-dis-2.c: Likewise. | |
230 | * aarch64-opc-2.c: Likewise. | |
231 | ||
c006a730 JB |
232 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
233 | ||
234 | * i386-opc.tbl (sysret): Drop DefaultSize. | |
235 | * i386-tbl.h: Re-generate. | |
236 | ||
c906a69a JB |
237 | 2020-01-21 Jan Beulich <jbeulich@suse.com> |
238 | ||
239 | * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and | |
240 | Dword. | |
241 | (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword. | |
242 | * i386-tbl.h: Re-generate. | |
243 | ||
26916852 NC |
244 | 2020-01-20 Nick Clifton <nickc@redhat.com> |
245 | ||
246 | * po/de.po: Updated German translation. | |
247 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
248 | * po/uk.po: Updated Ukranian translation. | |
249 | ||
4d6cbb64 AM |
250 | 2020-01-20 Alan Modra <amodra@gmail.com> |
251 | ||
252 | * hppa-dis.c (fput_const): Remove useless cast. | |
253 | ||
2bddb71a AM |
254 | 2020-01-20 Alan Modra <amodra@gmail.com> |
255 | ||
256 | * arm-dis.c (print_insn_arm): Wrap 'T' value. | |
257 | ||
1b1bb2c6 NC |
258 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
259 | ||
260 | * configure: Regenerate. | |
261 | * po/opcodes.pot: Regenerate. | |
262 | ||
ae774686 NC |
263 | 2020-01-18 Nick Clifton <nickc@redhat.com> |
264 | ||
265 | Binutils 2.34 branch created. | |
266 | ||
07f1f3aa CB |
267 | 2020-01-17 Christian Biesinger <cbiesinger@google.com> |
268 | ||
269 | * opintl.h: Fix spelling error (seperate). | |
270 | ||
42e04b36 L |
271 | 2020-01-17 H.J. Lu <hongjiu.lu@intel.com> |
272 | ||
273 | * i386-opc.tbl: Add {vex} pseudo prefix. | |
274 | * i386-tbl.h: Regenerated. | |
275 | ||
2da2eaf4 AV |
276 | 2020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
277 | ||
278 | PR 25376 | |
279 | * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits. | |
280 | (neon_opcodes): Likewise. | |
281 | (select_arm_features): Make sure we enable MVE bits when selecting | |
282 | armv8.1-m.main. Make sure we do not enable MVE bits when not selecting | |
283 | any architecture. | |
284 | ||
d0849eed JB |
285 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
286 | ||
287 | * i386-opc.tbl: Drop stale comment from XOP section. | |
288 | ||
9cf70a44 JB |
289 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
290 | ||
291 | * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms. | |
292 | (extractps): Add VexWIG to SSE2AVX forms. | |
293 | * i386-tbl.h: Re-generate. | |
294 | ||
4814632e JB |
295 | 2020-01-16 Jan Beulich <jbeulich@suse.com> |
296 | ||
297 | * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop | |
298 | Size64 from and use VexW1 on SSE2AVX forms. | |
299 | (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from | |
300 | VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1. | |
301 | * i386-tbl.h: Re-generate. | |
302 | ||
aad09917 AM |
303 | 2020-01-15 Alan Modra <amodra@gmail.com> |
304 | ||
305 | * tic4x-dis.c (tic4x_version): Make unsigned long. | |
306 | (optab, optab_special, registernames): New file scope vars. | |
307 | (tic4x_print_register): Set up registernames rather than | |
308 | malloc'd registertable. | |
309 | (tic4x_disassemble): Delete optable and optable_special. Use | |
310 | optab and optab_special instead. Throw away old optab, | |
311 | optab_special and registernames when info->mach changes. | |
312 | ||
7a6bf3be SB |
313 | 2020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com> |
314 | ||
315 | PR 25377 | |
316 | * z80-dis.c (suffix): Use .db instruction to generate double | |
317 | prefix. | |
318 | ||
ca1eaac0 AM |
319 | 2020-01-14 Alan Modra <amodra@gmail.com> |
320 | ||
321 | * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short | |
322 | values to unsigned before shifting. | |
323 | ||
1d67fe3b TT |
324 | 2020-01-13 Thomas Troeger <tstroege@gmx.de> |
325 | ||
326 | * arm-dis.c (print_insn_arm): Fill in insn info fields for control | |
327 | flow instructions. | |
328 | (print_insn_thumb16, print_insn_thumb32): Likewise. | |
329 | (print_insn): Initialize the insn info. | |
330 | * i386-dis.c (print_insn): Initialize the insn info fields, and | |
331 | detect jumps. | |
332 | ||
5e4f7e05 CZ |
333 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
334 | ||
335 | * arc-opc.c (C_NE): Make it required. | |
336 | ||
b9fe6b8a CZ |
337 | 2012-01-13 Claudiu Zissulescu <claziss@gmail.com> |
338 | ||
339 | * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo | |
340 | reserved register name. | |
341 | ||
90dee485 AM |
342 | 2020-01-13 Alan Modra <amodra@gmail.com> |
343 | ||
344 | * ns32k-dis.c (Is_gen): Use strchr, add 'f'. | |
345 | (print_insn_ns32k): Adjust ioffset for 'f' index_offset. | |
346 | ||
febda64f AM |
347 | 2020-01-13 Alan Modra <amodra@gmail.com> |
348 | ||
349 | * wasm32-dis.c (print_insn_wasm32): Localise variables. Store | |
350 | result of wasm_read_leb128 in a uint64_t and check that bits | |
351 | are not lost when copying to other locals. Use uint32_t for | |
352 | most locals. Use PRId64 when printing int64_t. | |
353 | ||
df08b588 AM |
354 | 2020-01-13 Alan Modra <amodra@gmail.com> |
355 | ||
356 | * score-dis.c: Formatting. | |
357 | * score7-dis.c: Formatting. | |
358 | ||
b2c759ce AM |
359 | 2020-01-13 Alan Modra <amodra@gmail.com> |
360 | ||
361 | * score-dis.c (print_insn_score48): Use unsigned variables for | |
362 | unsigned values. Don't left shift negative values. | |
363 | (print_insn_score32): Likewise. | |
364 | * score7-dis.c (print_insn_score32, print_insn_score16): Likewise. | |
365 | ||
5496abe1 AM |
366 | 2020-01-13 Alan Modra <amodra@gmail.com> |
367 | ||
368 | * tic4x-dis.c (tic4x_print_register): Remove dead code. | |
369 | ||
202e762b AM |
370 | 2020-01-13 Alan Modra <amodra@gmail.com> |
371 | ||
372 | * fr30-ibld.c: Regenerate. | |
373 | ||
7ef412cf AM |
374 | 2020-01-13 Alan Modra <amodra@gmail.com> |
375 | ||
376 | * xgate-dis.c (print_insn): Don't left shift signed value. | |
377 | (ripBits): Formatting, use 1u. | |
378 | ||
7f578b95 AM |
379 | 2020-01-10 Alan Modra <amodra@gmail.com> |
380 | ||
381 | * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned. | |
382 | * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval. | |
383 | ||
441af85b AM |
384 | 2020-01-10 Alan Modra <amodra@gmail.com> |
385 | ||
386 | * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG, | |
387 | and XRREG value earlier to avoid a shift with negative exponent. | |
388 | * m10200-dis.c (disassemble): Similarly. | |
389 | ||
bce58db4 NC |
390 | 2020-01-09 Nick Clifton <nickc@redhat.com> |
391 | ||
392 | PR 25224 | |
393 | * z80-dis.c (ld_ii_ii): Use correct cast. | |
394 | ||
40c75bc8 SB |
395 | 2020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com> |
396 | ||
397 | PR 25224 | |
398 | * z80-dis.c (ld_ii_ii): Use character constant when checking | |
399 | opcode byte value. | |
400 | ||
d835a58b JB |
401 | 2020-01-09 Jan Beulich <jbeulich@suse.com> |
402 | ||
403 | * i386-dis.c (SEP_Fixup): New. | |
404 | (SEP): Define. | |
405 | (dis386_twobyte): Use it for sysenter/sysexit. | |
406 | (enum x86_64_isa): Change amd64 enumerator to value 1. | |
407 | (OP_J): Compare isa64 against intel64 instead of amd64. | |
408 | * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64 | |
409 | forms. | |
410 | * i386-tbl.h: Re-generate. | |
411 | ||
030a2e78 AM |
412 | 2020-01-08 Alan Modra <amodra@gmail.com> |
413 | ||
414 | * z8k-dis.c: Include libiberty.h | |
415 | (instr_data_s): Make max_fetched unsigned. | |
416 | (z8k_lookup_instr): Make nibl_index and tabl_index unsigned. | |
417 | Don't exceed byte_info bounds. | |
418 | (output_instr): Make num_bytes unsigned. | |
419 | (unpack_instr): Likewise for nibl_count and loop. | |
420 | * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and | |
421 | idx unsigned. | |
422 | * z8k-opc.h: Regenerate. | |
423 | ||
bb82aefe SV |
424 | 2020-01-07 Shahab Vahedi <shahab@synopsys.com> |
425 | ||
426 | * arc-tbl.h (llock): Use 'LLOCK' as class. | |
427 | (llockd): Likewise. | |
428 | (scond): Use 'SCOND' as class. | |
429 | (scondd): Likewise. | |
430 | (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit. | |
431 | (scondd): Likewise. | |
432 | ||
cc6aa1a6 AM |
433 | 2020-01-06 Alan Modra <amodra@gmail.com> |
434 | ||
435 | * m32c-ibld.c: Regenerate. | |
436 | ||
660e62b1 AM |
437 | 2020-01-06 Alan Modra <amodra@gmail.com> |
438 | ||
439 | PR 25344 | |
440 | * z80-dis.c (suffix): Don't use a local struct buffer copy. | |
441 | Peek at next byte to prevent recursion on repeated prefix bytes. | |
442 | Ensure uninitialised "mybuf" is not accessed. | |
443 | (print_insn_z80): Don't zero n_fetch and n_used here,.. | |
444 | (print_insn_z80_buf): ..do it here instead. | |
445 | ||
c9ae58fe AM |
446 | 2020-01-04 Alan Modra <amodra@gmail.com> |
447 | ||
448 | * m32r-ibld.c: Regenerate. | |
449 | ||
5f57d4ec AM |
450 | 2020-01-04 Alan Modra <amodra@gmail.com> |
451 | ||
452 | * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value. | |
453 | ||
2c5c1196 AM |
454 | 2020-01-04 Alan Modra <amodra@gmail.com> |
455 | ||
456 | * crx-dis.c (match_opcode): Avoid shift left of signed value. | |
457 | ||
2e98c6c5 AM |
458 | 2020-01-04 Alan Modra <amodra@gmail.com> |
459 | ||
460 | * d30v-dis.c (print_insn): Avoid signed overflow in left shift. | |
461 | ||
567dfba2 JB |
462 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
463 | ||
5437a02a JB |
464 | * aarch64-tbl.h (aarch64_opcode_table): Use |
465 | SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}. | |
466 | ||
467 | 2020-01-03 Jan Beulich <jbeulich@suse.com> | |
468 | ||
469 | * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD | |
567dfba2 JB |
470 | forms of SUDOT and USDOT. |
471 | ||
8c45011a JB |
472 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
473 | ||
5437a02a | 474 | * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from |
8c45011a JB |
475 | uzip{1,2}. |
476 | * opcodes/aarch64-dis-2.c: Re-generate. | |
477 | ||
f4950f76 JB |
478 | 2020-01-03 Jan Beulich <jbeulich@suse.com> |
479 | ||
5437a02a | 480 | * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit |
f4950f76 JB |
481 | FMMLA encoding. |
482 | * opcodes/aarch64-dis-2.c: Re-generate. | |
483 | ||
6655dba2 SB |
484 | 2020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com> |
485 | ||
486 | * z80-dis.c: Add support for eZ80 and Z80 instructions. | |
487 | ||
b14ce8bf AM |
488 | 2020-01-01 Alan Modra <amodra@gmail.com> |
489 | ||
490 | Update year range in copyright notice of all files. | |
491 | ||
0b114740 | 492 | For older changes see ChangeLog-2019 |
3499769a | 493 | \f |
0b114740 | 494 | Copyright (C) 2020 Free Software Foundation, Inc. |
3499769a AM |
495 | |
496 | Copying and distribution of this file, with or without modification, | |
497 | are permitted in any medium without royalty provided the copyright | |
498 | notice and this notice are preserved. | |
499 | ||
500 | Local Variables: | |
501 | mode: change-log | |
502 | left-margin: 8 | |
503 | fill-column: 74 | |
504 | version-control: never | |
505 | End: |