projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 6394c606 YQ |
1 | 2017-06-14 Yao Qi <yao.qi@linaro.org> |
| 2 | ||
| 3 | * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. | |
| 4 | * arm-dis.c: Likewise. | |
| 5 | * ia64-dis.c: Likewise. | |
| 6 | * mips-dis.c: Likewise. | |
| 7 | * spu-dis.c: Likewise. | |
| 8 | * disassemble.h (print_insn_aarch64): New declaration, moved from | |
| 9 | include/dis-asm.h. | |
| 10 | (print_insn_big_arm, print_insn_big_mips): Likewise. | |
| 11 | (print_insn_i386, print_insn_ia64): Likewise. | |
| 12 | (print_insn_little_arm, print_insn_little_mips): Likewise. | |
| 13 | ||
| db5fa770 NC |
14 | 2017-06-14 Nick Clifton <nickc@redhat.com> |
| 15 | ||
| 16 | PR binutils/21587 | |
| 17 | * rx-decode.opc: Include libiberty.h | |
| 18 | (GET_SCALE): New macro - validates access to SCALE array. | |
| 19 | (GET_PSCALE): New macro - validates access to PSCALE array. | |
| 20 | (DIs, SIs, S2Is, rx_disp): Use new macros. | |
| 21 | * rx-decode.c: Regenerate. | |
| 22 | ||
| 05c966f3 AV |
23 | 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 24 | ||
| 25 | * arm-dis.c (print_insn_arm): Remove bogus entry for bx. | |
| 26 | ||
| 10045478 AK |
27 | 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com> |
| 28 | ||
| 29 | * arc-dis.c (enforced_isa_mask): Declare. | |
| 30 | (cpu_types): Likewise. | |
| 31 | (parse_cpu_option): New function. | |
| 32 | (parse_disassembler_options): Use it. | |
| 33 | (print_insn_arc): Use enforced_isa_mask. | |
| 34 | (print_arc_disassembler_options): Document new options. | |
| 35 | ||
| 88c1242d YQ |
36 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 37 | ||
| 38 | * alpha-dis.c: Include disassemble.h, don't include | |
| 39 | dis-asm.h. | |
| 40 | * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. | |
| 41 | * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. | |
| 42 | * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. | |
| 43 | * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. | |
| 44 | * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. | |
| 45 | * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. | |
| 46 | * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. | |
| 47 | * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. | |
| 48 | * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. | |
| 49 | * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. | |
| 50 | * moxie-dis.c, msp430-dis.c, mt-dis.c: | |
| 51 | * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. | |
| 52 | * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. | |
| 53 | * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. | |
| 54 | * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. | |
| 55 | * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. | |
| 56 | * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. | |
| 57 | * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. | |
| 58 | * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. | |
| 59 | * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. | |
| 60 | * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. | |
| 61 | * z80-dis.c, z8k-dis.c: Likewise. | |
| 62 | * disassemble.h: New file. | |
| 63 | ||
| ab20fa4a YQ |
64 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 65 | ||
| 66 | * rl78-dis.c (rl78_get_disassembler): If parameter abfd | |
| 67 | is NULL, set cpu to E_FLAG_RL78_ANY_CPU. | |
| 68 | ||
| 003ca0fd YQ |
69 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 70 | ||
| 71 | * disassemble.c (disassembler): Add arguments a, big and mach. | |
| 72 | Use them. | |
| 73 | ||
| 04ef582a L |
74 | 2017-05-22 H.J. Lu <hongjiu.lu@intel.com> |
| 75 | ||
| 76 | * i386-dis.c (NOTRACK_Fixup): New. | |
| 77 | (NOTRACK): Likewise. | |
| 78 | (NOTRACK_PREFIX): Likewise. | |
| 79 | (last_active_prefix): Likewise. | |
| 80 | (reg_table): Use NOTRACK on indirect call and jmp. | |
| 81 | (ckprefix): Set last_active_prefix. | |
| 82 | (prefix_name): Return "notrack" for NOTRACK_PREFIX. | |
| 83 | * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. | |
| 84 | * i386-opc.h (NoTrackPrefixOk): New. | |
| 85 | (i386_opcode_modifier): Add notrackprefixok. | |
| 86 | * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. | |
| 87 | Add notrack. | |
| 88 | * i386-tbl.h: Regenerated. | |
| 89 | ||
| 64517994 JM |
90 | 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 91 | ||
| 92 | * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. | |
| 93 | (X_IMM2): Define. | |
| 94 | (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and | |
| 95 | bfd_mach_sparc_v9m8. | |
| 96 | (print_insn_sparc): Handle new operand types. | |
| 97 | * sparc-opc.c (MASK_M8): Define. | |
| 98 | (v6): Add MASK_M8. | |
| 99 | (v6notlet): Likewise. | |
| 100 | (v7): Likewise. | |
| 101 | (v8): Likewise. | |
| 102 | (v9): Likewise. | |
| 103 | (v9a): Likewise. | |
| 104 | (v9b): Likewise. | |
| 105 | (v9c): Likewise. | |
| 106 | (v9d): Likewise. | |
| 107 | (v9e): Likewise. | |
| 108 | (v9v): Likewise. | |
| 109 | (v9m): Likewise. | |
| 110 | (v9andleon): Likewise. | |
| 111 | (m8): Define. | |
| 112 | (HWS_VM8): Define. | |
| 113 | (HWS2_VM8): Likewise. | |
| 114 | (sparc_opcode_archs): Add entry for "m8". | |
| 115 | (sparc_opcodes): Add OSA2017 and M8 instructions | |
| 116 | dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, | |
| 117 | fpx{ll,ra,rl}64x, | |
| 118 | ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, | |
| 119 | ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, | |
| 120 | revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, | |
| 121 | stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. | |
| 122 | (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, | |
| 123 | ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, | |
| 124 | ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, | |
| 125 | ASI_CORE_SELECT_COMMIT_NHT. | |
| 126 | ||
| 535b785f AM |
127 | 2017-05-18 Alan Modra <amodra@gmail.com> |
| 128 | ||
| 129 | * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE. | |
| 130 | * aarch64-dis.c: Likewise. | |
| 131 | * aarch64-gen.c: Likewise. | |
| 132 | * aarch64-opc.c: Likewise. | |
| 133 | ||
| 25499ac7 MR |
134 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
| 135 | Matthew Fortune <matthew.fortune@imgtec.com> | |
| 136 | ||
| 137 | * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and | |
| 138 | ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. | |
| 139 | (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. | |
| 140 | (print_insn_arg) <OP_REG28>: Add handler. | |
| 141 | (validate_insn_args) <OP_REG28>: Handle. | |
| 142 | (print_mips16_insn_arg): Handle MIPS16 instructions that require | |
| 143 | 32-bit encoding and 9-bit immediates. | |
| 144 | (print_insn_mips16): Handle MIPS16 instructions that require | |
| 145 | 32-bit encoding and MFC0/MTC0 operand decoding. | |
| 146 | * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> | |
| 147 | <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. | |
| 148 | (RD_C0, WR_C0, E2, E2MT): New macros. | |
| 149 | (mips16_opcodes): Add entries for MIPS16e2 instructions: | |
| 150 | GP-relative "addiu" and its "addu" spelling, "andi", "cache", | |
| 151 | "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", | |
| 152 | "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", | |
| 153 | "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", | |
| 154 | "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" | |
| 155 | instructions, "swl", "swr", "sync" and its "sync_acquire", | |
| 156 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, | |
| 157 | "xori", "dmt", "dvpe", "emt" and "evpe". Add split | |
| 158 | regular/extended entries for original MIPS16 ISA revision | |
| 159 | instructions whose extended forms are subdecoded in the MIPS16e2 | |
| 160 | ISA revision: "li", "sll" and "srl". | |
| 161 | ||
| fdfb4752 MR |
162 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
| 163 | ||
| 164 | * mips-dis.c (print_insn_args) <default>: Remove an MT ASE | |
| 165 | reference in CP0 move operand decoding. | |
| 166 | ||
| a4f89915 MR |
167 | 2017-05-12 Maciej W. Rozycki <macro@imgtec.com> |
| 168 | ||
| 169 | * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand | |
| 170 | type to hexadecimal. | |
| 171 | (mips16_opcodes): Add operandless "break" and "sdbbp" entries. | |
| 172 | ||
| 99e2d67a MR |
173 | 2017-05-11 Maciej W. Rozycki <macro@imgtec.com> |
| 174 | ||
| 175 | * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", | |
| 176 | "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release", | |
| 177 | "sync_rmb" and "sync_wmb" as aliases. | |
| 178 | * micromips-opc.c (micromips_opcodes): Mark "sync_acquire", | |
| 179 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. | |
| 180 | ||
| 53a346d8 CZ |
181 | 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> |
| 182 | ||
| 183 | * arc-dis.c (parse_option): Update quarkse_em option.. | |
| 184 | * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to | |
| 185 | QUARKSE1. | |
| 186 | (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. | |
| 187 | ||
| f91d48de KC |
188 | 2017-05-03 Kito Cheng <kito.cheng@gmail.com> |
| 189 | ||
| 190 | * riscv-dis.c (print_insn_args): Handle 'Co' operands. | |
| 191 | ||
| 43e379d7 MC |
192 | 2017-05-01 Michael Clark <michaeljclark@mac.com> |
| 193 | ||
| 194 | * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary | |
| 195 | register. | |
| 196 | ||
| a4ddc54e MR |
197 | 2017-05-02 Maciej W. Rozycki <macro@imgtec.com> |
| 198 | ||
| 199 | * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps | |
| 200 | and branches and not synthetic data instructions. | |
| 201 | ||
| fe50e98c BE |
202 | 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de> |
| 203 | ||
| 204 | * arm-dis.c (print_insn_thumb32): Fix value_in_comment. | |
| 205 | ||
| 126124cc CZ |
206 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| 207 | ||
| 208 | * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. | |
| 209 | * arc-opc.c (insert_r13el): New function. | |
| 210 | (R13_EL): Define. | |
| 211 | * arc-tbl.h: Add new enter/leave variants. | |
| 212 | ||
| be6a24d8 CZ |
213 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| 214 | ||
| 215 | * arc-tbl.h: Reorder NOP entry to be before MOV instructions. | |
| 216 | ||
| 0348fd79 MR |
217 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| 218 | ||
| 219 | * mips-dis.c (print_mips_disassembler_options): Add | |
| 220 | `no-aliases'. | |
| 221 | ||
| 6e3d1f07 MR |
222 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| 223 | ||
| 224 | * mips16-opc.c (AL): New macro. | |
| 225 | (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms | |
| 226 | of "ld" and "lw" as aliases. | |
| 227 | ||
| 957f6b39 TC |
228 | 2017-04-24 Tamar Christina <tamar.christina@arm.com> |
| 229 | ||
| 230 | * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE | |
| 231 | arguments. | |
| 232 | ||
| a8cc8a54 AM |
233 | 2017-04-22 Alexander Fedotov <alfedotov@gmail.com> |
| 234 | Alan Modra <amodra@gmail.com> | |
| 235 | ||
| 236 | * ppc-opc.c (ELEV): Define. | |
| 237 | (vle_opcodes): Add se_rfgi and e_sc. | |
| 238 | (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx | |
| 239 | for E200Z4. | |
| 240 | ||
| 3ab87b68 JM |
241 | 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 242 | ||
| 243 | * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9. | |
| 244 | ||
| 792f174f NC |
245 | 2017-04-21 Nick Clifton <nickc@redhat.com> |
| 246 | ||
| 247 | PR binutils/21380 | |
| 248 | * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R, | |
| 249 | LD3R and LD4R. | |
| 250 | ||
| 42742084 AM |
251 | 2017-04-13 Alan Modra <amodra@gmail.com> |
| 252 | ||
| 253 | * epiphany-desc.c: Regenerate. | |
| 254 | * fr30-desc.c: Regenerate. | |
| 255 | * frv-desc.c: Regenerate. | |
| 256 | * ip2k-desc.c: Regenerate. | |
| 257 | * iq2000-desc.c: Regenerate. | |
| 258 | * lm32-desc.c: Regenerate. | |
| 259 | * m32c-desc.c: Regenerate. | |
| 260 | * m32r-desc.c: Regenerate. | |
| 261 | * mep-desc.c: Regenerate. | |
| 262 | * mt-desc.c: Regenerate. | |
| 263 | * or1k-desc.c: Regenerate. | |
| 264 | * xc16x-desc.c: Regenerate. | |
| 265 | * xstormy16-desc.c: Regenerate. | |
| 266 | ||
| 9a85b496 AM |
267 | 2017-04-11 Alan Modra <amodra@gmail.com> |
| 268 | ||
| ef85eab0 | 269 | * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2, |
| c03dc33b AM |
270 | PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set |
| 271 | PPC_OPCODE_TMR for e6500. | |
| 9a85b496 AM |
272 | * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. |
| 273 | (PPCVEC3): Define as PPC_OPCODE_POWER9. | |
| 9570835e AM |
274 | (PPCVSX2): Define as PPC_OPCODE_POWER8. |
| 275 | (PPCVSX3): Define as PPC_OPCODE_POWER9. | |
| ef85eab0 | 276 | (PPCHTM): Define as PPC_OPCODE_POWER8. |
| c03dc33b | 277 | (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
| 9a85b496 | 278 | |
| 62adc510 AM |
279 | 2017-04-10 Alan Modra <amodra@gmail.com> |
| 280 | ||
| 281 | * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440. | |
| 282 | * ppc-opc.c (MULHW): Add PPC_OPCODE_476. | |
| 283 | (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit | |
| 284 | removal of PPC_OPCODE_440 from ppc476 cpu selection bits. | |
| 285 | ||
| aa808707 PC |
286 | 2017-04-09 Pip Cet <pipcet@gmail.com> |
| 287 | ||
| 288 | * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify | |
| 289 | appropriate floating-point precision directly. | |
| 290 | ||
| ac8f0f72 AM |
291 | 2017-04-07 Alan Modra <amodra@gmail.com> |
| 292 | ||
| 293 | * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl, | |
| 294 | lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx, | |
| 295 | lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx, | |
| 296 | lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only | |
| 297 | vector instructions with E6500 not PPCVEC2. | |
| 298 | ||
| 62ecb94c PC |
299 | 2017-04-06 Pip Cet <pipcet@gmail.com> |
| 300 | ||
| 301 | * Makefile.am: Add wasm32-dis.c. | |
| 302 | * configure.ac: Add wasm32-dis.c to wasm32 target. | |
| 303 | * disassemble.c: Add wasm32 disassembler code. | |
| 304 | * wasm32-dis.c: New file. | |
| 305 | * Makefile.in: Regenerate. | |
| 306 | * configure: Regenerate. | |
| 307 | * po/POTFILES.in: Regenerate. | |
| 308 | * po/opcodes.pot: Regenerate. | |
| 309 | ||
| f995bbe8 PA |
310 | 2017-04-05 Pedro Alves <palves@redhat.com> |
| 311 | ||
| 312 | * arc-dis.c (parse_option, parse_disassembler_options): Constify. | |
| 313 | * arm-dis.c (parse_arm_disassembler_options): Constify. | |
| 314 | * ppc-dis.c (powerpc_init_dialect): Constify local. | |
| 315 | * vax-dis.c (parse_disassembler_options): Constify. | |
| 316 | ||
| b5292032 PD |
317 | 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> |
| 318 | ||
| 319 | * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to | |
| 320 | RISCV_GP_SYMBOL. | |
| 321 | ||
| f96bd6c2 PC |
322 | 2017-03-30 Pip Cet <pipcet@gmail.com> |
| 323 | ||
| 324 | * configure.ac: Add (empty) bfd_wasm32_arch target. | |
| 325 | * configure: Regenerate | |
| 326 | * po/opcodes.pot: Regenerate. | |
| 327 | ||
| f7c514a3 JM |
328 | 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com> |
| 329 | ||
| 330 | Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, & | |
| 331 | OSA2015. | |
| 332 | * opcodes/sparc-opc.c (asi_table): New ASIs. | |
| 333 | ||
| 52be03fd AM |
334 | 2017-03-29 Alan Modra <amodra@gmail.com> |
| 335 | ||
| 336 | * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add | |
| 337 | "raw" option. | |
| 338 | (lookup_powerpc): Don't special case -1 dialect. Handle | |
| 339 | PPC_OPCODE_RAW. | |
| 340 | (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first | |
| 341 | lookup_powerpc call, pass it on second. | |
| 342 | ||
| 9b753937 AM |
343 | 2017-03-27 Alan Modra <amodra@gmail.com> |
| 344 | ||
| 345 | PR 21303 | |
| 346 | * ppc-dis.c (struct ppc_mopt): Comment. | |
| 347 | (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. | |
| 348 | ||
| c0c31e91 RZ |
349 | 2017-03-27 Rinat Zelig <rinat@mellanox.com> |
| 350 | ||
| 351 | * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. | |
| 352 | * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, | |
| 353 | F_NPS_M, F_NPS_CORE, F_NPS_ALL. | |
| 354 | (insert_nps_misc_imm_offset): New function. | |
| 355 | (extract_nps_misc imm_offset): New function. | |
| 356 | (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. | |
| 357 | (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. | |
| 358 | ||
| 2253c8f0 AK |
359 | 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 360 | ||
| 361 | * s390-mkopc.c (main): Remove vx2 check. | |
| 362 | * s390-opc.txt: Remove vx2 instruction flags. | |
| 363 | ||
| 645d3342 RZ |
364 | 2017-03-21 Rinat Zelig <rinat@mellanox.com> |
| 365 | ||
| 366 | * arc-nps400-tbl.h: Add cp32/cp16 instructions format. | |
| 367 | * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. | |
| 368 | (insert_nps_imm_offset): New function. | |
| 369 | (extract_nps_imm_offset): New function. | |
| 370 | (insert_nps_imm_entry): New function. | |
| 371 | (extract_nps_imm_entry): New function. | |
| 372 | ||
| 4b94dd2d AM |
373 | 2017-03-17 Alan Modra <amodra@gmail.com> |
| 374 | ||
| 375 | PR 21248 | |
| 376 | * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33, | |
| 377 | mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after | |
| 378 | those spr mnemonics they alias. Similarly for mtibatl, mtibatu. | |
| 379 | ||
| b416fe87 KC |
380 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 381 | ||
| 382 | * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. | |
| 383 | <c.andi>: Likewise. | |
| 384 | <c.addiw> Likewise. | |
| 385 | ||
| 03b039a5 KC |
386 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 387 | ||
| 388 | * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode. | |
| 389 | ||
| 2c232b83 AW |
390 | 2017-03-13 Andrew Waterman <andrew@sifive.com> |
| 391 | ||
| 392 | * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. | |
| 393 | <srl> Likewise. | |
| 394 | <srai> Likewise. | |
| 395 | <sra> Likewise. | |
| 396 | ||
| 86fa6981 L |
397 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 398 | ||
| 399 | * i386-gen.c (opcode_modifiers): Replace S with Load. | |
| 400 | * i386-opc.h (S): Removed. | |
| 401 | (Load): New. | |
| 402 | (i386_opcode_modifier): Replace s with load. | |
| 403 | * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} | |
| 404 | and {evex}. Replace S with Load. | |
| 405 | * i386-tbl.h: Regenerated. | |
| 406 | ||
| c1fe188b L |
407 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 408 | ||
| 409 | * i386-opc.tbl: Use CpuCET on rdsspq. | |
| 410 | * i386-tbl.h: Regenerated. | |
| 411 | ||
| 4b8b687e PB |
412 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| 413 | ||
| 414 | * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; | |
| 415 | <vsx>: Do not use PPC_OPCODE_VSX3; | |
| 416 | ||
| 1437d063 PB |
417 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| 418 | ||
| 419 | * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. | |
| 420 | ||
| 603555e5 L |
421 | 2017-03-06 H.J. Lu <hongjiu.lu@intel.com> |
| 422 | ||
| 423 | * i386-dis.c (REG_0F1E_MOD_3): New enum. | |
| 424 | (MOD_0F1E_PREFIX_1): Likewise. | |
| 425 | (MOD_0F38F5_PREFIX_2): Likewise. | |
| 426 | (MOD_0F38F6_PREFIX_0): Likewise. | |
| 427 | (RM_0F1E_MOD_3_REG_7): Likewise. | |
| 428 | (PREFIX_MOD_0_0F01_REG_5): Likewise. | |
| 429 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. | |
| 430 | (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. | |
| 431 | (PREFIX_0F1E): Likewise. | |
| 432 | (PREFIX_MOD_0_0FAE_REG_5): Likewise. | |
| 433 | (PREFIX_0F38F5): Likewise. | |
| 434 | (dis386_twobyte): Use PREFIX_0F1E. | |
| 435 | (reg_table): Add REG_0F1E_MOD_3. | |
| 436 | (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, | |
| 437 | PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, | |
| 438 | PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update | |
| 439 | PREFIX_0FAE_REG_6 and PREFIX_0F38F6. | |
| 440 | (three_byte_table): Use PREFIX_0F38F5. | |
| 441 | (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. | |
| 442 | Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. | |
| 443 | (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, | |
| 444 | RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and | |
| 445 | PREFIX_MOD_3_0F01_REG_5_RM_2. | |
| 446 | * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. | |
| 447 | (cpu_flags): Add CpuCET. | |
| 448 | * i386-opc.h (CpuCET): New enum. | |
| 449 | (CpuUnused): Commented out. | |
| 450 | (i386_cpu_flags): Add cpucet. | |
| 451 | * i386-opc.tbl: Add Intel CET instructions. | |
| 452 | * i386-init.h: Regenerated. | |
| 453 | * i386-tbl.h: Likewise. | |
| 454 | ||
| 73f07bff AM |
455 | 2017-03-06 Alan Modra <amodra@gmail.com> |
| 456 | ||
| 457 | PR 21124 | |
| 458 | * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) | |
| 459 | (extract_raq, extract_ras, extract_rbx): New functions. | |
| 460 | (powerpc_operands): Use opposite corresponding insert function. | |
| 461 | (Q_MASK): Define. | |
| 462 | (powerpc_opcodes): Apply Q_MASK to all quad insns with even | |
| 463 | register restriction. | |
| 464 | ||
| 65b48a81 PB |
465 | 2017-02-28 Peter Bergner <bergner@vnet.ibm.com> |
| 466 | ||
| 467 | * disassemble.c Include "safe-ctype.h". | |
| 468 | (disassemble_init_for_target): Handle s390 init. | |
| 469 | (remove_whitespace_and_extra_commas): New function. | |
| 470 | (disassembler_options_cmp): Likewise. | |
| 471 | * arm-dis.c: Include "libiberty.h". | |
| 472 | (NUM_ELEM): Delete. | |
| 473 | (regnames): Use long disassembler style names. | |
| 474 | Add force-thumb and no-force-thumb options. | |
| 475 | (NUM_ARM_REGNAMES): Rename from this... | |
| 476 | (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. | |
| 477 | (get_arm_regname_num_options): Delete. | |
| 478 | (set_arm_regname_option): Likewise. | |
| 479 | (get_arm_regnames): Likewise. | |
| 480 | (parse_disassembler_options): Likewise. | |
| 481 | (parse_arm_disassembler_option): Rename from this... | |
| 482 | (parse_arm_disassembler_options): ...to this. Make static. | |
| 483 | Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. | |
| 484 | (print_insn): Use parse_arm_disassembler_options. | |
| 485 | (disassembler_options_arm): New function. | |
| 486 | (print_arm_disassembler_options): Handle updated regnames. | |
| 487 | * ppc-dis.c: Include "libiberty.h". | |
| 488 | (ppc_opts): Add "32" and "64" entries. | |
| 489 | (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. | |
| 490 | (powerpc_init_dialect): Add break to switch statement. | |
| 491 | Use new FOR_EACH_DISASSEMBLER_OPTION macro. | |
| 492 | (disassembler_options_powerpc): New function. | |
| 493 | (print_ppc_disassembler_options): Use ARRAY_SIZE. | |
| 494 | Remove printing of "32" and "64". | |
| 495 | * s390-dis.c: Include "libiberty.h". | |
| 496 | (init_flag): Remove unneeded variable. | |
| 497 | (struct s390_options_t): New structure type. | |
| 498 | (options): New structure. | |
| 499 | (init_disasm): Rename from this... | |
| 500 | (disassemble_init_s390): ...to this. Add initializations for | |
| 501 | current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. | |
| 502 | (print_insn_s390): Delete call to init_disasm. | |
| 503 | (disassembler_options_s390): New function. | |
| 504 | (print_s390_disassembler_options): Print using information from | |
| 505 | struct 'options'. | |
| 506 | * po/opcodes.pot: Regenerate. | |
| 507 | ||
| 15c7c1d8 JB |
508 | 2017-02-28 Jan Beulich <jbeulich@suse.com> |
| 509 | ||
| 510 | * i386-dis.c (PCMPESTR_Fixup): New. | |
| 511 | (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete. | |
| 512 | (prefix_table): Use PCMPESTR_Fixup. | |
| 513 | (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use | |
| 514 | PCMPESTR_Fixup. | |
| 515 | (vex_w_table): Delete VPCMPESTR{I,M} entries. | |
| 516 | * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm): | |
| 517 | Split 64-bit and non-64-bit variants. | |
| 518 | * opcodes/i386-tbl.h: Re-generate. | |
| 519 | ||
| 582e12bf RS |
520 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| 521 | ||
| 522 | * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) | |
| 523 | (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) | |
| 524 | (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) | |
| 525 | (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) | |
| 526 | (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) | |
| 527 | (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) | |
| 528 | (OP_SVE_V_HSD): New macros. | |
| 529 | (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) | |
| 530 | (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) | |
| 531 | (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. | |
| 532 | (aarch64_opcode_table): Add new SVE instructions. | |
| 533 | (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate | |
| 534 | for rotation operands. Add new SVE operands. | |
| 535 | * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. | |
| 536 | (ins_sve_quad_index): Likewise. | |
| 537 | (ins_imm_rotate): Split into... | |
| 538 | (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. | |
| 539 | * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... | |
| 540 | (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two | |
| 541 | functions. | |
| 542 | (aarch64_ins_sve_addr_ri_s4): New function. | |
| 543 | (aarch64_ins_sve_quad_index): Likewise. | |
| 544 | (do_misc_encoding): Handle "MOV Zn.Q, Qm". | |
| 545 | * aarch64-asm-2.c: Regenerate. | |
| 546 | * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. | |
| 547 | (ext_sve_quad_index): Likewise. | |
| 548 | (ext_imm_rotate): Split into... | |
| 549 | (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. | |
| 550 | * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... | |
| 551 | (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two | |
| 552 | functions. | |
| 553 | (aarch64_ext_sve_addr_ri_s4): New function. | |
| 554 | (aarch64_ext_sve_quad_index): Likewise. | |
| 555 | (aarch64_ext_sve_index): Allow quad indices. | |
| 556 | (do_misc_decoding): Likewise. | |
| 557 | * aarch64-dis-2.c: Regenerate. | |
| 558 | * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New | |
| 559 | aarch64_field_kinds. | |
| 560 | (OPD_F_OD_MASK): Widen by one bit. | |
| 561 | (OPD_F_NO_ZR): Bump accordingly. | |
| 562 | (get_operand_field_width): New function. | |
| 563 | * aarch64-opc.c (fields): Add new SVE fields. | |
| 564 | (operand_general_constraint_met_p): Handle new SVE operands. | |
| 565 | (aarch64_print_operand): Likewise. | |
| 566 | * aarch64-opc-2.c: Regenerate. | |
| 567 | ||
| f482d304 RS |
568 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| 569 | ||
| 570 | * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... | |
| 571 | (aarch64_feature_compnum): ...this. | |
| 572 | (SIMD_V8_3): Replace with... | |
| 573 | (COMPNUM): ...this. | |
| 574 | (CNUM_INSN): New macro. | |
| 575 | (aarch64_opcode_table): Use it for the complex number instructions. | |
| 576 | ||
| 7db2c588 JB |
577 | 2017-02-24 Jan Beulich <jbeulich@suse.com> |
| 578 | ||
| 579 | * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST. | |
| 580 | ||
| 1e9d41d4 SL |
581 | 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com> |
| 582 | ||
| 583 | Add support for associating SPARC ASIs with an architecture level. | |
| 584 | * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. | |
| 585 | * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ | |
| 586 | decoding of SPARC ASIs. | |
| 587 | ||
| 53c4d625 JB |
588 | 2017-02-23 Jan Beulich <jbeulich@suse.com> |
| 589 | ||
| 590 | * i386-dis.c (get_valid_dis386): Don't special case VEX opcode | |
| 591 | 82. For 3-byte VEX only special case opcode 77 in VEX_0F space. | |
| 592 | ||
| 11648de5 JB |
593 | 2017-02-21 Jan Beulich <jbeulich@suse.com> |
| 594 | ||
| 595 | * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand | |
| 596 | 1 (instead of to itself). Correct typo. | |
| 597 | ||
| f98d33be AW |
598 | 2017-02-14 Andrew Waterman <andrew@sifive.com> |
| 599 | ||
| 600 | * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and | |
| 601 | pseudoinstructions. | |
| 602 | ||
| 773fb663 RS |
603 | 2017-02-15 Richard Sandiford <richard.sandiford@arm.com> |
| 604 | ||
| 605 | * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. | |
| 606 | (aarch64_sys_reg_supported_p): Handle them. | |
| 607 | ||
| cc07cda6 CZ |
608 | 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> |
| 609 | ||
| 610 | * arc-opc.c (UIMM6_20R): Define. | |
| 611 | (SIMM12_20): Use above. | |
| 612 | (SIMM12_20R): Define. | |
| 613 | (SIMM3_5_S): Use above. | |
| 614 | (UIMM7_A32_11R_S): Define. | |
| 615 | (UIMM7_9_S): Use above. | |
| 616 | (UIMM3_13R_S): Define. | |
| 617 | (SIMM11_A32_7_S): Use above. | |
| 618 | (SIMM9_8R): Define. | |
| 619 | (UIMM10_A32_8_S): Use above. | |
| 620 | (UIMM8_8R_S): Define. | |
| 621 | (W6): Use above. | |
| 622 | (arc_relax_opcodes): Use all above defines. | |
| 623 | ||
| 66a5a740 VG |
624 | 2017-02-15 Vineet Gupta <vgupta@synopsys.com> |
| 625 | ||
| 626 | * arc-regs.h: Distinguish some of the registers different on | |
| 627 | ARC700 and HS38 cpus. | |
| 628 | ||
| 7e0de605 AM |
629 | 2017-02-14 Alan Modra <amodra@gmail.com> |
| 630 | ||
| 631 | PR 21118 | |
| 632 | * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries | |
| 633 | with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR. | |
| 634 | ||
| 54064fdb AM |
635 | 2017-02-11 Stafford Horne <shorne@gmail.com> |
| 636 | Alan Modra <amodra@gmail.com> | |
| 637 | ||
| 638 | * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. | |
| 639 | Use insn_bytes_value and insn_int_value directly instead. Don't | |
| 640 | free allocated memory until function exit. | |
| 641 | ||
| dce75bf9 NP |
642 | 2017-02-10 Nicholas Piggin <npiggin@gmail.com> |
| 643 | ||
| 644 | * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. | |
| 645 | ||
| 1b7e3d2f NC |
646 | 2017-02-03 Nick Clifton <nickc@redhat.com> |
| 647 | ||
| 648 | PR 21096 | |
| 649 | * aarch64-opc.c (print_register_list): Ensure that the register | |
| 650 | list index will fir into the tb buffer. | |
| 651 | (print_register_offset_address): Likewise. | |
| 652 | * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf. | |
| 653 | ||
| 8ec5cf65 AD |
654 | 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com> |
| 655 | ||
| 656 | PR 21056 | |
| 657 | * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel | |
| 658 | instructions when the previous fetch packet ends with a 32-bit | |
| 659 | instruction. | |
| 660 | ||
| a1aa5e81 DD |
661 | 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu> |
| 662 | ||
| 663 | * pru-opc.c: Remove vague reference to a future GDB port. | |
| 664 | ||
| add3afb2 NC |
665 | 2017-01-20 Nick Clifton <nickc@redhat.com> |
| 666 | ||
| 667 | * po/ga.po: Updated Irish translation. | |
| 668 | ||
| c13a63b0 SN |
669 | 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 670 | ||
| 671 | * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. | |
| 672 | ||
| 9608051a YQ |
673 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| 674 | ||
| 675 | * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 | |
| 676 | if FETCH_DATA returns 0. | |
| 677 | (m68k_scan_mask): Likewise. | |
| 678 | (print_insn_m68k): Update code to handle -1 return value. | |
| 679 | ||
| f622ea96 YQ |
680 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| 681 | ||
| 682 | * m68k-dis.c (enum print_insn_arg_error): New. | |
| 683 | (NEXTBYTE): Replace -3 with | |
| 684 | PRINT_INSN_ARG_MEMORY_ERROR. | |
| 685 | (NEXTULONG): Likewise. | |
| 686 | (NEXTSINGLE): Likewise. | |
| 687 | (NEXTDOUBLE): Likewise. | |
| 688 | (NEXTDOUBLE): Likewise. | |
| 689 | (NEXTPACKED): Likewise. | |
| 690 | (FETCH_ARG): Likewise. | |
| 691 | (FETCH_DATA): Update comments. | |
| 692 | (print_insn_arg): Update comments. Replace magic numbers with | |
| 693 | enum. | |
| 694 | (match_insn_m68k): Likewise. | |
| 695 | ||
| 620214f7 IT |
696 | 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 697 | ||
| 698 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. | |
| 699 | * i386-dis-evex.h (evex_table): Updated. | |
| 700 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, | |
| 701 | CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. | |
| 702 | (cpu_flags): Add CpuAVX512_VPOPCNTDQ. | |
| 703 | * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. | |
| 704 | (i386_cpu_flags): Add cpuavx512_vpopcntdq. | |
| 705 | * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. | |
| 706 | * i386-init.h: Regenerate. | |
| 707 | * i386-tbl.h: Ditto. | |
| 708 | ||
| d95014a2 YQ |
709 | 2017-01-12 Yao Qi <yao.qi@linaro.org> |
| 710 | ||
| 711 | * msp430-dis.c (msp430_singleoperand): Return -1 if | |
| 712 | msp430dis_opcode_signed returns false. | |
| 713 | (msp430_doubleoperand): Likewise. | |
| 714 | (msp430_branchinstr): Return -1 if | |
| 715 | msp430dis_opcode_unsigned returns false. | |
| 716 | (msp430x_calla_instr): Likewise. | |
| 717 | (print_insn_msp430): Likewise. | |
| 718 | ||
| 0ae60c3e NC |
719 | 2017-01-05 Nick Clifton <nickc@redhat.com> |
| 720 | ||
| 721 | PR 20946 | |
| 722 | * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name | |
| 723 | could not be matched. | |
| 724 | (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning | |
| 725 | NULL. | |
| 726 | ||
| d74d4880 SN |
727 | 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 728 | ||
| 729 | * aarch64-tbl.h (RCPC, RCPC_INSN): Define. | |
| 730 | (aarch64_opcode_table): Use RCPC_INSN. | |
| 731 | ||
| cc917fd9 KC |
732 | 2017-01-03 Kito Cheng <kito.cheng@gmail.com> |
| 733 | ||
| 734 | * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA | |
| 735 | extension. | |
| 736 | * riscv-opcodes/all-opcodes: Likewise. | |
| 737 | ||
| b52d3cfc DP |
738 | 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org> |
| 739 | ||
| 740 | * riscv-dis.c (print_insn_args): Add fall through comment. | |
| 741 | ||
| f90c58d5 NC |
742 | 2017-01-03 Nick Clifton <nickc@redhat.com> |
| 743 | ||
| 744 | * po/sr.po: New Serbian translation. | |
| 745 | * configure.ac (ALL_LINGUAS): Add sr. | |
| 746 | * configure: Regenerate. | |
| 747 | ||
| f47b0d4a AM |
748 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| 749 | ||
| 750 | * epiphany-desc.h: Regenerate. | |
| 751 | * epiphany-opc.h: Regenerate. | |
| 752 | * fr30-desc.h: Regenerate. | |
| 753 | * fr30-opc.h: Regenerate. | |
| 754 | * frv-desc.h: Regenerate. | |
| 755 | * frv-opc.h: Regenerate. | |
| 756 | * ip2k-desc.h: Regenerate. | |
| 757 | * ip2k-opc.h: Regenerate. | |
| 758 | * iq2000-desc.h: Regenerate. | |
| 759 | * iq2000-opc.h: Regenerate. | |
| 760 | * lm32-desc.h: Regenerate. | |
| 761 | * lm32-opc.h: Regenerate. | |
| 762 | * m32c-desc.h: Regenerate. | |
| 763 | * m32c-opc.h: Regenerate. | |
| 764 | * m32r-desc.h: Regenerate. | |
| 765 | * m32r-opc.h: Regenerate. | |
| 766 | * mep-desc.h: Regenerate. | |
| 767 | * mep-opc.h: Regenerate. | |
| 768 | * mt-desc.h: Regenerate. | |
| 769 | * mt-opc.h: Regenerate. | |
| 770 | * or1k-desc.h: Regenerate. | |
| 771 | * or1k-opc.h: Regenerate. | |
| 772 | * xc16x-desc.h: Regenerate. | |
| 773 | * xc16x-opc.h: Regenerate. | |
| 774 | * xstormy16-desc.h: Regenerate. | |
| 775 | * xstormy16-opc.h: Regenerate. | |
| 776 | ||
| 2571583a AM |
777 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| 778 | ||
| 779 | Update year range in copyright notice of all files. | |
| 780 | ||
| 5c1ad6b5 | 781 | For older changes see ChangeLog-2016 |
| 3499769a | 782 | \f |
| 5c1ad6b5 | 783 | Copyright (C) 2017 Free Software Foundation, Inc. |
| 3499769a AM |
784 | |
| 785 | Copying and distribution of this file, with or without modification, | |
| 786 | are permitted in any medium without royalty provided the copyright | |
| 787 | notice and this notice are preserved. | |
| 788 | ||
| 789 | Local Variables: | |
| 790 | mode: change-log | |
| 791 | left-margin: 8 | |
| 792 | fill-column: 74 | |
| 793 | version-control: never | |
| 794 | End: |