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gdb: Introduce global_symbol_searcher
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
8b301fbb
MI		 12019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
2
3 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
4 Change the coproc CRC conditions to use the extension
5 feature set, second word, base on ARM_EXT2_CRC.
6
6aa385b9
JB		 72019-11-14 Jan Beulich <jbeulich@suse.com>
8
9 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
10 * i386-tbl.h: Re-generate.
11
0cfa3eb3
JB		 122019-11-14 Jan Beulich <jbeulich@suse.com>
13
14 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
15 JumpInterSegment, and JumpAbsolute entries.
16 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
17 JUMP_ABSOLUTE): Define.
18 (struct i386_opcode_modifier): Extend jump field to 3 bits.
19 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
20 fields.
21 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
22 JumpInterSegment): Define.
23 * i386-tbl.h: Re-generate.
24
6f2f06be
JB		 252019-11-14 Jan Beulich <jbeulich@suse.com>
26
27 * i386-gen.c (operand_type_init): Remove
28 OPERAND_TYPE_JUMPABSOLUTE entry.
29 (opcode_modifiers): Add JumpAbsolute entry.
30 (operand_types): Remove JumpAbsolute entry.
31 * i386-opc.h (JumpAbsolute): Move between enums.
32 (struct i386_opcode_modifier): Add jumpabsolute field.
33 (union i386_operand_type): Remove jumpabsolute field.
34 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
35 * i386-init.h, i386-tbl.h: Re-generate.
36
601e8564
JB		 372019-11-14 Jan Beulich <jbeulich@suse.com>
38
39 * i386-gen.c (opcode_modifiers): Add AnySize entry.
40 (operand_types): Remove AnySize entry.
41 * i386-opc.h (AnySize): Move between enums.
42 (struct i386_opcode_modifier): Add anysize field.
43 (OTUnused): Un-comment.
44 (union i386_operand_type): Remove anysize field.
45 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
46 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
47 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
48 AnySize.
49 * i386-tbl.h: Re-generate.
50
7722d40a
JW		 512019-11-12 Nelson Chu <nelson.chu@sifive.com>
52
53 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
54 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
55 use the floating point register (FPR).
56
ce760a76
MI		 572019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
58
59 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
60 cmode 1101.
61 (is_mve_encoding_conflict): Update cmode conflict checks for
62 MVE_VMVN_IMM.
63
51c8edf6
JB		 642019-11-12 Jan Beulich <jbeulich@suse.com>
65
66 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
67 entry.
68 (operand_types): Remove EsSeg entry.
69 (main): Replace stale use of OTMax.
70 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
71 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
72 (EsSeg): Delete.
73 (OTUnused): Comment out.
74 (union i386_operand_type): Remove esseg field.
75 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
76 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
77 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
78 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
79 * i386-init.h, i386-tbl.h: Re-generate.
80
474da251
JB		 812019-11-12 Jan Beulich <jbeulich@suse.com>
82
83 * i386-gen.c (operand_instances): Add RegB entry.
84 * i386-opc.h (enum operand_instance): Add RegB.
85 * i386-opc.tbl (RegC, RegD, RegB): Define.
86 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
87 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
88 monitorx, mwaitx): Drop ImmExt and convert encodings
89 accordingly.
90 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
91 (edx, rdx): Add Instance=RegD.
92 (ebx, rbx): Add Instance=RegB.
93 * i386-tbl.h: Re-generate.
94
75e5731b
JB		 952019-11-12 Jan Beulich <jbeulich@suse.com>
96
97 * i386-gen.c (operand_type_init): Adjust
98 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
99 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
100 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
101 (operand_instances): New.
102 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
103 (output_operand_type): New parameter "instance". Process it.
104 (process_i386_operand_type): New local variable "instance".
105 (main): Adjust static assertions.
106 * i386-opc.h (INSTANCE_WIDTH): Define.
107 (enum operand_instance): New.
108 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
109 (union i386_operand_type): Replace acc, inoutportreg, and
110 shiftcount by instance.
111 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
112 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
113 Add Instance=.
114 * i386-init.h, i386-tbl.h: Re-generate.
115
91802f3c
JB		 1162019-11-11 Jan Beulich <jbeulich@suse.com>
117
118 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
119 smaxp/sminp entries' "tied_operand" field to 2.
120
4f5fc85d
JB		 1212019-11-11 Jan Beulich <jbeulich@suse.com>
122
123 * aarch64-opc.c (operand_general_constraint_met_p): Replace
124 "index" local variable by that of the already existing "num".
125
dc2be329
L		 1262019-11-08 H.J. Lu <hongjiu.lu@intel.com>
127
128 PR gas/25167
129 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
130 * i386-tbl.h: Regenerated.
131
f74a6307
JB		 1322019-11-08 Jan Beulich <jbeulich@suse.com>
133
134 * i386-gen.c (operand_type_init): Add Class= to
135 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
136 OPERAND_TYPE_REGBND entry.
137 (operand_classes): Add RegMask and RegBND entries.
138 (operand_types): Drop RegMask and RegBND entry.
139 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
140 (RegMask, RegBND): Delete.
141 (union i386_operand_type): Remove regmask and regbnd fields.
142 * i386-opc.tbl (RegMask, RegBND): Define.
143 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
144 Class=RegBND.
145 * i386-init.h, i386-tbl.h: Re-generate.
146
3528c362
JB		 1472019-11-08 Jan Beulich <jbeulich@suse.com>
148
149 * i386-gen.c (operand_type_init): Add Class= to
150 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
151 OPERAND_TYPE_REGZMM entries.
152 (operand_classes): Add RegMMX and RegSIMD entries.
153 (operand_types): Drop RegMMX and RegSIMD entries.
154 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
155 (RegMMX, RegSIMD): Delete.
156 (union i386_operand_type): Remove regmmx and regsimd fields.
157 * i386-opc.tbl (RegMMX): Define.
158 (RegXMM, RegYMM, RegZMM): Add Class=.
159 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
160 Class=RegSIMD.
161 * i386-init.h, i386-tbl.h: Re-generate.
162
4a5c67ed
JB		 1632019-11-08 Jan Beulich <jbeulich@suse.com>
164
165 * i386-gen.c (operand_type_init): Add Class= to
166 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
167 entries.
168 (operand_classes): Add RegCR, RegDR, and RegTR entries.
169 (operand_types): Drop Control, Debug, and Test entries.
170 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
171 (Control, Debug, Test): Delete.
172 (union i386_operand_type): Remove control, debug, and test
173 fields.
174 * i386-opc.tbl (Control, Debug, Test): Define.
175 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
176 Class=RegDR, and Test by Class=RegTR.
177 * i386-init.h, i386-tbl.h: Re-generate.
178
00cee14f
JB		 1792019-11-08 Jan Beulich <jbeulich@suse.com>
180
181 * i386-gen.c (operand_type_init): Add Class= to
182 OPERAND_TYPE_SREG entry.
183 (operand_classes): Add SReg entry.
184 (operand_types): Drop SReg entry.
185 * i386-opc.h (enum operand_class): Add SReg.
186 (SReg): Delete.
187 (union i386_operand_type): Remove sreg field.
188 * i386-opc.tbl (SReg): Define.
189 * i386-reg.tbl: Replace SReg by Class=SReg.
190 * i386-init.h, i386-tbl.h: Re-generate.
191
bab6aec1
JB		 1922019-11-08 Jan Beulich <jbeulich@suse.com>
193
194 * i386-gen.c (operand_type_init): Add Class=. New
195 OPERAND_TYPE_ANYIMM entry.
196 (operand_classes): New.
197 (operand_types): Drop Reg entry.
198 (output_operand_type): New parameter "class". Process it.
199 (process_i386_operand_type): New local variable "class".
200 (main): Adjust static assertions.
201 * i386-opc.h (CLASS_WIDTH): Define.
202 (enum operand_class): New.
203 (Reg): Replace by Class. Adjust comment.
204 (union i386_operand_type): Replace reg by class.
205 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
206 Class=.
207 * i386-reg.tbl: Replace Reg by Class=Reg.
208 * i386-init.h: Re-generate.
209
1f4cd317
MM		 2102019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
211
212 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
213 (aarch64_opcode_table): Add data gathering hint mnemonic.
214 * opcodes/aarch64-dis-2.c: Account for new instruction.
215
616ce08e
MM		 2162019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
217
218 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
219
220
8382113f
MM		 2212019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
222
223 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
224 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
225 aarch64_feature_f64mm): New feature sets.
226 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
227 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
228 instructions.
229 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
230 macros.
231 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
232 (OP_SVE_QQQ): New qualifier.
233 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
234 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
235 the movprfx constraint.
236 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
237 (aarch64_opcode_table): Define new instructions smmla,
238 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
239 uzip{1/2}, trn{1/2}.
240 * aarch64-opc.c (operand_general_constraint_met_p): Handle
241 AARCH64_OPND_SVE_ADDR_RI_S4x32.
242 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
243 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
244 Account for new instructions.
245 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
246 S4x32 operand.
247 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
248
aab2c27d
MM		 2492019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2502019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
251
252 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
253 Armv8.6-A.
254 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
255 (neon_opcodes): Add bfloat SIMD instructions.
256 (print_insn_coprocessor): Add new control character %b to print
257 condition code without checking cp_num.
258 (print_insn_neon): Account for BFloat16 instructions that have no
259 special top-byte handling.
260
33593eaf
MM		 2612019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2622019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
263
264 * arm-dis.c (print_insn_coprocessor,
265 print_insn_generic_coprocessor): Create wrapper functions around
266 the implementation of the print_insn_coprocessor control codes.
267 (print_insn_coprocessor_1): Original print_insn_coprocessor
268 function that now takes which array to look at as an argument.
269 (print_insn_arm): Use both print_insn_coprocessor and
270 print_insn_generic_coprocessor.
271 (print_insn_thumb32): As above.
272
df678013
MM		 2732019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2742019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
275
276 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
277 in reglane special case.
278 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
279 aarch64_find_next_opcode): Account for new instructions.
280 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
281 in reglane special case.
282 * aarch64-opc.c (struct operand_qualifier_data): Add data for
283 new AARCH64_OPND_QLF_S_2H qualifier.
284 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
285 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
286 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
287 sets.
288 (BFLOAT_SVE, BFLOAT): New feature set macros.
289 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
290 instructions.
291 (aarch64_opcode_table): Define new instructions bfdot,
292 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
293 bfcvtn2, bfcvt.
294
8ae2d3d9
MM		 2952019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
2962019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
297
298 * aarch64-tbl.h (ARMV8_6): New macro.
299
142861df
JB		 3002019-11-07 Jan Beulich <jbeulich@suse.com>
301
302 * i386-dis.c (prefix_table): Add mcommit.
303 (rm_table): Add rdpru.
304 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
305 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
306 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
307 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
308 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
309 * i386-opc.tbl (mcommit, rdpru): New.
310 * i386-init.h, i386-tbl.h: Re-generate.
311
081e283f
JB		 3122019-11-07 Jan Beulich <jbeulich@suse.com>
313
314 * i386-dis.c (OP_Mwait): Drop local variable "names", use
315 "names32" instead.
316 (OP_Monitor): Drop local variable "op1_names", re-purpose
317 "names" for it instead, and replace former "names" uses by
318 "names32" ones.
319
c050c89a
JB		 3202019-11-07 Jan Beulich <jbeulich@suse.com>
321
322 PR/gas 25167
323 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
324 operand-less forms.
325 * opcodes/i386-tbl.h: Re-generate.
326
7abb8d81
JB		 3272019-11-05 Jan Beulich <jbeulich@suse.com>
328
329 * i386-dis.c (OP_Mwaitx): Delete.
330 (prefix_table): Use OP_Mwait for mwaitx entry.
331 (OP_Mwait): Also handle mwaitx.
332
267b8516
JB		 3332019-11-05 Jan Beulich <jbeulich@suse.com>
334
335 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
336 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
337 (prefix_table): Add respective entries.
338 (rm_table): Link to those entries.
339
f8687e93
JB		 3402019-11-05 Jan Beulich <jbeulich@suse.com>
341
342 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
343 (REG_0F1C_P_0_MOD_0): ... this.
344 (REG_0F1E_MOD_3): Rename to ...
345 (REG_0F1E_P_1_MOD_3): ... this.
346 (RM_0F01_REG_5): Rename to ...
347 (RM_0F01_REG_5_MOD_3): ... this.
348 (RM_0F01_REG_7): Rename to ...
349 (RM_0F01_REG_7_MOD_3): ... this.
350 (RM_0F1E_MOD_3_REG_7): Rename to ...
351 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
352 (RM_0FAE_REG_6): Rename to ...
353 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
354 (RM_0FAE_REG_7): Rename to ...
355 (RM_0FAE_REG_7_MOD_3): ... this.
356 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
357 (PREFIX_0F01_REG_5_MOD_0): ... this.
358 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
359 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
360 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
361 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
362 (PREFIX_0FAE_REG_0): Rename to ...
363 (PREFIX_0FAE_REG_0_MOD_3): ... this.
364 (PREFIX_0FAE_REG_1): Rename to ...
365 (PREFIX_0FAE_REG_1_MOD_3): ... this.
366 (PREFIX_0FAE_REG_2): Rename to ...
367 (PREFIX_0FAE_REG_2_MOD_3): ... this.
368 (PREFIX_0FAE_REG_3): Rename to ...
369 (PREFIX_0FAE_REG_3_MOD_3): ... this.
370 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
371 (PREFIX_0FAE_REG_4_MOD_0): ... this.
372 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
373 (PREFIX_0FAE_REG_4_MOD_3): ... this.
374 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
375 (PREFIX_0FAE_REG_5_MOD_0): ... this.
376 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
377 (PREFIX_0FAE_REG_5_MOD_3): ... this.
378 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
379 (PREFIX_0FAE_REG_6_MOD_0): ... this.
380 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
381 (PREFIX_0FAE_REG_6_MOD_3): ... this.
382 (PREFIX_0FAE_REG_7): Rename to ...
383 (PREFIX_0FAE_REG_7_MOD_0): ... this.
384 (PREFIX_MOD_0_0FC3): Rename to ...
385 (PREFIX_0FC3_MOD_0): ... this.
386 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
387 (PREFIX_0FC7_REG_6_MOD_0): ... this.
388 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
389 (PREFIX_0FC7_REG_6_MOD_3): ... this.
390 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
391 (PREFIX_0FC7_REG_7_MOD_3): ... this.
392 (reg_table, prefix_table, mod_table, rm_table): Adjust
393 accordingly.
394
5103274f
NC		 3952019-11-04 Nick Clifton <nickc@redhat.com>
396
397 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
398 of a v850 system register. Move the v850_sreg_names array into
399 this function.
400 (get_v850_reg_name): Likewise for ordinary register names.
401 (get_v850_vreg_name): Likewise for vector register names.
402 (get_v850_cc_name): Likewise for condition codes.
403 * get_v850_float_cc_name): Likewise for floating point condition
404 codes.
405 (get_v850_cacheop_name): Likewise for cache-ops.
406 (get_v850_prefop_name): Likewise for pref-ops.
407 (disassemble): Use the new accessor functions.
408
1820262b
DB		 4092019-10-30 Delia Burduv <delia.burduv@arm.com>
410
411 * aarch64-opc.c (print_immediate_offset_address): Don't print the
412 immediate for the writeback form of ldraa/ldrab if it is 0.
413 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
414 * aarch64-opc-2.c: Regenerated.
415
3cc17af5
JB		 4162019-10-30 Jan Beulich <jbeulich@suse.com>
417
418 * i386-gen.c (operand_type_shorthands): Delete.
419 (operand_type_init): Expand previous shorthands.
420 (set_bitfield_from_shorthand): Rename back to ...
421 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
422 of operand_type_init[].
423 (set_bitfield): Adjust call to the above function.
424 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
425 RegXMM, RegYMM, RegZMM): Define.
426 * i386-reg.tbl: Expand prior shorthands.
427
a2cebd03
JB		 4282019-10-30 Jan Beulich <jbeulich@suse.com>
429
430 * i386-gen.c (output_i386_opcode): Change order of fields
431 emitted to output.
432 * i386-opc.h (struct insn_template): Move operands field.
433 Convert extension_opcode field to unsigned short.
434 * i386-tbl.h: Re-generate.
435
507916b8
JB		 4362019-10-30 Jan Beulich <jbeulich@suse.com>
437
438 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
439 of W.
440 * i386-opc.h (W): Extend comment.
441 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
442 general purpose variants not allowing for byte operands.
443 * i386-tbl.h: Re-generate.
444
efea62b4
NC		 4452019-10-29 Nick Clifton <nickc@redhat.com>
446
447 * tic30-dis.c (print_branch): Correct size of operand array.
448
9adb2591
NC		 4492019-10-29 Nick Clifton <nickc@redhat.com>
450
451 * d30v-dis.c (print_insn): Check that operand index is valid
452 before attempting to access the operands array.
453
993a00a9
NC		 4542019-10-29 Nick Clifton <nickc@redhat.com>
455
456 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
457 locating the bit to be tested.
458
66a66a17
NC		 4592019-10-29 Nick Clifton <nickc@redhat.com>
460
461 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
462 values.
463 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
464 (print_insn_s12z): Check for illegal size values.
465
1ee3542c
NC		 4662019-10-28 Nick Clifton <nickc@redhat.com>
467
468 * csky-dis.c (csky_chars_to_number): Check for a negative
469 count. Use an unsigned integer to construct the return value.
470
bbf9a0b5
NC		 4712019-10-28 Nick Clifton <nickc@redhat.com>
472
473 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
474 operand buffer. Set value to 15 not 13.
475 (get_register_operand): Use OPERAND_BUFFER_LEN.
476 (get_indirect_operand): Likewise.
477 (print_two_operand): Likewise.
478 (print_three_operand): Likewise.
479 (print_oar_insn): Likewise.
480
d1e304bc
NC		 4812019-10-28 Nick Clifton <nickc@redhat.com>
482
483 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
484 (bit_extract_simple): Likewise.
485 (bit_copy): Likewise.
486 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
487 index_offset array are not accessed.
488
dee33451
NC		 4892019-10-28 Nick Clifton <nickc@redhat.com>
490
491 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
492 operand.
493
27cee81d
NC		 4942019-10-25 Nick Clifton <nickc@redhat.com>
495
496 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
497 access to opcodes.op array element.
498
de6d8dc2
NC		 4992019-10-23 Nick Clifton <nickc@redhat.com>
500
501 * rx-dis.c (get_register_name): Fix spelling typo in error
502 message.
503 (get_condition_name, get_flag_name, get_double_register_name)
504 (get_double_register_high_name, get_double_register_low_name)
505 (get_double_control_register_name, get_double_condition_name)
506 (get_opsize_name, get_size_name): Likewise.
507
6207ed28
NC		 5082019-10-22 Nick Clifton <nickc@redhat.com>
509
510 * rx-dis.c (get_size_name): New function. Provides safe
511 access to name array.
512 (get_opsize_name): Likewise.
513 (print_insn_rx): Use the accessor functions.
514
12234dfd
NC		 5152019-10-16 Nick Clifton <nickc@redhat.com>
516
517 * rx-dis.c (get_register_name): New function. Provides safe
518 access to name array.
519 (get_condition_name, get_flag_name, get_double_register_name)
520 (get_double_register_high_name, get_double_register_low_name)
521 (get_double_control_register_name, get_double_condition_name):
522 Likewise.
523 (print_insn_rx): Use the accessor functions.
524
1d378749
NC		 5252019-10-09 Nick Clifton <nickc@redhat.com>
526
527 PR 25041
528 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
529 instructions.
530
d241b910
JB		 5312019-10-07 Jan Beulich <jbeulich@suse.com>
532
533 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
534 (cmpsd): Likewise. Move EsSeg to other operand.
535 * opcodes/i386-tbl.h: Re-generate.
536
f5c5b7c1
AM		 5372019-09-23 Alan Modra <amodra@gmail.com>
538
539 * m68k-dis.c: Include cpu-m68k.h
540
7beeaeb8
AM		 5412019-09-23 Alan Modra <amodra@gmail.com>
542
543 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
544 "elf/mips.h" earlier.
545
3f9aad11
JB		 5462018-09-20 Jan Beulich <jbeulich@suse.com>
547
548 PR gas/25012
549 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
550 with SReg operand.
551 * i386-tbl.h: Re-generate.
552
fd361982
AM		 5532019-09-18 Alan Modra <amodra@gmail.com>
554
555 * arc-ext.c: Update throughout for bfd section macro changes.
556
e0b2a78c
SM		 5572019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
558
559 * Makefile.in: Re-generate.
560 * configure: Re-generate.
561
7e9ad3a3
JW		 5622019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
563
564 * riscv-opc.c (riscv_opcodes): Change subset field
565 to insn_class field for all instructions.
566 (riscv_insn_types): Likewise.
567
bb695960
PB		 5682019-09-16 Phil Blundell <pb@pbcl.net>
569
570 * configure: Regenerated.
571
8063ab7e
MV		 5722019-09-10 Miod Vallat <miod@online.fr>
573
574 PR 24982
575 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
576
60391a25
PB		 5772019-09-09 Phil Blundell <pb@pbcl.net>
578
579 binutils 2.33 branch created.
580
f44b758d
NC		 5812019-09-03 Nick Clifton <nickc@redhat.com>
582
583 PR 24961
584 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
585 greater than zero before indexing via (bufcnt -1).
586
1e4b5e7d
NC		 5872019-09-03 Nick Clifton <nickc@redhat.com>
588
589 PR 24958
590 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
591 (MAX_SPEC_REG_NAME_LEN): Define.
592 (struct mmix_dis_info): Use defined constants for array lengths.
593 (get_reg_name): New function.
594 (get_sprec_reg_name): New function.
595 (print_insn_mmix): Use new functions.
596
c4a23bf8
SP		 5972019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
598
599 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
600 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
601 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
602
a051e2f3
KT		 6032019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
604
605 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
606 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
607 (aarch64_sys_reg_supported_p): Update checks for the above.
608
08132bdd
SP		 6092019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
610
611 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
612 cases MVE_SQRSHRL and MVE_UQRSHLL.
613 (print_insn_mve): Add case for specifier 'k' to check
614 specific bit of the instruction.
615
d88bdcb4
PA		 6162019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
617
618 PR 24854
619 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
620 encountering an unknown machine type.
621 (print_insn_arc): Handle arc_insn_length returning 0. In error
622 cases return -1 rather than calling abort.
623
bc750500
JB		 6242019-08-07 Jan Beulich <jbeulich@suse.com>
625
626 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
627 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
628 IgnoreSize.
629 * i386-tbl.h: Re-generate.
630
23d188c7
BW		 6312019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
632
633 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
634 instructions.
635
c0d6f62f
JW		 6362019-07-30 Mel Chen <mel.chen@sifive.com>
637
638 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
639 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
640
641 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
642 fscsr.
643
0f3f7167
CZ		 6442019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
645
646 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
647 and MPY class instructions.
648 (parse_option): Add nps400 option.
649 (print_arc_disassembler_options): Add nps400 info.
650
7e126ba3
CZ		 6512019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
652
653 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
654 (bspop): Likewise.
655 (modapp): Likewise.
656 * arc-opc.c (RAD_CHK): Add.
657 * arc-tbl.h: Regenerate.
658
a028026d
KT		 6592019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
660
661 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
662 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
663
ac79ff9e
NC		 6642019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
665
666 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
667 instructions as UNPREDICTABLE.
668
231097b0
JM		 6692019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
670
671 * bpf-desc.c: Regenerated.
672
1d942ae9
JB		 6732019-07-17 Jan Beulich <jbeulich@suse.com>
674
675 * i386-gen.c (static_assert): Define.
676 (main): Use it.
677 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
678 (Opcode_Modifier_Num): ... this.
679 (Mem): Delete.
680
dfd69174
JB		 6812019-07-16 Jan Beulich <jbeulich@suse.com>
682
683 * i386-gen.c (operand_types): Move RegMem ...
684 (opcode_modifiers): ... here.
685 * i386-opc.h (RegMem): Move to opcode modifer enum.
686 (union i386_operand_type): Move regmem field ...
687 (struct i386_opcode_modifier): ... here.
688 * i386-opc.tbl (RegMem): Define.
689 (mov, movq): Move RegMem on segment, control, debug, and test
690 register flavors.
691 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
692 to non-SSE2AVX flavor.
693 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
694 Move RegMem on register only flavors. Drop IgnoreSize from
695 legacy encoding flavors.
696 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
697 flavors.
698 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
699 register only flavors.
700 (vmovd): Move RegMem and drop IgnoreSize on register only
701 flavor. Change opcode and operand order to store form.
702 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
703
21df382b
JB		 7042019-07-16 Jan Beulich <jbeulich@suse.com>
705
706 * i386-gen.c (operand_type_init, operand_types): Replace SReg
707 entries.
708 * i386-opc.h (SReg2, SReg3): Replace by ...
709 (SReg): ... this.
710 (union i386_operand_type): Replace sreg fields.
711 * i386-opc.tbl (mov, ): Use SReg.
712 (push, pop): Likewies. Drop i386 and x86-64 specific segment
713 register flavors.
714 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
715 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
716
3719fd55
JM		 7172019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
718
719 * bpf-desc.c: Regenerate.
720 * bpf-opc.c: Likewise.
721 * bpf-opc.h: Likewise.
722
92434a14
JM		 7232019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
724
725 * bpf-desc.c: Regenerate.
726 * bpf-opc.c: Likewise.
727
43dd7626
HPN		 7282019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
729
730 * arm-dis.c (print_insn_coprocessor): Rename index to
731 index_operand.
732
98602811
JW		 7332019-07-05 Kito Cheng <kito.cheng@sifive.com>
734
735 * riscv-opc.c (riscv_insn_types): Add r4 type.
736
737 * riscv-opc.c (riscv_insn_types): Add b and j type.
738
739 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
740 format for sb type and correct s type.
741
01c1ee4a
RS		 7422019-07-02 Richard Sandiford <richard.sandiford@arm.com>
743
744 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
745 SVE FMOV alias of FCPY.
746
83adff69
RS		 7472019-07-02 Richard Sandiford <richard.sandiford@arm.com>
748
749 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
750 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
751
89418844
RS		 7522019-07-02 Richard Sandiford <richard.sandiford@arm.com>
753
754 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
755 registers in an instruction prefixed by MOVPRFX.
756
41be57ca
MM		 7572019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
758
759 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
760 sve_size_13 icode to account for variant behaviour of
761 pmull{t,b}.
762 * aarch64-dis-2.c: Regenerate.
763 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
764 sve_size_13 icode to account for variant behaviour of
765 pmull{t,b}.
766 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
767 (OP_SVE_VVV_Q_D): Add new qualifier.
768 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
769 (struct aarch64_opcode): Split pmull{t,b} into those requiring
770 AES and those not.
771
9d3bf266
JB		 7722019-07-01 Jan Beulich <jbeulich@suse.com>
773
774 * opcodes/i386-gen.c (operand_type_init): Remove
775 OPERAND_TYPE_VEC_IMM4 entry.
776 (operand_types): Remove Vec_Imm4.
777 * opcodes/i386-opc.h (Vec_Imm4): Delete.
778 (union i386_operand_type): Remove vec_imm4.
779 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
780 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
781
c3949f43
JB		 7822019-07-01 Jan Beulich <jbeulich@suse.com>
783
784 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
785 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
786 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
787 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
788 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
789 monitorx, mwaitx): Drop ImmExt from operand-less forms.
790 * i386-tbl.h: Re-generate.
791
5641ec01
JB		 7922019-07-01 Jan Beulich <jbeulich@suse.com>
793
794 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
795 register operands.
796 * i386-tbl.h: Re-generate.
797
79dec6b7
JB		 7982019-07-01 Jan Beulich <jbeulich@suse.com>
799
800 * i386-opc.tbl (C): New.
801 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
802 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
803 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
804 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
805 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
806 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
807 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
808 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
809 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
810 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
811 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
812 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
813 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
814 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
815 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
816 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
817 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
818 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
819 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
820 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
821 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
822 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
823 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
824 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
825 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
826 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
827 flavors.
828 * i386-tbl.h: Re-generate.
829
a0a1771e
JB		 8302019-07-01 Jan Beulich <jbeulich@suse.com>
831
832 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
833 register operands.
834 * i386-tbl.h: Re-generate.
835
cd546e7b
JB		 8362019-07-01 Jan Beulich <jbeulich@suse.com>
837
838 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
839 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
840 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
841 * i386-tbl.h: Re-generate.
842
e3bba3fc
JB		 8432019-07-01 Jan Beulich <jbeulich@suse.com>
844
845 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
846 Disp8MemShift from register only templates.
847 * i386-tbl.h: Re-generate.
848
36cc073e
JB		 8492019-07-01 Jan Beulich <jbeulich@suse.com>
850
851 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
852 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
853 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
854 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
855 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
856 EVEX_W_0F11_P_3_M_1): Delete.
857 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
858 EVEX_W_0F11_P_3): New.
859 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
860 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
861 MOD_EVEX_0F11_PREFIX_3 table entries.
862 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
863 PREFIX_EVEX_0F11 table entries.
864 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
865 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
866 EVEX_W_0F11_P_3_M_{0,1} table entries.
867
219920a7
JB		 8682019-07-01 Jan Beulich <jbeulich@suse.com>
869
870 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
871 Delete.
872
e395f487
L		 8732019-06-27 H.J. Lu <hongjiu.lu@intel.com>
874
875 PR binutils/24719
876 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
877 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
878 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
879 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
880 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
881 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
882 EVEX_LEN_0F38C7_R_6_P_2_W_1.
883 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
884 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
885 PREFIX_EVEX_0F38C6_REG_6 entries.
886 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
887 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
888 EVEX_W_0F38C7_R_6_P_2 entries.
889 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
890 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
891 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
892 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
893 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
894 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
895 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
896
2b7bcc87
JB		 8972019-06-27 Jan Beulich <jbeulich@suse.com>
898
899 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
900 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
901 VEX_LEN_0F2D_P_3): Delete.
902 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
903 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
904 (prefix_table): ... here.
905
c1dc7af5
JB		 9062019-06-27 Jan Beulich <jbeulich@suse.com>
907
908 * i386-dis.c (Iq): Delete.
909 (Id): New.
910 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
911 TBM insns.
912 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
913 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
914 (OP_E_memory): Also honor needindex when deciding whether an
915 address size prefix needs printing.
916 (OP_I): Remove handling of q_mode. Add handling of d_mode.
917
d7560e2d
JW		 9182019-06-26 Jim Wilson <jimw@sifive.com>
919
920 PR binutils/24739
921 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
922 Set info->display_endian to info->endian_code.
923
2c703856
JB		 9242019-06-25 Jan Beulich <jbeulich@suse.com>
925
926 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
927 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
928 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
929 OPERAND_TYPE_ACC64 entries.
930 * i386-init.h: Re-generate.
931
54fbadc0
JB		 9322019-06-25 Jan Beulich <jbeulich@suse.com>
933
934 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
935 Delete.
936 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
937 of dqa_mode.
938 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
939 entries here.
940 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
941 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
942
a280ab8e
JB		 9432019-06-25 Jan Beulich <jbeulich@suse.com>
944
945 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
946 variables.
947
e1a1babd
JB		 9482019-06-25 Jan Beulich <jbeulich@suse.com>
949
950 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
951 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
952 movnti.
d7560e2d 953 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 954 * i386-tbl.h: Re-generate.
955
b8364fa7
JB		 9562019-06-25 Jan Beulich <jbeulich@suse.com>
957
958 * i386-opc.tbl (and): Mark Imm8S form for optimization.
959 * i386-tbl.h: Re-generate.
960
ad692897
L		 9612019-06-21 H.J. Lu <hongjiu.lu@intel.com>
962
963 * i386-dis-evex.h: Break into ...
964 * i386-dis-evex-len.h: New file.
965 * i386-dis-evex-mod.h: Likewise.
966 * i386-dis-evex-prefix.h: Likewise.
967 * i386-dis-evex-reg.h: Likewise.
968 * i386-dis-evex-w.h: Likewise.
969 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
970 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
971 i386-dis-evex-mod.h.
972
f0a6222e
L		 9732019-06-19 H.J. Lu <hongjiu.lu@intel.com>
974
975 PR binutils/24700
976 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
977 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
978 EVEX_W_0F385B_P_2.
979 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
980 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
981 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
982 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
983 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
984 EVEX_LEN_0F385B_P_2_W_1.
985 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
986 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
987 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
988 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
989 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
990 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
991 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
992 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
993 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
994 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
995
6e1c90b7
L		 9962019-06-17 H.J. Lu <hongjiu.lu@intel.com>
997
998 PR binutils/24691
999 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1000 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1001 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1002 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1003 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1004 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1005 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1006 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1007 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1008 EVEX_LEN_0F3A43_P_2_W_1.
1009 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1010 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1011 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1012 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1013 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1014 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1015 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1016 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1017 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1018 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1019 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1020 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1021
bcc5a6eb
NC		 10222019-06-14 Nick Clifton <nickc@redhat.com>
1023
1024 * po/fr.po; Updated French translation.
1025
e4c4ac46
SH		 10262019-06-13 Stafford Horne <shorne@gmail.com>
1027
1028 * or1k-asm.c: Regenerated.
1029 * or1k-desc.c: Regenerated.
1030 * or1k-desc.h: Regenerated.
1031 * or1k-dis.c: Regenerated.
1032 * or1k-ibld.c: Regenerated.
1033 * or1k-opc.c: Regenerated.
1034 * or1k-opc.h: Regenerated.
1035 * or1k-opinst.c: Regenerated.
1036
a0e44ef5
PB		 10372019-06-12 Peter Bergner <bergner@linux.ibm.com>
1038
1039 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1040
12efd68d
L		 10412019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1042
1043 PR binutils/24633
1044 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1045 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1046 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1047 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1048 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1049 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1050 EVEX_LEN_0F3A1B_P_2_W_1.
1051 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1052 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1053 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1054 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1055 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1056 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1057 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1058 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1059
63c6fc6c
L		 10602019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1061
1062 PR binutils/24626
1063 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1064 EVEX.vvvv when disassembling VEX and EVEX instructions.
1065 (OP_VEX): Set vex.register_specifier to 0 after readding
1066 vex.register_specifier.
1067 (OP_Vex_2src_1): Likewise.
1068 (OP_Vex_2src_2): Likewise.
1069 (OP_LWP_E): Likewise.
1070 (OP_EX_Vex): Don't check vex.register_specifier.
1071 (OP_XMM_Vex): Likewise.
1072
9186c494
L		 10732019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1074 Lili Cui <lili.cui@intel.com>
1075
1076 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1077 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1078 instructions.
1079 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1080 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1081 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1082 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1083 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1084 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1085 * i386-init.h: Regenerated.
1086 * i386-tbl.h: Likewise.
1087
5d79adc4
L		 10882019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1089 Lili Cui <lili.cui@intel.com>
1090
1091 * doc/c-i386.texi: Document enqcmd.
1092 * testsuite/gas/i386/enqcmd-intel.d: New file.
1093 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1094 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1095 * testsuite/gas/i386/enqcmd.d: Likewise.
1096 * testsuite/gas/i386/enqcmd.s: Likewise.
1097 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1098 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1099 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1100 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1101 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1102 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1103 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1104 and x86-64-enqcmd.
1105
a9d96ab9
AH		 11062019-06-04 Alan Hayward <alan.hayward@arm.com>
1107
1108 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1109
4f6d070a
AM		 11102019-06-03 Alan Modra <amodra@gmail.com>
1111
1112 * ppc-dis.c (prefix_opcd_indices): Correct size.
1113
a2f4b66c
L		 11142019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1115
1116 PR gas/24625
1117 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1118 Disp8ShiftVL.
1119 * i386-tbl.h: Regenerated.
1120
405b5bd8
AM		 11212019-05-24 Alan Modra <amodra@gmail.com>
1122
1123 * po/POTFILES.in: Regenerate.
1124
8acf1435
PB		 11252019-05-24 Peter Bergner <bergner@linux.ibm.com>
1126 Alan Modra <amodra@gmail.com>
1127
1128 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1129 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1130 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1131 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1132 XTOP>): Define and add entries.
1133 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1134 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1135 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1136 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1137
dd7efa79
PB		 11382019-05-24 Peter Bergner <bergner@linux.ibm.com>
1139 Alan Modra <amodra@gmail.com>
1140
1141 * ppc-dis.c (ppc_opts): Add "future" entry.
1142 (PREFIX_OPCD_SEGS): Define.
1143 (prefix_opcd_indices): New array.
1144 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1145 (lookup_prefix): New function.
1146 (print_insn_powerpc): Handle 64-bit prefix instructions.
1147 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1148 (PMRR, POWERXX): Define.
1149 (prefix_opcodes): New instruction table.
1150 (prefix_num_opcodes): New constant.
1151
79472b45
JM		 11522019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1153
1154 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1155 * configure: Regenerated.
1156 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1157 and cpu/bpf.opc.
1158 (HFILES): Add bpf-desc.h and bpf-opc.h.
1159 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1160 bpf-ibld.c and bpf-opc.c.
1161 (BPF_DEPS): Define.
1162 * Makefile.in: Regenerated.
1163 * disassemble.c (ARCH_bpf): Define.
1164 (disassembler): Add case for bfd_arch_bpf.
1165 (disassemble_init_for_target): Likewise.
1166 (enum epbf_isa_attr): Define.
1167 * disassemble.h: extern print_insn_bpf.
1168 * bpf-asm.c: Generated.
1169 * bpf-opc.h: Likewise.
1170 * bpf-opc.c: Likewise.
1171 * bpf-ibld.c: Likewise.
1172 * bpf-dis.c: Likewise.
1173 * bpf-desc.h: Likewise.
1174 * bpf-desc.c: Likewise.
1175
ba6cd17f
SD		 11762019-05-21 Sudakshina Das <sudi.das@arm.com>
1177
1178 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1179 and VMSR with the new operands.
1180
e39c1607
SD		 11812019-05-21 Sudakshina Das <sudi.das@arm.com>
1182
1183 * arm-dis.c (enum mve_instructions): New enum
1184 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1185 and cneg.
1186 (mve_opcodes): New instructions as above.
1187 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1188 csneg and csel.
1189 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1190
23d00a41
SD		 11912019-05-21 Sudakshina Das <sudi.das@arm.com>
1192
1193 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1194 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1195 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1196 uqshl, urshrl and urshr.
1197 (is_mve_okay_in_it): Add new instructions to TRUE list.
1198 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1199 (print_insn_mve): Updated to accept new %j,
1200 %<bitfield>m and %<bitfield>n patterns.
1201
cd4797ee
FS		 12022019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1203
1204 * mips-opc.c (mips_builtin_opcodes): Change source register
1205 constraint for DAUI.
1206
999b073b
NC		 12072019-05-20 Nick Clifton <nickc@redhat.com>
1208
1209 * po/fr.po: Updated French translation.
1210
14b456f2
AV		 12112019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1212 Michael Collison <michael.collison@arm.com>
1213
1214 * arm-dis.c (thumb32_opcodes): Add new instructions.
1215 (enum mve_instructions): Likewise.
1216 (enum mve_undefined): Add new reasons.
1217 (is_mve_encoding_conflict): Handle new instructions.
1218 (is_mve_undefined): Likewise.
1219 (is_mve_unpredictable): Likewise.
1220 (print_mve_undefined): Likewise.
1221 (print_mve_size): Likewise.
1222
f49bb598
AV		 12232019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1224 Michael Collison <michael.collison@arm.com>
1225
1226 * arm-dis.c (thumb32_opcodes): Add new instructions.
1227 (enum mve_instructions): Likewise.
1228 (is_mve_encoding_conflict): Handle new instructions.
1229 (is_mve_undefined): Likewise.
1230 (is_mve_unpredictable): Likewise.
1231 (print_mve_size): Likewise.
1232
56858bea
AV		 12332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1234 Michael Collison <michael.collison@arm.com>
1235
1236 * arm-dis.c (thumb32_opcodes): Add new instructions.
1237 (enum mve_instructions): Likewise.
1238 (is_mve_encoding_conflict): Likewise.
1239 (is_mve_unpredictable): Likewise.
1240 (print_mve_size): Likewise.
1241
e523f101
AV		 12422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1243 Michael Collison <michael.collison@arm.com>
1244
1245 * arm-dis.c (thumb32_opcodes): Add new instructions.
1246 (enum mve_instructions): Likewise.
1247 (is_mve_encoding_conflict): Handle new instructions.
1248 (is_mve_undefined): Likewise.
1249 (is_mve_unpredictable): Likewise.
1250 (print_mve_size): Likewise.
1251
66dcaa5d
AV		 12522019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1253 Michael Collison <michael.collison@arm.com>
1254
1255 * arm-dis.c (thumb32_opcodes): Add new instructions.
1256 (enum mve_instructions): Likewise.
1257 (is_mve_encoding_conflict): Handle new instructions.
1258 (is_mve_undefined): Likewise.
1259 (is_mve_unpredictable): Likewise.
1260 (print_mve_size): Likewise.
1261 (print_insn_mve): Likewise.
1262
d052b9b7
AV		 12632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1264 Michael Collison <michael.collison@arm.com>
1265
1266 * arm-dis.c (thumb32_opcodes): Add new instructions.
1267 (print_insn_thumb32): Handle new instructions.
1268
ed63aa17
AV		 12692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1270 Michael Collison <michael.collison@arm.com>
1271
1272 * arm-dis.c (enum mve_instructions): Add new instructions.
1273 (enum mve_undefined): Add new reasons.
1274 (is_mve_encoding_conflict): Handle new instructions.
1275 (is_mve_undefined): Likewise.
1276 (is_mve_unpredictable): Likewise.
1277 (print_mve_undefined): Likewise.
1278 (print_mve_size): Likewise.
1279 (print_mve_shift_n): Likewise.
1280 (print_insn_mve): Likewise.
1281
897b9bbc
AV		 12822019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1283 Michael Collison <michael.collison@arm.com>
1284
1285 * arm-dis.c (enum mve_instructions): Add new instructions.
1286 (is_mve_encoding_conflict): Handle new instructions.
1287 (is_mve_unpredictable): Likewise.
1288 (print_mve_rotate): Likewise.
1289 (print_mve_size): Likewise.
1290 (print_insn_mve): Likewise.
1291
1c8f2df8
AV		 12922019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1293 Michael Collison <michael.collison@arm.com>
1294
1295 * arm-dis.c (enum mve_instructions): Add new instructions.
1296 (is_mve_encoding_conflict): Handle new instructions.
1297 (is_mve_unpredictable): Likewise.
1298 (print_mve_size): Likewise.
1299 (print_insn_mve): Likewise.
1300
d3b63143
AV		 13012019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1302 Michael Collison <michael.collison@arm.com>
1303
1304 * arm-dis.c (enum mve_instructions): Add new instructions.
1305 (enum mve_undefined): Add new reasons.
1306 (is_mve_encoding_conflict): Handle new instructions.
1307 (is_mve_undefined): Likewise.
1308 (is_mve_unpredictable): Likewise.
1309 (print_mve_undefined): Likewise.
1310 (print_mve_size): Likewise.
1311 (print_insn_mve): Likewise.
1312
14925797
AV		 13132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1314 Michael Collison <michael.collison@arm.com>
1315
1316 * arm-dis.c (enum mve_instructions): Add new instructions.
1317 (is_mve_encoding_conflict): Handle new instructions.
1318 (is_mve_undefined): Likewise.
1319 (is_mve_unpredictable): Likewise.
1320 (print_mve_size): Likewise.
1321 (print_insn_mve): Likewise.
1322
c507f10b
AV		 13232019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1324 Michael Collison <michael.collison@arm.com>
1325
1326 * arm-dis.c (enum mve_instructions): Add new instructions.
1327 (enum mve_unpredictable): Add new reasons.
1328 (enum mve_undefined): Likewise.
1329 (is_mve_okay_in_it): Handle new isntructions.
1330 (is_mve_encoding_conflict): Likewise.
1331 (is_mve_undefined): Likewise.
1332 (is_mve_unpredictable): Likewise.
1333 (print_mve_vmov_index): Likewise.
1334 (print_simd_imm8): Likewise.
1335 (print_mve_undefined): Likewise.
1336 (print_mve_unpredictable): Likewise.
1337 (print_mve_size): Likewise.
1338 (print_insn_mve): Likewise.
1339
bf0b396d
AV		 13402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1341 Michael Collison <michael.collison@arm.com>
1342
1343 * arm-dis.c (enum mve_instructions): Add new instructions.
1344 (enum mve_unpredictable): Add new reasons.
1345 (enum mve_undefined): Likewise.
1346 (is_mve_encoding_conflict): Handle new instructions.
1347 (is_mve_undefined): Likewise.
1348 (is_mve_unpredictable): Likewise.
1349 (print_mve_undefined): Likewise.
1350 (print_mve_unpredictable): Likewise.
1351 (print_mve_rounding_mode): Likewise.
1352 (print_mve_vcvt_size): Likewise.
1353 (print_mve_size): Likewise.
1354 (print_insn_mve): Likewise.
1355
ef1576a1
AV		 13562019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1357 Michael Collison <michael.collison@arm.com>
1358
1359 * arm-dis.c (enum mve_instructions): Add new instructions.
1360 (enum mve_unpredictable): Add new reasons.
1361 (enum mve_undefined): Likewise.
1362 (is_mve_undefined): Handle new instructions.
1363 (is_mve_unpredictable): Likewise.
1364 (print_mve_undefined): Likewise.
1365 (print_mve_unpredictable): Likewise.
1366 (print_mve_size): Likewise.
1367 (print_insn_mve): Likewise.
1368
aef6d006
AV		 13692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1370 Michael Collison <michael.collison@arm.com>
1371
1372 * arm-dis.c (enum mve_instructions): Add new instructions.
1373 (enum mve_undefined): Add new reasons.
1374 (insns): Add new instructions.
1375 (is_mve_encoding_conflict):
1376 (print_mve_vld_str_addr): New print function.
1377 (is_mve_undefined): Handle new instructions.
1378 (is_mve_unpredictable): Likewise.
1379 (print_mve_undefined): Likewise.
1380 (print_mve_size): Likewise.
1381 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1382 (print_insn_mve): Handle new operands.
1383
04d54ace
AV		 13842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1385 Michael Collison <michael.collison@arm.com>
1386
1387 * arm-dis.c (enum mve_instructions): Add new instructions.
1388 (enum mve_unpredictable): Add new reasons.
1389 (is_mve_encoding_conflict): Handle new instructions.
1390 (is_mve_unpredictable): Likewise.
1391 (mve_opcodes): Add new instructions.
1392 (print_mve_unpredictable): Handle new reasons.
1393 (print_mve_register_blocks): New print function.
1394 (print_mve_size): Handle new instructions.
1395 (print_insn_mve): Likewise.
1396
9743db03
AV		 13972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1398 Michael Collison <michael.collison@arm.com>
1399
1400 * arm-dis.c (enum mve_instructions): Add new instructions.
1401 (enum mve_unpredictable): Add new reasons.
1402 (enum mve_undefined): Likewise.
1403 (is_mve_encoding_conflict): Handle new instructions.
1404 (is_mve_undefined): Likewise.
1405 (is_mve_unpredictable): Likewise.
1406 (coprocessor_opcodes): Move NEON VDUP from here...
1407 (neon_opcodes): ... to here.
1408 (mve_opcodes): Add new instructions.
1409 (print_mve_undefined): Handle new reasons.
1410 (print_mve_unpredictable): Likewise.
1411 (print_mve_size): Handle new instructions.
1412 (print_insn_neon): Handle vdup.
1413 (print_insn_mve): Handle new operands.
1414
143275ea
AV		 14152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1416 Michael Collison <michael.collison@arm.com>
1417
1418 * arm-dis.c (enum mve_instructions): Add new instructions.
1419 (enum mve_unpredictable): Add new values.
1420 (mve_opcodes): Add new instructions.
1421 (vec_condnames): New array with vector conditions.
1422 (mve_predicatenames): New array with predicate suffixes.
1423 (mve_vec_sizename): New array with vector sizes.
1424 (enum vpt_pred_state): New enum with vector predication states.
1425 (struct vpt_block): New struct type for vpt blocks.
1426 (vpt_block_state): Global struct to keep track of state.
1427 (mve_extract_pred_mask): New helper function.
1428 (num_instructions_vpt_block): Likewise.
1429 (mark_outside_vpt_block): Likewise.
1430 (mark_inside_vpt_block): Likewise.
1431 (invert_next_predicate_state): Likewise.
1432 (update_next_predicate_state): Likewise.
1433 (update_vpt_block_state): Likewise.
1434 (is_vpt_instruction): Likewise.
1435 (is_mve_encoding_conflict): Add entries for new instructions.
1436 (is_mve_unpredictable): Likewise.
1437 (print_mve_unpredictable): Handle new cases.
1438 (print_instruction_predicate): Likewise.
1439 (print_mve_size): New function.
1440 (print_vec_condition): New function.
1441 (print_insn_mve): Handle vpt blocks and new print operands.
1442
f08d8ce3
AV		 14432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1444
1445 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1446 8, 14 and 15 for Armv8.1-M Mainline.
1447
73cd51e5
AV		 14482019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1449 Michael Collison <michael.collison@arm.com>
1450
1451 * arm-dis.c (enum mve_instructions): New enum.
1452 (enum mve_unpredictable): Likewise.
1453 (enum mve_undefined): Likewise.
1454 (struct mopcode32): New struct.
1455 (is_mve_okay_in_it): New function.
1456 (is_mve_architecture): Likewise.
1457 (arm_decode_field): Likewise.
1458 (arm_decode_field_multiple): Likewise.
1459 (is_mve_encoding_conflict): Likewise.
1460 (is_mve_undefined): Likewise.
1461 (is_mve_unpredictable): Likewise.
1462 (print_mve_undefined): Likewise.
1463 (print_mve_unpredictable): Likewise.
1464 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1465 (print_insn_mve): New function.
1466 (print_insn_thumb32): Handle MVE architecture.
1467 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1468
3076e594
NC		 14692019-05-10 Nick Clifton <nickc@redhat.com>
1470
1471 PR 24538
1472 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1473 end of the table prematurely.
1474
387e7624
FS		 14752019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1476
1477 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1478 macros for R6.
1479
0067be51
AM		 14802019-05-11 Alan Modra <amodra@gmail.com>
1481
1482 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1483 when -Mraw is in effect.
1484
42e6288f
MM		 14852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1486
1487 * aarch64-dis-2.c: Regenerate.
1488 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1489 (OP_SVE_BBB): New variant set.
1490 (OP_SVE_DDDD): New variant set.
1491 (OP_SVE_HHH): New variant set.
1492 (OP_SVE_HHHU): New variant set.
1493 (OP_SVE_SSS): New variant set.
1494 (OP_SVE_SSSU): New variant set.
1495 (OP_SVE_SHH): New variant set.
1496 (OP_SVE_SBBU): New variant set.
1497 (OP_SVE_DSS): New variant set.
1498 (OP_SVE_DHHU): New variant set.
1499 (OP_SVE_VMV_HSD_BHS): New variant set.
1500 (OP_SVE_VVU_HSD_BHS): New variant set.
1501 (OP_SVE_VVVU_SD_BH): New variant set.
1502 (OP_SVE_VVVU_BHSD): New variant set.
1503 (OP_SVE_VVV_QHD_DBS): New variant set.
1504 (OP_SVE_VVV_HSD_BHS): New variant set.
1505 (OP_SVE_VVV_HSD_BHS2): New variant set.
1506 (OP_SVE_VVV_BHS_HSD): New variant set.
1507 (OP_SVE_VV_BHS_HSD): New variant set.
1508 (OP_SVE_VVV_SD): New variant set.
1509 (OP_SVE_VVU_BHS_HSD): New variant set.
1510 (OP_SVE_VZVV_SD): New variant set.
1511 (OP_SVE_VZVV_BH): New variant set.
1512 (OP_SVE_VZV_SD): New variant set.
1513 (aarch64_opcode_table): Add sve2 instructions.
1514
28ed815a
MM		 15152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1516
1517 * aarch64-asm-2.c: Regenerated.
1518 * aarch64-dis-2.c: Regenerated.
1519 * aarch64-opc-2.c: Regenerated.
1520 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1521 for SVE_SHLIMM_UNPRED_22.
1522 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1523 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1524 operand.
1525
fd1dc4a0
MM		 15262019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1527
1528 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1529 sve_size_tsz_bhs iclass encode.
1530 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1531 sve_size_tsz_bhs iclass decode.
1532
31e36ab3
MM		 15332019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1534
1535 * aarch64-asm-2.c: Regenerated.
1536 * aarch64-dis-2.c: Regenerated.
1537 * aarch64-opc-2.c: Regenerated.
1538 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1539 for SVE_Zm4_11_INDEX.
1540 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1541 (fields): Handle SVE_i2h field.
1542 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1543 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1544
1be5f94f
MM		 15452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1546
1547 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1548 sve_shift_tsz_bhsd iclass encode.
1549 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1550 sve_shift_tsz_bhsd iclass decode.
1551
3c17238b
MM		 15522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1553
1554 * aarch64-asm-2.c: Regenerated.
1555 * aarch64-dis-2.c: Regenerated.
1556 * aarch64-opc-2.c: Regenerated.
1557 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1558 (aarch64_encode_variant_using_iclass): Handle
1559 sve_shift_tsz_hsd iclass encode.
1560 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1561 sve_shift_tsz_hsd iclass decode.
1562 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1563 for SVE_SHRIMM_UNPRED_22.
1564 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1565 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1566 operand.
1567
cd50a87a
MM		 15682019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1569
1570 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1571 sve_size_013 iclass encode.
1572 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1573 sve_size_013 iclass decode.
1574
3c705960
MM		 15752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1576
1577 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1578 sve_size_bh iclass encode.
1579 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1580 sve_size_bh iclass decode.
1581
0a57e14f
MM		 15822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1583
1584 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1585 sve_size_sd2 iclass encode.
1586 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1587 sve_size_sd2 iclass decode.
1588 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1589 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1590
c469c864
MM		 15912019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1592
1593 * aarch64-asm-2.c: Regenerated.
1594 * aarch64-dis-2.c: Regenerated.
1595 * aarch64-opc-2.c: Regenerated.
1596 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1597 for SVE_ADDR_ZX.
1598 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1599 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1600
116adc27
MM		 16012019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1602
1603 * aarch64-asm-2.c: Regenerated.
1604 * aarch64-dis-2.c: Regenerated.
1605 * aarch64-opc-2.c: Regenerated.
1606 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1607 for SVE_Zm3_11_INDEX.
1608 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1609 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1610 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1611 fields.
1612 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1613
3bd82c86
MM		 16142019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1615
1616 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1617 sve_size_hsd2 iclass encode.
1618 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1619 sve_size_hsd2 iclass decode.
1620 * aarch64-opc.c (fields): Handle SVE_size field.
1621 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1622
adccc507
MM		 16232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1624
1625 * aarch64-asm-2.c: Regenerated.
1626 * aarch64-dis-2.c: Regenerated.
1627 * aarch64-opc-2.c: Regenerated.
1628 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1629 for SVE_IMM_ROT3.
1630 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1631 (fields): Handle SVE_rot3 field.
1632 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1633 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1634
5cd99750
MM		 16352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1636
1637 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1638 instructions.
1639
7ce2460a
MM		 16402019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1641
1642 * aarch64-tbl.h
1643 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1644 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1645 aarch64_feature_sve2bitperm): New feature sets.
1646 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1647 for feature set addresses.
1648 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1649 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1650
41cee089
FS		 16512019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1652 Faraz Shahbazker <fshahbazker@wavecomp.com>
1653
1654 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1655 argument and set ASE_EVA_R6 appropriately.
1656 (set_default_mips_dis_options): Pass ISA to above.
1657 (parse_mips_dis_option): Likewise.
1658 * mips-opc.c (EVAR6): New macro.
1659 (mips_builtin_opcodes): Add llwpe, scwpe.
1660
b83b4b13
SD		 16612019-05-01 Sudakshina Das <sudi.das@arm.com>
1662
1663 * aarch64-asm-2.c: Regenerated.
1664 * aarch64-dis-2.c: Regenerated.
1665 * aarch64-opc-2.c: Regenerated.
1666 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1667 AARCH64_OPND_TME_UIMM16.
1668 (aarch64_print_operand): Likewise.
1669 * aarch64-tbl.h (QL_IMM_NIL): New.
1670 (TME): New.
1671 (_TME_INSN): New.
1672 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1673
4a90ce95
JD		 16742019-04-29 John Darrington <john@darrington.wattle.id.au>
1675
1676 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1677
a45328b9
AB		 16782019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1679 Faraz Shahbazker <fshahbazker@wavecomp.com>
1680
1681 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1682
d10be0cb
JD		 16832019-04-24 John Darrington <john@darrington.wattle.id.au>
1684
1685 * s12z-opc.h: Add extern "C" bracketing to help
1686 users who wish to use this interface in c++ code.
1687
a679f24e
JD		 16882019-04-24 John Darrington <john@darrington.wattle.id.au>
1689
1690 * s12z-opc.c (bm_decode): Handle bit map operations with the
1691 "reserved0" mode.
1692
32c36c3c
AV		 16932019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1694
1695 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1696 specifier. Add entries for VLDR and VSTR of system registers.
1697 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1698 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1699 of %J and %K format specifier.
1700
efd6b359
AV		 17012019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1702
1703 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1704 Add new entries for VSCCLRM instruction.
1705 (print_insn_coprocessor): Handle new %C format control code.
1706
6b0dd094
AV		 17072019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1708
1709 * arm-dis.c (enum isa): New enum.
1710 (struct sopcode32): New structure.
1711 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1712 set isa field of all current entries to ANY.
1713 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1714 Only match an entry if its isa field allows the current mode.
1715
4b5a202f
AV		 17162019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1717
1718 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1719 CLRM.
1720 (print_insn_thumb32): Add logic to print %n CLRM register list.
1721
60f993ce
AV		 17222019-04-15 Sudakshina Das <sudi.das@arm.com>
1723
1724 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1725 and %Q patterns.
1726
f6b2b12d
AV		 17272019-04-15 Sudakshina Das <sudi.das@arm.com>
1728
1729 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1730 (print_insn_thumb32): Edit the switch case for %Z.
1731
1889da70
AV		 17322019-04-15 Sudakshina Das <sudi.das@arm.com>
1733
1734 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1735
65d1bc05
AV		 17362019-04-15 Sudakshina Das <sudi.das@arm.com>
1737
1738 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1739
1caf72a5
AV		 17402019-04-15 Sudakshina Das <sudi.das@arm.com>
1741
1742 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1743
f1c7f421
AV		 17442019-04-15 Sudakshina Das <sudi.das@arm.com>
1745
1746 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1747 Arm register with r13 and r15 unpredictable.
1748 (thumb32_opcodes): New instructions for bfx and bflx.
1749
4389b29a
AV		 17502019-04-15 Sudakshina Das <sudi.das@arm.com>
1751
1752 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1753
e5d6e09e
AV		 17542019-04-15 Sudakshina Das <sudi.das@arm.com>
1755
1756 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1757
e12437dc
AV		 17582019-04-15 Sudakshina Das <sudi.das@arm.com>
1759
1760 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1761
031254f2
AV		 17622019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1763
1764 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1765
e5a557ac
JD		 17662019-04-12 John Darrington <john@darrington.wattle.id.au>
1767
1768 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1769 "optr". ("operator" is a reserved word in c++).
1770
bd7ceb8d
SD		 17712019-04-11 Sudakshina Das <sudi.das@arm.com>
1772
1773 * aarch64-opc.c (aarch64_print_operand): Add case for
1774 AARCH64_OPND_Rt_SP.
1775 (verify_constraints): Likewise.
1776 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1777 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1778 to accept Rt|SP as first operand.
1779 (AARCH64_OPERANDS): Add new Rt_SP.
1780 * aarch64-asm-2.c: Regenerated.
1781 * aarch64-dis-2.c: Regenerated.
1782 * aarch64-opc-2.c: Regenerated.
1783
e54010f1
SD		 17842019-04-11 Sudakshina Das <sudi.das@arm.com>
1785
1786 * aarch64-asm-2.c: Regenerated.
1787 * aarch64-dis-2.c: Likewise.
1788 * aarch64-opc-2.c: Likewise.
1789 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1790
7e96e219
RS		 17912019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1792
1793 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1794
6f2791d5
L		 17952019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1796
1797 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1798 * i386-init.h: Regenerated.
1799
e392bad3
AM		 18002019-04-07 Alan Modra <amodra@gmail.com>
1801
1802 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1803 op_separator to control printing of spaces, comma and parens
1804 rather than need_comma, need_paren and spaces vars.
1805
dffaa15c
AM		 18062019-04-07 Alan Modra <amodra@gmail.com>
1807
1808 PR 24421
1809 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1810 (print_insn_neon, print_insn_arm): Likewise.
1811
d6aab7a1
XG		 18122019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1813
1814 * i386-dis-evex.h (evex_table): Updated to support BF16
1815 instructions.
1816 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1817 and EVEX_W_0F3872_P_3.
1818 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1819 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1820 * i386-opc.h (enum): Add CpuAVX512_BF16.
1821 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1822 * i386-opc.tbl: Add AVX512 BF16 instructions.
1823 * i386-init.h: Regenerated.
1824 * i386-tbl.h: Likewise.
1825
66e85460
AM		 18262019-04-05 Alan Modra <amodra@gmail.com>
1827
1828 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1829 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1830 to favour printing of "-" branch hint when using the "y" bit.
1831 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1832
c2b1c275
AM		 18332019-04-05 Alan Modra <amodra@gmail.com>
1834
1835 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1836 opcode until first operand is output.
1837
aae9718e
PB		 18382019-04-04 Peter Bergner <bergner@linux.ibm.com>
1839
1840 PR gas/24349
1841 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1842 (valid_bo_post_v2): Add support for 'at' branch hints.
1843 (insert_bo): Only error on branch on ctr.
1844 (get_bo_hint_mask): New function.
1845 (insert_boe): Add new 'branch_taken' formal argument. Add support
1846 for inserting 'at' branch hints.
1847 (extract_boe): Add new 'branch_taken' formal argument. Add support
1848 for extracting 'at' branch hints.
1849 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1850 (BOE): Delete operand.
1851 (BOM, BOP): New operands.
1852 (RM): Update value.
1853 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1854 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1855 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1856 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1857 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1858 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1859 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1860 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1861 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1862 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1863 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1864 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1865 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1866 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1867 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1868 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1869 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1870 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1871 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1872 bttarl+>: New extended mnemonics.
1873
96a86c01
AM		 18742019-03-28 Alan Modra <amodra@gmail.com>
1875
1876 PR 24390
1877 * ppc-opc.c (BTF): Define.
1878 (powerpc_opcodes): Use for mtfsb*.
1879 * ppc-dis.c (print_insn_powerpc): Print fields with both
1880 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1881
796d6298
TC		 18822019-03-25 Tamar Christina <tamar.christina@arm.com>
1883
1884 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1885 (mapping_symbol_for_insn): Implement new algorithm.
1886 (print_insn): Remove duplicate code.
1887
60df3720
TC		 18882019-03-25 Tamar Christina <tamar.christina@arm.com>
1889
1890 * aarch64-dis.c (print_insn_aarch64):
1891 Implement override.
1892
51457761
TC		 18932019-03-25 Tamar Christina <tamar.christina@arm.com>
1894
1895 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1896 order.
1897
53b2f36b
TC		 18982019-03-25 Tamar Christina <tamar.christina@arm.com>
1899
1900 * aarch64-dis.c (last_stop_offset): New.
1901 (print_insn_aarch64): Use stop_offset.
1902
89199bb5
L		 19032019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1904
1905 PR gas/24359
1906 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1907 CPU_ANY_AVX2_FLAGS.
1908 * i386-init.h: Regenerated.
1909
97ed31ae
L		 19102019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1911
1912 PR gas/24348
1913 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1914 vmovdqu16, vmovdqu32 and vmovdqu64.
1915 * i386-tbl.h: Regenerated.
1916
0919bfe9
AK		 19172019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1918
1919 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1920 from vstrszb, vstrszh, and vstrszf.
1921
19222019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1923
1924 * s390-opc.txt: Add instruction descriptions.
1925
21820ebe
JW		 19262019-02-08 Jim Wilson <jimw@sifive.com>
1927
1928 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1929 <bne>: Likewise.
1930
f7dd2fb2
TC		 19312019-02-07 Tamar Christina <tamar.christina@arm.com>
1932
1933 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1934
6456d318
TC		 19352019-02-07 Tamar Christina <tamar.christina@arm.com>
1936
1937 PR binutils/23212
1938 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1939 * aarch64-opc.c (verify_elem_sd): New.
1940 (fields): Add FLD_sz entr.
1941 * aarch64-tbl.h (_SIMD_INSN): New.
1942 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1943 fmulx scalar and vector by element isns.
1944
4a83b610
NC		 19452019-02-07 Nick Clifton <nickc@redhat.com>
1946
1947 * po/sv.po: Updated Swedish translation.
1948
fc60b8c8
AK		 19492019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1950
1951 * s390-mkopc.c (main): Accept arch13 as cpu string.
1952 * s390-opc.c: Add new instruction formats and instruction opcode
1953 masks.
1954 * s390-opc.txt: Add new arch13 instructions.
1955
e10620d3
TC		 19562019-01-25 Sudakshina Das <sudi.das@arm.com>
1957
1958 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1959 (aarch64_opcode): Change encoding for stg, stzg
1960 st2g and st2zg.
1961 * aarch64-asm-2.c: Regenerated.
1962 * aarch64-dis-2.c: Regenerated.
1963 * aarch64-opc-2.c: Regenerated.
1964
20a4ca55
SD		 19652019-01-25 Sudakshina Das <sudi.das@arm.com>
1966
1967 * aarch64-asm-2.c: Regenerated.
1968 * aarch64-dis-2.c: Likewise.
1969 * aarch64-opc-2.c: Likewise.
1970 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1971
550fd7bf
SD		 19722019-01-25 Sudakshina Das <sudi.das@arm.com>
1973 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1974
1975 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1976 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1977 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1978 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1979 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1980 case for ldstgv_indexed.
1981 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1982 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1983 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1984 * aarch64-asm-2.c: Regenerated.
1985 * aarch64-dis-2.c: Regenerated.
1986 * aarch64-opc-2.c: Regenerated.
1987
d9938630
NC		 19882019-01-23 Nick Clifton <nickc@redhat.com>
1989
1990 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1991
375cd423
NC		 19922019-01-21 Nick Clifton <nickc@redhat.com>
1993
1994 * po/de.po: Updated German translation.
1995 * po/uk.po: Updated Ukranian translation.
1996
57299f48
CX		 19972019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1998 * mips-dis.c (mips_arch_choices): Fix typo in
1999 gs464, gs464e and gs264e descriptors.
2000
f48dfe41
NC		 20012019-01-19 Nick Clifton <nickc@redhat.com>
2002
2003 * configure: Regenerate.
2004 * po/opcodes.pot: Regenerate.
2005
f974f26c
NC		 20062018-06-24 Nick Clifton <nickc@redhat.com>
2007
2008 2.32 branch created.
2009
39f286cd
JD		 20102019-01-09 John Darrington <john@darrington.wattle.id.au>
2011
448b8ca8
JD		 2012 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2013 if it is null.
2014 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2015 zero.
2016
3107326d
AP		 20172019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2018
2019 * configure: Regenerate.
2020
7e9ca91e
AM		 20212019-01-07 Alan Modra <amodra@gmail.com>
2022
2023 * configure: Regenerate.
2024 * po/POTFILES.in: Regenerate.
2025
ef1ad42b
JD		 20262019-01-03 John Darrington <john@darrington.wattle.id.au>
2027
2028 * s12z-opc.c: New file.
2029 * s12z-opc.h: New file.
2030 * s12z-dis.c: Removed all code not directly related to display
2031 of instructions. Used the interface provided by the new files
2032 instead.
2033 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2034 * Makefile.in: Regenerate.
ef1ad42b 2035 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2036 * configure: Regenerate.
ef1ad42b 2037
82704155
AM		 20382019-01-01 Alan Modra <amodra@gmail.com>
2039
2040 Update year range in copyright notice of all files.
2041
d5c04e1b 2042For older changes see ChangeLog-2018
3499769a 2043\f
d5c04e1b 2044Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2045
2046Copying and distribution of this file, with or without modification,
2047are permitted in any medium without royalty provided the copyright
2048notice and this notice are preserved.
2049
2050Local Variables:
2051mode: change-log
2052left-margin: 8
2053fill-column: 74
2054version-control: never
2055End:
GDB Binutils - Deliverables
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