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[ARM] Update bfd's Tag_CPU_arch knowledge
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
c0c468d5
TP		 12018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
2
3 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
4 expected result.
5 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
6 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
7 * testsuite/ld-arm/tls-longplt.d: Likewise.
8
369c9167
TC		 92018-06-29 Tamar Christina <tamar.christina@arm.com>
10
11 PR binutils/23192
12 * aarch64-asm-2.c: Regenerate.
13 * aarch64-dis-2.c: Likewise.
14 * aarch64-opc-2.c: Likewise.
15 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
16 * aarch64-opc.c (operand_general_constraint_met_p,
17 aarch64_print_operand): Likewise.
18 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
19 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
20 fmlal2, fmlsl2.
21 (AARCH64_OPERANDS): Add Em2.
22
30aa1306
NC		 232018-06-26 Nick Clifton <nickc@redhat.com>
24
25 * po/uk.po: Updated Ukranian translation.
26 * po/de.po: Updated German translation.
27 * po/pt_BR.po: Updated Brazilian Portuguese translation.
28
eca4b721
NC		 292018-06-26 Nick Clifton <nickc@redhat.com>
30
31 * nfp-dis.c: Fix spelling mistake.
32
71300e2c
NC		 332018-06-24 Nick Clifton <nickc@redhat.com>
34
35 * configure: Regenerate.
36 * po/opcodes.pot: Regenerate.
37
719d8288
NC		 382018-06-24 Nick Clifton <nickc@redhat.com>
39
40 2.31 branch created.
41
514cd3a0
TC		 422018-06-19 Tamar Christina <tamar.christina@arm.com>
43
44 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
45 * aarch64-asm-2.c: Regenerate.
46 * aarch64-dis-2.c: Likewise.
47
385e4d0f
MR		 482018-06-21 Maciej W. Rozycki <macro@mips.com>
49
50 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
51 `-M ginv' option description.
52
160d1b3d
SH		 532018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
54
55 PR gas/23305
56 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
57 la and lla.
58
d0ac1c44
SM		 592018-06-19 Simon Marchi <simon.marchi@ericsson.com>
60
61 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
62 * configure.ac: Remove AC_PREREQ.
63 * Makefile.in: Re-generate.
64 * aclocal.m4: Re-generate.
65 * configure: Re-generate.
66
6f20c942
FS		 672018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
68
69 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
70 mips64r6 descriptors.
71 (parse_mips_ase_option): Handle -Mginv option.
72 (print_mips_disassembler_options): Document -Mginv.
73 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
74 (GINV): New macro.
75 (mips_opcodes): Define ginvi and ginvt.
76
730c3174
SE		 772018-06-13 Scott Egerton <scott.egerton@imgtec.com>
78 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
79
80 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
81 * mips-opc.c (CRC, CRC64): New macros.
82 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
83 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
84 crc32cd for CRC64.
85
cb366992
EB		 862018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
87
88 PR 20319
89 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
90 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
91
ce72cd46
AM		 922018-06-06 Alan Modra <amodra@gmail.com>
93
94 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
95 setjmp. Move init for some other vars later too.
96
4b8e28c7
MF		 972018-06-04 Max Filippov <jcmvbkbc@gmail.com>
98
99 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
100 (dis_private): Add new fields for property section tracking.
101 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
102 (xtensa_instruction_fits): New functions.
103 (fetch_data): Bump minimal fetch size to 4.
104 (print_insn_xtensa): Make struct dis_private static.
105 Load and prepare property table on section change.
106 Don't disassemble literals. Don't disassemble instructions that
107 cross property table boundaries.
108
55e99962
L		 1092018-06-01 H.J. Lu <hongjiu.lu@intel.com>
110
111 * configure: Regenerated.
112
733bd0ab
JB		 1132018-06-01 Jan Beulich <jbeulich@suse.com>
114
115 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
116 * i386-tbl.h: Re-generate.
117
dfd27d41
JB		 1182018-06-01 Jan Beulich <jbeulich@suse.com>
119
120 * i386-opc.tbl (sldt, str): Add NoRex64.
121 * i386-tbl.h: Re-generate.
122
64795710
JB		 1232018-06-01 Jan Beulich <jbeulich@suse.com>
124
125 * i386-opc.tbl (invpcid): Add Oword.
126 * i386-tbl.h: Re-generate.
127
030157d8
AM		 1282018-06-01 Alan Modra <amodra@gmail.com>
129
130 * sysdep.h (_bfd_error_handler): Don't declare.
131 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
132 * rl78-decode.opc: Likewise.
133 * msp430-decode.c: Regenerate.
134 * rl78-decode.c: Regenerate.
135
a9660a6f
AP		 1362018-05-30 Amit Pawar <Amit.Pawar@amd.com>
137
138 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
139 * i386-init.h : Regenerated.
140
277eb7f6
AM		 1412018-05-25 Alan Modra <amodra@gmail.com>
142
143 * Makefile.in: Regenerate.
144 * po/POTFILES.in: Regenerate.
145
98553ad3
PB		 1462018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
147
148 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
149 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
150 (insert_bab, extract_bab, insert_btab, extract_btab,
151 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
152 (BAT, BBA VBA RBS XB6S): Delete macros.
153 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
154 (BB, BD, RBX, XC6): Update for new macros.
155 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
156 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
157 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
158 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
159
7b4ae824
JD		 1602018-05-18 John Darrington <john@darrington.wattle.id.au>
161
162 * Makefile.am: Add support for s12z architecture.
163 * configure.ac: Likewise.
164 * disassemble.c: Likewise.
165 * disassemble.h: Likewise.
166 * Makefile.in: Regenerate.
167 * configure: Regenerate.
168 * s12z-dis.c: New file.
169 * s12z.h: New file.
170
29e0f0a1
AM		 1712018-05-18 Alan Modra <amodra@gmail.com>
172
173 * nfp-dis.c: Don't #include libbfd.h.
174 (init_nfp3200_priv): Use bfd_get_section_contents.
175 (nit_nfp6000_mecsr_sec): Likewise.
176
809276d2
NC		 1772018-05-17 Nick Clifton <nickc@redhat.com>
178
179 * po/zh_CN.po: Updated simplified Chinese translation.
180
ff329288
TC		 1812018-05-16 Tamar Christina <tamar.christina@arm.com>
182
183 PR binutils/23109
184 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
185 * aarch64-dis-2.c: Regenerate.
186
f9830ec1
TC		 1872018-05-15 Tamar Christina <tamar.christina@arm.com>
188
189 PR binutils/21446
190 * aarch64-asm.c (opintl.h): Include.
191 (aarch64_ins_sysreg): Enforce read/write constraints.
192 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
193 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
194 (F_REG_READ, F_REG_WRITE): New.
195 * aarch64-opc.c (aarch64_print_operand): Generate notes for
196 AARCH64_OPND_SYSREG.
197 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
198 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
199 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
200 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
201 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
202 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
203 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
204 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
205 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
206 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
207 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
208 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
209 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
210 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
211 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
212 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
213 msr (F_SYS_WRITE), mrs (F_SYS_READ).
214
7d02540a
TC		 2152018-05-15 Tamar Christina <tamar.christina@arm.com>
216
217 PR binutils/21446
218 * aarch64-dis.c (no_notes: New.
219 (parse_aarch64_dis_option): Support notes.
220 (aarch64_decode_insn, print_operands): Likewise.
221 (print_aarch64_disassembler_options): Document notes.
222 * aarch64-opc.c (aarch64_print_operand): Support notes.
223
561a72d4
TC		 2242018-05-15 Tamar Christina <tamar.christina@arm.com>
225
226 PR binutils/21446
227 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
228 and take error struct.
229 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
230 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
231 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
232 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
233 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
234 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
235 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
236 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
237 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
238 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
239 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
240 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
241 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
242 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
243 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
244 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
245 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
246 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
247 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
248 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
249 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
250 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
251 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
252 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
253 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
254 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
255 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
256 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
257 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
258 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
259 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
260 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
261 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
262 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
263 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
264 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
265 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
266 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
267 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
268 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
269 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
270 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
271 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
272 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
273 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
274 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
275 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
276 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
277 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
278 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
279 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
280 (determine_disassembling_preference, aarch64_decode_insn,
281 print_insn_aarch64_word, print_insn_data): Take errors struct.
282 (print_insn_aarch64): Use errors.
283 * aarch64-asm-2.c: Regenerate.
284 * aarch64-dis-2.c: Regenerate.
285 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
286 boolean in aarch64_insert_operan.
287 (print_operand_extractor): Likewise.
288 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
289
1678bd35
FT		 2902018-05-15 Francois H. Theron <francois.theron@netronome.com>
291
292 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
293
06cfb1c8
L		 2942018-05-09 H.J. Lu <hongjiu.lu@intel.com>
295
296 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
297
84f9f8c3
AM		 2982018-05-09 Sebastian Rasmussen <sebras@gmail.com>
299
300 * cr16-opc.c (cr16_instruction): Comment typo fix.
301 * hppa-dis.c (print_insn_hppa): Likewise.
302
e6f372ba
JW		 3032018-05-08 Jim Wilson <jimw@sifive.com>
304
305 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
306 (match_c_slli64, match_srxi_as_c_srxi): New.
307 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
308 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
309 <c.slli, c.srli, c.srai>: Use match_s_slli.
310 <c.slli64, c.srli64, c.srai64>: New.
311
f413a913
AM		 3122018-05-08 Alan Modra <amodra@gmail.com>
313
314 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
315 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
316 partition opcode space for index lookup.
317
a87a6478
PB		 3182018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
319
320 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
321 <insn_length>: ...with this. Update usage.
322 Remove duplicate call to *info->memory_error_func.
323
c0a30a9f
L		 3242018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
325 H.J. Lu <hongjiu.lu@intel.com>
326
327 * i386-dis.c (Gva): New.
328 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
329 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
330 (prefix_table): New instructions (see prefix above).
331 (mod_table): New instructions (see prefix above).
332 (OP_G): Handle va_mode.
333 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
334 CPU_MOVDIR64B_FLAGS.
335 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
336 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
337 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
338 * i386-opc.tbl: Add movidir{i,64b}.
339 * i386-init.h: Regenerated.
340 * i386-tbl.h: Likewise.
341
75c0a438
L		 3422018-05-07 H.J. Lu <hongjiu.lu@intel.com>
343
344 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
345 AddrPrefixOpReg.
346 * i386-opc.h (AddrPrefixOp0): Renamed to ...
347 (AddrPrefixOpReg): This.
348 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
349 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
350
2ceb7719
PB		 3512018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
352
353 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
354 (vle_num_opcodes): Likewise.
355 (spe2_num_opcodes): Likewise.
356 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
357 initialization loop.
358 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
359 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
360 only once.
361
b3ac5c6c
TC		 3622018-05-01 Tamar Christina <tamar.christina@arm.com>
363
364 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
365
fe944acf
FT		 3662018-04-30 Francois H. Theron <francois.theron@netronome.com>
367
368 Makefile.am: Added nfp-dis.c.
369 configure.ac: Added bfd_nfp_arch.
370 disassemble.h: Added print_insn_nfp prototype.
371 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
372 nfp-dis.c: New, for NFP support.
373 po/POTFILES.in: Added nfp-dis.c to the list.
374 Makefile.in: Regenerate.
375 configure: Regenerate.
376
e2195274
JB		 3772018-04-26 Jan Beulich <jbeulich@suse.com>
378
379 * i386-opc.tbl: Fold various non-memory operand AVX512VL
380 templates into their base ones.
381 * i386-tlb.h: Re-generate.
382
59ef5df4
JB		 3832018-04-26 Jan Beulich <jbeulich@suse.com>
384
385 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
386 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
387 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
388 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
389 * i386-init.h: Re-generate.
390
6e041cf4
JB		 3912018-04-26 Jan Beulich <jbeulich@suse.com>
392
393 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
394 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
395 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
396 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
397 comment.
398 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
399 and CpuRegMask.
400 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
401 CpuRegMask: Delete.
402 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
403 cpuregzmm, and cpuregmask.
404 * i386-init.h: Re-generate.
405 * i386-tbl.h: Re-generate.
406
0e0eea78
JB		 4072018-04-26 Jan Beulich <jbeulich@suse.com>
408
409 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
410 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
411 * i386-init.h: Re-generate.
412
2f1bada2
JB		 4132018-04-26 Jan Beulich <jbeulich@suse.com>
414
415 * i386-gen.c (VexImmExt): Delete.
416 * i386-opc.h (VexImmExt, veximmext): Delete.
417 * i386-opc.tbl: Drop all VexImmExt uses.
418 * i386-tlb.h: Re-generate.
419
bacd1457
JB		 4202018-04-25 Jan Beulich <jbeulich@suse.com>
421
422 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
423 register-only forms.
424 * i386-tlb.h: Re-generate.
425
10bba94b
TC		 4262018-04-25 Tamar Christina <tamar.christina@arm.com>
427
428 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
429
c48935d7
IT		 4302018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
431
432 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
433 PREFIX_0F1C.
434 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
435 (cpu_flags): Add CpuCLDEMOTE.
436 * i386-init.h: Regenerate.
437 * i386-opc.h (enum): Add CpuCLDEMOTE,
438 (i386_cpu_flags): Add cpucldemote.
439 * i386-opc.tbl: Add cldemote.
440 * i386-tbl.h: Regenerate.
441
211dc24b
AM		 4422018-04-16 Alan Modra <amodra@gmail.com>
443
444 * Makefile.am: Remove sh5 and sh64 support.
445 * configure.ac: Likewise.
446 * disassemble.c: Likewise.
447 * disassemble.h: Likewise.
448 * sh-dis.c: Likewise.
449 * sh64-dis.c: Delete.
450 * sh64-opc.c: Delete.
451 * sh64-opc.h: Delete.
452 * Makefile.in: Regenerate.
453 * configure: Regenerate.
454 * po/POTFILES.in: Regenerate.
455
a9a4b302
AM		 4562018-04-16 Alan Modra <amodra@gmail.com>
457
458 * Makefile.am: Remove w65 support.
459 * configure.ac: Likewise.
460 * disassemble.c: Likewise.
461 * disassemble.h: Likewise.
462 * w65-dis.c: Delete.
463 * w65-opc.h: Delete.
464 * Makefile.in: Regenerate.
465 * configure: Regenerate.
466 * po/POTFILES.in: Regenerate.
467
04cb01fd
AM		 4682018-04-16 Alan Modra <amodra@gmail.com>
469
470 * configure.ac: Remove we32k support.
471 * configure: Regenerate.
472
c2bf1eec
AM		 4732018-04-16 Alan Modra <amodra@gmail.com>
474
475 * Makefile.am: Remove m88k support.
476 * configure.ac: Likewise.
477 * disassemble.c: Likewise.
478 * disassemble.h: Likewise.
479 * m88k-dis.c: Delete.
480 * Makefile.in: Regenerate.
481 * configure: Regenerate.
482 * po/POTFILES.in: Regenerate.
483
6793974d
AM		 4842018-04-16 Alan Modra <amodra@gmail.com>
485
486 * Makefile.am: Remove i370 support.
487 * configure.ac: Likewise.
488 * disassemble.c: Likewise.
489 * disassemble.h: Likewise.
490 * i370-dis.c: Delete.
491 * i370-opc.c: Delete.
492 * Makefile.in: Regenerate.
493 * configure: Regenerate.
494 * po/POTFILES.in: Regenerate.
495
e82aa794
AM		 4962018-04-16 Alan Modra <amodra@gmail.com>
497
498 * Makefile.am: Remove h8500 support.
499 * configure.ac: Likewise.
500 * disassemble.c: Likewise.
501 * disassemble.h: Likewise.
502 * h8500-dis.c: Delete.
503 * h8500-opc.h: Delete.
504 * Makefile.in: Regenerate.
505 * configure: Regenerate.
506 * po/POTFILES.in: Regenerate.
507
fceadf09
AM		 5082018-04-16 Alan Modra <amodra@gmail.com>
509
510 * configure.ac: Remove tahoe support.
511 * configure: Regenerate.
512
ae1d3843
L		 5132018-04-15 H.J. Lu <hongjiu.lu@intel.com>
514
515 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
516 umwait.
517 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
518 64-bit mode.
519 * i386-tbl.h: Regenerated.
520
de89d0a3
IT		 5212018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
522
523 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
524 PREFIX_MOD_1_0FAE_REG_6.
525 (va_mode): New.
526 (OP_E_register): Use va_mode.
527 * i386-dis-evex.h (prefix_table):
528 New instructions (see prefixes above).
529 * i386-gen.c (cpu_flag_init): Add WAITPKG.
530 (cpu_flags): Likewise.
531 * i386-opc.h (enum): Likewise.
532 (i386_cpu_flags): Likewise.
533 * i386-opc.tbl: Add umonitor, umwait, tpause.
534 * i386-init.h: Regenerate.
535 * i386-tbl.h: Likewise.
536
a8eb42a8
AM		 5372018-04-11 Alan Modra <amodra@gmail.com>
538
539 * opcodes/i860-dis.c: Delete.
540 * opcodes/i960-dis.c: Delete.
541 * Makefile.am: Remove i860 and i960 support.
542 * configure.ac: Likewise.
543 * disassemble.c: Likewise.
544 * disassemble.h: Likewise.
545 * Makefile.in: Regenerate.
546 * configure: Regenerate.
547 * po/POTFILES.in: Regenerate.
548
caf0678c
L		 5492018-04-04 H.J. Lu <hongjiu.lu@intel.com>
550
551 PR binutils/23025
552 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
553 to 0.
554 (print_insn): Clear vex instead of vex.evex.
555
4fb0d2b9
NC		 5562018-04-04 Nick Clifton <nickc@redhat.com>
557
558 * po/es.po: Updated Spanish translation.
559
c39e5b26
JB		 5602018-03-28 Jan Beulich <jbeulich@suse.com>
561
562 * i386-gen.c (opcode_modifiers): Delete VecESize.
563 * i386-opc.h (VecESize): Delete.
564 (struct i386_opcode_modifier): Delete vecesize.
565 * i386-opc.tbl: Drop VecESize.
566 * i386-tlb.h: Re-generate.
567
8e6e0792
JB		 5682018-03-28 Jan Beulich <jbeulich@suse.com>
569
570 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
571 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
572 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
573 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
574 * i386-tlb.h: Re-generate.
575
9f123b91
JB		 5762018-03-28 Jan Beulich <jbeulich@suse.com>
577
578 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
579 Fold AVX512 forms
580 * i386-tlb.h: Re-generate.
581
9646c87b
JB		 5822018-03-28 Jan Beulich <jbeulich@suse.com>
583
584 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
585 (vex_len_table): Drop Y for vcvt*2si.
586 (putop): Replace plain 'Y' handling by abort().
587
c8d59609
NC		 5882018-03-28 Nick Clifton <nickc@redhat.com>
589
590 PR 22988
591 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
592 instructions with only a base address register.
593 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
594 handle AARHC64_OPND_SVE_ADDR_R.
595 (aarch64_print_operand): Likewise.
596 * aarch64-asm-2.c: Regenerate.
597 * aarch64_dis-2.c: Regenerate.
598 * aarch64-opc-2.c: Regenerate.
599
b8c169f3
JB		 6002018-03-22 Jan Beulich <jbeulich@suse.com>
601
602 * i386-opc.tbl: Drop VecESize from register only insn forms and
603 memory forms not allowing broadcast.
604 * i386-tlb.h: Re-generate.
605
96bc132a
JB		 6062018-03-22 Jan Beulich <jbeulich@suse.com>
607
608 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
609 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
610 sha256*): Drop Disp<N>.
611
9f79e886
JB		 6122018-03-22 Jan Beulich <jbeulich@suse.com>
613
614 * i386-dis.c (EbndS, bnd_swap_mode): New.
615 (prefix_table): Use EbndS.
616 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
617 * i386-opc.tbl (bndmov): Move misplaced Load.
618 * i386-tlb.h: Re-generate.
619
d6793fa1
JB		 6202018-03-22 Jan Beulich <jbeulich@suse.com>
621
622 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
623 templates allowing memory operands and folded ones for register
624 only flavors.
625 * i386-tlb.h: Re-generate.
626
f7768225
JB		 6272018-03-22 Jan Beulich <jbeulich@suse.com>
628
629 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
630 256-bit templates. Drop redundant leftover Disp<N>.
631 * i386-tlb.h: Re-generate.
632
0e35537d
JW		 6332018-03-14 Kito Cheng <kito.cheng@gmail.com>
634
635 * riscv-opc.c (riscv_insn_types): New.
636
b4a3689a
NC		 6372018-03-13 Nick Clifton <nickc@redhat.com>
638
639 * po/pt_BR.po: Updated Brazilian Portuguese translation.
640
d3d50934
L		 6412018-03-08 H.J. Lu <hongjiu.lu@intel.com>
642
643 * i386-opc.tbl: Add Optimize to clr.
644 * i386-tbl.h: Regenerated.
645
bd5dea88
L		 6462018-03-08 H.J. Lu <hongjiu.lu@intel.com>
647
648 * i386-gen.c (opcode_modifiers): Remove OldGcc.
649 * i386-opc.h (OldGcc): Removed.
650 (i386_opcode_modifier): Remove oldgcc.
651 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
652 instructions for old (<= 2.8.1) versions of gcc.
653 * i386-tbl.h: Regenerated.
654
e771e7c9
JB		 6552018-03-08 Jan Beulich <jbeulich@suse.com>
656
657 * i386-opc.h (EVEXDYN): New.
658 * i386-opc.tbl: Fold various AVX512VL templates.
659 * i386-tlb.h: Re-generate.
660
ed438a93
JB		 6612018-03-08 Jan Beulich <jbeulich@suse.com>
662
663 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
664 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
665 vpexpandd, vpexpandq): Fold AFX512VF templates.
666 * i386-tlb.h: Re-generate.
667
454172a9
JB		 6682018-03-08 Jan Beulich <jbeulich@suse.com>
669
670 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
671 Fold 128- and 256-bit VEX-encoded templates.
672 * i386-tlb.h: Re-generate.
673
36824150
JB		 6742018-03-08 Jan Beulich <jbeulich@suse.com>
675
676 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
677 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
678 vpexpandd, vpexpandq): Fold AVX512F templates.
679 * i386-tlb.h: Re-generate.
680
e7f5c0a9
JB		 6812018-03-08 Jan Beulich <jbeulich@suse.com>
682
683 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
684 64-bit templates. Drop Disp<N>.
685 * i386-tlb.h: Re-generate.
686
25a4277f
JB		 6872018-03-08 Jan Beulich <jbeulich@suse.com>
688
689 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
690 and 256-bit templates.
691 * i386-tlb.h: Re-generate.
692
d2224064
JB		 6932018-03-08 Jan Beulich <jbeulich@suse.com>
694
695 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
696 * i386-tlb.h: Re-generate.
697
1b193f0b
JB		 6982018-03-08 Jan Beulich <jbeulich@suse.com>
699
700 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
701 Drop NoAVX.
702 * i386-tlb.h: Re-generate.
703
f2f6a710
JB		 7042018-03-08 Jan Beulich <jbeulich@suse.com>
705
706 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
707 * i386-tlb.h: Re-generate.
708
38e314eb
JB		 7092018-03-08 Jan Beulich <jbeulich@suse.com>
710
711 * i386-gen.c (opcode_modifiers): Delete FloatD.
712 * i386-opc.h (FloatD): Delete.
713 (struct i386_opcode_modifier): Delete floatd.
714 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
715 FloatD by D.
716 * i386-tlb.h: Re-generate.
717
d53e6b98
JB		 7182018-03-08 Jan Beulich <jbeulich@suse.com>
719
720 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
721
2907c2f5
JB		 7222018-03-08 Jan Beulich <jbeulich@suse.com>
723
724 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
725 * i386-tlb.h: Re-generate.
726
73053c1f
JB		 7272018-03-08 Jan Beulich <jbeulich@suse.com>
728
729 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
730 forms.
731 * i386-tlb.h: Re-generate.
732
52fe4420
AM		 7332018-03-07 Alan Modra <amodra@gmail.com>
734
735 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
736 bfd_arch_rs6000.
737 * disassemble.h (print_insn_rs6000): Delete.
738 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
739 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
740 (print_insn_rs6000): Delete.
741
a6743a54
AM		 7422018-03-03 Alan Modra <amodra@gmail.com>
743
744 * sysdep.h (opcodes_error_handler): Define.
745 (_bfd_error_handler): Declare.
746 * Makefile.am: Remove stray #.
747 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
748 EDIT" comment.
749 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
750 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
751 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
752 opcodes_error_handler to print errors. Standardize error messages.
753 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
754 and include opintl.h.
755 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
756 * i386-gen.c: Standardize error messages.
757 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
758 * Makefile.in: Regenerate.
759 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
760 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
761 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
762 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
763 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
764 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
765 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
766 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
767 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
768 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
769 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
770 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
771 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
772
8305403a
L		 7732018-03-01 H.J. Lu <hongjiu.lu@intel.com>
774
775 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
776 vpsub[bwdq] instructions.
777 * i386-tbl.h: Regenerated.
778
e184813f
AM		 7792018-03-01 Alan Modra <amodra@gmail.com>
780
781 * configure.ac (ALL_LINGUAS): Sort.
782 * configure: Regenerate.
783
5b616bef
TP		 7842018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
785
786 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
787 macro by assignements.
788
b6f8c7c4
L		 7892018-02-27 H.J. Lu <hongjiu.lu@intel.com>
790
791 PR gas/22871
792 * i386-gen.c (opcode_modifiers): Add Optimize.
793 * i386-opc.h (Optimize): New enum.
794 (i386_opcode_modifier): Add optimize.
795 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
796 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
797 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
798 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
799 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
800 vpxord and vpxorq.
801 * i386-tbl.h: Regenerated.
802
e95b887f
AM		 8032018-02-26 Alan Modra <amodra@gmail.com>
804
805 * crx-dis.c (getregliststring): Allocate a large enough buffer
806 to silence false positive gcc8 warning.
807
0bccfb29
JW		 8082018-02-22 Shea Levy <shea@shealevy.com>
809
810 * disassemble.c (ARCH_riscv): Define if ARCH_all.
811
6b6b6807
L		 8122018-02-22 H.J. Lu <hongjiu.lu@intel.com>
813
814 * i386-opc.tbl: Add {rex},
815 * i386-tbl.h: Regenerated.
816
75f31665
MR		 8172018-02-20 Maciej W. Rozycki <macro@mips.com>
818
819 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
820 (mips16_opcodes): Replace `M' with `m' for "restore".
821
e207bc53
TP		 8222018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
823
824 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
825
87993319
MR		 8262018-02-13 Maciej W. Rozycki <macro@mips.com>
827
828 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
829 variable to `function_index'.
830
68d20676
NC		 8312018-02-13 Nick Clifton <nickc@redhat.com>
832
833 PR 22823
834 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
835 about truncation of printing.
836
d2159fdc
HW		 8372018-02-12 Henry Wong <henry@stuffedcow.net>
838
839 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
840
f174ef9f
NC		 8412018-02-05 Nick Clifton <nickc@redhat.com>
842
843 * po/pt_BR.po: Updated Brazilian Portuguese translation.
844
be3a8dca
IT		 8452018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
846
847 * i386-dis.c (enum): Add pconfig.
848 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
849 (cpu_flags): Add CpuPCONFIG.
850 * i386-opc.h (enum): Add CpuPCONFIG.
851 (i386_cpu_flags): Add cpupconfig.
852 * i386-opc.tbl: Add PCONFIG instruction.
853 * i386-init.h: Regenerate.
854 * i386-tbl.h: Likewise.
855
3233d7d0
IT		 8562018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
857
858 * i386-dis.c (enum): Add PREFIX_0F09.
859 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
860 (cpu_flags): Add CpuWBNOINVD.
861 * i386-opc.h (enum): Add CpuWBNOINVD.
862 (i386_cpu_flags): Add cpuwbnoinvd.
863 * i386-opc.tbl: Add WBNOINVD instruction.
864 * i386-init.h: Regenerate.
865 * i386-tbl.h: Likewise.
866
e925c834
JW		 8672018-01-17 Jim Wilson <jimw@sifive.com>
868
869 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
870
d777820b
IT		 8712018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
872
873 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
874 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
875 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
876 (cpu_flags): Add CpuIBT, CpuSHSTK.
877 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
878 (i386_cpu_flags): Add cpuibt, cpushstk.
879 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
880 * i386-init.h: Regenerate.
881 * i386-tbl.h: Likewise.
882
f6efed01
NC		 8832018-01-16 Nick Clifton <nickc@redhat.com>
884
885 * po/pt_BR.po: Updated Brazilian Portugese translation.
886 * po/de.po: Updated German translation.
887
2721d702
JW		 8882018-01-15 Jim Wilson <jimw@sifive.com>
889
890 * riscv-opc.c (match_c_nop): New.
891 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
892
616dcb87
NC		 8932018-01-15 Nick Clifton <nickc@redhat.com>
894
895 * po/uk.po: Updated Ukranian translation.
896
3957a496
NC		 8972018-01-13 Nick Clifton <nickc@redhat.com>
898
899 * po/opcodes.pot: Regenerated.
900
769c7ea5
NC		 9012018-01-13 Nick Clifton <nickc@redhat.com>
902
903 * configure: Regenerate.
904
faf766e3
NC		 9052018-01-13 Nick Clifton <nickc@redhat.com>
906
907 2.30 branch created.
908
888a89da
IT		 9092018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
910
911 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
912 * i386-tbl.h: Regenerate.
913
cbda583a
JB		 9142018-01-10 Jan Beulich <jbeulich@suse.com>
915
916 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
917 * i386-tbl.h: Re-generate.
918
c9e92278
JB		 9192018-01-10 Jan Beulich <jbeulich@suse.com>
920
921 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
922 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
923 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
924 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
925 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
926 Disp8MemShift of AVX512VL forms.
927 * i386-tbl.h: Re-generate.
928
35fd2b2b
JW		 9292018-01-09 Jim Wilson <jimw@sifive.com>
930
931 * riscv-dis.c (maybe_print_address): If base_reg is zero,
932 then the hi_addr value is zero.
933
91d8b670
JG		 9342018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
935
936 * arm-dis.c (arm_opcodes): Add csdb.
937 (thumb32_opcodes): Add csdb.
938
be2e7d95
JG		 9392018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
940
941 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
942 * aarch64-asm-2.c: Regenerate.
943 * aarch64-dis-2.c: Regenerate.
944 * aarch64-opc-2.c: Regenerate.
945
704a705d
L		 9462018-01-08 H.J. Lu <hongjiu.lu@intel.com>
947
948 PR gas/22681
949 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
950 Remove AVX512 vmovd with 64-bit operands.
951 * i386-tbl.h: Regenerated.
952
35eeb78f
JW		 9532018-01-05 Jim Wilson <jimw@sifive.com>
954
955 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
956 jalr.
957
219d1afa
AM		 9582018-01-03 Alan Modra <amodra@gmail.com>
959
960 Update year range in copyright notice of all files.
961
1508bbf5
JB		 9622018-01-02 Jan Beulich <jbeulich@suse.com>
963
964 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
965 and OPERAND_TYPE_REGZMM entries.
966
1e563868 967For older changes see ChangeLog-2017
3499769a 968\f
1e563868 969Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 970
971Copying and distribution of this file, with or without modification,
972are permitted in any medium without royalty provided the copyright
973notice and this notice are preserved.
974
975Local Variables:
976mode: change-log
977left-margin: 8
978fill-column: 74
979version-control: never
980End:
GDB Binutils - Deliverables
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