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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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8ebac3aa
AM		 12011-12-13 Alan Modra <amodra@gmail.com>
2
3 * ppc-opc.c (ISA_V2): Define and use for relevant BO field tests.
4 (valid_bo_pre_v2, valid_bo_post_v2): New functions, extracted from..
5 (valid_bo): ..here. When disassembling, accept either 'y' or 'at'
6 type encoding on second pass.
7 (powerpc_opcodes): Use ISA_V2 to enable branch insns rather than
8 POWER4.
9 * ppc-dis.c (print_insn_powerpc): Delete dialect_orig. Instead
10 ignore deprecated on second pass.
11
bb8e626d
AP		 122011-12-08 Andrew Pinski <apinski@cavium.com>
13
14 * mips-opc.c (mips_builtin_opcodes): Add "pause".
15
432233b3 162011-12-08 Andrew Pinski <apinski@cavium.com>
8ebac3aa 17 Adam Nemet <anemet@caviumnetworks.com>
432233b3
AP		 18
19 * mips-dis.c (mips_arch_choices): Add Octeon2.
20 For "octeon+", just include OcteonP for the insn.
21 * mips-opc.c (IOCT): Include Octeon2.
22 (IOCTP): Include Octeon2.
23 (IOCT2): New macro.
24 (mips_builtin_opcodes): Add "laa", "laad", "lac", "lacd", "lad",
25 "ladd", "lai", "laid", "las", "lasd", "law", "lawd".
26 Move "lbux", "ldx", "lhx", "lwx", and "lwux" up to where the standard
27 loads are, and add IOCT2 to them.
28 Add "lbx" and "lhux".
29 Add "qmac.00", "qmac.01", "qmac.02", "qmac.03", "qmacs.00",
30 "qmacs.01", "qmacs.01", "qmacs.02" and "qmacs.03".
31 Add "zcb" and "zcbt".
32
dd6a37e7
AP		 332011-11-29 Andrew Pinski <apinski@cavium.com>
34
35 * mips-dis.c (mips_arch_choices): Add Octeon+.
36 * mips-opc.c (IOCT): Include Octeon+.
37 (IOCTP): New macro.
38 (mips_builtin_opcodes): Add "saa" and "saad".
39
0c7533d3
PM		 402011-11-25 Pierre Muller <muller@ics.u-strasbg.fr>
41
42 * mips-dis.c (print_insn_micromips): Rename local variable iprintf
43 to infprintf to avoid shadow warning.
44
eda81062
NC		 452011-11-25 Nick Clifton <nickc@redhat.com>
46
47 * po/it.po: Updated Italian translation.
48
514f48bb
MR		 492011-11-16 Maciej W. Rozycki <macro@codesourcery.com>
50
51 * micromips-opc.c (micromips_opcodes): Use NODS rather than TRAP
52 for "alnv.ps".
53
207d428d
NC		 542011-11-02 Nick Clifton <nickc@redhat.com>
55
56 * po/it.po: New Italian translation.
57 * configure.in (ALL_LINGUAS): Add it.
58 * configure: Regenerate.
59 * po/opcodes.pot: Regenerate.
60
99c513f6
DD		 612011-11-01 DJ Delorie <dj@redhat.com>
62
63 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add rl78-decode.c and
64 rl78-dis.c.
65 (MAINTAINERCLEANFILES): Add rl78-decode.c.
66 (rl78-decode.c): New rule, built from rl78-decode.opc and opc2c.
67 * Makefile.in: Regenerate.
68 * configure.in: Add bfd_rl78_arch case.
69 * configure: Regenerate.
70 * disassemble.c: Define ARCH_rl78.
71 (disassembler): Add ARCH_rl78 case.
72 * rl78-decode.c: New file.
73 * rl78-decode.opc: New file.
74 * rl78-dis.c: New file.
75
a08fc942
PB		 762011-10-27 Peter Bergner <bergner@vnet.ibm.com>
77
8ebac3aa 78 * ppc-opc.c (powerpc_opcodes) <drrndq, drrndq., dtstexq, dctqpq,
a08fc942
PB		 79 dctqpq., dctfixq, dctfixq., dxexq, dxexq., dtstsfq, dcffixq, dcffixq.,
80 diexq, diexq.>: Use FRT, FRA, FRB and FRBp repsectively on DFP quad
81 instructions.
82
f6dd4781
NC		 832011-10-26 Nick Clifton <nickc@redhat.com>
84
85 PR binutils/13348
86 * i386-dis.c (print_insn): Fix testing of array subscript.
87
56b13185
JR		 882011-10-26 Joern Rennecke <joern.rennecke@embecosm.com>
89
90 * disassemble.c (ARCH_epiphany): Move into alphasorted spot.
fd936b4c
JR		 91 * epiphany-asm.c, epiphany-opc.h: Regenerate.
92
cfb8c092
NC		 932011-10-25 Joern Rennecke <joern.rennecke@embecosm.com>
94
95 * Makefile.am (HFILES): Add epiphany-desc.h and epiphany-opc.h .
96 (TARGET_LIBOPCODES_CFILES): Add epiphany-asm.c, epiphany-desc.c,
97 epiphany-dis.c, epiphany-ibld.c and epiphany-opc.c .
98 (CLEANFILES): Add stamp-epiphany.
99 (EPIPHANY_DEPS): Set. Make CGEN-generated Epiphany files depend on it.
100 (stamp-epiphany): New rule.
101 * configure.in: Handle bfd_epiphany_arch.
102 * disassemble.c (ARCH_epiphany): Define.
103 (disassembler): Handle bfd_arch_epiphany.
104 * epiphany-asm.c: New file.
105 * epiphany-desc.c: New file.
106 * epiphany-desc.h: New file.
107 * epiphany-dis.c: New file.
108 * epiphany-ibld.c: New file.
109 * epiphany-opc.c: New file.
110 * epiphany-opc.h: New file.
111 * Makefile.in: Regenerate.
112 * configure: Regenerate.
113 * po/POTFILES.in: Regenerate.
114 * po/opcodes.pot: Regenerate.
115
c3732716
JB		 1162011-10-24 Julian Brown <julian@codesourcery.com>
117
118 * m68k-opc.c (m68k_opcodes): Fix entries for ColdFire moveml.
119
9cae27dc
AK		 1202011-10-21 Jan Glauber <jang@linux.vnet.ibm.com>
121
122 * s390-opc.txt: Add CPUMF instructions.
123
a415b1cd
JB		 1242011-10-18 Jie Zhang <jie@codesourcery.com>
125 Julian Brown <julian@codesourcery.com>
126
127 * arm-dis.c (print_insn_arm): Explicitly specify rotation if needed.
128
d5698657
NC		 1292011-10-10 Nick Clifton <nickc@redhat.com>
130
131 * po/es.po: Updated Spanish translation.
132 * po/fi.po: Updated Finnish translation.
133
989993d8
JB		 1342011-09-28 Jan Beulich <jbeulich@suse.com>
135
136 * ppc-opc.c (insert_nbi, insert_rbx, FRAp, FRBp, FRSp, FRTp, NBI, RAX,
137 RBX): New.
138 (insert_bo, insert_boe): Reject bcctr with bit 2 in bo unset.
139 (powerpc_opcodes): Use RAX for second and RBXC for third operand of
140 lswx. Use NBI for third operand of lswi. Use FRTp for first operand of
141 lfdp and lfdpx. Use FRSp for first operand of stfdp and stfdpx, and
142 mark them as invalid on POWER7. Use FRTp, FRAp, and FRBp repsectively
143 on DFP quad instructions.
144
92a7795b
DM		 1452011-09-27 David S. Miller <davem@davemloft.net>
146
147 * sparc-opc.c (sparc_opcodes): Fix random instruction to write
148 to a float instead of an integer register.
149
e91d1076
DM		 1502011-09-26 David S. Miller <davem@davemloft.net>
151
152 * sparc-opc.c (sparc_opcodes): Add integer multiply-add
153 instructions.
154
9e8c70f9
DM		 1552011-09-21 David S. Miller <davem@davemloft.net>
156
157 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
158 bits. Fix "fchksm16" mnemonic.
159
9bf29d72
DM		 1602011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
161
162 The changes below bring 'mov' and 'ticc' instructions into line
163 with the V8 SPARC Architecture Manual.
164 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
165 * sparc-opc.c (sparc_opcodes): Add alias entries for
166 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
167 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
168 * sparc-opc.c (sparc_opcodes): Move/Change entries for
169 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
170 and 'mov imm,%tbr'.
171 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
172 mov aliases.
173
8dbb9eb3
DM		 174 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
175 This has been reported as being accepted by the Sun assmebler.
176
cdf49201
DM		 1772011-09-08 David S. Miller <davem@davemloft.net>
178
179 * sparc-opc.c (pdistn): Destination is integer not float register.
180
96e67898
AS		 1812011-09-07 Andreas Schwab <schwab@linux-m68k.org>
182
b2ea1829 183 PR gas/13145
96e67898
AS		 184 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
185
7cf80422
NC		 1862011-08-26 Nick Clifton <nickc@redhat.com>
187
188 * po/es.po: Updated Spanish translation.
189
dc15e575
NC		 1902011-08-22 Nick Clifton <nickc@redhat.com>
191
192 * Makefile.am (CPUDIR): Redfine to point to top level cpu
193 directory.
194 (stamp-frv): Use CPUDIR.
195 (stamp-iq2000): Likewise.
196 (stamp-lm32): Likewise.
197 (stamp-m32c): Likewise.
198 (stamp-mt): Likewise.
199 (stamp-xc16x): Likewise.
200 * Makefile.in: Regenerate.
201
dec0624d 2022011-08-09 Chao-ying Fu <fu@mips.com>
8ebac3aa 203 Maciej W. Rozycki <macro@codesourcery.com>
dec0624d
MR		 204
205 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
206 and "mips64r2".
207 (print_insn_args, print_insn_micromips): Handle MCU.
208 * micromips-opc.c (MC): New macro.
209 (micromips_opcodes): Add "aclr", "aset" and "iret".
210 * mips-opc.c (MC): New macro.
211 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
212
2b0c8b40
MR		 2132011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
214
215 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
216 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
217 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
218 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
219 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
220 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
221 (WR_s): Update macro.
222 (micromips_opcodes): Update register use flags of: "addiu",
223 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
224 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
225 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
226 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
227 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
228 "swm" and "xor" instructions.
229
ea783ef3
DM		 2302011-08-05 David S. Miller <davem@davemloft.net>
231
232 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
233 (X_RS3): New macro.
234 (print_insn_sparc): Handle '4', '5', and '(' format codes.
235 Accept %asr numbers below 28.
236 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
237 instructions.
238
3929df09
QN		 2392011-08-02 Quentin Neill <quentin.neill@amd.com>
240
241 * i386-dis.c (xop_table): Remove spurious bextr insn.
242
d7921315
L		 2432011-08-01 H.J. Lu <hongjiu.lu@intel.com>
244
245 PR ld/13048
246 * i386-dis.c (print_insn): Optimize info->mach check.
247
00f51a41
L		 2482011-08-01 H.J. Lu <hongjiu.lu@intel.com>
249
250 PR gas/13046
251 * i386-opc.tbl: Add Disp32S to 64bit call.
252 * i386-tbl.h: Regenerated.
253
df58fc94 2542011-07-24 Chao-ying Fu <fu@mips.com>
8ebac3aa 255 Maciej W. Rozycki <macro@codesourcery.com>
df58fc94
RS		 256
257 * micromips-opc.c: New file.
258 * mips-dis.c (micromips_to_32_reg_b_map): New array.
259 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
260 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
261 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
262 (micromips_to_32_reg_q_map): Likewise.
263 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
264 (micromips_ase): New variable.
265 (is_micromips): New function.
266 (set_default_mips_dis_options): Handle microMIPS ASE.
267 (print_insn_micromips): New function.
268 (is_compressed_mode_p): Likewise.
269 (_print_insn_mips): Handle microMIPS instructions.
270 * Makefile.am (CFILES): Add micromips-opc.c.
271 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
272 * Makefile.in: Regenerate.
273 * configure: Regenerate.
274
275 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
276 (micromips_to_32_reg_i_map): Likewise.
277 (micromips_to_32_reg_m_map): Likewise.
278 (micromips_to_32_reg_n_map): New macro.
279
bcd530a7
RS		 2802011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
281
282 * mips-opc.c (NODS): New macro.
283 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
284 (DSP_VOLA): Likewise.
285 (mips_builtin_opcodes): Add NODS annotation to "deret" and
286 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
287 place of TRAP for "wait", "waiti" and "yield".
288 * mips16-opc.c (NODS): New macro.
289 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
290 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
291 "restore" and "save".
292
7a9068fe
L		 2932011-07-22 H.J. Lu <hongjiu.lu@intel.com>
294
295 * configure.in: Handle bfd_k1om_arch.
296 * configure: Regenerated.
297
298 * disassemble.c (disassembler): Handle bfd_k1om_arch.
299
300 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
301 bfd_mach_k1om_intel_syntax.
302
303 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
304 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
305 (cpu_flags): Add CpuK1OM.
306
307 * i386-opc.h (CpuK1OM): New.
308 (i386_cpu_flags): Add cpuk1om.
309
310 * i386-init.h: Regenerated.
311 * i386-tbl.h: Likewise.
312
1b93226d
NC		 3132011-07-12 Nick Clifton <nickc@redhat.com>
314
315 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
316 accidental change.
317
5d73b1f1
NC		 3182011-07-01 Nick Clifton <nickc@redhat.com>
319
320 PR binutils/12329
321 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
322 insns using post-increment addressing.
323
182ae480
L		 3242011-06-30 H.J. Lu <hongjiu.lu@intel.com>
325
326 * i386-dis.c (vex_len_table): Update rorxS.
327
4cb0953d
L		 3282011-06-30 H.J. Lu <hongjiu.lu@intel.com>
329
330 AVX Programming Reference (June, 2011)
331 * i386-dis.c (vex_len_table): Correct rorxS.
332
333 * i386-opc.tbl: Correct rorx.
334 * i386-tbl.h: Regenerated.
335
906efcbc
L		 3362011-06-29 H.J. Lu <hongjiu.lu@intel.com>
337
338 * tilegx-opc.c (find_opcode): Replace "index" with "i".
339 * tilepro-opc.c (find_opcode): Likewise.
340
ceb94aa5
RS		 3412011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
342
343 * mips16-opc.c (jalrc, jrc): Move earlier in file.
344
f7002f42
L		 3452011-06-21 H.J. Lu <hongjiu.lu@intel.com>
346
347 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
348 PREFIX_VEX_0F388E.
349
56300268
AS		 3502011-06-17 Andreas Schwab <schwab@redhat.com>
351
352 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
353 (MOSTLYCLEANFILES): ... here.
354 * Makefile.in: Regenerate.
355
bcf2cf9f
AM		 3562011-06-14 Alan Modra <amodra@gmail.com>
357
358 * Makefile.in: Regenerate.
359
aa137e4d
NC		 3602011-06-13 Walter Lee <walt@tilera.com>
361
362 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
363 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
364 * Makefile.in: Regenerate.
365 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
366 * configure: Regenerate.
367 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
368 * po/POTFILES.in: Regenerate.
369 * tilegx-dis.c: New file.
370 * tilegx-opc.c: New file.
371 * tilepro-dis.c: New file.
372 * tilepro-opc.c: New file.
373
6c30d220
L		 3742011-06-10 H.J. Lu <hongjiu.lu@intel.com>
375
376 AVX Programming Reference (June, 2011)
377 * i386-dis.c (XMGatherQ): New.
378 * i386-dis.c (EXxmm_mb): New.
379 (EXxmm_mb): Likewise.
380 (EXxmm_mw): Likewise.
381 (EXxmm_md): Likewise.
382 (EXxmm_mq): Likewise.
383 (EXxmmdw): Likewise.
384 (EXxmmqd): Likewise.
385 (VexGatherQ): Likewise.
386 (MVexVSIBDWpX): Likewise.
387 (MVexVSIBQWpX): Likewise.
388 (xmm_mb_mode): Likewise.
389 (xmm_mw_mode): Likewise.
390 (xmm_md_mode): Likewise.
391 (xmm_mq_mode): Likewise.
392 (xmmdw_mode): Likewise.
393 (xmmqd_mode): Likewise.
394 (ymmxmm_mode): Likewise.
395 (vex_vsib_d_w_dq_mode): Likewise.
396 (vex_vsib_q_w_dq_mode): Likewise.
397 (MOD_VEX_0F385A_PREFIX_2): Likewise.
398 (MOD_VEX_0F388C_PREFIX_2): Likewise.
399 (MOD_VEX_0F388E_PREFIX_2): Likewise.
400 (PREFIX_0F3882): Likewise.
401 (PREFIX_VEX_0F3816): Likewise.
402 (PREFIX_VEX_0F3836): Likewise.
403 (PREFIX_VEX_0F3845): Likewise.
404 (PREFIX_VEX_0F3846): Likewise.
405 (PREFIX_VEX_0F3847): Likewise.
406 (PREFIX_VEX_0F3858): Likewise.
407 (PREFIX_VEX_0F3859): Likewise.
408 (PREFIX_VEX_0F385A): Likewise.
409 (PREFIX_VEX_0F3878): Likewise.
410 (PREFIX_VEX_0F3879): Likewise.
411 (PREFIX_VEX_0F388C): Likewise.
412 (PREFIX_VEX_0F388E): Likewise.
413 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
414 (PREFIX_VEX_0F38F5): Likewise.
415 (PREFIX_VEX_0F38F6): Likewise.
416 (PREFIX_VEX_0F3A00): Likewise.
417 (PREFIX_VEX_0F3A01): Likewise.
418 (PREFIX_VEX_0F3A02): Likewise.
419 (PREFIX_VEX_0F3A38): Likewise.
420 (PREFIX_VEX_0F3A39): Likewise.
421 (PREFIX_VEX_0F3A46): Likewise.
422 (PREFIX_VEX_0F3AF0): Likewise.
423 (VEX_LEN_0F3816_P_2): Likewise.
424 (VEX_LEN_0F3819_P_2): Likewise.
425 (VEX_LEN_0F3836_P_2): Likewise.
426 (VEX_LEN_0F385A_P_2_M_0): Likewise.
427 (VEX_LEN_0F38F5_P_0): Likewise.
428 (VEX_LEN_0F38F5_P_1): Likewise.
429 (VEX_LEN_0F38F5_P_3): Likewise.
430 (VEX_LEN_0F38F6_P_3): Likewise.
431 (VEX_LEN_0F38F7_P_1): Likewise.
432 (VEX_LEN_0F38F7_P_2): Likewise.
433 (VEX_LEN_0F38F7_P_3): Likewise.
434 (VEX_LEN_0F3A00_P_2): Likewise.
435 (VEX_LEN_0F3A01_P_2): Likewise.
436 (VEX_LEN_0F3A38_P_2): Likewise.
437 (VEX_LEN_0F3A39_P_2): Likewise.
438 (VEX_LEN_0F3A46_P_2): Likewise.
439 (VEX_LEN_0F3AF0_P_3): Likewise.
440 (VEX_W_0F3816_P_2): Likewise.
441 (VEX_W_0F3818_P_2): Likewise.
442 (VEX_W_0F3819_P_2): Likewise.
443 (VEX_W_0F3836_P_2): Likewise.
444 (VEX_W_0F3846_P_2): Likewise.
445 (VEX_W_0F3858_P_2): Likewise.
446 (VEX_W_0F3859_P_2): Likewise.
447 (VEX_W_0F385A_P_2_M_0): Likewise.
448 (VEX_W_0F3878_P_2): Likewise.
449 (VEX_W_0F3879_P_2): Likewise.
450 (VEX_W_0F3A00_P_2): Likewise.
451 (VEX_W_0F3A01_P_2): Likewise.
452 (VEX_W_0F3A02_P_2): Likewise.
453 (VEX_W_0F3A38_P_2): Likewise.
454 (VEX_W_0F3A39_P_2): Likewise.
455 (VEX_W_0F3A46_P_2): Likewise.
456 (MOD_VEX_0F3818_PREFIX_2): Removed.
457 (MOD_VEX_0F3819_PREFIX_2): Likewise.
458 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
459 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
460 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
461 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
462 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
463 (VEX_LEN_0F3A0E_P_2): Likewise.
464 (VEX_LEN_0F3A0F_P_2): Likewise.
465 (VEX_LEN_0F3A42_P_2): Likewise.
466 (VEX_LEN_0F3A4C_P_2): Likewise.
467 (VEX_W_0F3818_P_2_M_0): Likewise.
468 (VEX_W_0F3819_P_2_M_0): Likewise.
469 (prefix_table): Updated.
470 (three_byte_table): Likewise.
471 (vex_table): Likewise.
472 (vex_len_table): Likewise.
473 (vex_w_table): Likewise.
474 (mod_table): Likewise.
475 (putop): Handle "LW".
476 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
477 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
478 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
479 (OP_EX): Likewise.
480 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
481 vex_vsib_q_w_dq_mode.
482 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
483 (OP_VEX): Likewise.
484
485 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
486 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
487 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
488 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
489 (opcode_modifiers): Add VecSIB.
490
491 * i386-opc.h (CpuAVX2): New.
492 (CpuBMI2): Likewise.
493 (CpuLZCNT): Likewise.
494 (CpuINVPCID): Likewise.
495 (VecSIB128): Likewise.
496 (VecSIB256): Likewise.
497 (VecSIB): Likewise.
498 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
499 (i386_opcode_modifier): Add vecsib.
500
501 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
502 * i386-init.h: Regenerated.
503 * i386-tbl.h: Likewise.
504
d535accd
QN		 5052011-06-03 Quentin Neill <quentin.neill@amd.com>
506
507 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
508 * i386-init.h: Regenerated.
509
f8b960bc
NC		 5102011-06-03 Nick Clifton <nickc@redhat.com>
511
512 PR binutils/12752
513 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
514 computing address offsets.
515 (print_arm_address): Likewise.
516 (print_insn_arm): Likewise.
517 (print_insn_thumb16): Likewise.
518 (print_insn_thumb32): Likewise.
519
26d97720
NS		 5202011-06-02 Jie Zhang <jie@codesourcery.com>
521 Nathan Sidwell <nathan@codesourcery.com>
522 Maciej Rozycki <macro@codesourcery.com>
523
524 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
525 as address offset.
526 (print_arm_address): Likewise. Elide positive #0 appropriately.
527 (print_insn_arm): Likewise.
528
f8b960bc
NC		 5292011-06-02 Nick Clifton <nickc@redhat.com>
530
531 PR gas/12752
532 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
533 passed to print_address_func.
534
cc643b88
NC		 5352011-06-02 Nick Clifton <nickc@redhat.com>
536
537 * arm-dis.c: Fix spelling mistakes.
538 * op/opcodes.pot: Regenerate.
539
c8fa16ed
AK		 5402011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
541
542 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
543 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
544 * s390-opc.txt: Fix cxr instruction type.
545
5e4b319c
AK		 5462011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
547
548 * s390-opc.c: Add new instruction types marking register pair
549 operands.
550 * s390-opc.txt: Match instructions having register pair operands
551 to the new instruction types.
552
fda544a2
NC		 5532011-05-19 Nick Clifton <nickc@redhat.com>
554
555 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
556 operands.
557
4cab4add
QN		 5582011-05-10 Quentin Neill <quentin.neill@amd.com>
559
560 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
561 * i386-init.h: Regenerated.
562
b4e7b885
NC		 5632011-04-27 Nick Clifton <nickc@redhat.com>
564
565 * po/da.po: Updated Danish translation.
566
2f7f7710
AM		 5672011-04-26 Anton Blanchard <anton@samba.org>
568
569 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
570
9887672f
DD		 5712011-04-21 DJ Delorie <dj@redhat.com>
572
573 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
574 * rx-decode.c: Regenerate.
575
3251b375
L		 5762011-04-20 H.J. Lu <hongjiu.lu@intel.com>
577
578 * i386-init.h: Regenerated.
579
b13a3ca6
QN		 5802011-04-19 Quentin Neill <quentin.neill@amd.com>
581
582 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
583 from bdver1 flags.
584
7d063384
NC		 5852011-04-13 Nick Clifton <nickc@redhat.com>
586
587 * v850-dis.c (disassemble): Always print a closing square brace if
588 an opening square brace was printed.
589
32a94698
NC		 5902011-04-12 Nick Clifton <nickc@redhat.com>
591
592 PR binutils/12534
593 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
594 patterns.
595 (print_insn_thumb32): Handle %L.
596
d2cd1205
JB		 5972011-04-11 Julian Brown <julian@codesourcery.com>
598
599 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
600 (print_insn_thumb32): Add APSR bitmask support.
601
1fbaefec
PB		 6022011-04-07 Paul Carroll<pcarroll@codesourcery.com>
603
604 * arm-dis.c (print_insn): init vars moved into private_data structure.
605
67171547
MF		 6062011-03-24 Mike Frysinger <vapier@gentoo.org>
607
608 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
609
8cc66334
EW		 6102011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
611
612 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
613 post-increment to support LPM Z+ instruction. Add support for 'E'
614 constraint for DES instruction.
615 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
616
34e77a92
RS		 6172011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
618
619 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
620
35fc36a8
RS		 6212011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
622
623 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
624 Use branch types instead.
625 (print_insn): Likewise.
626
0067d8fc
MR		 6272011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
628
629 * mips-opc.c (mips_builtin_opcodes): Correct register use
630 annotation of "alnv.ps".
631
3eebd5eb
MR		 6322011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
633
634 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
635
500cccad
MF		 6362011-02-22 Mike Frysinger <vapier@gentoo.org>
637
638 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
639
f5caf9f4
MF		 6402011-02-22 Mike Frysinger <vapier@gentoo.org>
641
642 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
643
e5bc4265
MF		 6442011-02-19 Mike Frysinger <vapier@gentoo.org>
645
646 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
647 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
648 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
649 exception, end_of_registers, msize, memory, bfd_mach.
650 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
651 LB0REG, LC1REG, LT1REG, LB1REG): Delete
652 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
653 (get_allreg): Change to new defines. Fallback to abort().
654
602427c4
MF		 6552011-02-14 Mike Frysinger <vapier@gentoo.org>
656
657 * bfin-dis.c: Add whitespace/parenthesis where needed.
658
298c1ec2
MF		 6592011-02-14 Mike Frysinger <vapier@gentoo.org>
660
661 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
662 than 7.
663
822ce8ee
RW		 6642011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
665
666 * configure: Regenerate.
667
13c02f06
MF		 6682011-02-13 Mike Frysinger <vapier@gentoo.org>
669
670 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
671
4db66394
MF		 6722011-02-13 Mike Frysinger <vapier@gentoo.org>
673
674 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
675 dregs only when P is set, and dregs_lo otherwise.
676
36f44611
MF		 6772011-02-13 Mike Frysinger <vapier@gentoo.org>
678
679 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
680
9805c0a5
MF		 6812011-02-12 Mike Frysinger <vapier@gentoo.org>
682
683 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
684
43a6aa65
MF		 6852011-02-12 Mike Frysinger <vapier@gentoo.org>
686
687 * bfin-dis.c (machine_registers): Delete REG_GP.
688 (reg_names): Delete "GP".
689 (decode_allregs): Change REG_GP to REG_LASTREG.
690
26bb3ddd
MF		 6912011-02-12 Mike Frysinger <vapier@gentoo.org>
692
89c0d58c
MR		 693 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
694 M_IH, M_IU): Delete.
26bb3ddd 695
69b8ea4a
MF		 6962011-02-11 Mike Frysinger <vapier@gentoo.org>
697
698 * bfin-dis.c (reg_names): Add const.
699 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
700 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
701 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
702 decode_counters, decode_allregs): Likewise.
703
42d5f9c6
MS		 7042011-02-09 Michael Snyder <msnyder@vmware.com>
705
56300268 706 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 707 truncated addresses.
708 (print_insn): Fix indentation off-by-one.
709
4be0c941
NC		 7102011-02-01 Nick Clifton <nickc@redhat.com>
711
712 * po/da.po: Updated Danish translation.
713
6b069ee7
AM		 7142011-01-21 Dave Murphy <davem@devkitpro.org>
715
716 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
717
e3949f17
L		 7182011-01-18 H.J. Lu <hongjiu.lu@intel.com>
719
720 * i386-dis.c (sIbT): New.
721 (b_T_mode): Likewise.
722 (dis386): Replace sIb with sIbT on "pushT".
723 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
724 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
725
752573b2
JK		 7262011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
727
728 * i386-init.h: Regenerated.
729 * i386-tbl.h: Regenerated
730
2a2a0f38
QN		 7312011-01-17 Quentin Neill <quentin.neill@amd.com>
732
733 * i386-dis.c (REG_XOP_TBM_01): New.
734 (REG_XOP_TBM_02): New.
735 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
736 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
737 entries, and add bextr instruction.
738
739 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
740 (cpu_flags): Add CpuTBM.
741
742 * i386-opc.h (CpuTBM) New.
743 (i386_cpu_flags): Add bit cputbm.
744
745 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
746 blcs, blsfill, blsic, t1mskc, and tzmsk.
747
90d6ff62
DD		 7482011-01-12 DJ Delorie <dj@redhat.com>
749
750 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
751
c95354ed
MX		 7522011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
753
754 * mips-dis.c (print_insn_args): Adjust the value to print the real
755 offset for "+c" argument.
756
f7465604
NC		 7572011-01-10 Nick Clifton <nickc@redhat.com>
758
759 * po/da.po: Updated Danish translation.
760
639e30d2
NS		 7612011-01-05 Nathan Sidwell <nathan@codesourcery.com>
762
763 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
764
f12dc422
L		 7652011-01-04 H.J. Lu <hongjiu.lu@intel.com>
766
767 * i386-dis.c (REG_VEX_38F3): New.
768 (PREFIX_0FBC): Likewise.
769 (PREFIX_VEX_38F2): Likewise.
770 (PREFIX_VEX_38F3_REG_1): Likewise.
771 (PREFIX_VEX_38F3_REG_2): Likewise.
772 (PREFIX_VEX_38F3_REG_3): Likewise.
773 (PREFIX_VEX_38F7): Likewise.
774 (VEX_LEN_38F2_P_0): Likewise.
775 (VEX_LEN_38F3_R_1_P_0): Likewise.
776 (VEX_LEN_38F3_R_2_P_0): Likewise.
777 (VEX_LEN_38F3_R_3_P_0): Likewise.
778 (VEX_LEN_38F7_P_0): Likewise.
779 (dis386_twobyte): Use PREFIX_0FBC.
780 (reg_table): Add REG_VEX_38F3.
781 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
782 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
783 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
784 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
785 PREFIX_VEX_38F7.
786 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
787 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
788 VEX_LEN_38F7_P_0.
789
790 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
791 (cpu_flags): Add CpuBMI.
792
793 * i386-opc.h (CpuBMI): New.
794 (i386_cpu_flags): Add cpubmi.
795
796 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
797 * i386-init.h: Regenerated.
798 * i386-tbl.h: Likewise.
799
cb21baef
L		 8002011-01-04 H.J. Lu <hongjiu.lu@intel.com>
801
802 * i386-dis.c (VexGdq): New.
803 (OP_VEX): Handle dq_mode.
804
0db46eb4
L		 8052011-01-01 H.J. Lu <hongjiu.lu@intel.com>
806
807 * i386-gen.c (process_copyright): Update copyright to 2011.
808
9e9e0820 809For older changes see ChangeLog-2010
252b5132
RH		 810\f
811Local Variables:
2f6d2f85
NC		 812mode: change-log
813left-margin: 8
814fill-column: 74
252b5132
RH		 815version-control: never
816End:
GDB Binutils - Deliverables
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