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x86: drop bogus IgnoreSize from SSE4.2 insns
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0001cfd0
JB		 12018-09-13 Jan Beulich <jbeulich@suse.com>
2
3 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
4 meaningless.
5 * i386-tbl.h: Re-generate.
6
be4b452e
JB		 72018-09-13 Jan Beulich <jbeulich@suse.com>
8
9 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
10 meaningless.
11 * i386-tbl.h: Re-generate.
12
d09a1394
JB		 132018-09-13 Jan Beulich <jbeulich@suse.com>
14
15 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
16 meaningless.
17 * i386-tbl.h: Re-generate.
18
07599e13
JB		 192018-09-13 Jan Beulich <jbeulich@suse.com>
20
21 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
22 * i386-tbl.h: Re-generate.
23
1ee3e487
JB		 242018-09-13 Jan Beulich <jbeulich@suse.com>
25
26 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
27 * i386-tbl.h: Re-generate.
28
a5f580e5
JB		 292018-09-13 Jan Beulich <jbeulich@suse.com>
30
31 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
32 * i386-tbl.h: Re-generate.
33
49d5d12d
JB		 342018-09-13 Jan Beulich <jbeulich@suse.com>
35
36 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
37 (vpbroadcastw, rdpid): Drop NoRex64.
38 * i386-tbl.h: Re-generate.
39
f5eb1d70
JB		 402018-09-13 Jan Beulich <jbeulich@suse.com>
41
42 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
43 store templates, adding D.
44 * i386-tbl.h: Re-generate.
45
dbbc8b7e
JB		 462018-09-13 Jan Beulich <jbeulich@suse.com>
47
48 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
49 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
50 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
51 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
52 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
53 Fold load and store templates where possible, adding D. Drop
54 IgnoreSize where it was pointlessly present. Drop redundant
55 *word.
56 * i386-tbl.h: Re-generate.
57
d276ec69
JB		 582018-09-13 Jan Beulich <jbeulich@suse.com>
59
60 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
61 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
62 (intel_operand_size): Handle v_bndmk_mode.
63 (OP_E_memory): Likewise. Produce (bad) when also riprel.
64
9da4dfd6
JD		 652018-09-08 John Darrington <john@darrington.wattle.id.au>
66
67 * disassemble.c (ARCH_s12z): Define if ARCH_all.
68
be192bc2
JW		 692018-08-31 Kito Cheng <kito@andestech.com>
70
71 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
72 compressed floating point instructions.
73
43135d3b
JW		 742018-08-30 Kito Cheng <kito@andestech.com>
75
76 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
77 riscv_opcode.xlen_requirement.
78 * riscv-opc.c (riscv_opcodes): Update for struct change.
79
df28970f
MA		 802018-08-29 Martin Aberg <maberg@gaisler.com>
81
82 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
83 psr (PWRPSR) instruction.
84
9108bc33
CX		 852018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
86
87 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
88
bd782c07
CX		 892018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
90
91 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
92
ac8cb70f
CX		 932018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
94
95 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
96 loongson3a as an alias of gs464 for compatibility.
97 * mips-opc.c (mips_opcodes): Change Comments.
98
a693765e
CX		 992018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
100
101 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
102 option.
103 (print_mips_disassembler_options): Document -M loongson-ext.
104 * mips-opc.c (LEXT2): New macro.
105 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
106
bdc6c06e
CX		 1072018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
108
109 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
110 descriptors.
111 (parse_mips_ase_option): Handle -M loongson-ext option.
112 (print_mips_disassembler_options): Document -M loongson-ext.
113 * mips-opc.c (IL3A): Delete.
114 * mips-opc.c (LEXT): New macro.
115 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
116 instructions.
117
716c08de
CX		 1182018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
119
120 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
121 descriptors.
122 (parse_mips_ase_option): Handle -M loongson-cam option.
123 (print_mips_disassembler_options): Document -M loongson-cam.
124 * mips-opc.c (LCAM): New macro.
125 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
126 instructions.
127
9cf7e568
AM		 1282018-08-21 Alan Modra <amodra@gmail.com>
129
130 * ppc-dis.c (operand_value_powerpc): Init "invalid".
131 (skip_optional_operands): Count optional operands, and update
132 ppc_optional_operand_value call.
133 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
134 (extract_vlensi): Likewise.
135 (extract_fxm): Return default value for missing optional operand.
136 (extract_ls, extract_raq, extract_tbr): Likewise.
137 (insert_sxl, extract_sxl): New functions.
138 (insert_esync, extract_esync): Remove Power9 handling and simplify.
139 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
140 flag and extra entry.
141 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
142 extract_sxl.
143
d203b41a 1442018-08-20 Alan Modra <amodra@gmail.com>
f4107842 145
d203b41a 146 * sh-opc.h (MASK): Simplify.
f4107842 147
08a8fe2f 1482018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 149
d203b41a
AM		 150 * s12z-dis.c (bm_decode): Deal with cases where the mode is
151 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 152 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 153
08a8fe2f 1542018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 155
156 * s12z.h: Delete.
7ba3ba91 157
1bc60e56
L		 1582018-08-14 H.J. Lu <hongjiu.lu@intel.com>
159
160 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
161 address with the addr32 prefix and without base nor index
162 registers.
163
d871f3f4
L		 1642018-08-11 H.J. Lu <hongjiu.lu@intel.com>
165
166 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
167 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
168 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
169 (cpu_flags): Add CpuCMOV and CpuFXSR.
170 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
171 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
172 * i386-init.h: Regenerated.
173 * i386-tbl.h: Likewise.
174
b6523c37 1752018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
176
177 * arc-regs.h: Update auxiliary registers.
178
e968fc9b
JB		 1792018-08-06 Jan Beulich <jbeulich@suse.com>
180
181 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
182 (RegIP, RegIZ): Define.
183 * i386-reg.tbl: Adjust comments.
184 (rip): Use Qword instead of BaseIndex. Use RegIP.
185 (eip): Use Dword instead of BaseIndex. Use RegIP.
186 (riz): Add Qword. Use RegIZ.
187 (eiz): Add Dword. Use RegIZ.
188 * i386-tbl.h: Re-generate.
189
dbf8be89
JB		 1902018-08-03 Jan Beulich <jbeulich@suse.com>
191
192 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
193 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
194 vpmovzxdq, vpmovzxwd): Remove NoRex64.
195 * i386-tbl.h: Re-generate.
196
c48dadc9
JB		 1972018-08-03 Jan Beulich <jbeulich@suse.com>
198
199 * i386-gen.c (operand_types): Remove Mem field.
200 * i386-opc.h (union i386_operand_type): Remove mem field.
201 * i386-init.h, i386-tbl.h: Re-generate.
202
cb86a42a
AM		 2032018-08-01 Alan Modra <amodra@gmail.com>
204
205 * po/POTFILES.in: Regenerate.
206
07cc0450
NC		 2072018-07-31 Nick Clifton <nickc@redhat.com>
208
209 * po/sv.po: Updated Swedish translation.
210
1424ad86
JB		 2112018-07-31 Jan Beulich <jbeulich@suse.com>
212
213 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
214 * i386-init.h, i386-tbl.h: Re-generate.
215
ae2387fe
JB		 2162018-07-31 Jan Beulich <jbeulich@suse.com>
217
218 * i386-opc.h (ZEROING_MASKING) Rename to ...
219 (DYNAMIC_MASKING): ... this. Adjust comment.
220 * i386-opc.tbl (MaskingMorZ): Define.
221 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
222 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
223 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
224 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
225 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
226 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
227 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
228 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
229 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
230
6ff00b5e
JB		 2312018-07-31 Jan Beulich <jbeulich@suse.com>
232
233 * i386-opc.tbl: Use element rather than vector size for AVX512*
234 scatter/gather insns.
235 * i386-tbl.h: Re-generate.
236
e951d5ca
JB		 2372018-07-31 Jan Beulich <jbeulich@suse.com>
238
239 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
240 (cpu_flags): Drop CpuVREX.
241 * i386-opc.h (CpuVREX): Delete.
242 (union i386_cpu_flags): Remove cpuvrex.
243 * i386-init.h, i386-tbl.h: Re-generate.
244
eb41b248
JW		 2452018-07-30 Jim Wilson <jimw@sifive.com>
246
247 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
248 fields.
249 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
250
b8891f8d
AJ		 2512018-07-30 Andrew Jenner <andrew@codesourcery.com>
252
253 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
254 * Makefile.in: Regenerated.
255 * configure.ac: Add C-SKY.
256 * configure: Regenerated.
257 * csky-dis.c: New file.
258 * csky-opc.h: New file.
259 * disassemble.c (ARCH_csky): Define.
260 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
261 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
262
16065af1
AM		 2632018-07-27 Alan Modra <amodra@gmail.com>
264
265 * ppc-opc.c (insert_sprbat): Correct function parameter and
266 return type.
267 (extract_sprbat): Likewise, variable too.
268
fa758a70
AC		 2692018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
270 Alan Modra <amodra@gmail.com>
271
272 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
273 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
274 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
275 support disjointed BAT.
276 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
277 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
278 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
279
4a1b91ea
L		 2802018-07-25 H.J. Lu <hongjiu.lu@intel.com>
281 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
282
283 * i386-gen.c (adjust_broadcast_modifier): New function.
284 (process_i386_opcode_modifier): Add an argument for operands.
285 Adjust the Broadcast value based on operands.
286 (output_i386_opcode): Pass operand_types to
287 process_i386_opcode_modifier.
288 (process_i386_opcodes): Pass NULL as operands to
289 process_i386_opcode_modifier.
290 * i386-opc.h (BYTE_BROADCAST): New.
291 (WORD_BROADCAST): Likewise.
292 (DWORD_BROADCAST): Likewise.
293 (QWORD_BROADCAST): Likewise.
294 (i386_opcode_modifier): Expand broadcast to 3 bits.
295 * i386-tbl.h: Regenerated.
296
67ce483b
AM		 2972018-07-24 Alan Modra <amodra@gmail.com>
298
299 PR 23430
300 * or1k-desc.h: Regenerate.
301
4174bfff
JB		 3022018-07-24 Jan Beulich <jbeulich@suse.com>
303
304 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
305 vcvtusi2ss, and vcvtusi2sd.
306 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
307 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
308 * i386-tbl.h: Re-generate.
309
04e65276
CZ		 3102018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
311
312 * arc-opc.c (extract_w6): Fix extending the sign.
313
47e6f81c
CZ		 3142018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
315
316 * arc-tbl.h (vewt): Allow it for ARC EM family.
317
bb71536f
AM		 3182018-07-23 Alan Modra <amodra@gmail.com>
319
320 PR 23419
321 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
322 opcode variants for mtspr/mfspr encodings.
323
8095d2f7
CX		 3242018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
325 Maciej W. Rozycki <macro@mips.com>
326
327 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
328 loongson3a descriptors.
329 (parse_mips_ase_option): Handle -M loongson-mmi option.
330 (print_mips_disassembler_options): Document -M loongson-mmi.
331 * mips-opc.c (LMMI): New macro.
332 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
333 instructions.
334
5f32791e
JB		 3352018-07-19 Jan Beulich <jbeulich@suse.com>
336
337 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
338 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
339 IgnoreSize and [XYZ]MMword where applicable.
340 * i386-tbl.h: Re-generate.
341
625cbd7a
JB		 3422018-07-19 Jan Beulich <jbeulich@suse.com>
343
344 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
345 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
346 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
347 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
348 * i386-tbl.h: Re-generate.
349
86b15c32
JB		 3502018-07-19 Jan Beulich <jbeulich@suse.com>
351
352 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
353 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
354 VPCLMULQDQ templates into their respective AVX512VL counterparts
355 where possible, using Disp8ShiftVL and CheckRegSize instead of
356 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
357 * i386-tbl.h: Re-generate.
358
cf769ed5
JB		 3592018-07-19 Jan Beulich <jbeulich@suse.com>
360
361 * i386-opc.tbl: Fold AVX512DQ templates into their respective
362 AVX512VL counterparts where possible, using Disp8ShiftVL and
363 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
364 IgnoreSize) as appropriate.
365 * i386-tbl.h: Re-generate.
366
8282b7ad
JB		 3672018-07-19 Jan Beulich <jbeulich@suse.com>
368
369 * i386-opc.tbl: Fold AVX512BW templates into their respective
370 AVX512VL counterparts where possible, using Disp8ShiftVL and
371 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
372 IgnoreSize) as appropriate.
373 * i386-tbl.h: Re-generate.
374
755908cc
JB		 3752018-07-19 Jan Beulich <jbeulich@suse.com>
376
377 * i386-opc.tbl: Fold AVX512CD templates into their respective
378 AVX512VL counterparts where possible, using Disp8ShiftVL and
379 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
380 IgnoreSize) as appropriate.
381 * i386-tbl.h: Re-generate.
382
7091c612
JB		 3832018-07-19 Jan Beulich <jbeulich@suse.com>
384
385 * i386-opc.h (DISP8_SHIFT_VL): New.
386 * i386-opc.tbl (Disp8ShiftVL): Define.
387 (various): Fold AVX512VL templates into their respective
388 AVX512F counterparts where possible, using Disp8ShiftVL and
389 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
390 IgnoreSize) as appropriate.
391 * i386-tbl.h: Re-generate.
392
c30be56e
JB		 3932018-07-19 Jan Beulich <jbeulich@suse.com>
394
395 * Makefile.am: Change dependencies and rule for
396 $(srcdir)/i386-init.h.
397 * Makefile.in: Re-generate.
398 * i386-gen.c (process_i386_opcodes): New local variable
399 "marker". Drop opening of input file. Recognize marker and line
400 number directives.
401 * i386-opc.tbl (OPCODE_I386_H): Define.
402 (i386-opc.h): Include it.
403 (None): Undefine.
404
11a322db
L		 4052018-07-18 H.J. Lu <hongjiu.lu@intel.com>
406
407 PR gas/23418
408 * i386-opc.h (Byte): Update comments.
409 (Word): Likewise.
410 (Dword): Likewise.
411 (Fword): Likewise.
412 (Qword): Likewise.
413 (Tbyte): Likewise.
414 (Xmmword): Likewise.
415 (Ymmword): Likewise.
416 (Zmmword): Likewise.
417 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
418 vcvttps2uqq.
419 * i386-tbl.h: Regenerated.
420
cde3679e
NC		 4212018-07-12 Sudakshina Das <sudi.das@arm.com>
422
423 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
424 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
425 * aarch64-asm-2.c: Regenerate.
426 * aarch64-dis-2.c: Regenerate.
427 * aarch64-opc-2.c: Regenerate.
428
45a28947
TC		 4292018-07-12 Tamar Christina <tamar.christina@arm.com>
430
431 PR binutils/23192
432 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
433 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
434 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
435 sqdmulh, sqrdmulh): Use Em16.
436
c597cc3d
SD		 4372018-07-11 Sudakshina Das <sudi.das@arm.com>
438
439 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
440 csdb together with them.
441 (thumb32_opcodes): Likewise.
442
a79eaed6
JB		 4432018-07-11 Jan Beulich <jbeulich@suse.com>
444
445 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
446 requiring 32-bit registers as operands 2 and 3. Improve
447 comments.
448 (mwait, mwaitx): Fold templates. Improve comments.
449 OPERAND_TYPE_INOUTPORTREG.
450 * i386-tbl.h: Re-generate.
451
2fb5be8d
JB		 4522018-07-11 Jan Beulich <jbeulich@suse.com>
453
454 * i386-gen.c (operand_type_init): Remove
455 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
456 OPERAND_TYPE_INOUTPORTREG.
457 * i386-init.h: Re-generate.
458
7f5cad30
JB		 4592018-07-11 Jan Beulich <jbeulich@suse.com>
460
461 * i386-opc.tbl (wrssd, wrussd): Add Dword.
462 (wrssq, wrussq): Add Qword.
463 * i386-tbl.h: Re-generate.
464
f0a85b07
JB		 4652018-07-11 Jan Beulich <jbeulich@suse.com>
466
467 * i386-opc.h: Rename OTMax to OTNum.
468 (OTNumOfUints): Adjust calculation.
469 (OTUnused): Directly alias to OTNum.
470
9dcb0ba4
MR		 4712018-07-09 Maciej W. Rozycki <macro@mips.com>
472
473 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
474 `reg_xys'.
475 (lea_reg_xys): Likewise.
476 (print_insn_loop_primitive): Rename `reg' local variable to
477 `reg_dxy'.
478
f311ba7e
TC		 4792018-07-06 Tamar Christina <tamar.christina@arm.com>
480
481 PR binutils/23242
482 * aarch64-tbl.h (ldarh): Fix disassembly mask.
483
cba05feb
TC		 4842018-07-06 Tamar Christina <tamar.christina@arm.com>
485
486 PR binutils/23369
487 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
488 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
489
471b9d15
MR		 4902018-07-02 Maciej W. Rozycki <macro@mips.com>
491
492 PR tdep/8282
493 * mips-dis.c (mips_option_arg_t): New enumeration.
494 (mips_options): New variable.
495 (disassembler_options_mips): New function.
496 (print_mips_disassembler_options): Reimplement in terms of
497 `disassembler_options_mips'.
498 * arm-dis.c (disassembler_options_arm): Adapt to using the
499 `disasm_options_and_args_t' structure.
500 * ppc-dis.c (disassembler_options_powerpc): Likewise.
501 * s390-dis.c (disassembler_options_s390): Likewise.
502
c0c468d5
TP		 5032018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
504
505 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
506 expected result.
507 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
508 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
509 * testsuite/ld-arm/tls-longplt.d: Likewise.
510
369c9167
TC		 5112018-06-29 Tamar Christina <tamar.christina@arm.com>
512
513 PR binutils/23192
514 * aarch64-asm-2.c: Regenerate.
515 * aarch64-dis-2.c: Likewise.
516 * aarch64-opc-2.c: Likewise.
517 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
518 * aarch64-opc.c (operand_general_constraint_met_p,
519 aarch64_print_operand): Likewise.
520 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
521 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
522 fmlal2, fmlsl2.
523 (AARCH64_OPERANDS): Add Em2.
524
30aa1306
NC		 5252018-06-26 Nick Clifton <nickc@redhat.com>
526
527 * po/uk.po: Updated Ukranian translation.
528 * po/de.po: Updated German translation.
529 * po/pt_BR.po: Updated Brazilian Portuguese translation.
530
eca4b721
NC		 5312018-06-26 Nick Clifton <nickc@redhat.com>
532
533 * nfp-dis.c: Fix spelling mistake.
534
71300e2c
NC		 5352018-06-24 Nick Clifton <nickc@redhat.com>
536
537 * configure: Regenerate.
538 * po/opcodes.pot: Regenerate.
539
719d8288
NC		 5402018-06-24 Nick Clifton <nickc@redhat.com>
541
542 2.31 branch created.
543
514cd3a0
TC		 5442018-06-19 Tamar Christina <tamar.christina@arm.com>
545
546 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
547 * aarch64-asm-2.c: Regenerate.
548 * aarch64-dis-2.c: Likewise.
549
385e4d0f
MR		 5502018-06-21 Maciej W. Rozycki <macro@mips.com>
551
552 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
553 `-M ginv' option description.
554
160d1b3d
SH		 5552018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
556
557 PR gas/23305
558 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
559 la and lla.
560
d0ac1c44
SM		 5612018-06-19 Simon Marchi <simon.marchi@ericsson.com>
562
563 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
564 * configure.ac: Remove AC_PREREQ.
565 * Makefile.in: Re-generate.
566 * aclocal.m4: Re-generate.
567 * configure: Re-generate.
568
6f20c942
FS		 5692018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
570
571 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
572 mips64r6 descriptors.
573 (parse_mips_ase_option): Handle -Mginv option.
574 (print_mips_disassembler_options): Document -Mginv.
575 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
576 (GINV): New macro.
577 (mips_opcodes): Define ginvi and ginvt.
578
730c3174
SE		 5792018-06-13 Scott Egerton <scott.egerton@imgtec.com>
580 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
581
582 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
583 * mips-opc.c (CRC, CRC64): New macros.
584 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
585 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
586 crc32cd for CRC64.
587
cb366992
EB		 5882018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
589
590 PR 20319
591 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
592 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
593
ce72cd46
AM		 5942018-06-06 Alan Modra <amodra@gmail.com>
595
596 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
597 setjmp. Move init for some other vars later too.
598
4b8e28c7
MF		 5992018-06-04 Max Filippov <jcmvbkbc@gmail.com>
600
601 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
602 (dis_private): Add new fields for property section tracking.
603 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
604 (xtensa_instruction_fits): New functions.
605 (fetch_data): Bump minimal fetch size to 4.
606 (print_insn_xtensa): Make struct dis_private static.
607 Load and prepare property table on section change.
608 Don't disassemble literals. Don't disassemble instructions that
609 cross property table boundaries.
610
55e99962
L		 6112018-06-01 H.J. Lu <hongjiu.lu@intel.com>
612
613 * configure: Regenerated.
614
733bd0ab
JB		 6152018-06-01 Jan Beulich <jbeulich@suse.com>
616
617 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
618 * i386-tbl.h: Re-generate.
619
dfd27d41
JB		 6202018-06-01 Jan Beulich <jbeulich@suse.com>
621
622 * i386-opc.tbl (sldt, str): Add NoRex64.
623 * i386-tbl.h: Re-generate.
624
64795710
JB		 6252018-06-01 Jan Beulich <jbeulich@suse.com>
626
627 * i386-opc.tbl (invpcid): Add Oword.
628 * i386-tbl.h: Re-generate.
629
030157d8
AM		 6302018-06-01 Alan Modra <amodra@gmail.com>
631
632 * sysdep.h (_bfd_error_handler): Don't declare.
633 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
634 * rl78-decode.opc: Likewise.
635 * msp430-decode.c: Regenerate.
636 * rl78-decode.c: Regenerate.
637
a9660a6f
AP		 6382018-05-30 Amit Pawar <Amit.Pawar@amd.com>
639
640 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
641 * i386-init.h : Regenerated.
642
277eb7f6
AM		 6432018-05-25 Alan Modra <amodra@gmail.com>
644
645 * Makefile.in: Regenerate.
646 * po/POTFILES.in: Regenerate.
647
98553ad3
PB		 6482018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
649
650 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
651 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
652 (insert_bab, extract_bab, insert_btab, extract_btab,
653 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
654 (BAT, BBA VBA RBS XB6S): Delete macros.
655 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
656 (BB, BD, RBX, XC6): Update for new macros.
657 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
658 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
659 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
660 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
661
7b4ae824
JD		 6622018-05-18 John Darrington <john@darrington.wattle.id.au>
663
664 * Makefile.am: Add support for s12z architecture.
665 * configure.ac: Likewise.
666 * disassemble.c: Likewise.
667 * disassemble.h: Likewise.
668 * Makefile.in: Regenerate.
669 * configure: Regenerate.
670 * s12z-dis.c: New file.
671 * s12z.h: New file.
672
29e0f0a1
AM		 6732018-05-18 Alan Modra <amodra@gmail.com>
674
675 * nfp-dis.c: Don't #include libbfd.h.
676 (init_nfp3200_priv): Use bfd_get_section_contents.
677 (nit_nfp6000_mecsr_sec): Likewise.
678
809276d2
NC		 6792018-05-17 Nick Clifton <nickc@redhat.com>
680
681 * po/zh_CN.po: Updated simplified Chinese translation.
682
ff329288
TC		 6832018-05-16 Tamar Christina <tamar.christina@arm.com>
684
685 PR binutils/23109
686 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
687 * aarch64-dis-2.c: Regenerate.
688
f9830ec1
TC		 6892018-05-15 Tamar Christina <tamar.christina@arm.com>
690
691 PR binutils/21446
692 * aarch64-asm.c (opintl.h): Include.
693 (aarch64_ins_sysreg): Enforce read/write constraints.
694 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
695 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
696 (F_REG_READ, F_REG_WRITE): New.
697 * aarch64-opc.c (aarch64_print_operand): Generate notes for
698 AARCH64_OPND_SYSREG.
699 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
700 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
701 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
702 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
703 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
704 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
705 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
706 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
707 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
708 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
709 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
710 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
711 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
712 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
713 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
714 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
715 msr (F_SYS_WRITE), mrs (F_SYS_READ).
716
7d02540a
TC		 7172018-05-15 Tamar Christina <tamar.christina@arm.com>
718
719 PR binutils/21446
720 * aarch64-dis.c (no_notes: New.
721 (parse_aarch64_dis_option): Support notes.
722 (aarch64_decode_insn, print_operands): Likewise.
723 (print_aarch64_disassembler_options): Document notes.
724 * aarch64-opc.c (aarch64_print_operand): Support notes.
725
561a72d4
TC		 7262018-05-15 Tamar Christina <tamar.christina@arm.com>
727
728 PR binutils/21446
729 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
730 and take error struct.
731 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
732 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
733 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
734 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
735 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
736 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
737 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
738 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
739 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
740 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
741 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
742 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
743 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
744 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
745 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
746 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
747 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
748 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
749 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
750 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
751 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
752 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
753 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
754 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
755 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
756 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
757 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
758 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
759 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
760 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
761 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
762 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
763 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
764 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
765 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
766 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
767 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
768 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
769 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
770 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
771 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
772 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
773 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
774 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
775 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
776 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
777 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
778 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
779 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
780 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
781 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
782 (determine_disassembling_preference, aarch64_decode_insn,
783 print_insn_aarch64_word, print_insn_data): Take errors struct.
784 (print_insn_aarch64): Use errors.
785 * aarch64-asm-2.c: Regenerate.
786 * aarch64-dis-2.c: Regenerate.
787 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
788 boolean in aarch64_insert_operan.
789 (print_operand_extractor): Likewise.
790 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
791
1678bd35
FT		 7922018-05-15 Francois H. Theron <francois.theron@netronome.com>
793
794 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
795
06cfb1c8
L		 7962018-05-09 H.J. Lu <hongjiu.lu@intel.com>
797
798 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
799
84f9f8c3
AM		 8002018-05-09 Sebastian Rasmussen <sebras@gmail.com>
801
802 * cr16-opc.c (cr16_instruction): Comment typo fix.
803 * hppa-dis.c (print_insn_hppa): Likewise.
804
e6f372ba
JW		 8052018-05-08 Jim Wilson <jimw@sifive.com>
806
807 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
808 (match_c_slli64, match_srxi_as_c_srxi): New.
809 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
810 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
811 <c.slli, c.srli, c.srai>: Use match_s_slli.
812 <c.slli64, c.srli64, c.srai64>: New.
813
f413a913
AM		 8142018-05-08 Alan Modra <amodra@gmail.com>
815
816 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
817 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
818 partition opcode space for index lookup.
819
a87a6478
PB		 8202018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
821
822 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
823 <insn_length>: ...with this. Update usage.
824 Remove duplicate call to *info->memory_error_func.
825
c0a30a9f
L		 8262018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
827 H.J. Lu <hongjiu.lu@intel.com>
828
829 * i386-dis.c (Gva): New.
830 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
831 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
832 (prefix_table): New instructions (see prefix above).
833 (mod_table): New instructions (see prefix above).
834 (OP_G): Handle va_mode.
835 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
836 CPU_MOVDIR64B_FLAGS.
837 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
838 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
839 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
840 * i386-opc.tbl: Add movidir{i,64b}.
841 * i386-init.h: Regenerated.
842 * i386-tbl.h: Likewise.
843
75c0a438
L		 8442018-05-07 H.J. Lu <hongjiu.lu@intel.com>
845
846 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
847 AddrPrefixOpReg.
848 * i386-opc.h (AddrPrefixOp0): Renamed to ...
849 (AddrPrefixOpReg): This.
850 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
851 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
852
2ceb7719
PB		 8532018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
854
855 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
856 (vle_num_opcodes): Likewise.
857 (spe2_num_opcodes): Likewise.
858 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
859 initialization loop.
860 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
861 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
862 only once.
863
b3ac5c6c
TC		 8642018-05-01 Tamar Christina <tamar.christina@arm.com>
865
866 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
867
fe944acf
FT		 8682018-04-30 Francois H. Theron <francois.theron@netronome.com>
869
870 Makefile.am: Added nfp-dis.c.
871 configure.ac: Added bfd_nfp_arch.
872 disassemble.h: Added print_insn_nfp prototype.
873 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
874 nfp-dis.c: New, for NFP support.
875 po/POTFILES.in: Added nfp-dis.c to the list.
876 Makefile.in: Regenerate.
877 configure: Regenerate.
878
e2195274
JB		 8792018-04-26 Jan Beulich <jbeulich@suse.com>
880
881 * i386-opc.tbl: Fold various non-memory operand AVX512VL
882 templates into their base ones.
883 * i386-tlb.h: Re-generate.
884
59ef5df4
JB		 8852018-04-26 Jan Beulich <jbeulich@suse.com>
886
887 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
888 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
889 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
890 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
891 * i386-init.h: Re-generate.
892
6e041cf4
JB		 8932018-04-26 Jan Beulich <jbeulich@suse.com>
894
895 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
896 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
897 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
898 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
899 comment.
900 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
901 and CpuRegMask.
902 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
903 CpuRegMask: Delete.
904 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
905 cpuregzmm, and cpuregmask.
906 * i386-init.h: Re-generate.
907 * i386-tbl.h: Re-generate.
908
0e0eea78
JB		 9092018-04-26 Jan Beulich <jbeulich@suse.com>
910
911 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
912 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
913 * i386-init.h: Re-generate.
914
2f1bada2
JB		 9152018-04-26 Jan Beulich <jbeulich@suse.com>
916
917 * i386-gen.c (VexImmExt): Delete.
918 * i386-opc.h (VexImmExt, veximmext): Delete.
919 * i386-opc.tbl: Drop all VexImmExt uses.
920 * i386-tlb.h: Re-generate.
921
bacd1457
JB		 9222018-04-25 Jan Beulich <jbeulich@suse.com>
923
924 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
925 register-only forms.
926 * i386-tlb.h: Re-generate.
927
10bba94b
TC		 9282018-04-25 Tamar Christina <tamar.christina@arm.com>
929
930 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
931
c48935d7
IT		 9322018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
933
934 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
935 PREFIX_0F1C.
936 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
937 (cpu_flags): Add CpuCLDEMOTE.
938 * i386-init.h: Regenerate.
939 * i386-opc.h (enum): Add CpuCLDEMOTE,
940 (i386_cpu_flags): Add cpucldemote.
941 * i386-opc.tbl: Add cldemote.
942 * i386-tbl.h: Regenerate.
943
211dc24b
AM		 9442018-04-16 Alan Modra <amodra@gmail.com>
945
946 * Makefile.am: Remove sh5 and sh64 support.
947 * configure.ac: Likewise.
948 * disassemble.c: Likewise.
949 * disassemble.h: Likewise.
950 * sh-dis.c: Likewise.
951 * sh64-dis.c: Delete.
952 * sh64-opc.c: Delete.
953 * sh64-opc.h: Delete.
954 * Makefile.in: Regenerate.
955 * configure: Regenerate.
956 * po/POTFILES.in: Regenerate.
957
a9a4b302
AM		 9582018-04-16 Alan Modra <amodra@gmail.com>
959
960 * Makefile.am: Remove w65 support.
961 * configure.ac: Likewise.
962 * disassemble.c: Likewise.
963 * disassemble.h: Likewise.
964 * w65-dis.c: Delete.
965 * w65-opc.h: Delete.
966 * Makefile.in: Regenerate.
967 * configure: Regenerate.
968 * po/POTFILES.in: Regenerate.
969
04cb01fd
AM		 9702018-04-16 Alan Modra <amodra@gmail.com>
971
972 * configure.ac: Remove we32k support.
973 * configure: Regenerate.
974
c2bf1eec
AM		 9752018-04-16 Alan Modra <amodra@gmail.com>
976
977 * Makefile.am: Remove m88k support.
978 * configure.ac: Likewise.
979 * disassemble.c: Likewise.
980 * disassemble.h: Likewise.
981 * m88k-dis.c: Delete.
982 * Makefile.in: Regenerate.
983 * configure: Regenerate.
984 * po/POTFILES.in: Regenerate.
985
6793974d
AM		 9862018-04-16 Alan Modra <amodra@gmail.com>
987
988 * Makefile.am: Remove i370 support.
989 * configure.ac: Likewise.
990 * disassemble.c: Likewise.
991 * disassemble.h: Likewise.
992 * i370-dis.c: Delete.
993 * i370-opc.c: Delete.
994 * Makefile.in: Regenerate.
995 * configure: Regenerate.
996 * po/POTFILES.in: Regenerate.
997
e82aa794
AM		 9982018-04-16 Alan Modra <amodra@gmail.com>
999
1000 * Makefile.am: Remove h8500 support.
1001 * configure.ac: Likewise.
1002 * disassemble.c: Likewise.
1003 * disassemble.h: Likewise.
1004 * h8500-dis.c: Delete.
1005 * h8500-opc.h: Delete.
1006 * Makefile.in: Regenerate.
1007 * configure: Regenerate.
1008 * po/POTFILES.in: Regenerate.
1009
fceadf09
AM		 10102018-04-16 Alan Modra <amodra@gmail.com>
1011
1012 * configure.ac: Remove tahoe support.
1013 * configure: Regenerate.
1014
ae1d3843
L		 10152018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1016
1017 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1018 umwait.
1019 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1020 64-bit mode.
1021 * i386-tbl.h: Regenerated.
1022
de89d0a3
IT		 10232018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1024
1025 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1026 PREFIX_MOD_1_0FAE_REG_6.
1027 (va_mode): New.
1028 (OP_E_register): Use va_mode.
1029 * i386-dis-evex.h (prefix_table):
1030 New instructions (see prefixes above).
1031 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1032 (cpu_flags): Likewise.
1033 * i386-opc.h (enum): Likewise.
1034 (i386_cpu_flags): Likewise.
1035 * i386-opc.tbl: Add umonitor, umwait, tpause.
1036 * i386-init.h: Regenerate.
1037 * i386-tbl.h: Likewise.
1038
a8eb42a8
AM		 10392018-04-11 Alan Modra <amodra@gmail.com>
1040
1041 * opcodes/i860-dis.c: Delete.
1042 * opcodes/i960-dis.c: Delete.
1043 * Makefile.am: Remove i860 and i960 support.
1044 * configure.ac: Likewise.
1045 * disassemble.c: Likewise.
1046 * disassemble.h: Likewise.
1047 * Makefile.in: Regenerate.
1048 * configure: Regenerate.
1049 * po/POTFILES.in: Regenerate.
1050
caf0678c
L		 10512018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1052
1053 PR binutils/23025
1054 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1055 to 0.
1056 (print_insn): Clear vex instead of vex.evex.
1057
4fb0d2b9
NC		 10582018-04-04 Nick Clifton <nickc@redhat.com>
1059
1060 * po/es.po: Updated Spanish translation.
1061
c39e5b26
JB		 10622018-03-28 Jan Beulich <jbeulich@suse.com>
1063
1064 * i386-gen.c (opcode_modifiers): Delete VecESize.
1065 * i386-opc.h (VecESize): Delete.
1066 (struct i386_opcode_modifier): Delete vecesize.
1067 * i386-opc.tbl: Drop VecESize.
1068 * i386-tlb.h: Re-generate.
1069
8e6e0792
JB		 10702018-03-28 Jan Beulich <jbeulich@suse.com>
1071
1072 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1073 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1074 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1075 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1076 * i386-tlb.h: Re-generate.
1077
9f123b91
JB		 10782018-03-28 Jan Beulich <jbeulich@suse.com>
1079
1080 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1081 Fold AVX512 forms
1082 * i386-tlb.h: Re-generate.
1083
9646c87b
JB		 10842018-03-28 Jan Beulich <jbeulich@suse.com>
1085
1086 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1087 (vex_len_table): Drop Y for vcvt*2si.
1088 (putop): Replace plain 'Y' handling by abort().
1089
c8d59609
NC		 10902018-03-28 Nick Clifton <nickc@redhat.com>
1091
1092 PR 22988
1093 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1094 instructions with only a base address register.
1095 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1096 handle AARHC64_OPND_SVE_ADDR_R.
1097 (aarch64_print_operand): Likewise.
1098 * aarch64-asm-2.c: Regenerate.
1099 * aarch64_dis-2.c: Regenerate.
1100 * aarch64-opc-2.c: Regenerate.
1101
b8c169f3
JB		 11022018-03-22 Jan Beulich <jbeulich@suse.com>
1103
1104 * i386-opc.tbl: Drop VecESize from register only insn forms and
1105 memory forms not allowing broadcast.
1106 * i386-tlb.h: Re-generate.
1107
96bc132a
JB		 11082018-03-22 Jan Beulich <jbeulich@suse.com>
1109
1110 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1111 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1112 sha256*): Drop Disp<N>.
1113
9f79e886
JB		 11142018-03-22 Jan Beulich <jbeulich@suse.com>
1115
1116 * i386-dis.c (EbndS, bnd_swap_mode): New.
1117 (prefix_table): Use EbndS.
1118 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1119 * i386-opc.tbl (bndmov): Move misplaced Load.
1120 * i386-tlb.h: Re-generate.
1121
d6793fa1
JB		 11222018-03-22 Jan Beulich <jbeulich@suse.com>
1123
1124 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1125 templates allowing memory operands and folded ones for register
1126 only flavors.
1127 * i386-tlb.h: Re-generate.
1128
f7768225
JB		 11292018-03-22 Jan Beulich <jbeulich@suse.com>
1130
1131 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1132 256-bit templates. Drop redundant leftover Disp<N>.
1133 * i386-tlb.h: Re-generate.
1134
0e35537d
JW		 11352018-03-14 Kito Cheng <kito.cheng@gmail.com>
1136
1137 * riscv-opc.c (riscv_insn_types): New.
1138
b4a3689a
NC		 11392018-03-13 Nick Clifton <nickc@redhat.com>
1140
1141 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1142
d3d50934
L		 11432018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1144
1145 * i386-opc.tbl: Add Optimize to clr.
1146 * i386-tbl.h: Regenerated.
1147
bd5dea88
L		 11482018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1149
1150 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1151 * i386-opc.h (OldGcc): Removed.
1152 (i386_opcode_modifier): Remove oldgcc.
1153 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1154 instructions for old (<= 2.8.1) versions of gcc.
1155 * i386-tbl.h: Regenerated.
1156
e771e7c9
JB		 11572018-03-08 Jan Beulich <jbeulich@suse.com>
1158
1159 * i386-opc.h (EVEXDYN): New.
1160 * i386-opc.tbl: Fold various AVX512VL templates.
1161 * i386-tlb.h: Re-generate.
1162
ed438a93
JB		 11632018-03-08 Jan Beulich <jbeulich@suse.com>
1164
1165 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1166 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1167 vpexpandd, vpexpandq): Fold AFX512VF templates.
1168 * i386-tlb.h: Re-generate.
1169
454172a9
JB		 11702018-03-08 Jan Beulich <jbeulich@suse.com>
1171
1172 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1173 Fold 128- and 256-bit VEX-encoded templates.
1174 * i386-tlb.h: Re-generate.
1175
36824150
JB		 11762018-03-08 Jan Beulich <jbeulich@suse.com>
1177
1178 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1179 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1180 vpexpandd, vpexpandq): Fold AVX512F templates.
1181 * i386-tlb.h: Re-generate.
1182
e7f5c0a9
JB		 11832018-03-08 Jan Beulich <jbeulich@suse.com>
1184
1185 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1186 64-bit templates. Drop Disp<N>.
1187 * i386-tlb.h: Re-generate.
1188
25a4277f
JB		 11892018-03-08 Jan Beulich <jbeulich@suse.com>
1190
1191 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1192 and 256-bit templates.
1193 * i386-tlb.h: Re-generate.
1194
d2224064
JB		 11952018-03-08 Jan Beulich <jbeulich@suse.com>
1196
1197 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1198 * i386-tlb.h: Re-generate.
1199
1b193f0b
JB		 12002018-03-08 Jan Beulich <jbeulich@suse.com>
1201
1202 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1203 Drop NoAVX.
1204 * i386-tlb.h: Re-generate.
1205
f2f6a710
JB		 12062018-03-08 Jan Beulich <jbeulich@suse.com>
1207
1208 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1209 * i386-tlb.h: Re-generate.
1210
38e314eb
JB		 12112018-03-08 Jan Beulich <jbeulich@suse.com>
1212
1213 * i386-gen.c (opcode_modifiers): Delete FloatD.
1214 * i386-opc.h (FloatD): Delete.
1215 (struct i386_opcode_modifier): Delete floatd.
1216 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1217 FloatD by D.
1218 * i386-tlb.h: Re-generate.
1219
d53e6b98
JB		 12202018-03-08 Jan Beulich <jbeulich@suse.com>
1221
1222 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1223
2907c2f5
JB		 12242018-03-08 Jan Beulich <jbeulich@suse.com>
1225
1226 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1227 * i386-tlb.h: Re-generate.
1228
73053c1f
JB		 12292018-03-08 Jan Beulich <jbeulich@suse.com>
1230
1231 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1232 forms.
1233 * i386-tlb.h: Re-generate.
1234
52fe4420
AM		 12352018-03-07 Alan Modra <amodra@gmail.com>
1236
1237 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1238 bfd_arch_rs6000.
1239 * disassemble.h (print_insn_rs6000): Delete.
1240 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1241 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1242 (print_insn_rs6000): Delete.
1243
a6743a54
AM		 12442018-03-03 Alan Modra <amodra@gmail.com>
1245
1246 * sysdep.h (opcodes_error_handler): Define.
1247 (_bfd_error_handler): Declare.
1248 * Makefile.am: Remove stray #.
1249 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1250 EDIT" comment.
1251 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1252 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1253 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1254 opcodes_error_handler to print errors. Standardize error messages.
1255 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1256 and include opintl.h.
1257 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1258 * i386-gen.c: Standardize error messages.
1259 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1260 * Makefile.in: Regenerate.
1261 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1262 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1263 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1264 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1265 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1266 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1267 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1268 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1269 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1270 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1271 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1272 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1273 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1274
8305403a
L		 12752018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1276
1277 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1278 vpsub[bwdq] instructions.
1279 * i386-tbl.h: Regenerated.
1280
e184813f
AM		 12812018-03-01 Alan Modra <amodra@gmail.com>
1282
1283 * configure.ac (ALL_LINGUAS): Sort.
1284 * configure: Regenerate.
1285
5b616bef
TP		 12862018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1287
1288 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1289 macro by assignements.
1290
b6f8c7c4
L		 12912018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1292
1293 PR gas/22871
1294 * i386-gen.c (opcode_modifiers): Add Optimize.
1295 * i386-opc.h (Optimize): New enum.
1296 (i386_opcode_modifier): Add optimize.
1297 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1298 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1299 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1300 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1301 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1302 vpxord and vpxorq.
1303 * i386-tbl.h: Regenerated.
1304
e95b887f
AM		 13052018-02-26 Alan Modra <amodra@gmail.com>
1306
1307 * crx-dis.c (getregliststring): Allocate a large enough buffer
1308 to silence false positive gcc8 warning.
1309
0bccfb29
JW		 13102018-02-22 Shea Levy <shea@shealevy.com>
1311
1312 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1313
6b6b6807
L		 13142018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1315
1316 * i386-opc.tbl: Add {rex},
1317 * i386-tbl.h: Regenerated.
1318
75f31665
MR		 13192018-02-20 Maciej W. Rozycki <macro@mips.com>
1320
1321 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1322 (mips16_opcodes): Replace `M' with `m' for "restore".
1323
e207bc53
TP		 13242018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1325
1326 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1327
87993319
MR		 13282018-02-13 Maciej W. Rozycki <macro@mips.com>
1329
1330 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1331 variable to `function_index'.
1332
68d20676
NC		 13332018-02-13 Nick Clifton <nickc@redhat.com>
1334
1335 PR 22823
1336 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1337 about truncation of printing.
1338
d2159fdc
HW		 13392018-02-12 Henry Wong <henry@stuffedcow.net>
1340
1341 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1342
f174ef9f
NC		 13432018-02-05 Nick Clifton <nickc@redhat.com>
1344
1345 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1346
be3a8dca
IT		 13472018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1348
1349 * i386-dis.c (enum): Add pconfig.
1350 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1351 (cpu_flags): Add CpuPCONFIG.
1352 * i386-opc.h (enum): Add CpuPCONFIG.
1353 (i386_cpu_flags): Add cpupconfig.
1354 * i386-opc.tbl: Add PCONFIG instruction.
1355 * i386-init.h: Regenerate.
1356 * i386-tbl.h: Likewise.
1357
3233d7d0
IT		 13582018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1359
1360 * i386-dis.c (enum): Add PREFIX_0F09.
1361 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1362 (cpu_flags): Add CpuWBNOINVD.
1363 * i386-opc.h (enum): Add CpuWBNOINVD.
1364 (i386_cpu_flags): Add cpuwbnoinvd.
1365 * i386-opc.tbl: Add WBNOINVD instruction.
1366 * i386-init.h: Regenerate.
1367 * i386-tbl.h: Likewise.
1368
e925c834
JW		 13692018-01-17 Jim Wilson <jimw@sifive.com>
1370
1371 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1372
d777820b
IT		 13732018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1374
1375 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1376 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1377 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1378 (cpu_flags): Add CpuIBT, CpuSHSTK.
1379 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1380 (i386_cpu_flags): Add cpuibt, cpushstk.
1381 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1382 * i386-init.h: Regenerate.
1383 * i386-tbl.h: Likewise.
1384
f6efed01
NC		 13852018-01-16 Nick Clifton <nickc@redhat.com>
1386
1387 * po/pt_BR.po: Updated Brazilian Portugese translation.
1388 * po/de.po: Updated German translation.
1389
2721d702
JW		 13902018-01-15 Jim Wilson <jimw@sifive.com>
1391
1392 * riscv-opc.c (match_c_nop): New.
1393 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1394
616dcb87
NC		 13952018-01-15 Nick Clifton <nickc@redhat.com>
1396
1397 * po/uk.po: Updated Ukranian translation.
1398
3957a496
NC		 13992018-01-13 Nick Clifton <nickc@redhat.com>
1400
1401 * po/opcodes.pot: Regenerated.
1402
769c7ea5
NC		 14032018-01-13 Nick Clifton <nickc@redhat.com>
1404
1405 * configure: Regenerate.
1406
faf766e3
NC		 14072018-01-13 Nick Clifton <nickc@redhat.com>
1408
1409 2.30 branch created.
1410
888a89da
IT		 14112018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1412
1413 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1414 * i386-tbl.h: Regenerate.
1415
cbda583a
JB		 14162018-01-10 Jan Beulich <jbeulich@suse.com>
1417
1418 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1419 * i386-tbl.h: Re-generate.
1420
c9e92278
JB		 14212018-01-10 Jan Beulich <jbeulich@suse.com>
1422
1423 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1424 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1425 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1426 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1427 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1428 Disp8MemShift of AVX512VL forms.
1429 * i386-tbl.h: Re-generate.
1430
35fd2b2b
JW		 14312018-01-09 Jim Wilson <jimw@sifive.com>
1432
1433 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1434 then the hi_addr value is zero.
1435
91d8b670
JG		 14362018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1437
1438 * arm-dis.c (arm_opcodes): Add csdb.
1439 (thumb32_opcodes): Add csdb.
1440
be2e7d95
JG		 14412018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1442
1443 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1444 * aarch64-asm-2.c: Regenerate.
1445 * aarch64-dis-2.c: Regenerate.
1446 * aarch64-opc-2.c: Regenerate.
1447
704a705d
L		 14482018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1449
1450 PR gas/22681
1451 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1452 Remove AVX512 vmovd with 64-bit operands.
1453 * i386-tbl.h: Regenerated.
1454
35eeb78f
JW		 14552018-01-05 Jim Wilson <jimw@sifive.com>
1456
1457 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1458 jalr.
1459
219d1afa
AM		 14602018-01-03 Alan Modra <amodra@gmail.com>
1461
1462 Update year range in copyright notice of all files.
1463
1508bbf5
JB		 14642018-01-02 Jan Beulich <jbeulich@suse.com>
1465
1466 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1467 and OPERAND_TYPE_REGZMM entries.
1468
1e563868 1469For older changes see ChangeLog-2017
3499769a 1470\f
1e563868 1471Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1472
1473Copying and distribution of this file, with or without modification,
1474are permitted in any medium without royalty provided the copyright
1475notice and this notice are preserved.
1476
1477Local Variables:
1478mode: change-log
1479left-margin: 8
1480fill-column: 74
1481version-control: never
1482End:
GDB Binutils - Deliverables
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