projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
x86: convert SReg from bitfield to enumerator
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
00cee14f
JB		 12019-11-08 Jan Beulich <jbeulich@suse.com>
2
3 * i386-gen.c (operand_type_init): Add Class= to
4 OPERAND_TYPE_SREG entry.
5 (operand_classes): Add SReg entry.
6 (operand_types): Drop SReg entry.
7 * i386-opc.h (enum operand_class): Add SReg.
8 (SReg): Delete.
9 (union i386_operand_type): Remove sreg field.
10 * i386-opc.tbl (SReg): Define.
11 * i386-reg.tbl: Replace SReg by Class=SReg.
12 * i386-init.h, i386-tbl.h: Re-generate.
13
bab6aec1
JB		 142019-11-08 Jan Beulich <jbeulich@suse.com>
15
16 * i386-gen.c (operand_type_init): Add Class=. New
17 OPERAND_TYPE_ANYIMM entry.
18 (operand_classes): New.
19 (operand_types): Drop Reg entry.
20 (output_operand_type): New parameter "class". Process it.
21 (process_i386_operand_type): New local variable "class".
22 (main): Adjust static assertions.
23 * i386-opc.h (CLASS_WIDTH): Define.
24 (enum operand_class): New.
25 (Reg): Replace by Class. Adjust comment.
26 (union i386_operand_type): Replace reg by class.
27 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
28 Class=.
29 * i386-reg.tbl: Replace Reg by Class=Reg.
30 * i386-init.h: Re-generate.
31
1f4cd317
MM		 322019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
33
34 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
35 (aarch64_opcode_table): Add data gathering hint mnemonic.
36 * opcodes/aarch64-dis-2.c: Account for new instruction.
37
616ce08e
MM		 382019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
39
40 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
41
42
8382113f
MM		 432019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
44
45 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
46 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
47 aarch64_feature_f64mm): New feature sets.
48 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
49 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
50 instructions.
51 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
52 macros.
53 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
54 (OP_SVE_QQQ): New qualifier.
55 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
56 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
57 the movprfx constraint.
58 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
59 (aarch64_opcode_table): Define new instructions smmla,
60 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
61 uzip{1/2}, trn{1/2}.
62 * aarch64-opc.c (operand_general_constraint_met_p): Handle
63 AARCH64_OPND_SVE_ADDR_RI_S4x32.
64 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
65 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
66 Account for new instructions.
67 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
68 S4x32 operand.
69 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
70
aab2c27d
MM		 712019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
722019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
73
74 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
75 Armv8.6-A.
76 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
77 (neon_opcodes): Add bfloat SIMD instructions.
78 (print_insn_coprocessor): Add new control character %b to print
79 condition code without checking cp_num.
80 (print_insn_neon): Account for BFloat16 instructions that have no
81 special top-byte handling.
82
33593eaf
MM		 832019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
842019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
85
86 * arm-dis.c (print_insn_coprocessor,
87 print_insn_generic_coprocessor): Create wrapper functions around
88 the implementation of the print_insn_coprocessor control codes.
89 (print_insn_coprocessor_1): Original print_insn_coprocessor
90 function that now takes which array to look at as an argument.
91 (print_insn_arm): Use both print_insn_coprocessor and
92 print_insn_generic_coprocessor.
93 (print_insn_thumb32): As above.
94
df678013
MM		 952019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
962019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
97
98 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
99 in reglane special case.
100 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
101 aarch64_find_next_opcode): Account for new instructions.
102 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
103 in reglane special case.
104 * aarch64-opc.c (struct operand_qualifier_data): Add data for
105 new AARCH64_OPND_QLF_S_2H qualifier.
106 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
107 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
108 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
109 sets.
110 (BFLOAT_SVE, BFLOAT): New feature set macros.
111 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
112 instructions.
113 (aarch64_opcode_table): Define new instructions bfdot,
114 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
115 bfcvtn2, bfcvt.
116
8ae2d3d9
MM		 1172019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
1182019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
119
120 * aarch64-tbl.h (ARMV8_6): New macro.
121
142861df
JB		 1222019-11-07 Jan Beulich <jbeulich@suse.com>
123
124 * i386-dis.c (prefix_table): Add mcommit.
125 (rm_table): Add rdpru.
126 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
127 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
128 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
129 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
130 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
131 * i386-opc.tbl (mcommit, rdpru): New.
132 * i386-init.h, i386-tbl.h: Re-generate.
133
081e283f
JB		 1342019-11-07 Jan Beulich <jbeulich@suse.com>
135
136 * i386-dis.c (OP_Mwait): Drop local variable "names", use
137 "names32" instead.
138 (OP_Monitor): Drop local variable "op1_names", re-purpose
139 "names" for it instead, and replace former "names" uses by
140 "names32" ones.
141
c050c89a
JB		 1422019-11-07 Jan Beulich <jbeulich@suse.com>
143
144 PR/gas 25167
145 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
146 operand-less forms.
147 * opcodes/i386-tbl.h: Re-generate.
148
7abb8d81
JB		 1492019-11-05 Jan Beulich <jbeulich@suse.com>
150
151 * i386-dis.c (OP_Mwaitx): Delete.
152 (prefix_table): Use OP_Mwait for mwaitx entry.
153 (OP_Mwait): Also handle mwaitx.
154
267b8516
JB		 1552019-11-05 Jan Beulich <jbeulich@suse.com>
156
157 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
158 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
159 (prefix_table): Add respective entries.
160 (rm_table): Link to those entries.
161
f8687e93
JB		 1622019-11-05 Jan Beulich <jbeulich@suse.com>
163
164 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
165 (REG_0F1C_P_0_MOD_0): ... this.
166 (REG_0F1E_MOD_3): Rename to ...
167 (REG_0F1E_P_1_MOD_3): ... this.
168 (RM_0F01_REG_5): Rename to ...
169 (RM_0F01_REG_5_MOD_3): ... this.
170 (RM_0F01_REG_7): Rename to ...
171 (RM_0F01_REG_7_MOD_3): ... this.
172 (RM_0F1E_MOD_3_REG_7): Rename to ...
173 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
174 (RM_0FAE_REG_6): Rename to ...
175 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
176 (RM_0FAE_REG_7): Rename to ...
177 (RM_0FAE_REG_7_MOD_3): ... this.
178 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
179 (PREFIX_0F01_REG_5_MOD_0): ... this.
180 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
181 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
182 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
183 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
184 (PREFIX_0FAE_REG_0): Rename to ...
185 (PREFIX_0FAE_REG_0_MOD_3): ... this.
186 (PREFIX_0FAE_REG_1): Rename to ...
187 (PREFIX_0FAE_REG_1_MOD_3): ... this.
188 (PREFIX_0FAE_REG_2): Rename to ...
189 (PREFIX_0FAE_REG_2_MOD_3): ... this.
190 (PREFIX_0FAE_REG_3): Rename to ...
191 (PREFIX_0FAE_REG_3_MOD_3): ... this.
192 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
193 (PREFIX_0FAE_REG_4_MOD_0): ... this.
194 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
195 (PREFIX_0FAE_REG_4_MOD_3): ... this.
196 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
197 (PREFIX_0FAE_REG_5_MOD_0): ... this.
198 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
199 (PREFIX_0FAE_REG_5_MOD_3): ... this.
200 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
201 (PREFIX_0FAE_REG_6_MOD_0): ... this.
202 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
203 (PREFIX_0FAE_REG_6_MOD_3): ... this.
204 (PREFIX_0FAE_REG_7): Rename to ...
205 (PREFIX_0FAE_REG_7_MOD_0): ... this.
206 (PREFIX_MOD_0_0FC3): Rename to ...
207 (PREFIX_0FC3_MOD_0): ... this.
208 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
209 (PREFIX_0FC7_REG_6_MOD_0): ... this.
210 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
211 (PREFIX_0FC7_REG_6_MOD_3): ... this.
212 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
213 (PREFIX_0FC7_REG_7_MOD_3): ... this.
214 (reg_table, prefix_table, mod_table, rm_table): Adjust
215 accordingly.
216
5103274f
NC		 2172019-11-04 Nick Clifton <nickc@redhat.com>
218
219 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
220 of a v850 system register. Move the v850_sreg_names array into
221 this function.
222 (get_v850_reg_name): Likewise for ordinary register names.
223 (get_v850_vreg_name): Likewise for vector register names.
224 (get_v850_cc_name): Likewise for condition codes.
225 * get_v850_float_cc_name): Likewise for floating point condition
226 codes.
227 (get_v850_cacheop_name): Likewise for cache-ops.
228 (get_v850_prefop_name): Likewise for pref-ops.
229 (disassemble): Use the new accessor functions.
230
1820262b
DB		 2312019-10-30 Delia Burduv <delia.burduv@arm.com>
232
233 * aarch64-opc.c (print_immediate_offset_address): Don't print the
234 immediate for the writeback form of ldraa/ldrab if it is 0.
235 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
236 * aarch64-opc-2.c: Regenerated.
237
3cc17af5
JB		 2382019-10-30 Jan Beulich <jbeulich@suse.com>
239
240 * i386-gen.c (operand_type_shorthands): Delete.
241 (operand_type_init): Expand previous shorthands.
242 (set_bitfield_from_shorthand): Rename back to ...
243 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
244 of operand_type_init[].
245 (set_bitfield): Adjust call to the above function.
246 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
247 RegXMM, RegYMM, RegZMM): Define.
248 * i386-reg.tbl: Expand prior shorthands.
249
a2cebd03
JB		 2502019-10-30 Jan Beulich <jbeulich@suse.com>
251
252 * i386-gen.c (output_i386_opcode): Change order of fields
253 emitted to output.
254 * i386-opc.h (struct insn_template): Move operands field.
255 Convert extension_opcode field to unsigned short.
256 * i386-tbl.h: Re-generate.
257
507916b8
JB		 2582019-10-30 Jan Beulich <jbeulich@suse.com>
259
260 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
261 of W.
262 * i386-opc.h (W): Extend comment.
263 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
264 general purpose variants not allowing for byte operands.
265 * i386-tbl.h: Re-generate.
266
efea62b4
NC		 2672019-10-29 Nick Clifton <nickc@redhat.com>
268
269 * tic30-dis.c (print_branch): Correct size of operand array.
270
9adb2591
NC		 2712019-10-29 Nick Clifton <nickc@redhat.com>
272
273 * d30v-dis.c (print_insn): Check that operand index is valid
274 before attempting to access the operands array.
275
993a00a9
NC		 2762019-10-29 Nick Clifton <nickc@redhat.com>
277
278 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
279 locating the bit to be tested.
280
66a66a17
NC		 2812019-10-29 Nick Clifton <nickc@redhat.com>
282
283 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
284 values.
285 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
286 (print_insn_s12z): Check for illegal size values.
287
1ee3542c
NC		 2882019-10-28 Nick Clifton <nickc@redhat.com>
289
290 * csky-dis.c (csky_chars_to_number): Check for a negative
291 count. Use an unsigned integer to construct the return value.
292
bbf9a0b5
NC		 2932019-10-28 Nick Clifton <nickc@redhat.com>
294
295 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
296 operand buffer. Set value to 15 not 13.
297 (get_register_operand): Use OPERAND_BUFFER_LEN.
298 (get_indirect_operand): Likewise.
299 (print_two_operand): Likewise.
300 (print_three_operand): Likewise.
301 (print_oar_insn): Likewise.
302
d1e304bc
NC		 3032019-10-28 Nick Clifton <nickc@redhat.com>
304
305 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
306 (bit_extract_simple): Likewise.
307 (bit_copy): Likewise.
308 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
309 index_offset array are not accessed.
310
dee33451
NC		 3112019-10-28 Nick Clifton <nickc@redhat.com>
312
313 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
314 operand.
315
27cee81d
NC		 3162019-10-25 Nick Clifton <nickc@redhat.com>
317
318 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
319 access to opcodes.op array element.
320
de6d8dc2
NC		 3212019-10-23 Nick Clifton <nickc@redhat.com>
322
323 * rx-dis.c (get_register_name): Fix spelling typo in error
324 message.
325 (get_condition_name, get_flag_name, get_double_register_name)
326 (get_double_register_high_name, get_double_register_low_name)
327 (get_double_control_register_name, get_double_condition_name)
328 (get_opsize_name, get_size_name): Likewise.
329
6207ed28
NC		 3302019-10-22 Nick Clifton <nickc@redhat.com>
331
332 * rx-dis.c (get_size_name): New function. Provides safe
333 access to name array.
334 (get_opsize_name): Likewise.
335 (print_insn_rx): Use the accessor functions.
336
12234dfd
NC		 3372019-10-16 Nick Clifton <nickc@redhat.com>
338
339 * rx-dis.c (get_register_name): New function. Provides safe
340 access to name array.
341 (get_condition_name, get_flag_name, get_double_register_name)
342 (get_double_register_high_name, get_double_register_low_name)
343 (get_double_control_register_name, get_double_condition_name):
344 Likewise.
345 (print_insn_rx): Use the accessor functions.
346
1d378749
NC		 3472019-10-09 Nick Clifton <nickc@redhat.com>
348
349 PR 25041
350 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
351 instructions.
352
d241b910
JB		 3532019-10-07 Jan Beulich <jbeulich@suse.com>
354
355 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
356 (cmpsd): Likewise. Move EsSeg to other operand.
357 * opcodes/i386-tbl.h: Re-generate.
358
f5c5b7c1
AM		 3592019-09-23 Alan Modra <amodra@gmail.com>
360
361 * m68k-dis.c: Include cpu-m68k.h
362
7beeaeb8
AM		 3632019-09-23 Alan Modra <amodra@gmail.com>
364
365 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
366 "elf/mips.h" earlier.
367
3f9aad11
JB		 3682018-09-20 Jan Beulich <jbeulich@suse.com>
369
370 PR gas/25012
371 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
372 with SReg operand.
373 * i386-tbl.h: Re-generate.
374
fd361982
AM		 3752019-09-18 Alan Modra <amodra@gmail.com>
376
377 * arc-ext.c: Update throughout for bfd section macro changes.
378
e0b2a78c
SM		 3792019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
380
381 * Makefile.in: Re-generate.
382 * configure: Re-generate.
383
7e9ad3a3
JW		 3842019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
385
386 * riscv-opc.c (riscv_opcodes): Change subset field
387 to insn_class field for all instructions.
388 (riscv_insn_types): Likewise.
389
bb695960
PB		 3902019-09-16 Phil Blundell <pb@pbcl.net>
391
392 * configure: Regenerated.
393
8063ab7e
MV		 3942019-09-10 Miod Vallat <miod@online.fr>
395
396 PR 24982
397 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
398
60391a25
PB		 3992019-09-09 Phil Blundell <pb@pbcl.net>
400
401 binutils 2.33 branch created.
402
f44b758d
NC		 4032019-09-03 Nick Clifton <nickc@redhat.com>
404
405 PR 24961
406 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
407 greater than zero before indexing via (bufcnt -1).
408
1e4b5e7d
NC		 4092019-09-03 Nick Clifton <nickc@redhat.com>
410
411 PR 24958
412 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
413 (MAX_SPEC_REG_NAME_LEN): Define.
414 (struct mmix_dis_info): Use defined constants for array lengths.
415 (get_reg_name): New function.
416 (get_sprec_reg_name): New function.
417 (print_insn_mmix): Use new functions.
418
c4a23bf8
SP		 4192019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
420
421 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
422 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
423 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
424
a051e2f3
KT		 4252019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
426
427 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
428 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
429 (aarch64_sys_reg_supported_p): Update checks for the above.
430
08132bdd
SP		 4312019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
432
433 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
434 cases MVE_SQRSHRL and MVE_UQRSHLL.
435 (print_insn_mve): Add case for specifier 'k' to check
436 specific bit of the instruction.
437
d88bdcb4
PA		 4382019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
439
440 PR 24854
441 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
442 encountering an unknown machine type.
443 (print_insn_arc): Handle arc_insn_length returning 0. In error
444 cases return -1 rather than calling abort.
445
bc750500
JB		 4462019-08-07 Jan Beulich <jbeulich@suse.com>
447
448 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
449 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
450 IgnoreSize.
451 * i386-tbl.h: Re-generate.
452
23d188c7
BW		 4532019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
454
455 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
456 instructions.
457
c0d6f62f
JW		 4582019-07-30 Mel Chen <mel.chen@sifive.com>
459
460 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
461 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
462
463 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
464 fscsr.
465
0f3f7167
CZ		 4662019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
467
468 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
469 and MPY class instructions.
470 (parse_option): Add nps400 option.
471 (print_arc_disassembler_options): Add nps400 info.
472
7e126ba3
CZ		 4732019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
474
475 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
476 (bspop): Likewise.
477 (modapp): Likewise.
478 * arc-opc.c (RAD_CHK): Add.
479 * arc-tbl.h: Regenerate.
480
a028026d
KT		 4812019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
482
483 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
484 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
485
ac79ff9e
NC		 4862019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
487
488 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
489 instructions as UNPREDICTABLE.
490
231097b0
JM		 4912019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
492
493 * bpf-desc.c: Regenerated.
494
1d942ae9
JB		 4952019-07-17 Jan Beulich <jbeulich@suse.com>
496
497 * i386-gen.c (static_assert): Define.
498 (main): Use it.
499 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
500 (Opcode_Modifier_Num): ... this.
501 (Mem): Delete.
502
dfd69174
JB		 5032019-07-16 Jan Beulich <jbeulich@suse.com>
504
505 * i386-gen.c (operand_types): Move RegMem ...
506 (opcode_modifiers): ... here.
507 * i386-opc.h (RegMem): Move to opcode modifer enum.
508 (union i386_operand_type): Move regmem field ...
509 (struct i386_opcode_modifier): ... here.
510 * i386-opc.tbl (RegMem): Define.
511 (mov, movq): Move RegMem on segment, control, debug, and test
512 register flavors.
513 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
514 to non-SSE2AVX flavor.
515 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
516 Move RegMem on register only flavors. Drop IgnoreSize from
517 legacy encoding flavors.
518 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
519 flavors.
520 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
521 register only flavors.
522 (vmovd): Move RegMem and drop IgnoreSize on register only
523 flavor. Change opcode and operand order to store form.
524 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
525
21df382b
JB		 5262019-07-16 Jan Beulich <jbeulich@suse.com>
527
528 * i386-gen.c (operand_type_init, operand_types): Replace SReg
529 entries.
530 * i386-opc.h (SReg2, SReg3): Replace by ...
531 (SReg): ... this.
532 (union i386_operand_type): Replace sreg fields.
533 * i386-opc.tbl (mov, ): Use SReg.
534 (push, pop): Likewies. Drop i386 and x86-64 specific segment
535 register flavors.
536 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
537 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
538
3719fd55
JM		 5392019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
540
541 * bpf-desc.c: Regenerate.
542 * bpf-opc.c: Likewise.
543 * bpf-opc.h: Likewise.
544
92434a14
JM		 5452019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
546
547 * bpf-desc.c: Regenerate.
548 * bpf-opc.c: Likewise.
549
43dd7626
HPN		 5502019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
551
552 * arm-dis.c (print_insn_coprocessor): Rename index to
553 index_operand.
554
98602811
JW		 5552019-07-05 Kito Cheng <kito.cheng@sifive.com>
556
557 * riscv-opc.c (riscv_insn_types): Add r4 type.
558
559 * riscv-opc.c (riscv_insn_types): Add b and j type.
560
561 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
562 format for sb type and correct s type.
563
01c1ee4a
RS		 5642019-07-02 Richard Sandiford <richard.sandiford@arm.com>
565
566 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
567 SVE FMOV alias of FCPY.
568
83adff69
RS		 5692019-07-02 Richard Sandiford <richard.sandiford@arm.com>
570
571 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
572 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
573
89418844
RS		 5742019-07-02 Richard Sandiford <richard.sandiford@arm.com>
575
576 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
577 registers in an instruction prefixed by MOVPRFX.
578
41be57ca
MM		 5792019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
580
581 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
582 sve_size_13 icode to account for variant behaviour of
583 pmull{t,b}.
584 * aarch64-dis-2.c: Regenerate.
585 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
586 sve_size_13 icode to account for variant behaviour of
587 pmull{t,b}.
588 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
589 (OP_SVE_VVV_Q_D): Add new qualifier.
590 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
591 (struct aarch64_opcode): Split pmull{t,b} into those requiring
592 AES and those not.
593
9d3bf266
JB		 5942019-07-01 Jan Beulich <jbeulich@suse.com>
595
596 * opcodes/i386-gen.c (operand_type_init): Remove
597 OPERAND_TYPE_VEC_IMM4 entry.
598 (operand_types): Remove Vec_Imm4.
599 * opcodes/i386-opc.h (Vec_Imm4): Delete.
600 (union i386_operand_type): Remove vec_imm4.
601 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
602 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
603
c3949f43
JB		 6042019-07-01 Jan Beulich <jbeulich@suse.com>
605
606 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
607 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
608 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
609 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
610 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
611 monitorx, mwaitx): Drop ImmExt from operand-less forms.
612 * i386-tbl.h: Re-generate.
613
5641ec01
JB		 6142019-07-01 Jan Beulich <jbeulich@suse.com>
615
616 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
617 register operands.
618 * i386-tbl.h: Re-generate.
619
79dec6b7
JB		 6202019-07-01 Jan Beulich <jbeulich@suse.com>
621
622 * i386-opc.tbl (C): New.
623 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
624 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
625 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
626 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
627 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
628 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
629 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
630 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
631 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
632 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
633 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
634 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
635 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
636 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
637 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
638 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
639 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
640 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
641 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
642 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
643 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
644 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
645 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
646 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
647 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
648 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
649 flavors.
650 * i386-tbl.h: Re-generate.
651
a0a1771e
JB		 6522019-07-01 Jan Beulich <jbeulich@suse.com>
653
654 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
655 register operands.
656 * i386-tbl.h: Re-generate.
657
cd546e7b
JB		 6582019-07-01 Jan Beulich <jbeulich@suse.com>
659
660 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
661 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
662 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
663 * i386-tbl.h: Re-generate.
664
e3bba3fc
JB		 6652019-07-01 Jan Beulich <jbeulich@suse.com>
666
667 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
668 Disp8MemShift from register only templates.
669 * i386-tbl.h: Re-generate.
670
36cc073e
JB		 6712019-07-01 Jan Beulich <jbeulich@suse.com>
672
673 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
674 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
675 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
676 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
677 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
678 EVEX_W_0F11_P_3_M_1): Delete.
679 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
680 EVEX_W_0F11_P_3): New.
681 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
682 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
683 MOD_EVEX_0F11_PREFIX_3 table entries.
684 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
685 PREFIX_EVEX_0F11 table entries.
686 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
687 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
688 EVEX_W_0F11_P_3_M_{0,1} table entries.
689
219920a7
JB		 6902019-07-01 Jan Beulich <jbeulich@suse.com>
691
692 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
693 Delete.
694
e395f487
L		 6952019-06-27 H.J. Lu <hongjiu.lu@intel.com>
696
697 PR binutils/24719
698 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
699 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
700 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
701 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
702 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
703 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
704 EVEX_LEN_0F38C7_R_6_P_2_W_1.
705 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
706 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
707 PREFIX_EVEX_0F38C6_REG_6 entries.
708 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
709 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
710 EVEX_W_0F38C7_R_6_P_2 entries.
711 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
712 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
713 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
714 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
715 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
716 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
717 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
718
2b7bcc87
JB		 7192019-06-27 Jan Beulich <jbeulich@suse.com>
720
721 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
722 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
723 VEX_LEN_0F2D_P_3): Delete.
724 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
725 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
726 (prefix_table): ... here.
727
c1dc7af5
JB		 7282019-06-27 Jan Beulich <jbeulich@suse.com>
729
730 * i386-dis.c (Iq): Delete.
731 (Id): New.
732 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
733 TBM insns.
734 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
735 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
736 (OP_E_memory): Also honor needindex when deciding whether an
737 address size prefix needs printing.
738 (OP_I): Remove handling of q_mode. Add handling of d_mode.
739
d7560e2d
JW		 7402019-06-26 Jim Wilson <jimw@sifive.com>
741
742 PR binutils/24739
743 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
744 Set info->display_endian to info->endian_code.
745
2c703856
JB		 7462019-06-25 Jan Beulich <jbeulich@suse.com>
747
748 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
749 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
750 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
751 OPERAND_TYPE_ACC64 entries.
752 * i386-init.h: Re-generate.
753
54fbadc0
JB		 7542019-06-25 Jan Beulich <jbeulich@suse.com>
755
756 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
757 Delete.
758 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
759 of dqa_mode.
760 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
761 entries here.
762 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
763 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
764
a280ab8e
JB		 7652019-06-25 Jan Beulich <jbeulich@suse.com>
766
767 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
768 variables.
769
e1a1babd
JB		 7702019-06-25 Jan Beulich <jbeulich@suse.com>
771
772 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
773 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
774 movnti.
d7560e2d 775 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 776 * i386-tbl.h: Re-generate.
777
b8364fa7
JB		 7782019-06-25 Jan Beulich <jbeulich@suse.com>
779
780 * i386-opc.tbl (and): Mark Imm8S form for optimization.
781 * i386-tbl.h: Re-generate.
782
ad692897
L		 7832019-06-21 H.J. Lu <hongjiu.lu@intel.com>
784
785 * i386-dis-evex.h: Break into ...
786 * i386-dis-evex-len.h: New file.
787 * i386-dis-evex-mod.h: Likewise.
788 * i386-dis-evex-prefix.h: Likewise.
789 * i386-dis-evex-reg.h: Likewise.
790 * i386-dis-evex-w.h: Likewise.
791 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
792 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
793 i386-dis-evex-mod.h.
794
f0a6222e
L		 7952019-06-19 H.J. Lu <hongjiu.lu@intel.com>
796
797 PR binutils/24700
798 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
799 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
800 EVEX_W_0F385B_P_2.
801 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
802 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
803 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
804 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
805 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
806 EVEX_LEN_0F385B_P_2_W_1.
807 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
808 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
809 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
810 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
811 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
812 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
813 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
814 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
815 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
816 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
817
6e1c90b7
L		 8182019-06-17 H.J. Lu <hongjiu.lu@intel.com>
819
820 PR binutils/24691
821 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
822 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
823 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
824 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
825 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
826 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
827 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
828 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
829 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
830 EVEX_LEN_0F3A43_P_2_W_1.
831 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
832 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
833 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
834 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
835 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
836 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
837 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
838 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
839 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
840 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
841 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
842 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
843
bcc5a6eb
NC		 8442019-06-14 Nick Clifton <nickc@redhat.com>
845
846 * po/fr.po; Updated French translation.
847
e4c4ac46
SH		 8482019-06-13 Stafford Horne <shorne@gmail.com>
849
850 * or1k-asm.c: Regenerated.
851 * or1k-desc.c: Regenerated.
852 * or1k-desc.h: Regenerated.
853 * or1k-dis.c: Regenerated.
854 * or1k-ibld.c: Regenerated.
855 * or1k-opc.c: Regenerated.
856 * or1k-opc.h: Regenerated.
857 * or1k-opinst.c: Regenerated.
858
a0e44ef5
PB		 8592019-06-12 Peter Bergner <bergner@linux.ibm.com>
860
861 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
862
12efd68d
L		 8632019-06-05 H.J. Lu <hongjiu.lu@intel.com>
864
865 PR binutils/24633
866 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
867 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
868 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
869 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
870 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
871 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
872 EVEX_LEN_0F3A1B_P_2_W_1.
873 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
874 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
875 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
876 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
877 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
878 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
879 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
880 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
881
63c6fc6c
L		 8822019-06-04 H.J. Lu <hongjiu.lu@intel.com>
883
884 PR binutils/24626
885 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
886 EVEX.vvvv when disassembling VEX and EVEX instructions.
887 (OP_VEX): Set vex.register_specifier to 0 after readding
888 vex.register_specifier.
889 (OP_Vex_2src_1): Likewise.
890 (OP_Vex_2src_2): Likewise.
891 (OP_LWP_E): Likewise.
892 (OP_EX_Vex): Don't check vex.register_specifier.
893 (OP_XMM_Vex): Likewise.
894
9186c494
L		 8952019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
896 Lili Cui <lili.cui@intel.com>
897
898 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
899 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
900 instructions.
901 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
902 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
903 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
904 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
905 (i386_cpu_flags): Add cpuavx512_vp2intersect.
906 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
907 * i386-init.h: Regenerated.
908 * i386-tbl.h: Likewise.
909
5d79adc4
L		 9102019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
911 Lili Cui <lili.cui@intel.com>
912
913 * doc/c-i386.texi: Document enqcmd.
914 * testsuite/gas/i386/enqcmd-intel.d: New file.
915 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
916 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
917 * testsuite/gas/i386/enqcmd.d: Likewise.
918 * testsuite/gas/i386/enqcmd.s: Likewise.
919 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
920 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
921 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
922 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
923 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
924 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
925 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
926 and x86-64-enqcmd.
927
a9d96ab9
AH		 9282019-06-04 Alan Hayward <alan.hayward@arm.com>
929
930 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
931
4f6d070a
AM		 9322019-06-03 Alan Modra <amodra@gmail.com>
933
934 * ppc-dis.c (prefix_opcd_indices): Correct size.
935
a2f4b66c
L		 9362019-05-28 H.J. Lu <hongjiu.lu@intel.com>
937
938 PR gas/24625
939 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
940 Disp8ShiftVL.
941 * i386-tbl.h: Regenerated.
942
405b5bd8
AM		 9432019-05-24 Alan Modra <amodra@gmail.com>
944
945 * po/POTFILES.in: Regenerate.
946
8acf1435
PB		 9472019-05-24 Peter Bergner <bergner@linux.ibm.com>
948 Alan Modra <amodra@gmail.com>
949
950 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
951 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
952 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
953 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
954 XTOP>): Define and add entries.
955 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
956 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
957 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
958 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
959
dd7efa79
PB		 9602019-05-24 Peter Bergner <bergner@linux.ibm.com>
961 Alan Modra <amodra@gmail.com>
962
963 * ppc-dis.c (ppc_opts): Add "future" entry.
964 (PREFIX_OPCD_SEGS): Define.
965 (prefix_opcd_indices): New array.
966 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
967 (lookup_prefix): New function.
968 (print_insn_powerpc): Handle 64-bit prefix instructions.
969 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
970 (PMRR, POWERXX): Define.
971 (prefix_opcodes): New instruction table.
972 (prefix_num_opcodes): New constant.
973
79472b45
JM		 9742019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
975
976 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
977 * configure: Regenerated.
978 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
979 and cpu/bpf.opc.
980 (HFILES): Add bpf-desc.h and bpf-opc.h.
981 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
982 bpf-ibld.c and bpf-opc.c.
983 (BPF_DEPS): Define.
984 * Makefile.in: Regenerated.
985 * disassemble.c (ARCH_bpf): Define.
986 (disassembler): Add case for bfd_arch_bpf.
987 (disassemble_init_for_target): Likewise.
988 (enum epbf_isa_attr): Define.
989 * disassemble.h: extern print_insn_bpf.
990 * bpf-asm.c: Generated.
991 * bpf-opc.h: Likewise.
992 * bpf-opc.c: Likewise.
993 * bpf-ibld.c: Likewise.
994 * bpf-dis.c: Likewise.
995 * bpf-desc.h: Likewise.
996 * bpf-desc.c: Likewise.
997
ba6cd17f
SD		 9982019-05-21 Sudakshina Das <sudi.das@arm.com>
999
1000 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1001 and VMSR with the new operands.
1002
e39c1607
SD		 10032019-05-21 Sudakshina Das <sudi.das@arm.com>
1004
1005 * arm-dis.c (enum mve_instructions): New enum
1006 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1007 and cneg.
1008 (mve_opcodes): New instructions as above.
1009 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1010 csneg and csel.
1011 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1012
23d00a41
SD		 10132019-05-21 Sudakshina Das <sudi.das@arm.com>
1014
1015 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1016 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1017 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1018 uqshl, urshrl and urshr.
1019 (is_mve_okay_in_it): Add new instructions to TRUE list.
1020 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1021 (print_insn_mve): Updated to accept new %j,
1022 %<bitfield>m and %<bitfield>n patterns.
1023
cd4797ee
FS		 10242019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1025
1026 * mips-opc.c (mips_builtin_opcodes): Change source register
1027 constraint for DAUI.
1028
999b073b
NC		 10292019-05-20 Nick Clifton <nickc@redhat.com>
1030
1031 * po/fr.po: Updated French translation.
1032
14b456f2
AV		 10332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1034 Michael Collison <michael.collison@arm.com>
1035
1036 * arm-dis.c (thumb32_opcodes): Add new instructions.
1037 (enum mve_instructions): Likewise.
1038 (enum mve_undefined): Add new reasons.
1039 (is_mve_encoding_conflict): Handle new instructions.
1040 (is_mve_undefined): Likewise.
1041 (is_mve_unpredictable): Likewise.
1042 (print_mve_undefined): Likewise.
1043 (print_mve_size): Likewise.
1044
f49bb598
AV		 10452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1046 Michael Collison <michael.collison@arm.com>
1047
1048 * arm-dis.c (thumb32_opcodes): Add new instructions.
1049 (enum mve_instructions): Likewise.
1050 (is_mve_encoding_conflict): Handle new instructions.
1051 (is_mve_undefined): Likewise.
1052 (is_mve_unpredictable): Likewise.
1053 (print_mve_size): Likewise.
1054
56858bea
AV		 10552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1056 Michael Collison <michael.collison@arm.com>
1057
1058 * arm-dis.c (thumb32_opcodes): Add new instructions.
1059 (enum mve_instructions): Likewise.
1060 (is_mve_encoding_conflict): Likewise.
1061 (is_mve_unpredictable): Likewise.
1062 (print_mve_size): Likewise.
1063
e523f101
AV		 10642019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1065 Michael Collison <michael.collison@arm.com>
1066
1067 * arm-dis.c (thumb32_opcodes): Add new instructions.
1068 (enum mve_instructions): Likewise.
1069 (is_mve_encoding_conflict): Handle new instructions.
1070 (is_mve_undefined): Likewise.
1071 (is_mve_unpredictable): Likewise.
1072 (print_mve_size): Likewise.
1073
66dcaa5d
AV		 10742019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1075 Michael Collison <michael.collison@arm.com>
1076
1077 * arm-dis.c (thumb32_opcodes): Add new instructions.
1078 (enum mve_instructions): Likewise.
1079 (is_mve_encoding_conflict): Handle new instructions.
1080 (is_mve_undefined): Likewise.
1081 (is_mve_unpredictable): Likewise.
1082 (print_mve_size): Likewise.
1083 (print_insn_mve): Likewise.
1084
d052b9b7
AV		 10852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1086 Michael Collison <michael.collison@arm.com>
1087
1088 * arm-dis.c (thumb32_opcodes): Add new instructions.
1089 (print_insn_thumb32): Handle new instructions.
1090
ed63aa17
AV		 10912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1092 Michael Collison <michael.collison@arm.com>
1093
1094 * arm-dis.c (enum mve_instructions): Add new instructions.
1095 (enum mve_undefined): Add new reasons.
1096 (is_mve_encoding_conflict): Handle new instructions.
1097 (is_mve_undefined): Likewise.
1098 (is_mve_unpredictable): Likewise.
1099 (print_mve_undefined): Likewise.
1100 (print_mve_size): Likewise.
1101 (print_mve_shift_n): Likewise.
1102 (print_insn_mve): Likewise.
1103
897b9bbc
AV		 11042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1105 Michael Collison <michael.collison@arm.com>
1106
1107 * arm-dis.c (enum mve_instructions): Add new instructions.
1108 (is_mve_encoding_conflict): Handle new instructions.
1109 (is_mve_unpredictable): Likewise.
1110 (print_mve_rotate): Likewise.
1111 (print_mve_size): Likewise.
1112 (print_insn_mve): Likewise.
1113
1c8f2df8
AV		 11142019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1115 Michael Collison <michael.collison@arm.com>
1116
1117 * arm-dis.c (enum mve_instructions): Add new instructions.
1118 (is_mve_encoding_conflict): Handle new instructions.
1119 (is_mve_unpredictable): Likewise.
1120 (print_mve_size): Likewise.
1121 (print_insn_mve): Likewise.
1122
d3b63143
AV		 11232019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1124 Michael Collison <michael.collison@arm.com>
1125
1126 * arm-dis.c (enum mve_instructions): Add new instructions.
1127 (enum mve_undefined): Add new reasons.
1128 (is_mve_encoding_conflict): Handle new instructions.
1129 (is_mve_undefined): Likewise.
1130 (is_mve_unpredictable): Likewise.
1131 (print_mve_undefined): Likewise.
1132 (print_mve_size): Likewise.
1133 (print_insn_mve): Likewise.
1134
14925797
AV		 11352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1136 Michael Collison <michael.collison@arm.com>
1137
1138 * arm-dis.c (enum mve_instructions): Add new instructions.
1139 (is_mve_encoding_conflict): Handle new instructions.
1140 (is_mve_undefined): Likewise.
1141 (is_mve_unpredictable): Likewise.
1142 (print_mve_size): Likewise.
1143 (print_insn_mve): Likewise.
1144
c507f10b
AV		 11452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1146 Michael Collison <michael.collison@arm.com>
1147
1148 * arm-dis.c (enum mve_instructions): Add new instructions.
1149 (enum mve_unpredictable): Add new reasons.
1150 (enum mve_undefined): Likewise.
1151 (is_mve_okay_in_it): Handle new isntructions.
1152 (is_mve_encoding_conflict): Likewise.
1153 (is_mve_undefined): Likewise.
1154 (is_mve_unpredictable): Likewise.
1155 (print_mve_vmov_index): Likewise.
1156 (print_simd_imm8): Likewise.
1157 (print_mve_undefined): Likewise.
1158 (print_mve_unpredictable): Likewise.
1159 (print_mve_size): Likewise.
1160 (print_insn_mve): Likewise.
1161
bf0b396d
AV		 11622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1163 Michael Collison <michael.collison@arm.com>
1164
1165 * arm-dis.c (enum mve_instructions): Add new instructions.
1166 (enum mve_unpredictable): Add new reasons.
1167 (enum mve_undefined): Likewise.
1168 (is_mve_encoding_conflict): Handle new instructions.
1169 (is_mve_undefined): Likewise.
1170 (is_mve_unpredictable): Likewise.
1171 (print_mve_undefined): Likewise.
1172 (print_mve_unpredictable): Likewise.
1173 (print_mve_rounding_mode): Likewise.
1174 (print_mve_vcvt_size): Likewise.
1175 (print_mve_size): Likewise.
1176 (print_insn_mve): Likewise.
1177
ef1576a1
AV		 11782019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1179 Michael Collison <michael.collison@arm.com>
1180
1181 * arm-dis.c (enum mve_instructions): Add new instructions.
1182 (enum mve_unpredictable): Add new reasons.
1183 (enum mve_undefined): Likewise.
1184 (is_mve_undefined): Handle new instructions.
1185 (is_mve_unpredictable): Likewise.
1186 (print_mve_undefined): Likewise.
1187 (print_mve_unpredictable): Likewise.
1188 (print_mve_size): Likewise.
1189 (print_insn_mve): Likewise.
1190
aef6d006
AV		 11912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1192 Michael Collison <michael.collison@arm.com>
1193
1194 * arm-dis.c (enum mve_instructions): Add new instructions.
1195 (enum mve_undefined): Add new reasons.
1196 (insns): Add new instructions.
1197 (is_mve_encoding_conflict):
1198 (print_mve_vld_str_addr): New print function.
1199 (is_mve_undefined): Handle new instructions.
1200 (is_mve_unpredictable): Likewise.
1201 (print_mve_undefined): Likewise.
1202 (print_mve_size): Likewise.
1203 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1204 (print_insn_mve): Handle new operands.
1205
04d54ace
AV		 12062019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1207 Michael Collison <michael.collison@arm.com>
1208
1209 * arm-dis.c (enum mve_instructions): Add new instructions.
1210 (enum mve_unpredictable): Add new reasons.
1211 (is_mve_encoding_conflict): Handle new instructions.
1212 (is_mve_unpredictable): Likewise.
1213 (mve_opcodes): Add new instructions.
1214 (print_mve_unpredictable): Handle new reasons.
1215 (print_mve_register_blocks): New print function.
1216 (print_mve_size): Handle new instructions.
1217 (print_insn_mve): Likewise.
1218
9743db03
AV		 12192019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1220 Michael Collison <michael.collison@arm.com>
1221
1222 * arm-dis.c (enum mve_instructions): Add new instructions.
1223 (enum mve_unpredictable): Add new reasons.
1224 (enum mve_undefined): Likewise.
1225 (is_mve_encoding_conflict): Handle new instructions.
1226 (is_mve_undefined): Likewise.
1227 (is_mve_unpredictable): Likewise.
1228 (coprocessor_opcodes): Move NEON VDUP from here...
1229 (neon_opcodes): ... to here.
1230 (mve_opcodes): Add new instructions.
1231 (print_mve_undefined): Handle new reasons.
1232 (print_mve_unpredictable): Likewise.
1233 (print_mve_size): Handle new instructions.
1234 (print_insn_neon): Handle vdup.
1235 (print_insn_mve): Handle new operands.
1236
143275ea
AV		 12372019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1238 Michael Collison <michael.collison@arm.com>
1239
1240 * arm-dis.c (enum mve_instructions): Add new instructions.
1241 (enum mve_unpredictable): Add new values.
1242 (mve_opcodes): Add new instructions.
1243 (vec_condnames): New array with vector conditions.
1244 (mve_predicatenames): New array with predicate suffixes.
1245 (mve_vec_sizename): New array with vector sizes.
1246 (enum vpt_pred_state): New enum with vector predication states.
1247 (struct vpt_block): New struct type for vpt blocks.
1248 (vpt_block_state): Global struct to keep track of state.
1249 (mve_extract_pred_mask): New helper function.
1250 (num_instructions_vpt_block): Likewise.
1251 (mark_outside_vpt_block): Likewise.
1252 (mark_inside_vpt_block): Likewise.
1253 (invert_next_predicate_state): Likewise.
1254 (update_next_predicate_state): Likewise.
1255 (update_vpt_block_state): Likewise.
1256 (is_vpt_instruction): Likewise.
1257 (is_mve_encoding_conflict): Add entries for new instructions.
1258 (is_mve_unpredictable): Likewise.
1259 (print_mve_unpredictable): Handle new cases.
1260 (print_instruction_predicate): Likewise.
1261 (print_mve_size): New function.
1262 (print_vec_condition): New function.
1263 (print_insn_mve): Handle vpt blocks and new print operands.
1264
f08d8ce3
AV		 12652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1266
1267 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1268 8, 14 and 15 for Armv8.1-M Mainline.
1269
73cd51e5
AV		 12702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1271 Michael Collison <michael.collison@arm.com>
1272
1273 * arm-dis.c (enum mve_instructions): New enum.
1274 (enum mve_unpredictable): Likewise.
1275 (enum mve_undefined): Likewise.
1276 (struct mopcode32): New struct.
1277 (is_mve_okay_in_it): New function.
1278 (is_mve_architecture): Likewise.
1279 (arm_decode_field): Likewise.
1280 (arm_decode_field_multiple): Likewise.
1281 (is_mve_encoding_conflict): Likewise.
1282 (is_mve_undefined): Likewise.
1283 (is_mve_unpredictable): Likewise.
1284 (print_mve_undefined): Likewise.
1285 (print_mve_unpredictable): Likewise.
1286 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1287 (print_insn_mve): New function.
1288 (print_insn_thumb32): Handle MVE architecture.
1289 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1290
3076e594
NC		 12912019-05-10 Nick Clifton <nickc@redhat.com>
1292
1293 PR 24538
1294 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1295 end of the table prematurely.
1296
387e7624
FS		 12972019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1298
1299 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1300 macros for R6.
1301
0067be51
AM		 13022019-05-11 Alan Modra <amodra@gmail.com>
1303
1304 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1305 when -Mraw is in effect.
1306
42e6288f
MM		 13072019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1308
1309 * aarch64-dis-2.c: Regenerate.
1310 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1311 (OP_SVE_BBB): New variant set.
1312 (OP_SVE_DDDD): New variant set.
1313 (OP_SVE_HHH): New variant set.
1314 (OP_SVE_HHHU): New variant set.
1315 (OP_SVE_SSS): New variant set.
1316 (OP_SVE_SSSU): New variant set.
1317 (OP_SVE_SHH): New variant set.
1318 (OP_SVE_SBBU): New variant set.
1319 (OP_SVE_DSS): New variant set.
1320 (OP_SVE_DHHU): New variant set.
1321 (OP_SVE_VMV_HSD_BHS): New variant set.
1322 (OP_SVE_VVU_HSD_BHS): New variant set.
1323 (OP_SVE_VVVU_SD_BH): New variant set.
1324 (OP_SVE_VVVU_BHSD): New variant set.
1325 (OP_SVE_VVV_QHD_DBS): New variant set.
1326 (OP_SVE_VVV_HSD_BHS): New variant set.
1327 (OP_SVE_VVV_HSD_BHS2): New variant set.
1328 (OP_SVE_VVV_BHS_HSD): New variant set.
1329 (OP_SVE_VV_BHS_HSD): New variant set.
1330 (OP_SVE_VVV_SD): New variant set.
1331 (OP_SVE_VVU_BHS_HSD): New variant set.
1332 (OP_SVE_VZVV_SD): New variant set.
1333 (OP_SVE_VZVV_BH): New variant set.
1334 (OP_SVE_VZV_SD): New variant set.
1335 (aarch64_opcode_table): Add sve2 instructions.
1336
28ed815a
MM		 13372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1338
1339 * aarch64-asm-2.c: Regenerated.
1340 * aarch64-dis-2.c: Regenerated.
1341 * aarch64-opc-2.c: Regenerated.
1342 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1343 for SVE_SHLIMM_UNPRED_22.
1344 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1345 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1346 operand.
1347
fd1dc4a0
MM		 13482019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1349
1350 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1351 sve_size_tsz_bhs iclass encode.
1352 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1353 sve_size_tsz_bhs iclass decode.
1354
31e36ab3
MM		 13552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1356
1357 * aarch64-asm-2.c: Regenerated.
1358 * aarch64-dis-2.c: Regenerated.
1359 * aarch64-opc-2.c: Regenerated.
1360 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1361 for SVE_Zm4_11_INDEX.
1362 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1363 (fields): Handle SVE_i2h field.
1364 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1365 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1366
1be5f94f
MM		 13672019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1368
1369 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1370 sve_shift_tsz_bhsd iclass encode.
1371 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1372 sve_shift_tsz_bhsd iclass decode.
1373
3c17238b
MM		 13742019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1375
1376 * aarch64-asm-2.c: Regenerated.
1377 * aarch64-dis-2.c: Regenerated.
1378 * aarch64-opc-2.c: Regenerated.
1379 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1380 (aarch64_encode_variant_using_iclass): Handle
1381 sve_shift_tsz_hsd iclass encode.
1382 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1383 sve_shift_tsz_hsd iclass decode.
1384 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1385 for SVE_SHRIMM_UNPRED_22.
1386 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1387 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1388 operand.
1389
cd50a87a
MM		 13902019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1391
1392 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1393 sve_size_013 iclass encode.
1394 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1395 sve_size_013 iclass decode.
1396
3c705960
MM		 13972019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1398
1399 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1400 sve_size_bh iclass encode.
1401 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1402 sve_size_bh iclass decode.
1403
0a57e14f
MM		 14042019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1405
1406 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1407 sve_size_sd2 iclass encode.
1408 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1409 sve_size_sd2 iclass decode.
1410 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1411 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1412
c469c864
MM		 14132019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1414
1415 * aarch64-asm-2.c: Regenerated.
1416 * aarch64-dis-2.c: Regenerated.
1417 * aarch64-opc-2.c: Regenerated.
1418 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1419 for SVE_ADDR_ZX.
1420 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1421 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1422
116adc27
MM		 14232019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1424
1425 * aarch64-asm-2.c: Regenerated.
1426 * aarch64-dis-2.c: Regenerated.
1427 * aarch64-opc-2.c: Regenerated.
1428 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1429 for SVE_Zm3_11_INDEX.
1430 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1431 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1432 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1433 fields.
1434 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1435
3bd82c86
MM		 14362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1437
1438 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1439 sve_size_hsd2 iclass encode.
1440 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1441 sve_size_hsd2 iclass decode.
1442 * aarch64-opc.c (fields): Handle SVE_size field.
1443 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1444
adccc507
MM		 14452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1446
1447 * aarch64-asm-2.c: Regenerated.
1448 * aarch64-dis-2.c: Regenerated.
1449 * aarch64-opc-2.c: Regenerated.
1450 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1451 for SVE_IMM_ROT3.
1452 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1453 (fields): Handle SVE_rot3 field.
1454 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1455 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1456
5cd99750
MM		 14572019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1458
1459 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1460 instructions.
1461
7ce2460a
MM		 14622019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1463
1464 * aarch64-tbl.h
1465 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1466 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1467 aarch64_feature_sve2bitperm): New feature sets.
1468 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1469 for feature set addresses.
1470 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1471 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1472
41cee089
FS		 14732019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1474 Faraz Shahbazker <fshahbazker@wavecomp.com>
1475
1476 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1477 argument and set ASE_EVA_R6 appropriately.
1478 (set_default_mips_dis_options): Pass ISA to above.
1479 (parse_mips_dis_option): Likewise.
1480 * mips-opc.c (EVAR6): New macro.
1481 (mips_builtin_opcodes): Add llwpe, scwpe.
1482
b83b4b13
SD		 14832019-05-01 Sudakshina Das <sudi.das@arm.com>
1484
1485 * aarch64-asm-2.c: Regenerated.
1486 * aarch64-dis-2.c: Regenerated.
1487 * aarch64-opc-2.c: Regenerated.
1488 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1489 AARCH64_OPND_TME_UIMM16.
1490 (aarch64_print_operand): Likewise.
1491 * aarch64-tbl.h (QL_IMM_NIL): New.
1492 (TME): New.
1493 (_TME_INSN): New.
1494 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1495
4a90ce95
JD		 14962019-04-29 John Darrington <john@darrington.wattle.id.au>
1497
1498 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1499
a45328b9
AB		 15002019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1501 Faraz Shahbazker <fshahbazker@wavecomp.com>
1502
1503 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1504
d10be0cb
JD		 15052019-04-24 John Darrington <john@darrington.wattle.id.au>
1506
1507 * s12z-opc.h: Add extern "C" bracketing to help
1508 users who wish to use this interface in c++ code.
1509
a679f24e
JD		 15102019-04-24 John Darrington <john@darrington.wattle.id.au>
1511
1512 * s12z-opc.c (bm_decode): Handle bit map operations with the
1513 "reserved0" mode.
1514
32c36c3c
AV		 15152019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1516
1517 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1518 specifier. Add entries for VLDR and VSTR of system registers.
1519 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1520 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1521 of %J and %K format specifier.
1522
efd6b359
AV		 15232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1524
1525 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1526 Add new entries for VSCCLRM instruction.
1527 (print_insn_coprocessor): Handle new %C format control code.
1528
6b0dd094
AV		 15292019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1530
1531 * arm-dis.c (enum isa): New enum.
1532 (struct sopcode32): New structure.
1533 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1534 set isa field of all current entries to ANY.
1535 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1536 Only match an entry if its isa field allows the current mode.
1537
4b5a202f
AV		 15382019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1539
1540 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1541 CLRM.
1542 (print_insn_thumb32): Add logic to print %n CLRM register list.
1543
60f993ce
AV		 15442019-04-15 Sudakshina Das <sudi.das@arm.com>
1545
1546 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1547 and %Q patterns.
1548
f6b2b12d
AV		 15492019-04-15 Sudakshina Das <sudi.das@arm.com>
1550
1551 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1552 (print_insn_thumb32): Edit the switch case for %Z.
1553
1889da70
AV		 15542019-04-15 Sudakshina Das <sudi.das@arm.com>
1555
1556 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1557
65d1bc05
AV		 15582019-04-15 Sudakshina Das <sudi.das@arm.com>
1559
1560 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1561
1caf72a5
AV		 15622019-04-15 Sudakshina Das <sudi.das@arm.com>
1563
1564 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1565
f1c7f421
AV		 15662019-04-15 Sudakshina Das <sudi.das@arm.com>
1567
1568 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1569 Arm register with r13 and r15 unpredictable.
1570 (thumb32_opcodes): New instructions for bfx and bflx.
1571
4389b29a
AV		 15722019-04-15 Sudakshina Das <sudi.das@arm.com>
1573
1574 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1575
e5d6e09e
AV		 15762019-04-15 Sudakshina Das <sudi.das@arm.com>
1577
1578 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1579
e12437dc
AV		 15802019-04-15 Sudakshina Das <sudi.das@arm.com>
1581
1582 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1583
031254f2
AV		 15842019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1585
1586 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1587
e5a557ac
JD		 15882019-04-12 John Darrington <john@darrington.wattle.id.au>
1589
1590 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1591 "optr". ("operator" is a reserved word in c++).
1592
bd7ceb8d
SD		 15932019-04-11 Sudakshina Das <sudi.das@arm.com>
1594
1595 * aarch64-opc.c (aarch64_print_operand): Add case for
1596 AARCH64_OPND_Rt_SP.
1597 (verify_constraints): Likewise.
1598 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1599 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1600 to accept Rt|SP as first operand.
1601 (AARCH64_OPERANDS): Add new Rt_SP.
1602 * aarch64-asm-2.c: Regenerated.
1603 * aarch64-dis-2.c: Regenerated.
1604 * aarch64-opc-2.c: Regenerated.
1605
e54010f1
SD		 16062019-04-11 Sudakshina Das <sudi.das@arm.com>
1607
1608 * aarch64-asm-2.c: Regenerated.
1609 * aarch64-dis-2.c: Likewise.
1610 * aarch64-opc-2.c: Likewise.
1611 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1612
7e96e219
RS		 16132019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1614
1615 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1616
6f2791d5
L		 16172019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1618
1619 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1620 * i386-init.h: Regenerated.
1621
e392bad3
AM		 16222019-04-07 Alan Modra <amodra@gmail.com>
1623
1624 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1625 op_separator to control printing of spaces, comma and parens
1626 rather than need_comma, need_paren and spaces vars.
1627
dffaa15c
AM		 16282019-04-07 Alan Modra <amodra@gmail.com>
1629
1630 PR 24421
1631 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1632 (print_insn_neon, print_insn_arm): Likewise.
1633
d6aab7a1
XG		 16342019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1635
1636 * i386-dis-evex.h (evex_table): Updated to support BF16
1637 instructions.
1638 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1639 and EVEX_W_0F3872_P_3.
1640 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1641 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1642 * i386-opc.h (enum): Add CpuAVX512_BF16.
1643 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1644 * i386-opc.tbl: Add AVX512 BF16 instructions.
1645 * i386-init.h: Regenerated.
1646 * i386-tbl.h: Likewise.
1647
66e85460
AM		 16482019-04-05 Alan Modra <amodra@gmail.com>
1649
1650 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1651 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1652 to favour printing of "-" branch hint when using the "y" bit.
1653 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1654
c2b1c275
AM		 16552019-04-05 Alan Modra <amodra@gmail.com>
1656
1657 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1658 opcode until first operand is output.
1659
aae9718e
PB		 16602019-04-04 Peter Bergner <bergner@linux.ibm.com>
1661
1662 PR gas/24349
1663 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1664 (valid_bo_post_v2): Add support for 'at' branch hints.
1665 (insert_bo): Only error on branch on ctr.
1666 (get_bo_hint_mask): New function.
1667 (insert_boe): Add new 'branch_taken' formal argument. Add support
1668 for inserting 'at' branch hints.
1669 (extract_boe): Add new 'branch_taken' formal argument. Add support
1670 for extracting 'at' branch hints.
1671 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1672 (BOE): Delete operand.
1673 (BOM, BOP): New operands.
1674 (RM): Update value.
1675 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1676 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1677 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1678 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1679 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1680 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1681 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1682 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1683 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1684 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1685 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1686 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1687 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1688 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1689 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1690 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1691 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1692 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1693 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1694 bttarl+>: New extended mnemonics.
1695
96a86c01
AM		 16962019-03-28 Alan Modra <amodra@gmail.com>
1697
1698 PR 24390
1699 * ppc-opc.c (BTF): Define.
1700 (powerpc_opcodes): Use for mtfsb*.
1701 * ppc-dis.c (print_insn_powerpc): Print fields with both
1702 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1703
796d6298
TC		 17042019-03-25 Tamar Christina <tamar.christina@arm.com>
1705
1706 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1707 (mapping_symbol_for_insn): Implement new algorithm.
1708 (print_insn): Remove duplicate code.
1709
60df3720
TC		 17102019-03-25 Tamar Christina <tamar.christina@arm.com>
1711
1712 * aarch64-dis.c (print_insn_aarch64):
1713 Implement override.
1714
51457761
TC		 17152019-03-25 Tamar Christina <tamar.christina@arm.com>
1716
1717 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1718 order.
1719
53b2f36b
TC		 17202019-03-25 Tamar Christina <tamar.christina@arm.com>
1721
1722 * aarch64-dis.c (last_stop_offset): New.
1723 (print_insn_aarch64): Use stop_offset.
1724
89199bb5
L		 17252019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1726
1727 PR gas/24359
1728 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1729 CPU_ANY_AVX2_FLAGS.
1730 * i386-init.h: Regenerated.
1731
97ed31ae
L		 17322019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1733
1734 PR gas/24348
1735 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1736 vmovdqu16, vmovdqu32 and vmovdqu64.
1737 * i386-tbl.h: Regenerated.
1738
0919bfe9
AK		 17392019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1740
1741 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1742 from vstrszb, vstrszh, and vstrszf.
1743
17442019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1745
1746 * s390-opc.txt: Add instruction descriptions.
1747
21820ebe
JW		 17482019-02-08 Jim Wilson <jimw@sifive.com>
1749
1750 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1751 <bne>: Likewise.
1752
f7dd2fb2
TC		 17532019-02-07 Tamar Christina <tamar.christina@arm.com>
1754
1755 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1756
6456d318
TC		 17572019-02-07 Tamar Christina <tamar.christina@arm.com>
1758
1759 PR binutils/23212
1760 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1761 * aarch64-opc.c (verify_elem_sd): New.
1762 (fields): Add FLD_sz entr.
1763 * aarch64-tbl.h (_SIMD_INSN): New.
1764 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1765 fmulx scalar and vector by element isns.
1766
4a83b610
NC		 17672019-02-07 Nick Clifton <nickc@redhat.com>
1768
1769 * po/sv.po: Updated Swedish translation.
1770
fc60b8c8
AK		 17712019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1772
1773 * s390-mkopc.c (main): Accept arch13 as cpu string.
1774 * s390-opc.c: Add new instruction formats and instruction opcode
1775 masks.
1776 * s390-opc.txt: Add new arch13 instructions.
1777
e10620d3
TC		 17782019-01-25 Sudakshina Das <sudi.das@arm.com>
1779
1780 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1781 (aarch64_opcode): Change encoding for stg, stzg
1782 st2g and st2zg.
1783 * aarch64-asm-2.c: Regenerated.
1784 * aarch64-dis-2.c: Regenerated.
1785 * aarch64-opc-2.c: Regenerated.
1786
20a4ca55
SD		 17872019-01-25 Sudakshina Das <sudi.das@arm.com>
1788
1789 * aarch64-asm-2.c: Regenerated.
1790 * aarch64-dis-2.c: Likewise.
1791 * aarch64-opc-2.c: Likewise.
1792 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1793
550fd7bf
SD		 17942019-01-25 Sudakshina Das <sudi.das@arm.com>
1795 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1796
1797 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1798 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1799 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1800 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1801 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1802 case for ldstgv_indexed.
1803 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1804 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1805 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1806 * aarch64-asm-2.c: Regenerated.
1807 * aarch64-dis-2.c: Regenerated.
1808 * aarch64-opc-2.c: Regenerated.
1809
d9938630
NC		 18102019-01-23 Nick Clifton <nickc@redhat.com>
1811
1812 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1813
375cd423
NC		 18142019-01-21 Nick Clifton <nickc@redhat.com>
1815
1816 * po/de.po: Updated German translation.
1817 * po/uk.po: Updated Ukranian translation.
1818
57299f48
CX		 18192019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1820 * mips-dis.c (mips_arch_choices): Fix typo in
1821 gs464, gs464e and gs264e descriptors.
1822
f48dfe41
NC		 18232019-01-19 Nick Clifton <nickc@redhat.com>
1824
1825 * configure: Regenerate.
1826 * po/opcodes.pot: Regenerate.
1827
f974f26c
NC		 18282018-06-24 Nick Clifton <nickc@redhat.com>
1829
1830 2.32 branch created.
1831
39f286cd
JD		 18322019-01-09 John Darrington <john@darrington.wattle.id.au>
1833
448b8ca8
JD		 1834 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1835 if it is null.
1836 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1837 zero.
1838
3107326d
AP		 18392019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1840
1841 * configure: Regenerate.
1842
7e9ca91e
AM		 18432019-01-07 Alan Modra <amodra@gmail.com>
1844
1845 * configure: Regenerate.
1846 * po/POTFILES.in: Regenerate.
1847
ef1ad42b
JD		 18482019-01-03 John Darrington <john@darrington.wattle.id.au>
1849
1850 * s12z-opc.c: New file.
1851 * s12z-opc.h: New file.
1852 * s12z-dis.c: Removed all code not directly related to display
1853 of instructions. Used the interface provided by the new files
1854 instead.
1855 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1856 * Makefile.in: Regenerate.
ef1ad42b 1857 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1858 * configure: Regenerate.
ef1ad42b 1859
82704155
AM		 18602019-01-01 Alan Modra <amodra@gmail.com>
1861
1862 Update year range in copyright notice of all files.
1863
d5c04e1b 1864For older changes see ChangeLog-2018
3499769a 1865\f
d5c04e1b 1866Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1867
1868Copying and distribution of this file, with or without modification,
1869are permitted in any medium without royalty provided the copyright
1870notice and this notice are preserved.
1871
1872Local Variables:
1873mode: change-log
1874left-margin: 8
1875fill-column: 74
1876version-control: never
1877End:
GDB Binutils - Deliverables
This page took 0.320032 seconds and 4 git commands to generate.