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x86: Don't set eh->local_ref to 1 for linker defined symbols
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
29e0f0a1
AM		 12018-05-18 Alan Modra <amodra@gmail.com>
2
3 * nfp-dis.c: Don't #include libbfd.h.
4 (init_nfp3200_priv): Use bfd_get_section_contents.
5 (nit_nfp6000_mecsr_sec): Likewise.
6
809276d2
NC		 72018-05-17 Nick Clifton <nickc@redhat.com>
8
9 * po/zh_CN.po: Updated simplified Chinese translation.
10
ff329288
TC		 112018-05-16 Tamar Christina <tamar.christina@arm.com>
12
13 PR binutils/23109
14 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
15 * aarch64-dis-2.c: Regenerate.
16
f9830ec1
TC		 172018-05-15 Tamar Christina <tamar.christina@arm.com>
18
19 PR binutils/21446
20 * aarch64-asm.c (opintl.h): Include.
21 (aarch64_ins_sysreg): Enforce read/write constraints.
22 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
23 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
24 (F_REG_READ, F_REG_WRITE): New.
25 * aarch64-opc.c (aarch64_print_operand): Generate notes for
26 AARCH64_OPND_SYSREG.
27 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
28 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
29 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
30 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
31 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
32 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
33 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
34 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
35 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
36 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
37 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
38 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
39 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
40 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
41 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
42 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
43 msr (F_SYS_WRITE), mrs (F_SYS_READ).
44
7d02540a
TC		 452018-05-15 Tamar Christina <tamar.christina@arm.com>
46
47 PR binutils/21446
48 * aarch64-dis.c (no_notes: New.
49 (parse_aarch64_dis_option): Support notes.
50 (aarch64_decode_insn, print_operands): Likewise.
51 (print_aarch64_disassembler_options): Document notes.
52 * aarch64-opc.c (aarch64_print_operand): Support notes.
53
561a72d4
TC		 542018-05-15 Tamar Christina <tamar.christina@arm.com>
55
56 PR binutils/21446
57 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
58 and take error struct.
59 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
60 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
61 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
62 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
63 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
64 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
65 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
66 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
67 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
68 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
69 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
70 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
71 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
72 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
73 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
74 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
75 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
76 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
77 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
78 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
79 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
80 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
81 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
82 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
83 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
84 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
85 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
86 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
87 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
88 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
89 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
90 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
91 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
92 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
93 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
94 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
95 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
96 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
97 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
98 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
99 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
100 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
101 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
102 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
103 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
104 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
105 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
106 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
107 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
108 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
109 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
110 (determine_disassembling_preference, aarch64_decode_insn,
111 print_insn_aarch64_word, print_insn_data): Take errors struct.
112 (print_insn_aarch64): Use errors.
113 * aarch64-asm-2.c: Regenerate.
114 * aarch64-dis-2.c: Regenerate.
115 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
116 boolean in aarch64_insert_operan.
117 (print_operand_extractor): Likewise.
118 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
119
1678bd35
FT		 1202018-05-15 Francois H. Theron <francois.theron@netronome.com>
121
122 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
123
06cfb1c8
L		 1242018-05-09 H.J. Lu <hongjiu.lu@intel.com>
125
126 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
127
84f9f8c3
AM		 1282018-05-09 Sebastian Rasmussen <sebras@gmail.com>
129
130 * cr16-opc.c (cr16_instruction): Comment typo fix.
131 * hppa-dis.c (print_insn_hppa): Likewise.
132
e6f372ba
JW		 1332018-05-08 Jim Wilson <jimw@sifive.com>
134
135 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
136 (match_c_slli64, match_srxi_as_c_srxi): New.
137 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
138 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
139 <c.slli, c.srli, c.srai>: Use match_s_slli.
140 <c.slli64, c.srli64, c.srai64>: New.
141
f413a913
AM		 1422018-05-08 Alan Modra <amodra@gmail.com>
143
144 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
145 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
146 partition opcode space for index lookup.
147
a87a6478
PB		 1482018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
149
150 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
151 <insn_length>: ...with this. Update usage.
152 Remove duplicate call to *info->memory_error_func.
153
c0a30a9f
L		 1542018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
155 H.J. Lu <hongjiu.lu@intel.com>
156
157 * i386-dis.c (Gva): New.
158 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
159 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
160 (prefix_table): New instructions (see prefix above).
161 (mod_table): New instructions (see prefix above).
162 (OP_G): Handle va_mode.
163 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
164 CPU_MOVDIR64B_FLAGS.
165 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
166 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
167 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
168 * i386-opc.tbl: Add movidir{i,64b}.
169 * i386-init.h: Regenerated.
170 * i386-tbl.h: Likewise.
171
75c0a438
L		 1722018-05-07 H.J. Lu <hongjiu.lu@intel.com>
173
174 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
175 AddrPrefixOpReg.
176 * i386-opc.h (AddrPrefixOp0): Renamed to ...
177 (AddrPrefixOpReg): This.
178 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
179 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
180
2ceb7719
PB		 1812018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
182
183 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
184 (vle_num_opcodes): Likewise.
185 (spe2_num_opcodes): Likewise.
186 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
187 initialization loop.
188 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
189 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
190 only once.
191
b3ac5c6c
TC		 1922018-05-01 Tamar Christina <tamar.christina@arm.com>
193
194 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
195
fe944acf
FT		 1962018-04-30 Francois H. Theron <francois.theron@netronome.com>
197
198 Makefile.am: Added nfp-dis.c.
199 configure.ac: Added bfd_nfp_arch.
200 disassemble.h: Added print_insn_nfp prototype.
201 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
202 nfp-dis.c: New, for NFP support.
203 po/POTFILES.in: Added nfp-dis.c to the list.
204 Makefile.in: Regenerate.
205 configure: Regenerate.
206
e2195274
JB		 2072018-04-26 Jan Beulich <jbeulich@suse.com>
208
209 * i386-opc.tbl: Fold various non-memory operand AVX512VL
210 templates into their base ones.
211 * i386-tlb.h: Re-generate.
212
59ef5df4
JB		 2132018-04-26 Jan Beulich <jbeulich@suse.com>
214
215 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
216 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
217 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
218 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
219 * i386-init.h: Re-generate.
220
6e041cf4
JB		 2212018-04-26 Jan Beulich <jbeulich@suse.com>
222
223 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
224 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
225 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
226 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
227 comment.
228 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
229 and CpuRegMask.
230 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
231 CpuRegMask: Delete.
232 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
233 cpuregzmm, and cpuregmask.
234 * i386-init.h: Re-generate.
235 * i386-tbl.h: Re-generate.
236
0e0eea78
JB		 2372018-04-26 Jan Beulich <jbeulich@suse.com>
238
239 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
240 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
241 * i386-init.h: Re-generate.
242
2f1bada2
JB		 2432018-04-26 Jan Beulich <jbeulich@suse.com>
244
245 * i386-gen.c (VexImmExt): Delete.
246 * i386-opc.h (VexImmExt, veximmext): Delete.
247 * i386-opc.tbl: Drop all VexImmExt uses.
248 * i386-tlb.h: Re-generate.
249
bacd1457
JB		 2502018-04-25 Jan Beulich <jbeulich@suse.com>
251
252 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
253 register-only forms.
254 * i386-tlb.h: Re-generate.
255
10bba94b
TC		 2562018-04-25 Tamar Christina <tamar.christina@arm.com>
257
258 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
259
c48935d7
IT		 2602018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
261
262 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
263 PREFIX_0F1C.
264 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
265 (cpu_flags): Add CpuCLDEMOTE.
266 * i386-init.h: Regenerate.
267 * i386-opc.h (enum): Add CpuCLDEMOTE,
268 (i386_cpu_flags): Add cpucldemote.
269 * i386-opc.tbl: Add cldemote.
270 * i386-tbl.h: Regenerate.
271
211dc24b
AM		 2722018-04-16 Alan Modra <amodra@gmail.com>
273
274 * Makefile.am: Remove sh5 and sh64 support.
275 * configure.ac: Likewise.
276 * disassemble.c: Likewise.
277 * disassemble.h: Likewise.
278 * sh-dis.c: Likewise.
279 * sh64-dis.c: Delete.
280 * sh64-opc.c: Delete.
281 * sh64-opc.h: Delete.
282 * Makefile.in: Regenerate.
283 * configure: Regenerate.
284 * po/POTFILES.in: Regenerate.
285
a9a4b302
AM		 2862018-04-16 Alan Modra <amodra@gmail.com>
287
288 * Makefile.am: Remove w65 support.
289 * configure.ac: Likewise.
290 * disassemble.c: Likewise.
291 * disassemble.h: Likewise.
292 * w65-dis.c: Delete.
293 * w65-opc.h: Delete.
294 * Makefile.in: Regenerate.
295 * configure: Regenerate.
296 * po/POTFILES.in: Regenerate.
297
04cb01fd
AM		 2982018-04-16 Alan Modra <amodra@gmail.com>
299
300 * configure.ac: Remove we32k support.
301 * configure: Regenerate.
302
c2bf1eec
AM		 3032018-04-16 Alan Modra <amodra@gmail.com>
304
305 * Makefile.am: Remove m88k support.
306 * configure.ac: Likewise.
307 * disassemble.c: Likewise.
308 * disassemble.h: Likewise.
309 * m88k-dis.c: Delete.
310 * Makefile.in: Regenerate.
311 * configure: Regenerate.
312 * po/POTFILES.in: Regenerate.
313
6793974d
AM		 3142018-04-16 Alan Modra <amodra@gmail.com>
315
316 * Makefile.am: Remove i370 support.
317 * configure.ac: Likewise.
318 * disassemble.c: Likewise.
319 * disassemble.h: Likewise.
320 * i370-dis.c: Delete.
321 * i370-opc.c: Delete.
322 * Makefile.in: Regenerate.
323 * configure: Regenerate.
324 * po/POTFILES.in: Regenerate.
325
e82aa794
AM		 3262018-04-16 Alan Modra <amodra@gmail.com>
327
328 * Makefile.am: Remove h8500 support.
329 * configure.ac: Likewise.
330 * disassemble.c: Likewise.
331 * disassemble.h: Likewise.
332 * h8500-dis.c: Delete.
333 * h8500-opc.h: Delete.
334 * Makefile.in: Regenerate.
335 * configure: Regenerate.
336 * po/POTFILES.in: Regenerate.
337
fceadf09
AM		 3382018-04-16 Alan Modra <amodra@gmail.com>
339
340 * configure.ac: Remove tahoe support.
341 * configure: Regenerate.
342
ae1d3843
L		 3432018-04-15 H.J. Lu <hongjiu.lu@intel.com>
344
345 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
346 umwait.
347 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
348 64-bit mode.
349 * i386-tbl.h: Regenerated.
350
de89d0a3
IT		 3512018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
352
353 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
354 PREFIX_MOD_1_0FAE_REG_6.
355 (va_mode): New.
356 (OP_E_register): Use va_mode.
357 * i386-dis-evex.h (prefix_table):
358 New instructions (see prefixes above).
359 * i386-gen.c (cpu_flag_init): Add WAITPKG.
360 (cpu_flags): Likewise.
361 * i386-opc.h (enum): Likewise.
362 (i386_cpu_flags): Likewise.
363 * i386-opc.tbl: Add umonitor, umwait, tpause.
364 * i386-init.h: Regenerate.
365 * i386-tbl.h: Likewise.
366
a8eb42a8
AM		 3672018-04-11 Alan Modra <amodra@gmail.com>
368
369 * opcodes/i860-dis.c: Delete.
370 * opcodes/i960-dis.c: Delete.
371 * Makefile.am: Remove i860 and i960 support.
372 * configure.ac: Likewise.
373 * disassemble.c: Likewise.
374 * disassemble.h: Likewise.
375 * Makefile.in: Regenerate.
376 * configure: Regenerate.
377 * po/POTFILES.in: Regenerate.
378
caf0678c
L		 3792018-04-04 H.J. Lu <hongjiu.lu@intel.com>
380
381 PR binutils/23025
382 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
383 to 0.
384 (print_insn): Clear vex instead of vex.evex.
385
4fb0d2b9
NC		 3862018-04-04 Nick Clifton <nickc@redhat.com>
387
388 * po/es.po: Updated Spanish translation.
389
c39e5b26
JB		 3902018-03-28 Jan Beulich <jbeulich@suse.com>
391
392 * i386-gen.c (opcode_modifiers): Delete VecESize.
393 * i386-opc.h (VecESize): Delete.
394 (struct i386_opcode_modifier): Delete vecesize.
395 * i386-opc.tbl: Drop VecESize.
396 * i386-tlb.h: Re-generate.
397
8e6e0792
JB		 3982018-03-28 Jan Beulich <jbeulich@suse.com>
399
400 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
401 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
402 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
403 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
404 * i386-tlb.h: Re-generate.
405
9f123b91
JB		 4062018-03-28 Jan Beulich <jbeulich@suse.com>
407
408 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
409 Fold AVX512 forms
410 * i386-tlb.h: Re-generate.
411
9646c87b
JB		 4122018-03-28 Jan Beulich <jbeulich@suse.com>
413
414 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
415 (vex_len_table): Drop Y for vcvt*2si.
416 (putop): Replace plain 'Y' handling by abort().
417
c8d59609
NC		 4182018-03-28 Nick Clifton <nickc@redhat.com>
419
420 PR 22988
421 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
422 instructions with only a base address register.
423 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
424 handle AARHC64_OPND_SVE_ADDR_R.
425 (aarch64_print_operand): Likewise.
426 * aarch64-asm-2.c: Regenerate.
427 * aarch64_dis-2.c: Regenerate.
428 * aarch64-opc-2.c: Regenerate.
429
b8c169f3
JB		 4302018-03-22 Jan Beulich <jbeulich@suse.com>
431
432 * i386-opc.tbl: Drop VecESize from register only insn forms and
433 memory forms not allowing broadcast.
434 * i386-tlb.h: Re-generate.
435
96bc132a
JB		 4362018-03-22 Jan Beulich <jbeulich@suse.com>
437
438 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
439 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
440 sha256*): Drop Disp<N>.
441
9f79e886
JB		 4422018-03-22 Jan Beulich <jbeulich@suse.com>
443
444 * i386-dis.c (EbndS, bnd_swap_mode): New.
445 (prefix_table): Use EbndS.
446 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
447 * i386-opc.tbl (bndmov): Move misplaced Load.
448 * i386-tlb.h: Re-generate.
449
d6793fa1
JB		 4502018-03-22 Jan Beulich <jbeulich@suse.com>
451
452 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
453 templates allowing memory operands and folded ones for register
454 only flavors.
455 * i386-tlb.h: Re-generate.
456
f7768225
JB		 4572018-03-22 Jan Beulich <jbeulich@suse.com>
458
459 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
460 256-bit templates. Drop redundant leftover Disp<N>.
461 * i386-tlb.h: Re-generate.
462
0e35537d
JW		 4632018-03-14 Kito Cheng <kito.cheng@gmail.com>
464
465 * riscv-opc.c (riscv_insn_types): New.
466
b4a3689a
NC		 4672018-03-13 Nick Clifton <nickc@redhat.com>
468
469 * po/pt_BR.po: Updated Brazilian Portuguese translation.
470
d3d50934
L		 4712018-03-08 H.J. Lu <hongjiu.lu@intel.com>
472
473 * i386-opc.tbl: Add Optimize to clr.
474 * i386-tbl.h: Regenerated.
475
bd5dea88
L		 4762018-03-08 H.J. Lu <hongjiu.lu@intel.com>
477
478 * i386-gen.c (opcode_modifiers): Remove OldGcc.
479 * i386-opc.h (OldGcc): Removed.
480 (i386_opcode_modifier): Remove oldgcc.
481 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
482 instructions for old (<= 2.8.1) versions of gcc.
483 * i386-tbl.h: Regenerated.
484
e771e7c9
JB		 4852018-03-08 Jan Beulich <jbeulich@suse.com>
486
487 * i386-opc.h (EVEXDYN): New.
488 * i386-opc.tbl: Fold various AVX512VL templates.
489 * i386-tlb.h: Re-generate.
490
ed438a93
JB		 4912018-03-08 Jan Beulich <jbeulich@suse.com>
492
493 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
494 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
495 vpexpandd, vpexpandq): Fold AFX512VF templates.
496 * i386-tlb.h: Re-generate.
497
454172a9
JB		 4982018-03-08 Jan Beulich <jbeulich@suse.com>
499
500 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
501 Fold 128- and 256-bit VEX-encoded templates.
502 * i386-tlb.h: Re-generate.
503
36824150
JB		 5042018-03-08 Jan Beulich <jbeulich@suse.com>
505
506 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
507 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
508 vpexpandd, vpexpandq): Fold AVX512F templates.
509 * i386-tlb.h: Re-generate.
510
e7f5c0a9
JB		 5112018-03-08 Jan Beulich <jbeulich@suse.com>
512
513 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
514 64-bit templates. Drop Disp<N>.
515 * i386-tlb.h: Re-generate.
516
25a4277f
JB		 5172018-03-08 Jan Beulich <jbeulich@suse.com>
518
519 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
520 and 256-bit templates.
521 * i386-tlb.h: Re-generate.
522
d2224064
JB		 5232018-03-08 Jan Beulich <jbeulich@suse.com>
524
525 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
526 * i386-tlb.h: Re-generate.
527
1b193f0b
JB		 5282018-03-08 Jan Beulich <jbeulich@suse.com>
529
530 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
531 Drop NoAVX.
532 * i386-tlb.h: Re-generate.
533
f2f6a710
JB		 5342018-03-08 Jan Beulich <jbeulich@suse.com>
535
536 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
537 * i386-tlb.h: Re-generate.
538
38e314eb
JB		 5392018-03-08 Jan Beulich <jbeulich@suse.com>
540
541 * i386-gen.c (opcode_modifiers): Delete FloatD.
542 * i386-opc.h (FloatD): Delete.
543 (struct i386_opcode_modifier): Delete floatd.
544 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
545 FloatD by D.
546 * i386-tlb.h: Re-generate.
547
d53e6b98
JB		 5482018-03-08 Jan Beulich <jbeulich@suse.com>
549
550 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
551
2907c2f5
JB		 5522018-03-08 Jan Beulich <jbeulich@suse.com>
553
554 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
555 * i386-tlb.h: Re-generate.
556
73053c1f
JB		 5572018-03-08 Jan Beulich <jbeulich@suse.com>
558
559 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
560 forms.
561 * i386-tlb.h: Re-generate.
562
52fe4420
AM		 5632018-03-07 Alan Modra <amodra@gmail.com>
564
565 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
566 bfd_arch_rs6000.
567 * disassemble.h (print_insn_rs6000): Delete.
568 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
569 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
570 (print_insn_rs6000): Delete.
571
a6743a54
AM		 5722018-03-03 Alan Modra <amodra@gmail.com>
573
574 * sysdep.h (opcodes_error_handler): Define.
575 (_bfd_error_handler): Declare.
576 * Makefile.am: Remove stray #.
577 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
578 EDIT" comment.
579 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
580 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
581 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
582 opcodes_error_handler to print errors. Standardize error messages.
583 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
584 and include opintl.h.
585 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
586 * i386-gen.c: Standardize error messages.
587 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
588 * Makefile.in: Regenerate.
589 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
590 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
591 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
592 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
593 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
594 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
595 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
596 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
597 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
598 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
599 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
600 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
601 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
602
8305403a
L		 6032018-03-01 H.J. Lu <hongjiu.lu@intel.com>
604
605 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
606 vpsub[bwdq] instructions.
607 * i386-tbl.h: Regenerated.
608
e184813f
AM		 6092018-03-01 Alan Modra <amodra@gmail.com>
610
611 * configure.ac (ALL_LINGUAS): Sort.
612 * configure: Regenerate.
613
5b616bef
TP		 6142018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
615
616 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
617 macro by assignements.
618
b6f8c7c4
L		 6192018-02-27 H.J. Lu <hongjiu.lu@intel.com>
620
621 PR gas/22871
622 * i386-gen.c (opcode_modifiers): Add Optimize.
623 * i386-opc.h (Optimize): New enum.
624 (i386_opcode_modifier): Add optimize.
625 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
626 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
627 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
628 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
629 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
630 vpxord and vpxorq.
631 * i386-tbl.h: Regenerated.
632
e95b887f
AM		 6332018-02-26 Alan Modra <amodra@gmail.com>
634
635 * crx-dis.c (getregliststring): Allocate a large enough buffer
636 to silence false positive gcc8 warning.
637
0bccfb29
JW		 6382018-02-22 Shea Levy <shea@shealevy.com>
639
640 * disassemble.c (ARCH_riscv): Define if ARCH_all.
641
6b6b6807
L		 6422018-02-22 H.J. Lu <hongjiu.lu@intel.com>
643
644 * i386-opc.tbl: Add {rex},
645 * i386-tbl.h: Regenerated.
646
75f31665
MR		 6472018-02-20 Maciej W. Rozycki <macro@mips.com>
648
649 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
650 (mips16_opcodes): Replace `M' with `m' for "restore".
651
e207bc53
TP		 6522018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
653
654 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
655
87993319
MR		 6562018-02-13 Maciej W. Rozycki <macro@mips.com>
657
658 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
659 variable to `function_index'.
660
68d20676
NC		 6612018-02-13 Nick Clifton <nickc@redhat.com>
662
663 PR 22823
664 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
665 about truncation of printing.
666
d2159fdc
HW		 6672018-02-12 Henry Wong <henry@stuffedcow.net>
668
669 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
670
f174ef9f
NC		 6712018-02-05 Nick Clifton <nickc@redhat.com>
672
673 * po/pt_BR.po: Updated Brazilian Portuguese translation.
674
be3a8dca
IT		 6752018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
676
677 * i386-dis.c (enum): Add pconfig.
678 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
679 (cpu_flags): Add CpuPCONFIG.
680 * i386-opc.h (enum): Add CpuPCONFIG.
681 (i386_cpu_flags): Add cpupconfig.
682 * i386-opc.tbl: Add PCONFIG instruction.
683 * i386-init.h: Regenerate.
684 * i386-tbl.h: Likewise.
685
3233d7d0
IT		 6862018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
687
688 * i386-dis.c (enum): Add PREFIX_0F09.
689 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
690 (cpu_flags): Add CpuWBNOINVD.
691 * i386-opc.h (enum): Add CpuWBNOINVD.
692 (i386_cpu_flags): Add cpuwbnoinvd.
693 * i386-opc.tbl: Add WBNOINVD instruction.
694 * i386-init.h: Regenerate.
695 * i386-tbl.h: Likewise.
696
e925c834
JW		 6972018-01-17 Jim Wilson <jimw@sifive.com>
698
699 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
700
d777820b
IT		 7012018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
702
703 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
704 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
705 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
706 (cpu_flags): Add CpuIBT, CpuSHSTK.
707 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
708 (i386_cpu_flags): Add cpuibt, cpushstk.
709 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
710 * i386-init.h: Regenerate.
711 * i386-tbl.h: Likewise.
712
f6efed01
NC		 7132018-01-16 Nick Clifton <nickc@redhat.com>
714
715 * po/pt_BR.po: Updated Brazilian Portugese translation.
716 * po/de.po: Updated German translation.
717
2721d702
JW		 7182018-01-15 Jim Wilson <jimw@sifive.com>
719
720 * riscv-opc.c (match_c_nop): New.
721 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
722
616dcb87
NC		 7232018-01-15 Nick Clifton <nickc@redhat.com>
724
725 * po/uk.po: Updated Ukranian translation.
726
3957a496
NC		 7272018-01-13 Nick Clifton <nickc@redhat.com>
728
729 * po/opcodes.pot: Regenerated.
730
769c7ea5
NC		 7312018-01-13 Nick Clifton <nickc@redhat.com>
732
733 * configure: Regenerate.
734
faf766e3
NC		 7352018-01-13 Nick Clifton <nickc@redhat.com>
736
737 2.30 branch created.
738
888a89da
IT		 7392018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
740
741 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
742 * i386-tbl.h: Regenerate.
743
cbda583a
JB		 7442018-01-10 Jan Beulich <jbeulich@suse.com>
745
746 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
747 * i386-tbl.h: Re-generate.
748
c9e92278
JB		 7492018-01-10 Jan Beulich <jbeulich@suse.com>
750
751 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
752 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
753 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
754 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
755 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
756 Disp8MemShift of AVX512VL forms.
757 * i386-tbl.h: Re-generate.
758
35fd2b2b
JW		 7592018-01-09 Jim Wilson <jimw@sifive.com>
760
761 * riscv-dis.c (maybe_print_address): If base_reg is zero,
762 then the hi_addr value is zero.
763
91d8b670
JG		 7642018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
765
766 * arm-dis.c (arm_opcodes): Add csdb.
767 (thumb32_opcodes): Add csdb.
768
be2e7d95
JG		 7692018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
770
771 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
772 * aarch64-asm-2.c: Regenerate.
773 * aarch64-dis-2.c: Regenerate.
774 * aarch64-opc-2.c: Regenerate.
775
704a705d
L		 7762018-01-08 H.J. Lu <hongjiu.lu@intel.com>
777
778 PR gas/22681
779 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
780 Remove AVX512 vmovd with 64-bit operands.
781 * i386-tbl.h: Regenerated.
782
35eeb78f
JW		 7832018-01-05 Jim Wilson <jimw@sifive.com>
784
785 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
786 jalr.
787
219d1afa
AM		 7882018-01-03 Alan Modra <amodra@gmail.com>
789
790 Update year range in copyright notice of all files.
791
1508bbf5
JB		 7922018-01-02 Jan Beulich <jbeulich@suse.com>
793
794 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
795 and OPERAND_TYPE_REGZMM entries.
796
1e563868 797For older changes see ChangeLog-2017
3499769a 798\f
1e563868 799Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 800
801Copying and distribution of this file, with or without modification,
802are permitted in any medium without royalty provided the copyright
803notice and this notice are preserved.
804
805Local Variables:
806mode: change-log
807left-margin: 8
808fill-column: 74
809version-control: never
810End:
GDB Binutils - Deliverables
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