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Fix the use by the RL78 assembler of an uninitialised field in the expresion structure.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9da4dfd6
JD		 12018-09-08 John Darrington <john@darrington.wattle.id.au>
2
3 * disassemble.c (ARCH_s12z): Define if ARCH_all.
4
be192bc2
JW		 52018-08-31 Kito Cheng <kito@andestech.com>
6
7 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
8 compressed floating point instructions.
9
43135d3b
JW		 102018-08-30 Kito Cheng <kito@andestech.com>
11
12 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
13 riscv_opcode.xlen_requirement.
14 * riscv-opc.c (riscv_opcodes): Update for struct change.
15
df28970f
MA		 162018-08-29 Martin Aberg <maberg@gaisler.com>
17
18 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
19 psr (PWRPSR) instruction.
20
9108bc33
CX		 212018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
22
23 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
24
bd782c07
CX		 252018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
26
27 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
28
ac8cb70f
CX		 292018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
30
31 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
32 loongson3a as an alias of gs464 for compatibility.
33 * mips-opc.c (mips_opcodes): Change Comments.
34
a693765e
CX		 352018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
36
37 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
38 option.
39 (print_mips_disassembler_options): Document -M loongson-ext.
40 * mips-opc.c (LEXT2): New macro.
41 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
42
bdc6c06e
CX		 432018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
44
45 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
46 descriptors.
47 (parse_mips_ase_option): Handle -M loongson-ext option.
48 (print_mips_disassembler_options): Document -M loongson-ext.
49 * mips-opc.c (IL3A): Delete.
50 * mips-opc.c (LEXT): New macro.
51 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
52 instructions.
53
716c08de
CX		 542018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
55
56 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
57 descriptors.
58 (parse_mips_ase_option): Handle -M loongson-cam option.
59 (print_mips_disassembler_options): Document -M loongson-cam.
60 * mips-opc.c (LCAM): New macro.
61 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
62 instructions.
63
9cf7e568
AM		 642018-08-21 Alan Modra <amodra@gmail.com>
65
66 * ppc-dis.c (operand_value_powerpc): Init "invalid".
67 (skip_optional_operands): Count optional operands, and update
68 ppc_optional_operand_value call.
69 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
70 (extract_vlensi): Likewise.
71 (extract_fxm): Return default value for missing optional operand.
72 (extract_ls, extract_raq, extract_tbr): Likewise.
73 (insert_sxl, extract_sxl): New functions.
74 (insert_esync, extract_esync): Remove Power9 handling and simplify.
75 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
76 flag and extra entry.
77 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
78 extract_sxl.
79
d203b41a 802018-08-20 Alan Modra <amodra@gmail.com>
f4107842 81
d203b41a 82 * sh-opc.h (MASK): Simplify.
f4107842 83
08a8fe2f 842018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 85
d203b41a
AM		 86 * s12z-dis.c (bm_decode): Deal with cases where the mode is
87 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 88 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 89
08a8fe2f 902018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 91
92 * s12z.h: Delete.
7ba3ba91 93
1bc60e56
L		 942018-08-14 H.J. Lu <hongjiu.lu@intel.com>
95
96 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
97 address with the addr32 prefix and without base nor index
98 registers.
99
d871f3f4
L		 1002018-08-11 H.J. Lu <hongjiu.lu@intel.com>
101
102 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
103 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
104 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
105 (cpu_flags): Add CpuCMOV and CpuFXSR.
106 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
107 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
108 * i386-init.h: Regenerated.
109 * i386-tbl.h: Likewise.
110
b6523c37 1112018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
112
113 * arc-regs.h: Update auxiliary registers.
114
e968fc9b
JB		 1152018-08-06 Jan Beulich <jbeulich@suse.com>
116
117 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
118 (RegIP, RegIZ): Define.
119 * i386-reg.tbl: Adjust comments.
120 (rip): Use Qword instead of BaseIndex. Use RegIP.
121 (eip): Use Dword instead of BaseIndex. Use RegIP.
122 (riz): Add Qword. Use RegIZ.
123 (eiz): Add Dword. Use RegIZ.
124 * i386-tbl.h: Re-generate.
125
dbf8be89
JB		 1262018-08-03 Jan Beulich <jbeulich@suse.com>
127
128 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
129 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
130 vpmovzxdq, vpmovzxwd): Remove NoRex64.
131 * i386-tbl.h: Re-generate.
132
c48dadc9
JB		 1332018-08-03 Jan Beulich <jbeulich@suse.com>
134
135 * i386-gen.c (operand_types): Remove Mem field.
136 * i386-opc.h (union i386_operand_type): Remove mem field.
137 * i386-init.h, i386-tbl.h: Re-generate.
138
cb86a42a
AM		 1392018-08-01 Alan Modra <amodra@gmail.com>
140
141 * po/POTFILES.in: Regenerate.
142
07cc0450
NC		 1432018-07-31 Nick Clifton <nickc@redhat.com>
144
145 * po/sv.po: Updated Swedish translation.
146
1424ad86
JB		 1472018-07-31 Jan Beulich <jbeulich@suse.com>
148
149 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
150 * i386-init.h, i386-tbl.h: Re-generate.
151
ae2387fe
JB		 1522018-07-31 Jan Beulich <jbeulich@suse.com>
153
154 * i386-opc.h (ZEROING_MASKING) Rename to ...
155 (DYNAMIC_MASKING): ... this. Adjust comment.
156 * i386-opc.tbl (MaskingMorZ): Define.
157 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
158 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
159 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
160 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
161 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
162 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
163 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
164 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
165 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
166
6ff00b5e
JB		 1672018-07-31 Jan Beulich <jbeulich@suse.com>
168
169 * i386-opc.tbl: Use element rather than vector size for AVX512*
170 scatter/gather insns.
171 * i386-tbl.h: Re-generate.
172
e951d5ca
JB		 1732018-07-31 Jan Beulich <jbeulich@suse.com>
174
175 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
176 (cpu_flags): Drop CpuVREX.
177 * i386-opc.h (CpuVREX): Delete.
178 (union i386_cpu_flags): Remove cpuvrex.
179 * i386-init.h, i386-tbl.h: Re-generate.
180
eb41b248
JW		 1812018-07-30 Jim Wilson <jimw@sifive.com>
182
183 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
184 fields.
185 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
186
b8891f8d
AJ		 1872018-07-30 Andrew Jenner <andrew@codesourcery.com>
188
189 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
190 * Makefile.in: Regenerated.
191 * configure.ac: Add C-SKY.
192 * configure: Regenerated.
193 * csky-dis.c: New file.
194 * csky-opc.h: New file.
195 * disassemble.c (ARCH_csky): Define.
196 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
197 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
198
16065af1
AM		 1992018-07-27 Alan Modra <amodra@gmail.com>
200
201 * ppc-opc.c (insert_sprbat): Correct function parameter and
202 return type.
203 (extract_sprbat): Likewise, variable too.
204
fa758a70
AC		 2052018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
206 Alan Modra <amodra@gmail.com>
207
208 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
209 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
210 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
211 support disjointed BAT.
212 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
213 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
214 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
215
4a1b91ea
L		 2162018-07-25 H.J. Lu <hongjiu.lu@intel.com>
217 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
218
219 * i386-gen.c (adjust_broadcast_modifier): New function.
220 (process_i386_opcode_modifier): Add an argument for operands.
221 Adjust the Broadcast value based on operands.
222 (output_i386_opcode): Pass operand_types to
223 process_i386_opcode_modifier.
224 (process_i386_opcodes): Pass NULL as operands to
225 process_i386_opcode_modifier.
226 * i386-opc.h (BYTE_BROADCAST): New.
227 (WORD_BROADCAST): Likewise.
228 (DWORD_BROADCAST): Likewise.
229 (QWORD_BROADCAST): Likewise.
230 (i386_opcode_modifier): Expand broadcast to 3 bits.
231 * i386-tbl.h: Regenerated.
232
67ce483b
AM		 2332018-07-24 Alan Modra <amodra@gmail.com>
234
235 PR 23430
236 * or1k-desc.h: Regenerate.
237
4174bfff
JB		 2382018-07-24 Jan Beulich <jbeulich@suse.com>
239
240 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
241 vcvtusi2ss, and vcvtusi2sd.
242 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
243 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
244 * i386-tbl.h: Re-generate.
245
04e65276
CZ		 2462018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
247
248 * arc-opc.c (extract_w6): Fix extending the sign.
249
47e6f81c
CZ		 2502018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
251
252 * arc-tbl.h (vewt): Allow it for ARC EM family.
253
bb71536f
AM		 2542018-07-23 Alan Modra <amodra@gmail.com>
255
256 PR 23419
257 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
258 opcode variants for mtspr/mfspr encodings.
259
8095d2f7
CX		 2602018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
261 Maciej W. Rozycki <macro@mips.com>
262
263 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
264 loongson3a descriptors.
265 (parse_mips_ase_option): Handle -M loongson-mmi option.
266 (print_mips_disassembler_options): Document -M loongson-mmi.
267 * mips-opc.c (LMMI): New macro.
268 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
269 instructions.
270
5f32791e
JB		 2712018-07-19 Jan Beulich <jbeulich@suse.com>
272
273 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
274 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
275 IgnoreSize and [XYZ]MMword where applicable.
276 * i386-tbl.h: Re-generate.
277
625cbd7a
JB		 2782018-07-19 Jan Beulich <jbeulich@suse.com>
279
280 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
281 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
282 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
283 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
284 * i386-tbl.h: Re-generate.
285
86b15c32
JB		 2862018-07-19 Jan Beulich <jbeulich@suse.com>
287
288 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
289 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
290 VPCLMULQDQ templates into their respective AVX512VL counterparts
291 where possible, using Disp8ShiftVL and CheckRegSize instead of
292 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
293 * i386-tbl.h: Re-generate.
294
cf769ed5
JB		 2952018-07-19 Jan Beulich <jbeulich@suse.com>
296
297 * i386-opc.tbl: Fold AVX512DQ templates into their respective
298 AVX512VL counterparts where possible, using Disp8ShiftVL and
299 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
300 IgnoreSize) as appropriate.
301 * i386-tbl.h: Re-generate.
302
8282b7ad
JB		 3032018-07-19 Jan Beulich <jbeulich@suse.com>
304
305 * i386-opc.tbl: Fold AVX512BW templates into their respective
306 AVX512VL counterparts where possible, using Disp8ShiftVL and
307 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
308 IgnoreSize) as appropriate.
309 * i386-tbl.h: Re-generate.
310
755908cc
JB		 3112018-07-19 Jan Beulich <jbeulich@suse.com>
312
313 * i386-opc.tbl: Fold AVX512CD templates into their respective
314 AVX512VL counterparts where possible, using Disp8ShiftVL and
315 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
316 IgnoreSize) as appropriate.
317 * i386-tbl.h: Re-generate.
318
7091c612
JB		 3192018-07-19 Jan Beulich <jbeulich@suse.com>
320
321 * i386-opc.h (DISP8_SHIFT_VL): New.
322 * i386-opc.tbl (Disp8ShiftVL): Define.
323 (various): Fold AVX512VL templates into their respective
324 AVX512F counterparts where possible, using Disp8ShiftVL and
325 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
326 IgnoreSize) as appropriate.
327 * i386-tbl.h: Re-generate.
328
c30be56e
JB		 3292018-07-19 Jan Beulich <jbeulich@suse.com>
330
331 * Makefile.am: Change dependencies and rule for
332 $(srcdir)/i386-init.h.
333 * Makefile.in: Re-generate.
334 * i386-gen.c (process_i386_opcodes): New local variable
335 "marker". Drop opening of input file. Recognize marker and line
336 number directives.
337 * i386-opc.tbl (OPCODE_I386_H): Define.
338 (i386-opc.h): Include it.
339 (None): Undefine.
340
11a322db
L		 3412018-07-18 H.J. Lu <hongjiu.lu@intel.com>
342
343 PR gas/23418
344 * i386-opc.h (Byte): Update comments.
345 (Word): Likewise.
346 (Dword): Likewise.
347 (Fword): Likewise.
348 (Qword): Likewise.
349 (Tbyte): Likewise.
350 (Xmmword): Likewise.
351 (Ymmword): Likewise.
352 (Zmmword): Likewise.
353 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
354 vcvttps2uqq.
355 * i386-tbl.h: Regenerated.
356
cde3679e
NC		 3572018-07-12 Sudakshina Das <sudi.das@arm.com>
358
359 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
360 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
361 * aarch64-asm-2.c: Regenerate.
362 * aarch64-dis-2.c: Regenerate.
363 * aarch64-opc-2.c: Regenerate.
364
45a28947
TC		 3652018-07-12 Tamar Christina <tamar.christina@arm.com>
366
367 PR binutils/23192
368 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
369 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
370 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
371 sqdmulh, sqrdmulh): Use Em16.
372
c597cc3d
SD		 3732018-07-11 Sudakshina Das <sudi.das@arm.com>
374
375 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
376 csdb together with them.
377 (thumb32_opcodes): Likewise.
378
a79eaed6
JB		 3792018-07-11 Jan Beulich <jbeulich@suse.com>
380
381 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
382 requiring 32-bit registers as operands 2 and 3. Improve
383 comments.
384 (mwait, mwaitx): Fold templates. Improve comments.
385 OPERAND_TYPE_INOUTPORTREG.
386 * i386-tbl.h: Re-generate.
387
2fb5be8d
JB		 3882018-07-11 Jan Beulich <jbeulich@suse.com>
389
390 * i386-gen.c (operand_type_init): Remove
391 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
392 OPERAND_TYPE_INOUTPORTREG.
393 * i386-init.h: Re-generate.
394
7f5cad30
JB		 3952018-07-11 Jan Beulich <jbeulich@suse.com>
396
397 * i386-opc.tbl (wrssd, wrussd): Add Dword.
398 (wrssq, wrussq): Add Qword.
399 * i386-tbl.h: Re-generate.
400
f0a85b07
JB		 4012018-07-11 Jan Beulich <jbeulich@suse.com>
402
403 * i386-opc.h: Rename OTMax to OTNum.
404 (OTNumOfUints): Adjust calculation.
405 (OTUnused): Directly alias to OTNum.
406
9dcb0ba4
MR		 4072018-07-09 Maciej W. Rozycki <macro@mips.com>
408
409 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
410 `reg_xys'.
411 (lea_reg_xys): Likewise.
412 (print_insn_loop_primitive): Rename `reg' local variable to
413 `reg_dxy'.
414
f311ba7e
TC		 4152018-07-06 Tamar Christina <tamar.christina@arm.com>
416
417 PR binutils/23242
418 * aarch64-tbl.h (ldarh): Fix disassembly mask.
419
cba05feb
TC		 4202018-07-06 Tamar Christina <tamar.christina@arm.com>
421
422 PR binutils/23369
423 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
424 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
425
471b9d15
MR		 4262018-07-02 Maciej W. Rozycki <macro@mips.com>
427
428 PR tdep/8282
429 * mips-dis.c (mips_option_arg_t): New enumeration.
430 (mips_options): New variable.
431 (disassembler_options_mips): New function.
432 (print_mips_disassembler_options): Reimplement in terms of
433 `disassembler_options_mips'.
434 * arm-dis.c (disassembler_options_arm): Adapt to using the
435 `disasm_options_and_args_t' structure.
436 * ppc-dis.c (disassembler_options_powerpc): Likewise.
437 * s390-dis.c (disassembler_options_s390): Likewise.
438
c0c468d5
TP		 4392018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
440
441 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
442 expected result.
443 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
444 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
445 * testsuite/ld-arm/tls-longplt.d: Likewise.
446
369c9167
TC		 4472018-06-29 Tamar Christina <tamar.christina@arm.com>
448
449 PR binutils/23192
450 * aarch64-asm-2.c: Regenerate.
451 * aarch64-dis-2.c: Likewise.
452 * aarch64-opc-2.c: Likewise.
453 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
454 * aarch64-opc.c (operand_general_constraint_met_p,
455 aarch64_print_operand): Likewise.
456 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
457 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
458 fmlal2, fmlsl2.
459 (AARCH64_OPERANDS): Add Em2.
460
30aa1306
NC		 4612018-06-26 Nick Clifton <nickc@redhat.com>
462
463 * po/uk.po: Updated Ukranian translation.
464 * po/de.po: Updated German translation.
465 * po/pt_BR.po: Updated Brazilian Portuguese translation.
466
eca4b721
NC		 4672018-06-26 Nick Clifton <nickc@redhat.com>
468
469 * nfp-dis.c: Fix spelling mistake.
470
71300e2c
NC		 4712018-06-24 Nick Clifton <nickc@redhat.com>
472
473 * configure: Regenerate.
474 * po/opcodes.pot: Regenerate.
475
719d8288
NC		 4762018-06-24 Nick Clifton <nickc@redhat.com>
477
478 2.31 branch created.
479
514cd3a0
TC		 4802018-06-19 Tamar Christina <tamar.christina@arm.com>
481
482 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
483 * aarch64-asm-2.c: Regenerate.
484 * aarch64-dis-2.c: Likewise.
485
385e4d0f
MR		 4862018-06-21 Maciej W. Rozycki <macro@mips.com>
487
488 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
489 `-M ginv' option description.
490
160d1b3d
SH		 4912018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
492
493 PR gas/23305
494 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
495 la and lla.
496
d0ac1c44
SM		 4972018-06-19 Simon Marchi <simon.marchi@ericsson.com>
498
499 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
500 * configure.ac: Remove AC_PREREQ.
501 * Makefile.in: Re-generate.
502 * aclocal.m4: Re-generate.
503 * configure: Re-generate.
504
6f20c942
FS		 5052018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
506
507 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
508 mips64r6 descriptors.
509 (parse_mips_ase_option): Handle -Mginv option.
510 (print_mips_disassembler_options): Document -Mginv.
511 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
512 (GINV): New macro.
513 (mips_opcodes): Define ginvi and ginvt.
514
730c3174
SE		 5152018-06-13 Scott Egerton <scott.egerton@imgtec.com>
516 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
517
518 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
519 * mips-opc.c (CRC, CRC64): New macros.
520 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
521 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
522 crc32cd for CRC64.
523
cb366992
EB		 5242018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
525
526 PR 20319
527 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
528 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
529
ce72cd46
AM		 5302018-06-06 Alan Modra <amodra@gmail.com>
531
532 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
533 setjmp. Move init for some other vars later too.
534
4b8e28c7
MF		 5352018-06-04 Max Filippov <jcmvbkbc@gmail.com>
536
537 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
538 (dis_private): Add new fields for property section tracking.
539 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
540 (xtensa_instruction_fits): New functions.
541 (fetch_data): Bump minimal fetch size to 4.
542 (print_insn_xtensa): Make struct dis_private static.
543 Load and prepare property table on section change.
544 Don't disassemble literals. Don't disassemble instructions that
545 cross property table boundaries.
546
55e99962
L		 5472018-06-01 H.J. Lu <hongjiu.lu@intel.com>
548
549 * configure: Regenerated.
550
733bd0ab
JB		 5512018-06-01 Jan Beulich <jbeulich@suse.com>
552
553 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
554 * i386-tbl.h: Re-generate.
555
dfd27d41
JB		 5562018-06-01 Jan Beulich <jbeulich@suse.com>
557
558 * i386-opc.tbl (sldt, str): Add NoRex64.
559 * i386-tbl.h: Re-generate.
560
64795710
JB		 5612018-06-01 Jan Beulich <jbeulich@suse.com>
562
563 * i386-opc.tbl (invpcid): Add Oword.
564 * i386-tbl.h: Re-generate.
565
030157d8
AM		 5662018-06-01 Alan Modra <amodra@gmail.com>
567
568 * sysdep.h (_bfd_error_handler): Don't declare.
569 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
570 * rl78-decode.opc: Likewise.
571 * msp430-decode.c: Regenerate.
572 * rl78-decode.c: Regenerate.
573
a9660a6f
AP		 5742018-05-30 Amit Pawar <Amit.Pawar@amd.com>
575
576 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
577 * i386-init.h : Regenerated.
578
277eb7f6
AM		 5792018-05-25 Alan Modra <amodra@gmail.com>
580
581 * Makefile.in: Regenerate.
582 * po/POTFILES.in: Regenerate.
583
98553ad3
PB		 5842018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
585
586 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
587 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
588 (insert_bab, extract_bab, insert_btab, extract_btab,
589 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
590 (BAT, BBA VBA RBS XB6S): Delete macros.
591 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
592 (BB, BD, RBX, XC6): Update for new macros.
593 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
594 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
595 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
596 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
597
7b4ae824
JD		 5982018-05-18 John Darrington <john@darrington.wattle.id.au>
599
600 * Makefile.am: Add support for s12z architecture.
601 * configure.ac: Likewise.
602 * disassemble.c: Likewise.
603 * disassemble.h: Likewise.
604 * Makefile.in: Regenerate.
605 * configure: Regenerate.
606 * s12z-dis.c: New file.
607 * s12z.h: New file.
608
29e0f0a1
AM		 6092018-05-18 Alan Modra <amodra@gmail.com>
610
611 * nfp-dis.c: Don't #include libbfd.h.
612 (init_nfp3200_priv): Use bfd_get_section_contents.
613 (nit_nfp6000_mecsr_sec): Likewise.
614
809276d2
NC		 6152018-05-17 Nick Clifton <nickc@redhat.com>
616
617 * po/zh_CN.po: Updated simplified Chinese translation.
618
ff329288
TC		 6192018-05-16 Tamar Christina <tamar.christina@arm.com>
620
621 PR binutils/23109
622 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
623 * aarch64-dis-2.c: Regenerate.
624
f9830ec1
TC		 6252018-05-15 Tamar Christina <tamar.christina@arm.com>
626
627 PR binutils/21446
628 * aarch64-asm.c (opintl.h): Include.
629 (aarch64_ins_sysreg): Enforce read/write constraints.
630 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
631 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
632 (F_REG_READ, F_REG_WRITE): New.
633 * aarch64-opc.c (aarch64_print_operand): Generate notes for
634 AARCH64_OPND_SYSREG.
635 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
636 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
637 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
638 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
639 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
640 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
641 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
642 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
643 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
644 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
645 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
646 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
647 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
648 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
649 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
650 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
651 msr (F_SYS_WRITE), mrs (F_SYS_READ).
652
7d02540a
TC		 6532018-05-15 Tamar Christina <tamar.christina@arm.com>
654
655 PR binutils/21446
656 * aarch64-dis.c (no_notes: New.
657 (parse_aarch64_dis_option): Support notes.
658 (aarch64_decode_insn, print_operands): Likewise.
659 (print_aarch64_disassembler_options): Document notes.
660 * aarch64-opc.c (aarch64_print_operand): Support notes.
661
561a72d4
TC		 6622018-05-15 Tamar Christina <tamar.christina@arm.com>
663
664 PR binutils/21446
665 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
666 and take error struct.
667 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
668 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
669 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
670 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
671 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
672 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
673 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
674 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
675 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
676 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
677 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
678 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
679 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
680 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
681 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
682 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
683 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
684 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
685 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
686 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
687 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
688 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
689 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
690 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
691 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
692 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
693 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
694 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
695 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
696 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
697 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
698 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
699 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
700 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
701 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
702 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
703 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
704 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
705 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
706 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
707 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
708 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
709 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
710 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
711 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
712 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
713 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
714 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
715 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
716 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
717 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
718 (determine_disassembling_preference, aarch64_decode_insn,
719 print_insn_aarch64_word, print_insn_data): Take errors struct.
720 (print_insn_aarch64): Use errors.
721 * aarch64-asm-2.c: Regenerate.
722 * aarch64-dis-2.c: Regenerate.
723 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
724 boolean in aarch64_insert_operan.
725 (print_operand_extractor): Likewise.
726 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
727
1678bd35
FT		 7282018-05-15 Francois H. Theron <francois.theron@netronome.com>
729
730 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
731
06cfb1c8
L		 7322018-05-09 H.J. Lu <hongjiu.lu@intel.com>
733
734 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
735
84f9f8c3
AM		 7362018-05-09 Sebastian Rasmussen <sebras@gmail.com>
737
738 * cr16-opc.c (cr16_instruction): Comment typo fix.
739 * hppa-dis.c (print_insn_hppa): Likewise.
740
e6f372ba
JW		 7412018-05-08 Jim Wilson <jimw@sifive.com>
742
743 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
744 (match_c_slli64, match_srxi_as_c_srxi): New.
745 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
746 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
747 <c.slli, c.srli, c.srai>: Use match_s_slli.
748 <c.slli64, c.srli64, c.srai64>: New.
749
f413a913
AM		 7502018-05-08 Alan Modra <amodra@gmail.com>
751
752 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
753 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
754 partition opcode space for index lookup.
755
a87a6478
PB		 7562018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
757
758 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
759 <insn_length>: ...with this. Update usage.
760 Remove duplicate call to *info->memory_error_func.
761
c0a30a9f
L		 7622018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
763 H.J. Lu <hongjiu.lu@intel.com>
764
765 * i386-dis.c (Gva): New.
766 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
767 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
768 (prefix_table): New instructions (see prefix above).
769 (mod_table): New instructions (see prefix above).
770 (OP_G): Handle va_mode.
771 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
772 CPU_MOVDIR64B_FLAGS.
773 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
774 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
775 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
776 * i386-opc.tbl: Add movidir{i,64b}.
777 * i386-init.h: Regenerated.
778 * i386-tbl.h: Likewise.
779
75c0a438
L		 7802018-05-07 H.J. Lu <hongjiu.lu@intel.com>
781
782 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
783 AddrPrefixOpReg.
784 * i386-opc.h (AddrPrefixOp0): Renamed to ...
785 (AddrPrefixOpReg): This.
786 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
787 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
788
2ceb7719
PB		 7892018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
790
791 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
792 (vle_num_opcodes): Likewise.
793 (spe2_num_opcodes): Likewise.
794 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
795 initialization loop.
796 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
797 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
798 only once.
799
b3ac5c6c
TC		 8002018-05-01 Tamar Christina <tamar.christina@arm.com>
801
802 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
803
fe944acf
FT		 8042018-04-30 Francois H. Theron <francois.theron@netronome.com>
805
806 Makefile.am: Added nfp-dis.c.
807 configure.ac: Added bfd_nfp_arch.
808 disassemble.h: Added print_insn_nfp prototype.
809 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
810 nfp-dis.c: New, for NFP support.
811 po/POTFILES.in: Added nfp-dis.c to the list.
812 Makefile.in: Regenerate.
813 configure: Regenerate.
814
e2195274
JB		 8152018-04-26 Jan Beulich <jbeulich@suse.com>
816
817 * i386-opc.tbl: Fold various non-memory operand AVX512VL
818 templates into their base ones.
819 * i386-tlb.h: Re-generate.
820
59ef5df4
JB		 8212018-04-26 Jan Beulich <jbeulich@suse.com>
822
823 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
824 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
825 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
826 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
827 * i386-init.h: Re-generate.
828
6e041cf4
JB		 8292018-04-26 Jan Beulich <jbeulich@suse.com>
830
831 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
832 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
833 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
834 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
835 comment.
836 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
837 and CpuRegMask.
838 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
839 CpuRegMask: Delete.
840 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
841 cpuregzmm, and cpuregmask.
842 * i386-init.h: Re-generate.
843 * i386-tbl.h: Re-generate.
844
0e0eea78
JB		 8452018-04-26 Jan Beulich <jbeulich@suse.com>
846
847 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
848 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
849 * i386-init.h: Re-generate.
850
2f1bada2
JB		 8512018-04-26 Jan Beulich <jbeulich@suse.com>
852
853 * i386-gen.c (VexImmExt): Delete.
854 * i386-opc.h (VexImmExt, veximmext): Delete.
855 * i386-opc.tbl: Drop all VexImmExt uses.
856 * i386-tlb.h: Re-generate.
857
bacd1457
JB		 8582018-04-25 Jan Beulich <jbeulich@suse.com>
859
860 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
861 register-only forms.
862 * i386-tlb.h: Re-generate.
863
10bba94b
TC		 8642018-04-25 Tamar Christina <tamar.christina@arm.com>
865
866 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
867
c48935d7
IT		 8682018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
869
870 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
871 PREFIX_0F1C.
872 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
873 (cpu_flags): Add CpuCLDEMOTE.
874 * i386-init.h: Regenerate.
875 * i386-opc.h (enum): Add CpuCLDEMOTE,
876 (i386_cpu_flags): Add cpucldemote.
877 * i386-opc.tbl: Add cldemote.
878 * i386-tbl.h: Regenerate.
879
211dc24b
AM		 8802018-04-16 Alan Modra <amodra@gmail.com>
881
882 * Makefile.am: Remove sh5 and sh64 support.
883 * configure.ac: Likewise.
884 * disassemble.c: Likewise.
885 * disassemble.h: Likewise.
886 * sh-dis.c: Likewise.
887 * sh64-dis.c: Delete.
888 * sh64-opc.c: Delete.
889 * sh64-opc.h: Delete.
890 * Makefile.in: Regenerate.
891 * configure: Regenerate.
892 * po/POTFILES.in: Regenerate.
893
a9a4b302
AM		 8942018-04-16 Alan Modra <amodra@gmail.com>
895
896 * Makefile.am: Remove w65 support.
897 * configure.ac: Likewise.
898 * disassemble.c: Likewise.
899 * disassemble.h: Likewise.
900 * w65-dis.c: Delete.
901 * w65-opc.h: Delete.
902 * Makefile.in: Regenerate.
903 * configure: Regenerate.
904 * po/POTFILES.in: Regenerate.
905
04cb01fd
AM		 9062018-04-16 Alan Modra <amodra@gmail.com>
907
908 * configure.ac: Remove we32k support.
909 * configure: Regenerate.
910
c2bf1eec
AM		 9112018-04-16 Alan Modra <amodra@gmail.com>
912
913 * Makefile.am: Remove m88k support.
914 * configure.ac: Likewise.
915 * disassemble.c: Likewise.
916 * disassemble.h: Likewise.
917 * m88k-dis.c: Delete.
918 * Makefile.in: Regenerate.
919 * configure: Regenerate.
920 * po/POTFILES.in: Regenerate.
921
6793974d
AM		 9222018-04-16 Alan Modra <amodra@gmail.com>
923
924 * Makefile.am: Remove i370 support.
925 * configure.ac: Likewise.
926 * disassemble.c: Likewise.
927 * disassemble.h: Likewise.
928 * i370-dis.c: Delete.
929 * i370-opc.c: Delete.
930 * Makefile.in: Regenerate.
931 * configure: Regenerate.
932 * po/POTFILES.in: Regenerate.
933
e82aa794
AM		 9342018-04-16 Alan Modra <amodra@gmail.com>
935
936 * Makefile.am: Remove h8500 support.
937 * configure.ac: Likewise.
938 * disassemble.c: Likewise.
939 * disassemble.h: Likewise.
940 * h8500-dis.c: Delete.
941 * h8500-opc.h: Delete.
942 * Makefile.in: Regenerate.
943 * configure: Regenerate.
944 * po/POTFILES.in: Regenerate.
945
fceadf09
AM		 9462018-04-16 Alan Modra <amodra@gmail.com>
947
948 * configure.ac: Remove tahoe support.
949 * configure: Regenerate.
950
ae1d3843
L		 9512018-04-15 H.J. Lu <hongjiu.lu@intel.com>
952
953 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
954 umwait.
955 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
956 64-bit mode.
957 * i386-tbl.h: Regenerated.
958
de89d0a3
IT		 9592018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
960
961 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
962 PREFIX_MOD_1_0FAE_REG_6.
963 (va_mode): New.
964 (OP_E_register): Use va_mode.
965 * i386-dis-evex.h (prefix_table):
966 New instructions (see prefixes above).
967 * i386-gen.c (cpu_flag_init): Add WAITPKG.
968 (cpu_flags): Likewise.
969 * i386-opc.h (enum): Likewise.
970 (i386_cpu_flags): Likewise.
971 * i386-opc.tbl: Add umonitor, umwait, tpause.
972 * i386-init.h: Regenerate.
973 * i386-tbl.h: Likewise.
974
a8eb42a8
AM		 9752018-04-11 Alan Modra <amodra@gmail.com>
976
977 * opcodes/i860-dis.c: Delete.
978 * opcodes/i960-dis.c: Delete.
979 * Makefile.am: Remove i860 and i960 support.
980 * configure.ac: Likewise.
981 * disassemble.c: Likewise.
982 * disassemble.h: Likewise.
983 * Makefile.in: Regenerate.
984 * configure: Regenerate.
985 * po/POTFILES.in: Regenerate.
986
caf0678c
L		 9872018-04-04 H.J. Lu <hongjiu.lu@intel.com>
988
989 PR binutils/23025
990 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
991 to 0.
992 (print_insn): Clear vex instead of vex.evex.
993
4fb0d2b9
NC		 9942018-04-04 Nick Clifton <nickc@redhat.com>
995
996 * po/es.po: Updated Spanish translation.
997
c39e5b26
JB		 9982018-03-28 Jan Beulich <jbeulich@suse.com>
999
1000 * i386-gen.c (opcode_modifiers): Delete VecESize.
1001 * i386-opc.h (VecESize): Delete.
1002 (struct i386_opcode_modifier): Delete vecesize.
1003 * i386-opc.tbl: Drop VecESize.
1004 * i386-tlb.h: Re-generate.
1005
8e6e0792
JB		 10062018-03-28 Jan Beulich <jbeulich@suse.com>
1007
1008 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1009 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1010 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1011 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1012 * i386-tlb.h: Re-generate.
1013
9f123b91
JB		 10142018-03-28 Jan Beulich <jbeulich@suse.com>
1015
1016 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1017 Fold AVX512 forms
1018 * i386-tlb.h: Re-generate.
1019
9646c87b
JB		 10202018-03-28 Jan Beulich <jbeulich@suse.com>
1021
1022 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1023 (vex_len_table): Drop Y for vcvt*2si.
1024 (putop): Replace plain 'Y' handling by abort().
1025
c8d59609
NC		 10262018-03-28 Nick Clifton <nickc@redhat.com>
1027
1028 PR 22988
1029 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1030 instructions with only a base address register.
1031 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1032 handle AARHC64_OPND_SVE_ADDR_R.
1033 (aarch64_print_operand): Likewise.
1034 * aarch64-asm-2.c: Regenerate.
1035 * aarch64_dis-2.c: Regenerate.
1036 * aarch64-opc-2.c: Regenerate.
1037
b8c169f3
JB		 10382018-03-22 Jan Beulich <jbeulich@suse.com>
1039
1040 * i386-opc.tbl: Drop VecESize from register only insn forms and
1041 memory forms not allowing broadcast.
1042 * i386-tlb.h: Re-generate.
1043
96bc132a
JB		 10442018-03-22 Jan Beulich <jbeulich@suse.com>
1045
1046 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1047 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1048 sha256*): Drop Disp<N>.
1049
9f79e886
JB		 10502018-03-22 Jan Beulich <jbeulich@suse.com>
1051
1052 * i386-dis.c (EbndS, bnd_swap_mode): New.
1053 (prefix_table): Use EbndS.
1054 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1055 * i386-opc.tbl (bndmov): Move misplaced Load.
1056 * i386-tlb.h: Re-generate.
1057
d6793fa1
JB		 10582018-03-22 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1061 templates allowing memory operands and folded ones for register
1062 only flavors.
1063 * i386-tlb.h: Re-generate.
1064
f7768225
JB		 10652018-03-22 Jan Beulich <jbeulich@suse.com>
1066
1067 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1068 256-bit templates. Drop redundant leftover Disp<N>.
1069 * i386-tlb.h: Re-generate.
1070
0e35537d
JW		 10712018-03-14 Kito Cheng <kito.cheng@gmail.com>
1072
1073 * riscv-opc.c (riscv_insn_types): New.
1074
b4a3689a
NC		 10752018-03-13 Nick Clifton <nickc@redhat.com>
1076
1077 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1078
d3d50934
L		 10792018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1080
1081 * i386-opc.tbl: Add Optimize to clr.
1082 * i386-tbl.h: Regenerated.
1083
bd5dea88
L		 10842018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1085
1086 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1087 * i386-opc.h (OldGcc): Removed.
1088 (i386_opcode_modifier): Remove oldgcc.
1089 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1090 instructions for old (<= 2.8.1) versions of gcc.
1091 * i386-tbl.h: Regenerated.
1092
e771e7c9
JB		 10932018-03-08 Jan Beulich <jbeulich@suse.com>
1094
1095 * i386-opc.h (EVEXDYN): New.
1096 * i386-opc.tbl: Fold various AVX512VL templates.
1097 * i386-tlb.h: Re-generate.
1098
ed438a93
JB		 10992018-03-08 Jan Beulich <jbeulich@suse.com>
1100
1101 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1102 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1103 vpexpandd, vpexpandq): Fold AFX512VF templates.
1104 * i386-tlb.h: Re-generate.
1105
454172a9
JB		 11062018-03-08 Jan Beulich <jbeulich@suse.com>
1107
1108 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1109 Fold 128- and 256-bit VEX-encoded templates.
1110 * i386-tlb.h: Re-generate.
1111
36824150
JB		 11122018-03-08 Jan Beulich <jbeulich@suse.com>
1113
1114 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1115 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1116 vpexpandd, vpexpandq): Fold AVX512F templates.
1117 * i386-tlb.h: Re-generate.
1118
e7f5c0a9
JB		 11192018-03-08 Jan Beulich <jbeulich@suse.com>
1120
1121 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
1122 64-bit templates. Drop Disp<N>.
1123 * i386-tlb.h: Re-generate.
1124
25a4277f
JB		 11252018-03-08 Jan Beulich <jbeulich@suse.com>
1126
1127 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
1128 and 256-bit templates.
1129 * i386-tlb.h: Re-generate.
1130
d2224064
JB		 11312018-03-08 Jan Beulich <jbeulich@suse.com>
1132
1133 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
1134 * i386-tlb.h: Re-generate.
1135
1b193f0b
JB		 11362018-03-08 Jan Beulich <jbeulich@suse.com>
1137
1138 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
1139 Drop NoAVX.
1140 * i386-tlb.h: Re-generate.
1141
f2f6a710
JB		 11422018-03-08 Jan Beulich <jbeulich@suse.com>
1143
1144 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
1145 * i386-tlb.h: Re-generate.
1146
38e314eb
JB		 11472018-03-08 Jan Beulich <jbeulich@suse.com>
1148
1149 * i386-gen.c (opcode_modifiers): Delete FloatD.
1150 * i386-opc.h (FloatD): Delete.
1151 (struct i386_opcode_modifier): Delete floatd.
1152 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
1153 FloatD by D.
1154 * i386-tlb.h: Re-generate.
1155
d53e6b98
JB		 11562018-03-08 Jan Beulich <jbeulich@suse.com>
1157
1158 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
1159
2907c2f5
JB		 11602018-03-08 Jan Beulich <jbeulich@suse.com>
1161
1162 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
1163 * i386-tlb.h: Re-generate.
1164
73053c1f
JB		 11652018-03-08 Jan Beulich <jbeulich@suse.com>
1166
1167 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
1168 forms.
1169 * i386-tlb.h: Re-generate.
1170
52fe4420
AM		 11712018-03-07 Alan Modra <amodra@gmail.com>
1172
1173 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
1174 bfd_arch_rs6000.
1175 * disassemble.h (print_insn_rs6000): Delete.
1176 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
1177 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
1178 (print_insn_rs6000): Delete.
1179
a6743a54
AM		 11802018-03-03 Alan Modra <amodra@gmail.com>
1181
1182 * sysdep.h (opcodes_error_handler): Define.
1183 (_bfd_error_handler): Declare.
1184 * Makefile.am: Remove stray #.
1185 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
1186 EDIT" comment.
1187 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
1188 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
1189 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
1190 opcodes_error_handler to print errors. Standardize error messages.
1191 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
1192 and include opintl.h.
1193 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
1194 * i386-gen.c: Standardize error messages.
1195 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
1196 * Makefile.in: Regenerate.
1197 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
1198 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
1199 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
1200 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
1201 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
1202 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
1203 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
1204 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
1205 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
1206 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
1207 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
1208 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
1209 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
1210
8305403a
L		 12112018-03-01 H.J. Lu <hongjiu.lu@intel.com>
1212
1213 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
1214 vpsub[bwdq] instructions.
1215 * i386-tbl.h: Regenerated.
1216
e184813f
AM		 12172018-03-01 Alan Modra <amodra@gmail.com>
1218
1219 * configure.ac (ALL_LINGUAS): Sort.
1220 * configure: Regenerate.
1221
5b616bef
TP		 12222018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
1223
1224 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
1225 macro by assignements.
1226
b6f8c7c4
L		 12272018-02-27 H.J. Lu <hongjiu.lu@intel.com>
1228
1229 PR gas/22871
1230 * i386-gen.c (opcode_modifiers): Add Optimize.
1231 * i386-opc.h (Optimize): New enum.
1232 (i386_opcode_modifier): Add optimize.
1233 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
1234 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
1235 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
1236 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
1237 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
1238 vpxord and vpxorq.
1239 * i386-tbl.h: Regenerated.
1240
e95b887f
AM		 12412018-02-26 Alan Modra <amodra@gmail.com>
1242
1243 * crx-dis.c (getregliststring): Allocate a large enough buffer
1244 to silence false positive gcc8 warning.
1245
0bccfb29
JW		 12462018-02-22 Shea Levy <shea@shealevy.com>
1247
1248 * disassemble.c (ARCH_riscv): Define if ARCH_all.
1249
6b6b6807
L		 12502018-02-22 H.J. Lu <hongjiu.lu@intel.com>
1251
1252 * i386-opc.tbl: Add {rex},
1253 * i386-tbl.h: Regenerated.
1254
75f31665
MR		 12552018-02-20 Maciej W. Rozycki <macro@mips.com>
1256
1257 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
1258 (mips16_opcodes): Replace `M' with `m' for "restore".
1259
e207bc53
TP		 12602018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
1261
1262 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
1263
87993319
MR		 12642018-02-13 Maciej W. Rozycki <macro@mips.com>
1265
1266 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
1267 variable to `function_index'.
1268
68d20676
NC		 12692018-02-13 Nick Clifton <nickc@redhat.com>
1270
1271 PR 22823
1272 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
1273 about truncation of printing.
1274
d2159fdc
HW		 12752018-02-12 Henry Wong <henry@stuffedcow.net>
1276
1277 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
1278
f174ef9f
NC		 12792018-02-05 Nick Clifton <nickc@redhat.com>
1280
1281 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1282
be3a8dca
IT		 12832018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1284
1285 * i386-dis.c (enum): Add pconfig.
1286 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
1287 (cpu_flags): Add CpuPCONFIG.
1288 * i386-opc.h (enum): Add CpuPCONFIG.
1289 (i386_cpu_flags): Add cpupconfig.
1290 * i386-opc.tbl: Add PCONFIG instruction.
1291 * i386-init.h: Regenerate.
1292 * i386-tbl.h: Likewise.
1293
3233d7d0
IT		 12942018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1295
1296 * i386-dis.c (enum): Add PREFIX_0F09.
1297 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
1298 (cpu_flags): Add CpuWBNOINVD.
1299 * i386-opc.h (enum): Add CpuWBNOINVD.
1300 (i386_cpu_flags): Add cpuwbnoinvd.
1301 * i386-opc.tbl: Add WBNOINVD instruction.
1302 * i386-init.h: Regenerate.
1303 * i386-tbl.h: Likewise.
1304
e925c834
JW		 13052018-01-17 Jim Wilson <jimw@sifive.com>
1306
1307 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
1308
d777820b
IT		 13092018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1310
1311 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
1312 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
1313 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
1314 (cpu_flags): Add CpuIBT, CpuSHSTK.
1315 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
1316 (i386_cpu_flags): Add cpuibt, cpushstk.
1317 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
1318 * i386-init.h: Regenerate.
1319 * i386-tbl.h: Likewise.
1320
f6efed01
NC		 13212018-01-16 Nick Clifton <nickc@redhat.com>
1322
1323 * po/pt_BR.po: Updated Brazilian Portugese translation.
1324 * po/de.po: Updated German translation.
1325
2721d702
JW		 13262018-01-15 Jim Wilson <jimw@sifive.com>
1327
1328 * riscv-opc.c (match_c_nop): New.
1329 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
1330
616dcb87
NC		 13312018-01-15 Nick Clifton <nickc@redhat.com>
1332
1333 * po/uk.po: Updated Ukranian translation.
1334
3957a496
NC		 13352018-01-13 Nick Clifton <nickc@redhat.com>
1336
1337 * po/opcodes.pot: Regenerated.
1338
769c7ea5
NC		 13392018-01-13 Nick Clifton <nickc@redhat.com>
1340
1341 * configure: Regenerate.
1342
faf766e3
NC		 13432018-01-13 Nick Clifton <nickc@redhat.com>
1344
1345 2.30 branch created.
1346
888a89da
IT		 13472018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1348
1349 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
1350 * i386-tbl.h: Regenerate.
1351
cbda583a
JB		 13522018-01-10 Jan Beulich <jbeulich@suse.com>
1353
1354 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
1355 * i386-tbl.h: Re-generate.
1356
c9e92278
JB		 13572018-01-10 Jan Beulich <jbeulich@suse.com>
1358
1359 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
1360 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
1361 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
1362 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
1363 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
1364 Disp8MemShift of AVX512VL forms.
1365 * i386-tbl.h: Re-generate.
1366
35fd2b2b
JW		 13672018-01-09 Jim Wilson <jimw@sifive.com>
1368
1369 * riscv-dis.c (maybe_print_address): If base_reg is zero,
1370 then the hi_addr value is zero.
1371
91d8b670
JG		 13722018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1373
1374 * arm-dis.c (arm_opcodes): Add csdb.
1375 (thumb32_opcodes): Add csdb.
1376
be2e7d95
JG		 13772018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
1378
1379 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
1380 * aarch64-asm-2.c: Regenerate.
1381 * aarch64-dis-2.c: Regenerate.
1382 * aarch64-opc-2.c: Regenerate.
1383
704a705d
L		 13842018-01-08 H.J. Lu <hongjiu.lu@intel.com>
1385
1386 PR gas/22681
1387 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
1388 Remove AVX512 vmovd with 64-bit operands.
1389 * i386-tbl.h: Regenerated.
1390
35eeb78f
JW		 13912018-01-05 Jim Wilson <jimw@sifive.com>
1392
1393 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
1394 jalr.
1395
219d1afa
AM		 13962018-01-03 Alan Modra <amodra@gmail.com>
1397
1398 Update year range in copyright notice of all files.
1399
1508bbf5
JB		 14002018-01-02 Jan Beulich <jbeulich@suse.com>
1401
1402 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
1403 and OPERAND_TYPE_REGZMM entries.
1404
1e563868 1405For older changes see ChangeLog-2017
3499769a 1406\f
1e563868 1407Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 1408
1409Copying and distribution of this file, with or without modification,
1410are permitted in any medium without royalty provided the copyright
1411notice and this notice are preserved.
1412
1413Local Variables:
1414mode: change-log
1415left-margin: 8
1416fill-column: 74
1417version-control: never
1418End:
GDB Binutils - Deliverables
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