projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Merge branch 'master' into merge-job
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0e62b37a
JB		 12019-12-23 Jan Beulich <jbeulich@suse.com>
2
3 * ppc-dis.c (print_insn_powerpc): Rename local variable "spaces"
4 to "blanks".
5 * ppc-opc.c (D34, SI34, NSI34): Use UINT64_C().
6
7936714c
AM		 72019-12-23 Alan Modra <amodra@gmail.com>
8
9 * score-dis.c (print_insn_score32): Avoid signed overflow.
10 (print_insn_score48): Likewise. Don't cast to int when printing
11 hex values.
12
3e1056a1
AM		 132019-12-23 Alan Modra <amodra@gmail.com>
14
15 * iq2000-ibld.c: Regenerate.
16
1a1e2852
AM		 172019-12-23 Alan Modra <amodra@gmail.com>
18
19 * d30v-dis.c (extract_value): Make num param a uint64_t, constify
20 oper. Use unsigned vars.
21 (print_insn): Make num var uint64_t. Constify oper and remove now
22 unnecessary casts on extract_value calls.
23 (print_insn_d30v): Use unsigned vars. Adjust printf formats.
24
27c1c427
AM		 252019-12-23 Alan Modra <amodra@gmail.com>
26
27 * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts.
28 Catch value overflow. Sign extend only on terminating byte.
29
cda8d785
AM		 302019-12-20 Alan Modra <amodra@gmail.com>
31
32 PR 25281
33 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY
34 and MOVY_NOPX insns. For invalid cases include 0xf000 in the word
35 printed. Print .word in more cases.
36
bcd9f578
AM		 372019-12-20 Alan Modra <amodra@gmail.com>
38
39 * or1k-ibld.c: Regenerate.
40
15d2859f
AM		 412019-12-20 Alan Modra <amodra@gmail.com>
42
43 * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use
44 unsigned variables.
45
000fe1a7
AM		 462019-12-20 Alan Modra <amodra@gmail.com>
47
48 * m68hc11-dis.c (read_memory): Delete forward decls.
49 (print_indexed_operand, print_insn): Likewise.
50 (print_indexed_operand): Formatting. Don't rely on short being
51 exactly 16 bits, make sign extension explicit.
52 (print_insn): Likewise. Avoid signed overflow.
53
f0090188
AM		 542019-12-19 Alan Modra <amodra@gmail.com>
55
56 * vax-dis.c (print_insn_mode): Stop index mode recursion.
57
1d29ab86
DF		 582019-12-19 Dr N.W. Filardo <nwf20@cam.ac.uk>
59
60 PR 25277
61 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and
62 fdiv with "mbi_".
63 * microblaze-opc.h (opcodes): Adjust to suit.
64
2480b6fa
AM		 652019-12-18 Alan Modra <amodra@gmail.com>
66
67 * alpha-opc.c (OP): Avoid signed overflow.
68 * arm-dis.c (print_insn): Likewise.
69 * mcore-dis.c (print_insn_mcore): Likewise.
70 * pj-dis.c (get_int): Likewise.
71 * ppc-opc.c (EBD15, EBD15BI): Likewise.
72 * score7-dis.c (s7_print_insn): Likewise.
73 * tic30-dis.c (print_insn_tic30): Likewise.
74 * v850-opc.c (insert_SELID): Likewise.
75 * vax-dis.c (print_insn_vax): Likewise.
76 * arc-ext.c (create_map): Likewise.
77 (struct ExtAuxRegister): Make "address" field unsigned int.
78 (arcExtMap_auxRegName): Pass unsigned address.
79 (dump_ARC_extmap): Adjust.
80 * arc-ext.h (arcExtMap_auxRegName): Update prototype.
81
eb7b5046
AM		 822019-12-17 Alan Modra <amodra@gmail.com>
83
84 * visium-dis.c (print_insn_visium): Avoid signed overflow.
85
29298bf6
AM		 862019-12-17 Alan Modra <amodra@gmail.com>
87
88 * aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow.
89 (value_fit_unsigned_field_p): Likewise.
90 (aarch64_wide_constant_p): Likewise.
91 (operand_general_constraint_met_p): Likewise.
92 * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
93
e46d79a7
AM		 942019-12-17 Alan Modra <amodra@gmail.com>
95
96 * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow.
97 (print_insn_nds32): Use uint64_t for "given" and "given1".
98
5b660084
AM		 992019-12-17 Alan Modra <amodra@gmail.com>
100
101 * tic80-dis.c: Delete file.
102 * tic80-opc.c: Delete file.
103 * disassemble.c: Remove tic80 support.
104 * disassemble.h: Likewise.
105 * Makefile.am: Likewise.
106 * configure.ac: Likewise.
107 * Makefile.in: Regenerate.
108 * configure: Regenerate.
109 * po/POTFILES.in: Regenerate.
110
62e65990
AM		 1112019-12-17 Alan Modra <amodra@gmail.com>
112
113 * bpf-ibld.c: Regenerate.
114
f81e7e2d
AM		 1152019-12-16 Alan Modra <amodra@gmail.com>
116
117 * aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without
118 conditional.
119 (aarch64_ext_imm): Avoid signed overflow.
120
488d02fe
AM		 1212019-12-16 Alan Modra <amodra@gmail.com>
122
123 * microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
124
8a92faab
AM		 1252019-12-16 Alan Modra <amodra@gmail.com>
126
127 * nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
128
e6ced26a
AM		 1292019-12-16 Alan Modra <amodra@gmail.com>
130
131 * xstormy16-ibld.c: Regenerate.
132
84e098cd
AM		 1332019-12-16 Alan Modra <amodra@gmail.com>
134
135 * score-dis.c (print_insn_score16): Move rpush/rpop imm field
136 value adjustment so that it doesn't affect reg field too.
137
36bd8ea7
AM		 1382019-12-16 Alan Modra <amodra@gmail.com>
139
140 * crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
141 (get_number_of_operands, getargtype, getbits, getregname),
142 (getcopregname, getprocregname, gettrapstring, getcinvstring),
143 (getregliststring, get_word_at_PC, get_words_at_PC, build_mask),
144 (powerof2, match_opcode, make_instruction, print_arguments),
145 (print_arg): Delete forward declarations, moving static to..
146 (getregname, getcopregname, getregliststring): ..these definitions.
147 (build_mask): Return unsigned int mask.
148 (match_opcode): Use unsigned int vars.
149
cedfc774
AM		 1502019-12-16 Alan Modra <amodra@gmail.com>
151
152 * bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
153
4bdb25fe
AM		 1542019-12-16 Alan Modra <amodra@gmail.com>
155
156 * nds32-dis.c (print_insn16, print_insn32): Remove forward decls.
157 (struct objdump_disasm_info): Delete.
158 (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of
159 N32_IMMS to unsigned before shifting left.
160
cf950fd4
AM		 1612019-12-16 Alan Modra <amodra@gmail.com>
162
163 * moxie-dis.c (INST2OFFSET): Don't left shift a signed value.
164 (print_insn_moxie): Remove unnecessary cast.
165
967354c3
AM		 1662019-12-12 Alan Modra <amodra@gmail.com>
167
168 * csky-dis.c (csky_chars_to_number): Remove abort and unnecessary
169 mask.
170
1d61b032
AM		 1712019-12-11 Alan Modra <amodra@gmail.com>
172
173 * arc-dis.c (BITS): Don't truncate high bits with shifts.
174 * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts.
175 * tic54x-dis.c (print_instruction): Likewise.
176 * tilegx-opc.c (parse_insn_tilegx): Likewise.
177 * tilepro-opc.c (parse_insn_tilepro): Likewise.
178 * visium-dis.c (disassem_class0): Likewise.
179 * pdp11-dis.c (sign_extend): Likewise.
180 (SIGN_BITS): Delete.
181 * epiphany-ibld.c: Regenerate.
182 * lm32-ibld.c: Regenerate.
183 * m32c-ibld.c: Regenerate.
184
5afa80e9
AM		 1852019-12-11 Alan Modra <amodra@gmail.com>
186
187 * ns32k-dis.c (sign_extend): Correct last patch.
188
5c05618a
AM		 1892019-12-11 Alan Modra <amodra@gmail.com>
190
191 * vax-dis.c (NEXTLONG): Avoid signed overflow.
192
2a81ccbb
AM		 1932019-12-11 Alan Modra <amodra@gmail.com>
194
195 * v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't
196 sign extend using shifts.
197
b84f6152
AM		 1982019-12-11 Alan Modra <amodra@gmail.com>
199
200 * tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
201
66152f16
AM		 2022019-12-11 Alan Modra <amodra@gmail.com>
203
204 * tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault
205 on NULL registertable entry.
206 (tic4x_hash_opcode): Use unsigned arithmetic.
207
205c426a
AM		 2082019-12-11 Alan Modra <amodra@gmail.com>
209
210 * s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
211
fb4cb4e2
AM		 2122019-12-11 Alan Modra <amodra@gmail.com>
213
214 * ns32k-dis.c (bit_extract): Use unsigned arithmetic.
215 (bit_extract_simple, sign_extend): Likewise.
216
96f1f604
AM		 2172019-12-11 Alan Modra <amodra@gmail.com>
218
219 * nios2-dis.c (nios2_print_insn_arg): Use 1u << 31.
220
8c9b4171
AM		 2212019-12-11 Alan Modra <amodra@gmail.com>
222
223 * moxie-dis.c (INST2OFFSET): Don't sign extend using shifts.
224
334175b6
AM		 2252019-12-11 Alan Modra <amodra@gmail.com>
226
227 * m68k-dis.c (COERCE32): Cast value first.
228 (NEXTLONG, NEXTULONG): Avoid signed overflow.
229
f8a87c78
AM		 2302019-12-11 Alan Modra <amodra@gmail.com>
231
232 * h8300-dis.c (extract_immediate): Avoid signed overflow.
233 (bfd_h8_disassemble): Likewise.
234
159653d8
AM		 2352019-12-11 Alan Modra <amodra@gmail.com>
236
237 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
238 past end of operands array.
239
d93bba9e
AM		 2402019-12-11 Alan Modra <amodra@gmail.com>
241
242 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
243 overflow when collecting bytes of a number.
244
c202f69e
AM		 2452019-12-11 Alan Modra <amodra@gmail.com>
246
247 * cris-dis.c (print_with_operands): Avoid signed integer
248 overflow when collecting bytes of a 32-bit integer.
249
0ef562a4
AM		 2502019-12-11 Alan Modra <amodra@gmail.com>
251
252 * cr16-dis.c (EXTRACT, SBM): Rewrite.
253 (cr16_match_opcode): Delete duplicate bcond test.
254
2fd2b153
AM		 2552019-12-11 Alan Modra <amodra@gmail.com>
256
257 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
258 (SIGNBIT): New.
259 (MASKBITS, SIGNEXTEND): Rewrite.
260 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
261 unsigned arithmetic, instead assign result of SIGNEXTEND back
262 to x.
263 (fmtconst_val): Use 1u in shift expression.
264
a11db3e9
AM		 2652019-12-11 Alan Modra <amodra@gmail.com>
266
267 * arc-dis.c (find_format_from_table): Use ull constant when
268 shifting by up to 32.
269
9d48687b
AM		 2702019-12-11 Alan Modra <amodra@gmail.com>
271
272 PR 25270
273 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
274 false when field is zero for sve_size_tsz_bhs.
275
b8e61daa
AM		 2762019-12-11 Alan Modra <amodra@gmail.com>
277
278 * epiphany-ibld.c: Regenerate.
279
20135676
AM		 2802019-12-10 Alan Modra <amodra@gmail.com>
281
282 PR 24960
283 * disassemble.c (disassemble_free_target): New function.
284
103ebbc3
AM		 2852019-12-10 Alan Modra <amodra@gmail.com>
286
287 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
288 * disassemble.c (disassemble_init_for_target): Likewise.
289 * bpf-dis.c: Regenerate.
290 * epiphany-dis.c: Regenerate.
291 * fr30-dis.c: Regenerate.
292 * frv-dis.c: Regenerate.
293 * ip2k-dis.c: Regenerate.
294 * iq2000-dis.c: Regenerate.
295 * lm32-dis.c: Regenerate.
296 * m32c-dis.c: Regenerate.
297 * m32r-dis.c: Regenerate.
298 * mep-dis.c: Regenerate.
299 * mt-dis.c: Regenerate.
300 * or1k-dis.c: Regenerate.
301 * xc16x-dis.c: Regenerate.
302 * xstormy16-dis.c: Regenerate.
303
6f0e0752
AM		 3042019-12-10 Alan Modra <amodra@gmail.com>
305
306 * ppc-dis.c (private): Delete variable.
307 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
308 (powerpc_init_dialect): Don't use global private.
309
e7c22a69
AM		 3102019-12-10 Alan Modra <amodra@gmail.com>
311
312 * s12z-opc.c: Formatting.
313
0a6aef6b
AM		 3142019-12-08 Alan Modra <amodra@gmail.com>
315
316 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
317 registers.
318
2dc4b12f
JB		 3192019-12-05 Jan Beulich <jbeulich@suse.com>
320
321 * aarch64-tbl.h (aarch64_feature_crypto,
322 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
323 CRYPTO_V8_2_INSN): Delete.
324
378fd436
AM		 3252019-12-05 Alan Modra <amodra@gmail.com>
326
327 PR 25249
328 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
329 (struct string_buf): New.
330 (strbuf): New function.
331 (get_field): Use strbuf rather than strdup of local temp.
332 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
333 (get_field_rfsl, get_field_imm15): Likewise.
334 (get_field_rd, get_field_r1, get_field_r2): Update macros.
335 (get_field_special): Likewise. Don't strcpy spr. Formatting.
336 (print_insn_microblaze): Formatting. Init and pass string_buf to
337 get_field functions.
338
0ba59a29
JB		 3392019-12-04 Jan Beulich <jbeulich@suse.com>
340
341 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
342 * i386-tbl.h: Re-generate.
343
77ad8092
JB		 3442019-12-04 Jan Beulich <jbeulich@suse.com>
345
346 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
347
3036c899
JB		 3482019-12-04 Jan Beulich <jbeulich@suse.com>
349
350 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
351 forms.
352 (xbegin): Drop DefaultSize.
353 * i386-tbl.h: Re-generate.
354
8b301fbb
MI		 3552019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
356
357 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
358 Change the coproc CRC conditions to use the extension
359 feature set, second word, base on ARM_EXT2_CRC.
360
6aa385b9
JB		 3612019-11-14 Jan Beulich <jbeulich@suse.com>
362
363 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
364 * i386-tbl.h: Re-generate.
365
0cfa3eb3
JB		 3662019-11-14 Jan Beulich <jbeulich@suse.com>
367
368 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
369 JumpInterSegment, and JumpAbsolute entries.
370 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
371 JUMP_ABSOLUTE): Define.
372 (struct i386_opcode_modifier): Extend jump field to 3 bits.
373 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
374 fields.
375 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
376 JumpInterSegment): Define.
377 * i386-tbl.h: Re-generate.
378
6f2f06be
JB		 3792019-11-14 Jan Beulich <jbeulich@suse.com>
380
381 * i386-gen.c (operand_type_init): Remove
382 OPERAND_TYPE_JUMPABSOLUTE entry.
383 (opcode_modifiers): Add JumpAbsolute entry.
384 (operand_types): Remove JumpAbsolute entry.
385 * i386-opc.h (JumpAbsolute): Move between enums.
386 (struct i386_opcode_modifier): Add jumpabsolute field.
387 (union i386_operand_type): Remove jumpabsolute field.
388 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
389 * i386-init.h, i386-tbl.h: Re-generate.
390
601e8564
JB		 3912019-11-14 Jan Beulich <jbeulich@suse.com>
392
393 * i386-gen.c (opcode_modifiers): Add AnySize entry.
394 (operand_types): Remove AnySize entry.
395 * i386-opc.h (AnySize): Move between enums.
396 (struct i386_opcode_modifier): Add anysize field.
397 (OTUnused): Un-comment.
398 (union i386_operand_type): Remove anysize field.
399 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
400 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
401 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
402 AnySize.
403 * i386-tbl.h: Re-generate.
404
7722d40a
JW		 4052019-11-12 Nelson Chu <nelson.chu@sifive.com>
406
407 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
408 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
409 use the floating point register (FPR).
410
ce760a76
MI		 4112019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
412
413 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
414 cmode 1101.
415 (is_mve_encoding_conflict): Update cmode conflict checks for
416 MVE_VMVN_IMM.
417
51c8edf6
JB		 4182019-11-12 Jan Beulich <jbeulich@suse.com>
419
420 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
421 entry.
422 (operand_types): Remove EsSeg entry.
423 (main): Replace stale use of OTMax.
424 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
425 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
426 (EsSeg): Delete.
427 (OTUnused): Comment out.
428 (union i386_operand_type): Remove esseg field.
429 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
430 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
431 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
432 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
433 * i386-init.h, i386-tbl.h: Re-generate.
434
474da251
JB		 4352019-11-12 Jan Beulich <jbeulich@suse.com>
436
437 * i386-gen.c (operand_instances): Add RegB entry.
438 * i386-opc.h (enum operand_instance): Add RegB.
439 * i386-opc.tbl (RegC, RegD, RegB): Define.
440 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
441 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
442 monitorx, mwaitx): Drop ImmExt and convert encodings
443 accordingly.
444 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
445 (edx, rdx): Add Instance=RegD.
446 (ebx, rbx): Add Instance=RegB.
447 * i386-tbl.h: Re-generate.
448
75e5731b
JB		 4492019-11-12 Jan Beulich <jbeulich@suse.com>
450
451 * i386-gen.c (operand_type_init): Adjust
452 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
453 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
454 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
455 (operand_instances): New.
456 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
457 (output_operand_type): New parameter "instance". Process it.
458 (process_i386_operand_type): New local variable "instance".
459 (main): Adjust static assertions.
460 * i386-opc.h (INSTANCE_WIDTH): Define.
461 (enum operand_instance): New.
462 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
463 (union i386_operand_type): Replace acc, inoutportreg, and
464 shiftcount by instance.
465 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
466 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
467 Add Instance=.
468 * i386-init.h, i386-tbl.h: Re-generate.
469
91802f3c
JB		 4702019-11-11 Jan Beulich <jbeulich@suse.com>
471
472 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
473 smaxp/sminp entries' "tied_operand" field to 2.
474
4f5fc85d
JB		 4752019-11-11 Jan Beulich <jbeulich@suse.com>
476
477 * aarch64-opc.c (operand_general_constraint_met_p): Replace
478 "index" local variable by that of the already existing "num".
479
dc2be329
L		 4802019-11-08 H.J. Lu <hongjiu.lu@intel.com>
481
482 PR gas/25167
483 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
484 * i386-tbl.h: Regenerated.
485
f74a6307
JB		 4862019-11-08 Jan Beulich <jbeulich@suse.com>
487
488 * i386-gen.c (operand_type_init): Add Class= to
489 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
490 OPERAND_TYPE_REGBND entry.
491 (operand_classes): Add RegMask and RegBND entries.
492 (operand_types): Drop RegMask and RegBND entry.
493 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
494 (RegMask, RegBND): Delete.
495 (union i386_operand_type): Remove regmask and regbnd fields.
496 * i386-opc.tbl (RegMask, RegBND): Define.
497 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
498 Class=RegBND.
499 * i386-init.h, i386-tbl.h: Re-generate.
500
3528c362
JB		 5012019-11-08 Jan Beulich <jbeulich@suse.com>
502
503 * i386-gen.c (operand_type_init): Add Class= to
504 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
505 OPERAND_TYPE_REGZMM entries.
506 (operand_classes): Add RegMMX and RegSIMD entries.
507 (operand_types): Drop RegMMX and RegSIMD entries.
508 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
509 (RegMMX, RegSIMD): Delete.
510 (union i386_operand_type): Remove regmmx and regsimd fields.
511 * i386-opc.tbl (RegMMX): Define.
512 (RegXMM, RegYMM, RegZMM): Add Class=.
513 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
514 Class=RegSIMD.
515 * i386-init.h, i386-tbl.h: Re-generate.
516
4a5c67ed
JB		 5172019-11-08 Jan Beulich <jbeulich@suse.com>
518
519 * i386-gen.c (operand_type_init): Add Class= to
520 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
521 entries.
522 (operand_classes): Add RegCR, RegDR, and RegTR entries.
523 (operand_types): Drop Control, Debug, and Test entries.
524 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
525 (Control, Debug, Test): Delete.
526 (union i386_operand_type): Remove control, debug, and test
527 fields.
528 * i386-opc.tbl (Control, Debug, Test): Define.
529 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
530 Class=RegDR, and Test by Class=RegTR.
531 * i386-init.h, i386-tbl.h: Re-generate.
532
00cee14f
JB		 5332019-11-08 Jan Beulich <jbeulich@suse.com>
534
535 * i386-gen.c (operand_type_init): Add Class= to
536 OPERAND_TYPE_SREG entry.
537 (operand_classes): Add SReg entry.
538 (operand_types): Drop SReg entry.
539 * i386-opc.h (enum operand_class): Add SReg.
540 (SReg): Delete.
541 (union i386_operand_type): Remove sreg field.
542 * i386-opc.tbl (SReg): Define.
543 * i386-reg.tbl: Replace SReg by Class=SReg.
544 * i386-init.h, i386-tbl.h: Re-generate.
545
bab6aec1
JB		 5462019-11-08 Jan Beulich <jbeulich@suse.com>
547
548 * i386-gen.c (operand_type_init): Add Class=. New
549 OPERAND_TYPE_ANYIMM entry.
550 (operand_classes): New.
551 (operand_types): Drop Reg entry.
552 (output_operand_type): New parameter "class". Process it.
553 (process_i386_operand_type): New local variable "class".
554 (main): Adjust static assertions.
555 * i386-opc.h (CLASS_WIDTH): Define.
556 (enum operand_class): New.
557 (Reg): Replace by Class. Adjust comment.
558 (union i386_operand_type): Replace reg by class.
559 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
560 Class=.
561 * i386-reg.tbl: Replace Reg by Class=Reg.
562 * i386-init.h: Re-generate.
563
1f4cd317
MM		 5642019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
565
566 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
567 (aarch64_opcode_table): Add data gathering hint mnemonic.
568 * opcodes/aarch64-dis-2.c: Account for new instruction.
569
616ce08e
MM		 5702019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
571
572 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
573
574
8382113f
MM		 5752019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
576
577 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
578 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
579 aarch64_feature_f64mm): New feature sets.
580 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
581 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
582 instructions.
583 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
584 macros.
585 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
586 (OP_SVE_QQQ): New qualifier.
587 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
588 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
589 the movprfx constraint.
590 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
591 (aarch64_opcode_table): Define new instructions smmla,
592 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
593 uzip{1/2}, trn{1/2}.
594 * aarch64-opc.c (operand_general_constraint_met_p): Handle
595 AARCH64_OPND_SVE_ADDR_RI_S4x32.
596 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
597 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
598 Account for new instructions.
599 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
600 S4x32 operand.
601 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
602
aab2c27d
MM		 6032019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6042019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
605
606 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
607 Armv8.6-A.
608 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
609 (neon_opcodes): Add bfloat SIMD instructions.
610 (print_insn_coprocessor): Add new control character %b to print
611 condition code without checking cp_num.
612 (print_insn_neon): Account for BFloat16 instructions that have no
613 special top-byte handling.
614
33593eaf
MM		 6152019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6162019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
617
618 * arm-dis.c (print_insn_coprocessor,
619 print_insn_generic_coprocessor): Create wrapper functions around
620 the implementation of the print_insn_coprocessor control codes.
621 (print_insn_coprocessor_1): Original print_insn_coprocessor
622 function that now takes which array to look at as an argument.
623 (print_insn_arm): Use both print_insn_coprocessor and
624 print_insn_generic_coprocessor.
625 (print_insn_thumb32): As above.
626
df678013
MM		 6272019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6282019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
629
630 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
631 in reglane special case.
632 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
633 aarch64_find_next_opcode): Account for new instructions.
634 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
635 in reglane special case.
636 * aarch64-opc.c (struct operand_qualifier_data): Add data for
637 new AARCH64_OPND_QLF_S_2H qualifier.
638 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
639 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
640 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
641 sets.
642 (BFLOAT_SVE, BFLOAT): New feature set macros.
643 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
644 instructions.
645 (aarch64_opcode_table): Define new instructions bfdot,
646 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
647 bfcvtn2, bfcvt.
648
8ae2d3d9
MM		 6492019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
6502019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
651
652 * aarch64-tbl.h (ARMV8_6): New macro.
653
142861df
JB		 6542019-11-07 Jan Beulich <jbeulich@suse.com>
655
656 * i386-dis.c (prefix_table): Add mcommit.
657 (rm_table): Add rdpru.
658 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
659 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
660 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
661 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
662 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
663 * i386-opc.tbl (mcommit, rdpru): New.
664 * i386-init.h, i386-tbl.h: Re-generate.
665
081e283f
JB		 6662019-11-07 Jan Beulich <jbeulich@suse.com>
667
668 * i386-dis.c (OP_Mwait): Drop local variable "names", use
669 "names32" instead.
670 (OP_Monitor): Drop local variable "op1_names", re-purpose
671 "names" for it instead, and replace former "names" uses by
672 "names32" ones.
673
c050c89a
JB		 6742019-11-07 Jan Beulich <jbeulich@suse.com>
675
676 PR/gas 25167
677 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
678 operand-less forms.
679 * opcodes/i386-tbl.h: Re-generate.
680
7abb8d81
JB		 6812019-11-05 Jan Beulich <jbeulich@suse.com>
682
683 * i386-dis.c (OP_Mwaitx): Delete.
684 (prefix_table): Use OP_Mwait for mwaitx entry.
685 (OP_Mwait): Also handle mwaitx.
686
267b8516
JB		 6872019-11-05 Jan Beulich <jbeulich@suse.com>
688
689 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
690 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
691 (prefix_table): Add respective entries.
692 (rm_table): Link to those entries.
693
f8687e93
JB		 6942019-11-05 Jan Beulich <jbeulich@suse.com>
695
696 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
697 (REG_0F1C_P_0_MOD_0): ... this.
698 (REG_0F1E_MOD_3): Rename to ...
699 (REG_0F1E_P_1_MOD_3): ... this.
700 (RM_0F01_REG_5): Rename to ...
701 (RM_0F01_REG_5_MOD_3): ... this.
702 (RM_0F01_REG_7): Rename to ...
703 (RM_0F01_REG_7_MOD_3): ... this.
704 (RM_0F1E_MOD_3_REG_7): Rename to ...
705 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
706 (RM_0FAE_REG_6): Rename to ...
707 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
708 (RM_0FAE_REG_7): Rename to ...
709 (RM_0FAE_REG_7_MOD_3): ... this.
710 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
711 (PREFIX_0F01_REG_5_MOD_0): ... this.
712 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
713 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
714 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
715 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
716 (PREFIX_0FAE_REG_0): Rename to ...
717 (PREFIX_0FAE_REG_0_MOD_3): ... this.
718 (PREFIX_0FAE_REG_1): Rename to ...
719 (PREFIX_0FAE_REG_1_MOD_3): ... this.
720 (PREFIX_0FAE_REG_2): Rename to ...
721 (PREFIX_0FAE_REG_2_MOD_3): ... this.
722 (PREFIX_0FAE_REG_3): Rename to ...
723 (PREFIX_0FAE_REG_3_MOD_3): ... this.
724 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
725 (PREFIX_0FAE_REG_4_MOD_0): ... this.
726 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
727 (PREFIX_0FAE_REG_4_MOD_3): ... this.
728 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
729 (PREFIX_0FAE_REG_5_MOD_0): ... this.
730 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
731 (PREFIX_0FAE_REG_5_MOD_3): ... this.
732 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
733 (PREFIX_0FAE_REG_6_MOD_0): ... this.
734 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
735 (PREFIX_0FAE_REG_6_MOD_3): ... this.
736 (PREFIX_0FAE_REG_7): Rename to ...
737 (PREFIX_0FAE_REG_7_MOD_0): ... this.
738 (PREFIX_MOD_0_0FC3): Rename to ...
739 (PREFIX_0FC3_MOD_0): ... this.
740 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
741 (PREFIX_0FC7_REG_6_MOD_0): ... this.
742 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
743 (PREFIX_0FC7_REG_6_MOD_3): ... this.
744 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
745 (PREFIX_0FC7_REG_7_MOD_3): ... this.
746 (reg_table, prefix_table, mod_table, rm_table): Adjust
747 accordingly.
748
5103274f
NC		 7492019-11-04 Nick Clifton <nickc@redhat.com>
750
751 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
752 of a v850 system register. Move the v850_sreg_names array into
753 this function.
754 (get_v850_reg_name): Likewise for ordinary register names.
755 (get_v850_vreg_name): Likewise for vector register names.
756 (get_v850_cc_name): Likewise for condition codes.
757 * get_v850_float_cc_name): Likewise for floating point condition
758 codes.
759 (get_v850_cacheop_name): Likewise for cache-ops.
760 (get_v850_prefop_name): Likewise for pref-ops.
761 (disassemble): Use the new accessor functions.
762
1820262b
DB		 7632019-10-30 Delia Burduv <delia.burduv@arm.com>
764
765 * aarch64-opc.c (print_immediate_offset_address): Don't print the
766 immediate for the writeback form of ldraa/ldrab if it is 0.
767 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
768 * aarch64-opc-2.c: Regenerated.
769
3cc17af5
JB		 7702019-10-30 Jan Beulich <jbeulich@suse.com>
771
772 * i386-gen.c (operand_type_shorthands): Delete.
773 (operand_type_init): Expand previous shorthands.
774 (set_bitfield_from_shorthand): Rename back to ...
775 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
776 of operand_type_init[].
777 (set_bitfield): Adjust call to the above function.
778 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
779 RegXMM, RegYMM, RegZMM): Define.
780 * i386-reg.tbl: Expand prior shorthands.
781
a2cebd03
JB		 7822019-10-30 Jan Beulich <jbeulich@suse.com>
783
784 * i386-gen.c (output_i386_opcode): Change order of fields
785 emitted to output.
786 * i386-opc.h (struct insn_template): Move operands field.
787 Convert extension_opcode field to unsigned short.
788 * i386-tbl.h: Re-generate.
789
507916b8
JB		 7902019-10-30 Jan Beulich <jbeulich@suse.com>
791
792 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
793 of W.
794 * i386-opc.h (W): Extend comment.
795 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
796 general purpose variants not allowing for byte operands.
797 * i386-tbl.h: Re-generate.
798
efea62b4
NC		 7992019-10-29 Nick Clifton <nickc@redhat.com>
800
801 * tic30-dis.c (print_branch): Correct size of operand array.
802
9adb2591
NC		 8032019-10-29 Nick Clifton <nickc@redhat.com>
804
805 * d30v-dis.c (print_insn): Check that operand index is valid
806 before attempting to access the operands array.
807
993a00a9
NC		 8082019-10-29 Nick Clifton <nickc@redhat.com>
809
810 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
811 locating the bit to be tested.
812
66a66a17
NC		 8132019-10-29 Nick Clifton <nickc@redhat.com>
814
815 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
816 values.
817 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
818 (print_insn_s12z): Check for illegal size values.
819
1ee3542c
NC		 8202019-10-28 Nick Clifton <nickc@redhat.com>
821
822 * csky-dis.c (csky_chars_to_number): Check for a negative
823 count. Use an unsigned integer to construct the return value.
824
bbf9a0b5
NC		 8252019-10-28 Nick Clifton <nickc@redhat.com>
826
827 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
828 operand buffer. Set value to 15 not 13.
829 (get_register_operand): Use OPERAND_BUFFER_LEN.
830 (get_indirect_operand): Likewise.
831 (print_two_operand): Likewise.
832 (print_three_operand): Likewise.
833 (print_oar_insn): Likewise.
834
d1e304bc
NC		 8352019-10-28 Nick Clifton <nickc@redhat.com>
836
837 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
838 (bit_extract_simple): Likewise.
839 (bit_copy): Likewise.
840 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
841 index_offset array are not accessed.
842
dee33451
NC		 8432019-10-28 Nick Clifton <nickc@redhat.com>
844
845 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
846 operand.
847
27cee81d
NC		 8482019-10-25 Nick Clifton <nickc@redhat.com>
849
850 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
851 access to opcodes.op array element.
852
de6d8dc2
NC		 8532019-10-23 Nick Clifton <nickc@redhat.com>
854
855 * rx-dis.c (get_register_name): Fix spelling typo in error
856 message.
857 (get_condition_name, get_flag_name, get_double_register_name)
858 (get_double_register_high_name, get_double_register_low_name)
859 (get_double_control_register_name, get_double_condition_name)
860 (get_opsize_name, get_size_name): Likewise.
861
6207ed28
NC		 8622019-10-22 Nick Clifton <nickc@redhat.com>
863
864 * rx-dis.c (get_size_name): New function. Provides safe
865 access to name array.
866 (get_opsize_name): Likewise.
867 (print_insn_rx): Use the accessor functions.
868
12234dfd
NC		 8692019-10-16 Nick Clifton <nickc@redhat.com>
870
871 * rx-dis.c (get_register_name): New function. Provides safe
872 access to name array.
873 (get_condition_name, get_flag_name, get_double_register_name)
874 (get_double_register_high_name, get_double_register_low_name)
875 (get_double_control_register_name, get_double_condition_name):
876 Likewise.
877 (print_insn_rx): Use the accessor functions.
878
1d378749
NC		 8792019-10-09 Nick Clifton <nickc@redhat.com>
880
881 PR 25041
882 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
883 instructions.
884
d241b910
JB		 8852019-10-07 Jan Beulich <jbeulich@suse.com>
886
887 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
888 (cmpsd): Likewise. Move EsSeg to other operand.
889 * opcodes/i386-tbl.h: Re-generate.
890
f5c5b7c1
AM		 8912019-09-23 Alan Modra <amodra@gmail.com>
892
893 * m68k-dis.c: Include cpu-m68k.h
894
7beeaeb8
AM		 8952019-09-23 Alan Modra <amodra@gmail.com>
896
897 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
898 "elf/mips.h" earlier.
899
3f9aad11
JB		 9002018-09-20 Jan Beulich <jbeulich@suse.com>
901
902 PR gas/25012
903 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
904 with SReg operand.
905 * i386-tbl.h: Re-generate.
906
fd361982
AM		 9072019-09-18 Alan Modra <amodra@gmail.com>
908
909 * arc-ext.c: Update throughout for bfd section macro changes.
910
e0b2a78c
SM		 9112019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
912
913 * Makefile.in: Re-generate.
914 * configure: Re-generate.
915
7e9ad3a3
JW		 9162019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
917
918 * riscv-opc.c (riscv_opcodes): Change subset field
919 to insn_class field for all instructions.
920 (riscv_insn_types): Likewise.
921
bb695960
PB		 9222019-09-16 Phil Blundell <pb@pbcl.net>
923
924 * configure: Regenerated.
925
8063ab7e
MV		 9262019-09-10 Miod Vallat <miod@online.fr>
927
928 PR 24982
929 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
930
60391a25
PB		 9312019-09-09 Phil Blundell <pb@pbcl.net>
932
933 binutils 2.33 branch created.
934
f44b758d
NC		 9352019-09-03 Nick Clifton <nickc@redhat.com>
936
937 PR 24961
938 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
939 greater than zero before indexing via (bufcnt -1).
940
1e4b5e7d
NC		 9412019-09-03 Nick Clifton <nickc@redhat.com>
942
943 PR 24958
944 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
945 (MAX_SPEC_REG_NAME_LEN): Define.
946 (struct mmix_dis_info): Use defined constants for array lengths.
947 (get_reg_name): New function.
948 (get_sprec_reg_name): New function.
949 (print_insn_mmix): Use new functions.
950
c4a23bf8
SP		 9512019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
952
953 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
954 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
955 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
956
a051e2f3
KT		 9572019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
958
959 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
960 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
961 (aarch64_sys_reg_supported_p): Update checks for the above.
962
08132bdd
SP		 9632019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
964
965 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
966 cases MVE_SQRSHRL and MVE_UQRSHLL.
967 (print_insn_mve): Add case for specifier 'k' to check
968 specific bit of the instruction.
969
d88bdcb4
PA		 9702019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
971
972 PR 24854
973 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
974 encountering an unknown machine type.
975 (print_insn_arc): Handle arc_insn_length returning 0. In error
976 cases return -1 rather than calling abort.
977
bc750500
JB		 9782019-08-07 Jan Beulich <jbeulich@suse.com>
979
980 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
981 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
982 IgnoreSize.
983 * i386-tbl.h: Re-generate.
984
23d188c7
BW		 9852019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
986
987 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
988 instructions.
989
c0d6f62f
JW		 9902019-07-30 Mel Chen <mel.chen@sifive.com>
991
992 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
993 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
994
995 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
996 fscsr.
997
0f3f7167
CZ		 9982019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
999
1000 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
1001 and MPY class instructions.
1002 (parse_option): Add nps400 option.
1003 (print_arc_disassembler_options): Add nps400 info.
1004
7e126ba3
CZ		 10052019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
1006
1007 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
1008 (bspop): Likewise.
1009 (modapp): Likewise.
1010 * arc-opc.c (RAD_CHK): Add.
1011 * arc-tbl.h: Regenerate.
1012
a028026d
KT		 10132019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1014
1015 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
1016 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
1017
ac79ff9e
NC		 10182019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
1019
1020 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
1021 instructions as UNPREDICTABLE.
1022
231097b0
JM		 10232019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1024
1025 * bpf-desc.c: Regenerated.
1026
1d942ae9
JB		 10272019-07-17 Jan Beulich <jbeulich@suse.com>
1028
1029 * i386-gen.c (static_assert): Define.
1030 (main): Use it.
1031 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
1032 (Opcode_Modifier_Num): ... this.
1033 (Mem): Delete.
1034
dfd69174
JB		 10352019-07-16 Jan Beulich <jbeulich@suse.com>
1036
1037 * i386-gen.c (operand_types): Move RegMem ...
1038 (opcode_modifiers): ... here.
1039 * i386-opc.h (RegMem): Move to opcode modifer enum.
1040 (union i386_operand_type): Move regmem field ...
1041 (struct i386_opcode_modifier): ... here.
1042 * i386-opc.tbl (RegMem): Define.
1043 (mov, movq): Move RegMem on segment, control, debug, and test
1044 register flavors.
1045 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
1046 to non-SSE2AVX flavor.
1047 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
1048 Move RegMem on register only flavors. Drop IgnoreSize from
1049 legacy encoding flavors.
1050 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
1051 flavors.
1052 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
1053 register only flavors.
1054 (vmovd): Move RegMem and drop IgnoreSize on register only
1055 flavor. Change opcode and operand order to store form.
1056 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1057
21df382b
JB		 10582019-07-16 Jan Beulich <jbeulich@suse.com>
1059
1060 * i386-gen.c (operand_type_init, operand_types): Replace SReg
1061 entries.
1062 * i386-opc.h (SReg2, SReg3): Replace by ...
1063 (SReg): ... this.
1064 (union i386_operand_type): Replace sreg fields.
1065 * i386-opc.tbl (mov, ): Use SReg.
1066 (push, pop): Likewies. Drop i386 and x86-64 specific segment
1067 register flavors.
1068 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
1069 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1070
3719fd55
JM		 10712019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
1072
1073 * bpf-desc.c: Regenerate.
1074 * bpf-opc.c: Likewise.
1075 * bpf-opc.h: Likewise.
1076
92434a14
JM		 10772019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
1078
1079 * bpf-desc.c: Regenerate.
1080 * bpf-opc.c: Likewise.
1081
43dd7626
HPN		 10822019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
1083
1084 * arm-dis.c (print_insn_coprocessor): Rename index to
1085 index_operand.
1086
98602811
JW		 10872019-07-05 Kito Cheng <kito.cheng@sifive.com>
1088
1089 * riscv-opc.c (riscv_insn_types): Add r4 type.
1090
1091 * riscv-opc.c (riscv_insn_types): Add b and j type.
1092
1093 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
1094 format for sb type and correct s type.
1095
01c1ee4a
RS		 10962019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1097
1098 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
1099 SVE FMOV alias of FCPY.
1100
83adff69
RS		 11012019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1102
1103 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
1104 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
1105
89418844
RS		 11062019-07-02 Richard Sandiford <richard.sandiford@arm.com>
1107
1108 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
1109 registers in an instruction prefixed by MOVPRFX.
1110
41be57ca
MM		 11112019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
1112
1113 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
1114 sve_size_13 icode to account for variant behaviour of
1115 pmull{t,b}.
1116 * aarch64-dis-2.c: Regenerate.
1117 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
1118 sve_size_13 icode to account for variant behaviour of
1119 pmull{t,b}.
1120 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
1121 (OP_SVE_VVV_Q_D): Add new qualifier.
1122 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
1123 (struct aarch64_opcode): Split pmull{t,b} into those requiring
1124 AES and those not.
1125
9d3bf266
JB		 11262019-07-01 Jan Beulich <jbeulich@suse.com>
1127
1128 * opcodes/i386-gen.c (operand_type_init): Remove
1129 OPERAND_TYPE_VEC_IMM4 entry.
1130 (operand_types): Remove Vec_Imm4.
1131 * opcodes/i386-opc.h (Vec_Imm4): Delete.
1132 (union i386_operand_type): Remove vec_imm4.
1133 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
1134 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
1135
c3949f43
JB		 11362019-07-01 Jan Beulich <jbeulich@suse.com>
1137
1138 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
1139 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
1140 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
1141 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
1142 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
1143 monitorx, mwaitx): Drop ImmExt from operand-less forms.
1144 * i386-tbl.h: Re-generate.
1145
5641ec01
JB		 11462019-07-01 Jan Beulich <jbeulich@suse.com>
1147
1148 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1149 register operands.
1150 * i386-tbl.h: Re-generate.
1151
79dec6b7
JB		 11522019-07-01 Jan Beulich <jbeulich@suse.com>
1153
1154 * i386-opc.tbl (C): New.
1155 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
1156 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
1157 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
1158 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
1159 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
1160 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
1161 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
1162 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
1163 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
1164 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
1165 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
1166 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
1167 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
1168 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
1169 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
1170 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
1171 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
1172 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
1173 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
1174 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
1175 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
1176 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
1177 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
1178 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
1179 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
1180 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
1181 flavors.
1182 * i386-tbl.h: Re-generate.
1183
a0a1771e
JB		 11842019-07-01 Jan Beulich <jbeulich@suse.com>
1185
1186 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
1187 register operands.
1188 * i386-tbl.h: Re-generate.
1189
cd546e7b
JB		 11902019-07-01 Jan Beulich <jbeulich@suse.com>
1191
1192 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
1193 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
1194 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
1195 * i386-tbl.h: Re-generate.
1196
e3bba3fc
JB		 11972019-07-01 Jan Beulich <jbeulich@suse.com>
1198
1199 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
1200 Disp8MemShift from register only templates.
1201 * i386-tbl.h: Re-generate.
1202
36cc073e
JB		 12032019-07-01 Jan Beulich <jbeulich@suse.com>
1204
1205 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
1206 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
1207 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
1208 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
1209 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
1210 EVEX_W_0F11_P_3_M_1): Delete.
1211 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
1212 EVEX_W_0F11_P_3): New.
1213 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
1214 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
1215 MOD_EVEX_0F11_PREFIX_3 table entries.
1216 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
1217 PREFIX_EVEX_0F11 table entries.
1218 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
1219 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
1220 EVEX_W_0F11_P_3_M_{0,1} table entries.
1221
219920a7
JB		 12222019-07-01 Jan Beulich <jbeulich@suse.com>
1223
1224 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
1225 Delete.
1226
e395f487
L		 12272019-06-27 H.J. Lu <hongjiu.lu@intel.com>
1228
1229 PR binutils/24719
1230 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1231 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1232 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1233 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1234 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1235 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1236 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1237 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1238 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1239 PREFIX_EVEX_0F38C6_REG_6 entries.
1240 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1241 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1242 EVEX_W_0F38C7_R_6_P_2 entries.
1243 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1244 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1245 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1246 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1247 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1248 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1249 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1250
2b7bcc87
JB		 12512019-06-27 Jan Beulich <jbeulich@suse.com>
1252
1253 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1254 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1255 VEX_LEN_0F2D_P_3): Delete.
1256 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1257 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1258 (prefix_table): ... here.
1259
c1dc7af5
JB		 12602019-06-27 Jan Beulich <jbeulich@suse.com>
1261
1262 * i386-dis.c (Iq): Delete.
1263 (Id): New.
1264 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1265 TBM insns.
1266 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1267 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1268 (OP_E_memory): Also honor needindex when deciding whether an
1269 address size prefix needs printing.
1270 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1271
d7560e2d
JW		 12722019-06-26 Jim Wilson <jimw@sifive.com>
1273
1274 PR binutils/24739
1275 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1276 Set info->display_endian to info->endian_code.
1277
2c703856
JB		 12782019-06-25 Jan Beulich <jbeulich@suse.com>
1279
1280 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1281 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1282 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1283 OPERAND_TYPE_ACC64 entries.
1284 * i386-init.h: Re-generate.
1285
54fbadc0
JB		 12862019-06-25 Jan Beulich <jbeulich@suse.com>
1287
1288 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1289 Delete.
1290 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1291 of dqa_mode.
1292 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1293 entries here.
1294 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1295 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1296
a280ab8e
JB		 12972019-06-25 Jan Beulich <jbeulich@suse.com>
1298
1299 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1300 variables.
1301
e1a1babd
JB		 13022019-06-25 Jan Beulich <jbeulich@suse.com>
1303
1304 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1305 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1306 movnti.
d7560e2d 1307 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1308 * i386-tbl.h: Re-generate.
1309
b8364fa7
JB		 13102019-06-25 Jan Beulich <jbeulich@suse.com>
1311
1312 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1313 * i386-tbl.h: Re-generate.
1314
ad692897
L		 13152019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1316
1317 * i386-dis-evex.h: Break into ...
1318 * i386-dis-evex-len.h: New file.
1319 * i386-dis-evex-mod.h: Likewise.
1320 * i386-dis-evex-prefix.h: Likewise.
1321 * i386-dis-evex-reg.h: Likewise.
1322 * i386-dis-evex-w.h: Likewise.
1323 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1324 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1325 i386-dis-evex-mod.h.
1326
f0a6222e
L		 13272019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1328
1329 PR binutils/24700
1330 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1331 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1332 EVEX_W_0F385B_P_2.
1333 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1334 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1335 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1336 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1337 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1338 EVEX_LEN_0F385B_P_2_W_1.
1339 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1340 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1341 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1342 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1343 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1344 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1345 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1346 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1347 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1348 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1349
6e1c90b7
L		 13502019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1351
1352 PR binutils/24691
1353 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1354 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1355 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1356 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1357 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1358 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1359 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1360 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1361 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1362 EVEX_LEN_0F3A43_P_2_W_1.
1363 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1364 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1365 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1366 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1367 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1368 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1369 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1370 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1371 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1372 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1373 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1374 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1375
bcc5a6eb
NC		 13762019-06-14 Nick Clifton <nickc@redhat.com>
1377
1378 * po/fr.po; Updated French translation.
1379
e4c4ac46
SH		 13802019-06-13 Stafford Horne <shorne@gmail.com>
1381
1382 * or1k-asm.c: Regenerated.
1383 * or1k-desc.c: Regenerated.
1384 * or1k-desc.h: Regenerated.
1385 * or1k-dis.c: Regenerated.
1386 * or1k-ibld.c: Regenerated.
1387 * or1k-opc.c: Regenerated.
1388 * or1k-opc.h: Regenerated.
1389 * or1k-opinst.c: Regenerated.
1390
a0e44ef5
PB		 13912019-06-12 Peter Bergner <bergner@linux.ibm.com>
1392
1393 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1394
12efd68d
L		 13952019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1396
1397 PR binutils/24633
1398 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1399 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1400 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1401 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1402 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1403 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1404 EVEX_LEN_0F3A1B_P_2_W_1.
1405 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1406 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1407 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1408 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1409 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1410 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1411 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1412 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1413
63c6fc6c
L		 14142019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1415
1416 PR binutils/24626
1417 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1418 EVEX.vvvv when disassembling VEX and EVEX instructions.
1419 (OP_VEX): Set vex.register_specifier to 0 after readding
1420 vex.register_specifier.
1421 (OP_Vex_2src_1): Likewise.
1422 (OP_Vex_2src_2): Likewise.
1423 (OP_LWP_E): Likewise.
1424 (OP_EX_Vex): Don't check vex.register_specifier.
1425 (OP_XMM_Vex): Likewise.
1426
9186c494
L		 14272019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1428 Lili Cui <lili.cui@intel.com>
1429
1430 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1431 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1432 instructions.
1433 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1434 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1435 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1436 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1437 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1438 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1439 * i386-init.h: Regenerated.
1440 * i386-tbl.h: Likewise.
1441
5d79adc4
L		 14422019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1443 Lili Cui <lili.cui@intel.com>
1444
1445 * doc/c-i386.texi: Document enqcmd.
1446 * testsuite/gas/i386/enqcmd-intel.d: New file.
1447 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1448 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1449 * testsuite/gas/i386/enqcmd.d: Likewise.
1450 * testsuite/gas/i386/enqcmd.s: Likewise.
1451 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1452 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1453 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1454 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1455 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1456 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1457 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1458 and x86-64-enqcmd.
1459
a9d96ab9
AH		 14602019-06-04 Alan Hayward <alan.hayward@arm.com>
1461
1462 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1463
4f6d070a
AM		 14642019-06-03 Alan Modra <amodra@gmail.com>
1465
1466 * ppc-dis.c (prefix_opcd_indices): Correct size.
1467
a2f4b66c
L		 14682019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1469
1470 PR gas/24625
1471 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1472 Disp8ShiftVL.
1473 * i386-tbl.h: Regenerated.
1474
405b5bd8
AM		 14752019-05-24 Alan Modra <amodra@gmail.com>
1476
1477 * po/POTFILES.in: Regenerate.
1478
8acf1435
PB		 14792019-05-24 Peter Bergner <bergner@linux.ibm.com>
1480 Alan Modra <amodra@gmail.com>
1481
1482 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1483 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1484 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1485 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1486 XTOP>): Define and add entries.
1487 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1488 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1489 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1490 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1491
dd7efa79
PB		 14922019-05-24 Peter Bergner <bergner@linux.ibm.com>
1493 Alan Modra <amodra@gmail.com>
1494
1495 * ppc-dis.c (ppc_opts): Add "future" entry.
1496 (PREFIX_OPCD_SEGS): Define.
1497 (prefix_opcd_indices): New array.
1498 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1499 (lookup_prefix): New function.
1500 (print_insn_powerpc): Handle 64-bit prefix instructions.
1501 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1502 (PMRR, POWERXX): Define.
1503 (prefix_opcodes): New instruction table.
1504 (prefix_num_opcodes): New constant.
1505
79472b45
JM		 15062019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1507
1508 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1509 * configure: Regenerated.
1510 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1511 and cpu/bpf.opc.
1512 (HFILES): Add bpf-desc.h and bpf-opc.h.
1513 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1514 bpf-ibld.c and bpf-opc.c.
1515 (BPF_DEPS): Define.
1516 * Makefile.in: Regenerated.
1517 * disassemble.c (ARCH_bpf): Define.
1518 (disassembler): Add case for bfd_arch_bpf.
1519 (disassemble_init_for_target): Likewise.
1520 (enum epbf_isa_attr): Define.
1521 * disassemble.h: extern print_insn_bpf.
1522 * bpf-asm.c: Generated.
1523 * bpf-opc.h: Likewise.
1524 * bpf-opc.c: Likewise.
1525 * bpf-ibld.c: Likewise.
1526 * bpf-dis.c: Likewise.
1527 * bpf-desc.h: Likewise.
1528 * bpf-desc.c: Likewise.
1529
ba6cd17f
SD		 15302019-05-21 Sudakshina Das <sudi.das@arm.com>
1531
1532 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1533 and VMSR with the new operands.
1534
e39c1607
SD		 15352019-05-21 Sudakshina Das <sudi.das@arm.com>
1536
1537 * arm-dis.c (enum mve_instructions): New enum
1538 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1539 and cneg.
1540 (mve_opcodes): New instructions as above.
1541 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1542 csneg and csel.
1543 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1544
23d00a41
SD		 15452019-05-21 Sudakshina Das <sudi.das@arm.com>
1546
1547 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1548 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1549 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1550 uqshl, urshrl and urshr.
1551 (is_mve_okay_in_it): Add new instructions to TRUE list.
1552 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1553 (print_insn_mve): Updated to accept new %j,
1554 %<bitfield>m and %<bitfield>n patterns.
1555
cd4797ee
FS		 15562019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1557
1558 * mips-opc.c (mips_builtin_opcodes): Change source register
1559 constraint for DAUI.
1560
999b073b
NC		 15612019-05-20 Nick Clifton <nickc@redhat.com>
1562
1563 * po/fr.po: Updated French translation.
1564
14b456f2
AV		 15652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1566 Michael Collison <michael.collison@arm.com>
1567
1568 * arm-dis.c (thumb32_opcodes): Add new instructions.
1569 (enum mve_instructions): Likewise.
1570 (enum mve_undefined): Add new reasons.
1571 (is_mve_encoding_conflict): Handle new instructions.
1572 (is_mve_undefined): Likewise.
1573 (is_mve_unpredictable): Likewise.
1574 (print_mve_undefined): Likewise.
1575 (print_mve_size): Likewise.
1576
f49bb598
AV		 15772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1578 Michael Collison <michael.collison@arm.com>
1579
1580 * arm-dis.c (thumb32_opcodes): Add new instructions.
1581 (enum mve_instructions): Likewise.
1582 (is_mve_encoding_conflict): Handle new instructions.
1583 (is_mve_undefined): Likewise.
1584 (is_mve_unpredictable): Likewise.
1585 (print_mve_size): Likewise.
1586
56858bea
AV		 15872019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1588 Michael Collison <michael.collison@arm.com>
1589
1590 * arm-dis.c (thumb32_opcodes): Add new instructions.
1591 (enum mve_instructions): Likewise.
1592 (is_mve_encoding_conflict): Likewise.
1593 (is_mve_unpredictable): Likewise.
1594 (print_mve_size): Likewise.
1595
e523f101
AV		 15962019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1597 Michael Collison <michael.collison@arm.com>
1598
1599 * arm-dis.c (thumb32_opcodes): Add new instructions.
1600 (enum mve_instructions): Likewise.
1601 (is_mve_encoding_conflict): Handle new instructions.
1602 (is_mve_undefined): Likewise.
1603 (is_mve_unpredictable): Likewise.
1604 (print_mve_size): Likewise.
1605
66dcaa5d
AV		 16062019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1607 Michael Collison <michael.collison@arm.com>
1608
1609 * arm-dis.c (thumb32_opcodes): Add new instructions.
1610 (enum mve_instructions): Likewise.
1611 (is_mve_encoding_conflict): Handle new instructions.
1612 (is_mve_undefined): Likewise.
1613 (is_mve_unpredictable): Likewise.
1614 (print_mve_size): Likewise.
1615 (print_insn_mve): Likewise.
1616
d052b9b7
AV		 16172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1618 Michael Collison <michael.collison@arm.com>
1619
1620 * arm-dis.c (thumb32_opcodes): Add new instructions.
1621 (print_insn_thumb32): Handle new instructions.
1622
ed63aa17
AV		 16232019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1624 Michael Collison <michael.collison@arm.com>
1625
1626 * arm-dis.c (enum mve_instructions): Add new instructions.
1627 (enum mve_undefined): Add new reasons.
1628 (is_mve_encoding_conflict): Handle new instructions.
1629 (is_mve_undefined): Likewise.
1630 (is_mve_unpredictable): Likewise.
1631 (print_mve_undefined): Likewise.
1632 (print_mve_size): Likewise.
1633 (print_mve_shift_n): Likewise.
1634 (print_insn_mve): Likewise.
1635
897b9bbc
AV		 16362019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1637 Michael Collison <michael.collison@arm.com>
1638
1639 * arm-dis.c (enum mve_instructions): Add new instructions.
1640 (is_mve_encoding_conflict): Handle new instructions.
1641 (is_mve_unpredictable): Likewise.
1642 (print_mve_rotate): Likewise.
1643 (print_mve_size): Likewise.
1644 (print_insn_mve): Likewise.
1645
1c8f2df8
AV		 16462019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1647 Michael Collison <michael.collison@arm.com>
1648
1649 * arm-dis.c (enum mve_instructions): Add new instructions.
1650 (is_mve_encoding_conflict): Handle new instructions.
1651 (is_mve_unpredictable): Likewise.
1652 (print_mve_size): Likewise.
1653 (print_insn_mve): Likewise.
1654
d3b63143
AV		 16552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1656 Michael Collison <michael.collison@arm.com>
1657
1658 * arm-dis.c (enum mve_instructions): Add new instructions.
1659 (enum mve_undefined): Add new reasons.
1660 (is_mve_encoding_conflict): Handle new instructions.
1661 (is_mve_undefined): Likewise.
1662 (is_mve_unpredictable): Likewise.
1663 (print_mve_undefined): Likewise.
1664 (print_mve_size): Likewise.
1665 (print_insn_mve): Likewise.
1666
14925797
AV		 16672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1668 Michael Collison <michael.collison@arm.com>
1669
1670 * arm-dis.c (enum mve_instructions): Add new instructions.
1671 (is_mve_encoding_conflict): Handle new instructions.
1672 (is_mve_undefined): Likewise.
1673 (is_mve_unpredictable): Likewise.
1674 (print_mve_size): Likewise.
1675 (print_insn_mve): Likewise.
1676
c507f10b
AV		 16772019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1678 Michael Collison <michael.collison@arm.com>
1679
1680 * arm-dis.c (enum mve_instructions): Add new instructions.
1681 (enum mve_unpredictable): Add new reasons.
1682 (enum mve_undefined): Likewise.
1683 (is_mve_okay_in_it): Handle new isntructions.
1684 (is_mve_encoding_conflict): Likewise.
1685 (is_mve_undefined): Likewise.
1686 (is_mve_unpredictable): Likewise.
1687 (print_mve_vmov_index): Likewise.
1688 (print_simd_imm8): Likewise.
1689 (print_mve_undefined): Likewise.
1690 (print_mve_unpredictable): Likewise.
1691 (print_mve_size): Likewise.
1692 (print_insn_mve): Likewise.
1693
bf0b396d
AV		 16942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1695 Michael Collison <michael.collison@arm.com>
1696
1697 * arm-dis.c (enum mve_instructions): Add new instructions.
1698 (enum mve_unpredictable): Add new reasons.
1699 (enum mve_undefined): Likewise.
1700 (is_mve_encoding_conflict): Handle new instructions.
1701 (is_mve_undefined): Likewise.
1702 (is_mve_unpredictable): Likewise.
1703 (print_mve_undefined): Likewise.
1704 (print_mve_unpredictable): Likewise.
1705 (print_mve_rounding_mode): Likewise.
1706 (print_mve_vcvt_size): Likewise.
1707 (print_mve_size): Likewise.
1708 (print_insn_mve): Likewise.
1709
ef1576a1
AV		 17102019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1711 Michael Collison <michael.collison@arm.com>
1712
1713 * arm-dis.c (enum mve_instructions): Add new instructions.
1714 (enum mve_unpredictable): Add new reasons.
1715 (enum mve_undefined): Likewise.
1716 (is_mve_undefined): Handle new instructions.
1717 (is_mve_unpredictable): Likewise.
1718 (print_mve_undefined): Likewise.
1719 (print_mve_unpredictable): Likewise.
1720 (print_mve_size): Likewise.
1721 (print_insn_mve): Likewise.
1722
aef6d006
AV		 17232019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1724 Michael Collison <michael.collison@arm.com>
1725
1726 * arm-dis.c (enum mve_instructions): Add new instructions.
1727 (enum mve_undefined): Add new reasons.
1728 (insns): Add new instructions.
1729 (is_mve_encoding_conflict):
1730 (print_mve_vld_str_addr): New print function.
1731 (is_mve_undefined): Handle new instructions.
1732 (is_mve_unpredictable): Likewise.
1733 (print_mve_undefined): Likewise.
1734 (print_mve_size): Likewise.
1735 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1736 (print_insn_mve): Handle new operands.
1737
04d54ace
AV		 17382019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1739 Michael Collison <michael.collison@arm.com>
1740
1741 * arm-dis.c (enum mve_instructions): Add new instructions.
1742 (enum mve_unpredictable): Add new reasons.
1743 (is_mve_encoding_conflict): Handle new instructions.
1744 (is_mve_unpredictable): Likewise.
1745 (mve_opcodes): Add new instructions.
1746 (print_mve_unpredictable): Handle new reasons.
1747 (print_mve_register_blocks): New print function.
1748 (print_mve_size): Handle new instructions.
1749 (print_insn_mve): Likewise.
1750
9743db03
AV		 17512019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1752 Michael Collison <michael.collison@arm.com>
1753
1754 * arm-dis.c (enum mve_instructions): Add new instructions.
1755 (enum mve_unpredictable): Add new reasons.
1756 (enum mve_undefined): Likewise.
1757 (is_mve_encoding_conflict): Handle new instructions.
1758 (is_mve_undefined): Likewise.
1759 (is_mve_unpredictable): Likewise.
1760 (coprocessor_opcodes): Move NEON VDUP from here...
1761 (neon_opcodes): ... to here.
1762 (mve_opcodes): Add new instructions.
1763 (print_mve_undefined): Handle new reasons.
1764 (print_mve_unpredictable): Likewise.
1765 (print_mve_size): Handle new instructions.
1766 (print_insn_neon): Handle vdup.
1767 (print_insn_mve): Handle new operands.
1768
143275ea
AV		 17692019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1770 Michael Collison <michael.collison@arm.com>
1771
1772 * arm-dis.c (enum mve_instructions): Add new instructions.
1773 (enum mve_unpredictable): Add new values.
1774 (mve_opcodes): Add new instructions.
1775 (vec_condnames): New array with vector conditions.
1776 (mve_predicatenames): New array with predicate suffixes.
1777 (mve_vec_sizename): New array with vector sizes.
1778 (enum vpt_pred_state): New enum with vector predication states.
1779 (struct vpt_block): New struct type for vpt blocks.
1780 (vpt_block_state): Global struct to keep track of state.
1781 (mve_extract_pred_mask): New helper function.
1782 (num_instructions_vpt_block): Likewise.
1783 (mark_outside_vpt_block): Likewise.
1784 (mark_inside_vpt_block): Likewise.
1785 (invert_next_predicate_state): Likewise.
1786 (update_next_predicate_state): Likewise.
1787 (update_vpt_block_state): Likewise.
1788 (is_vpt_instruction): Likewise.
1789 (is_mve_encoding_conflict): Add entries for new instructions.
1790 (is_mve_unpredictable): Likewise.
1791 (print_mve_unpredictable): Handle new cases.
1792 (print_instruction_predicate): Likewise.
1793 (print_mve_size): New function.
1794 (print_vec_condition): New function.
1795 (print_insn_mve): Handle vpt blocks and new print operands.
1796
f08d8ce3
AV		 17972019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1798
1799 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1800 8, 14 and 15 for Armv8.1-M Mainline.
1801
73cd51e5
AV		 18022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1803 Michael Collison <michael.collison@arm.com>
1804
1805 * arm-dis.c (enum mve_instructions): New enum.
1806 (enum mve_unpredictable): Likewise.
1807 (enum mve_undefined): Likewise.
1808 (struct mopcode32): New struct.
1809 (is_mve_okay_in_it): New function.
1810 (is_mve_architecture): Likewise.
1811 (arm_decode_field): Likewise.
1812 (arm_decode_field_multiple): Likewise.
1813 (is_mve_encoding_conflict): Likewise.
1814 (is_mve_undefined): Likewise.
1815 (is_mve_unpredictable): Likewise.
1816 (print_mve_undefined): Likewise.
1817 (print_mve_unpredictable): Likewise.
1818 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1819 (print_insn_mve): New function.
1820 (print_insn_thumb32): Handle MVE architecture.
1821 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1822
3076e594
NC		 18232019-05-10 Nick Clifton <nickc@redhat.com>
1824
1825 PR 24538
1826 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1827 end of the table prematurely.
1828
387e7624
FS		 18292019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1830
1831 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1832 macros for R6.
1833
0067be51
AM		 18342019-05-11 Alan Modra <amodra@gmail.com>
1835
1836 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1837 when -Mraw is in effect.
1838
42e6288f
MM		 18392019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1840
1841 * aarch64-dis-2.c: Regenerate.
1842 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1843 (OP_SVE_BBB): New variant set.
1844 (OP_SVE_DDDD): New variant set.
1845 (OP_SVE_HHH): New variant set.
1846 (OP_SVE_HHHU): New variant set.
1847 (OP_SVE_SSS): New variant set.
1848 (OP_SVE_SSSU): New variant set.
1849 (OP_SVE_SHH): New variant set.
1850 (OP_SVE_SBBU): New variant set.
1851 (OP_SVE_DSS): New variant set.
1852 (OP_SVE_DHHU): New variant set.
1853 (OP_SVE_VMV_HSD_BHS): New variant set.
1854 (OP_SVE_VVU_HSD_BHS): New variant set.
1855 (OP_SVE_VVVU_SD_BH): New variant set.
1856 (OP_SVE_VVVU_BHSD): New variant set.
1857 (OP_SVE_VVV_QHD_DBS): New variant set.
1858 (OP_SVE_VVV_HSD_BHS): New variant set.
1859 (OP_SVE_VVV_HSD_BHS2): New variant set.
1860 (OP_SVE_VVV_BHS_HSD): New variant set.
1861 (OP_SVE_VV_BHS_HSD): New variant set.
1862 (OP_SVE_VVV_SD): New variant set.
1863 (OP_SVE_VVU_BHS_HSD): New variant set.
1864 (OP_SVE_VZVV_SD): New variant set.
1865 (OP_SVE_VZVV_BH): New variant set.
1866 (OP_SVE_VZV_SD): New variant set.
1867 (aarch64_opcode_table): Add sve2 instructions.
1868
28ed815a
MM		 18692019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1870
1871 * aarch64-asm-2.c: Regenerated.
1872 * aarch64-dis-2.c: Regenerated.
1873 * aarch64-opc-2.c: Regenerated.
1874 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1875 for SVE_SHLIMM_UNPRED_22.
1876 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1877 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1878 operand.
1879
fd1dc4a0
MM		 18802019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1881
1882 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1883 sve_size_tsz_bhs iclass encode.
1884 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1885 sve_size_tsz_bhs iclass decode.
1886
31e36ab3
MM		 18872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1888
1889 * aarch64-asm-2.c: Regenerated.
1890 * aarch64-dis-2.c: Regenerated.
1891 * aarch64-opc-2.c: Regenerated.
1892 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1893 for SVE_Zm4_11_INDEX.
1894 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1895 (fields): Handle SVE_i2h field.
1896 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1897 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1898
1be5f94f
MM		 18992019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1900
1901 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1902 sve_shift_tsz_bhsd iclass encode.
1903 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1904 sve_shift_tsz_bhsd iclass decode.
1905
3c17238b
MM		 19062019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1907
1908 * aarch64-asm-2.c: Regenerated.
1909 * aarch64-dis-2.c: Regenerated.
1910 * aarch64-opc-2.c: Regenerated.
1911 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1912 (aarch64_encode_variant_using_iclass): Handle
1913 sve_shift_tsz_hsd iclass encode.
1914 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1915 sve_shift_tsz_hsd iclass decode.
1916 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1917 for SVE_SHRIMM_UNPRED_22.
1918 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1919 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1920 operand.
1921
cd50a87a
MM		 19222019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1923
1924 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1925 sve_size_013 iclass encode.
1926 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1927 sve_size_013 iclass decode.
1928
3c705960
MM		 19292019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1930
1931 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1932 sve_size_bh iclass encode.
1933 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1934 sve_size_bh iclass decode.
1935
0a57e14f
MM		 19362019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1937
1938 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1939 sve_size_sd2 iclass encode.
1940 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1941 sve_size_sd2 iclass decode.
1942 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1943 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1944
c469c864
MM		 19452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1946
1947 * aarch64-asm-2.c: Regenerated.
1948 * aarch64-dis-2.c: Regenerated.
1949 * aarch64-opc-2.c: Regenerated.
1950 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1951 for SVE_ADDR_ZX.
1952 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1953 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1954
116adc27
MM		 19552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1956
1957 * aarch64-asm-2.c: Regenerated.
1958 * aarch64-dis-2.c: Regenerated.
1959 * aarch64-opc-2.c: Regenerated.
1960 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1961 for SVE_Zm3_11_INDEX.
1962 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1963 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1964 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1965 fields.
1966 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1967
3bd82c86
MM		 19682019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1969
1970 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1971 sve_size_hsd2 iclass encode.
1972 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1973 sve_size_hsd2 iclass decode.
1974 * aarch64-opc.c (fields): Handle SVE_size field.
1975 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1976
adccc507
MM		 19772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1978
1979 * aarch64-asm-2.c: Regenerated.
1980 * aarch64-dis-2.c: Regenerated.
1981 * aarch64-opc-2.c: Regenerated.
1982 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1983 for SVE_IMM_ROT3.
1984 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1985 (fields): Handle SVE_rot3 field.
1986 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1987 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1988
5cd99750
MM		 19892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1990
1991 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1992 instructions.
1993
7ce2460a
MM		 19942019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1995
1996 * aarch64-tbl.h
1997 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1998 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1999 aarch64_feature_sve2bitperm): New feature sets.
2000 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
2001 for feature set addresses.
2002 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
2003 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
2004
41cee089
FS		 20052019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
2006 Faraz Shahbazker <fshahbazker@wavecomp.com>
2007
2008 * mips-dis.c (mips_calculate_combination_ases): Add ISA
2009 argument and set ASE_EVA_R6 appropriately.
2010 (set_default_mips_dis_options): Pass ISA to above.
2011 (parse_mips_dis_option): Likewise.
2012 * mips-opc.c (EVAR6): New macro.
2013 (mips_builtin_opcodes): Add llwpe, scwpe.
2014
b83b4b13
SD		 20152019-05-01 Sudakshina Das <sudi.das@arm.com>
2016
2017 * aarch64-asm-2.c: Regenerated.
2018 * aarch64-dis-2.c: Regenerated.
2019 * aarch64-opc-2.c: Regenerated.
2020 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
2021 AARCH64_OPND_TME_UIMM16.
2022 (aarch64_print_operand): Likewise.
2023 * aarch64-tbl.h (QL_IMM_NIL): New.
2024 (TME): New.
2025 (_TME_INSN): New.
2026 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
2027
4a90ce95
JD		 20282019-04-29 John Darrington <john@darrington.wattle.id.au>
2029
2030 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
2031
a45328b9
AB		 20322019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
2033 Faraz Shahbazker <fshahbazker@wavecomp.com>
2034
2035 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
2036
d10be0cb
JD		 20372019-04-24 John Darrington <john@darrington.wattle.id.au>
2038
2039 * s12z-opc.h: Add extern "C" bracketing to help
2040 users who wish to use this interface in c++ code.
2041
a679f24e
JD		 20422019-04-24 John Darrington <john@darrington.wattle.id.au>
2043
2044 * s12z-opc.c (bm_decode): Handle bit map operations with the
2045 "reserved0" mode.
2046
32c36c3c
AV		 20472019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2048
2049 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
2050 specifier. Add entries for VLDR and VSTR of system registers.
2051 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
2052 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
2053 of %J and %K format specifier.
2054
efd6b359
AV		 20552019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2056
2057 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
2058 Add new entries for VSCCLRM instruction.
2059 (print_insn_coprocessor): Handle new %C format control code.
2060
6b0dd094
AV		 20612019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2062
2063 * arm-dis.c (enum isa): New enum.
2064 (struct sopcode32): New structure.
2065 (coprocessor_opcodes): change type of entries to struct sopcode32 and
2066 set isa field of all current entries to ANY.
2067 (print_insn_coprocessor): Change type of insn to struct sopcode32.
2068 Only match an entry if its isa field allows the current mode.
2069
4b5a202f
AV		 20702019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2071
2072 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
2073 CLRM.
2074 (print_insn_thumb32): Add logic to print %n CLRM register list.
2075
60f993ce
AV		 20762019-04-15 Sudakshina Das <sudi.das@arm.com>
2077
2078 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
2079 and %Q patterns.
2080
f6b2b12d
AV		 20812019-04-15 Sudakshina Das <sudi.das@arm.com>
2082
2083 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
2084 (print_insn_thumb32): Edit the switch case for %Z.
2085
1889da70
AV		 20862019-04-15 Sudakshina Das <sudi.das@arm.com>
2087
2088 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
2089
65d1bc05
AV		 20902019-04-15 Sudakshina Das <sudi.das@arm.com>
2091
2092 * arm-dis.c (thumb32_opcodes): New instruction bfl.
2093
1caf72a5
AV		 20942019-04-15 Sudakshina Das <sudi.das@arm.com>
2095
2096 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
2097
f1c7f421
AV		 20982019-04-15 Sudakshina Das <sudi.das@arm.com>
2099
2100 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
2101 Arm register with r13 and r15 unpredictable.
2102 (thumb32_opcodes): New instructions for bfx and bflx.
2103
4389b29a
AV		 21042019-04-15 Sudakshina Das <sudi.das@arm.com>
2105
2106 * arm-dis.c (thumb32_opcodes): New instructions for bf.
2107
e5d6e09e
AV		 21082019-04-15 Sudakshina Das <sudi.das@arm.com>
2109
2110 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
2111
e12437dc
AV		 21122019-04-15 Sudakshina Das <sudi.das@arm.com>
2113
2114 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
2115
031254f2
AV		 21162019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
2117
2118 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
2119
e5a557ac
JD		 21202019-04-12 John Darrington <john@darrington.wattle.id.au>
2121
2122 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
2123 "optr". ("operator" is a reserved word in c++).
2124
bd7ceb8d
SD		 21252019-04-11 Sudakshina Das <sudi.das@arm.com>
2126
2127 * aarch64-opc.c (aarch64_print_operand): Add case for
2128 AARCH64_OPND_Rt_SP.
2129 (verify_constraints): Likewise.
2130 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
2131 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
2132 to accept Rt|SP as first operand.
2133 (AARCH64_OPERANDS): Add new Rt_SP.
2134 * aarch64-asm-2.c: Regenerated.
2135 * aarch64-dis-2.c: Regenerated.
2136 * aarch64-opc-2.c: Regenerated.
2137
e54010f1
SD		 21382019-04-11 Sudakshina Das <sudi.das@arm.com>
2139
2140 * aarch64-asm-2.c: Regenerated.
2141 * aarch64-dis-2.c: Likewise.
2142 * aarch64-opc-2.c: Likewise.
2143 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
2144
7e96e219
RS		 21452019-04-09 Robert Suchanek <robert.suchanek@mips.com>
2146
2147 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
2148
6f2791d5
L		 21492019-04-08 H.J. Lu <hongjiu.lu@intel.com>
2150
2151 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
2152 * i386-init.h: Regenerated.
2153
e392bad3
AM		 21542019-04-07 Alan Modra <amodra@gmail.com>
2155
2156 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
2157 op_separator to control printing of spaces, comma and parens
2158 rather than need_comma, need_paren and spaces vars.
2159
dffaa15c
AM		 21602019-04-07 Alan Modra <amodra@gmail.com>
2161
2162 PR 24421
2163 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
2164 (print_insn_neon, print_insn_arm): Likewise.
2165
d6aab7a1
XG		 21662019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
2167
2168 * i386-dis-evex.h (evex_table): Updated to support BF16
2169 instructions.
2170 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
2171 and EVEX_W_0F3872_P_3.
2172 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
2173 (cpu_flags): Add bitfield for CpuAVX512_BF16.
2174 * i386-opc.h (enum): Add CpuAVX512_BF16.
2175 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
2176 * i386-opc.tbl: Add AVX512 BF16 instructions.
2177 * i386-init.h: Regenerated.
2178 * i386-tbl.h: Likewise.
2179
66e85460
AM		 21802019-04-05 Alan Modra <amodra@gmail.com>
2181
2182 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
2183 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
2184 to favour printing of "-" branch hint when using the "y" bit.
2185 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
2186
c2b1c275
AM		 21872019-04-05 Alan Modra <amodra@gmail.com>
2188
2189 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
2190 opcode until first operand is output.
2191
aae9718e
PB		 21922019-04-04 Peter Bergner <bergner@linux.ibm.com>
2193
2194 PR gas/24349
2195 * ppc-opc.c (valid_bo_pre_v2): Add comments.
2196 (valid_bo_post_v2): Add support for 'at' branch hints.
2197 (insert_bo): Only error on branch on ctr.
2198 (get_bo_hint_mask): New function.
2199 (insert_boe): Add new 'branch_taken' formal argument. Add support
2200 for inserting 'at' branch hints.
2201 (extract_boe): Add new 'branch_taken' formal argument. Add support
2202 for extracting 'at' branch hints.
2203 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
2204 (BOE): Delete operand.
2205 (BOM, BOP): New operands.
2206 (RM): Update value.
2207 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
2208 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
2209 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
2210 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
2211 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
2212 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
2213 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
2214 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
2215 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
2216 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
2217 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
2218 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
2219 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
2220 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
2221 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
2222 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
2223 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
2224 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
2225 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
2226 bttarl+>: New extended mnemonics.
2227
96a86c01
AM		 22282019-03-28 Alan Modra <amodra@gmail.com>
2229
2230 PR 24390
2231 * ppc-opc.c (BTF): Define.
2232 (powerpc_opcodes): Use for mtfsb*.
2233 * ppc-dis.c (print_insn_powerpc): Print fields with both
2234 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2235
796d6298
TC		 22362019-03-25 Tamar Christina <tamar.christina@arm.com>
2237
2238 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2239 (mapping_symbol_for_insn): Implement new algorithm.
2240 (print_insn): Remove duplicate code.
2241
60df3720
TC		 22422019-03-25 Tamar Christina <tamar.christina@arm.com>
2243
2244 * aarch64-dis.c (print_insn_aarch64):
2245 Implement override.
2246
51457761
TC		 22472019-03-25 Tamar Christina <tamar.christina@arm.com>
2248
2249 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2250 order.
2251
53b2f36b
TC		 22522019-03-25 Tamar Christina <tamar.christina@arm.com>
2253
2254 * aarch64-dis.c (last_stop_offset): New.
2255 (print_insn_aarch64): Use stop_offset.
2256
89199bb5
L		 22572019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2258
2259 PR gas/24359
2260 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2261 CPU_ANY_AVX2_FLAGS.
2262 * i386-init.h: Regenerated.
2263
97ed31ae
L		 22642019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2265
2266 PR gas/24348
2267 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2268 vmovdqu16, vmovdqu32 and vmovdqu64.
2269 * i386-tbl.h: Regenerated.
2270
0919bfe9
AK		 22712019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2272
2273 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2274 from vstrszb, vstrszh, and vstrszf.
2275
22762019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2277
2278 * s390-opc.txt: Add instruction descriptions.
2279
21820ebe
JW		 22802019-02-08 Jim Wilson <jimw@sifive.com>
2281
2282 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2283 <bne>: Likewise.
2284
f7dd2fb2
TC		 22852019-02-07 Tamar Christina <tamar.christina@arm.com>
2286
2287 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2288
6456d318
TC		 22892019-02-07 Tamar Christina <tamar.christina@arm.com>
2290
2291 PR binutils/23212
2292 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2293 * aarch64-opc.c (verify_elem_sd): New.
2294 (fields): Add FLD_sz entr.
2295 * aarch64-tbl.h (_SIMD_INSN): New.
2296 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2297 fmulx scalar and vector by element isns.
2298
4a83b610
NC		 22992019-02-07 Nick Clifton <nickc@redhat.com>
2300
2301 * po/sv.po: Updated Swedish translation.
2302
fc60b8c8
AK		 23032019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2304
2305 * s390-mkopc.c (main): Accept arch13 as cpu string.
2306 * s390-opc.c: Add new instruction formats and instruction opcode
2307 masks.
2308 * s390-opc.txt: Add new arch13 instructions.
2309
e10620d3
TC		 23102019-01-25 Sudakshina Das <sudi.das@arm.com>
2311
2312 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2313 (aarch64_opcode): Change encoding for stg, stzg
2314 st2g and st2zg.
2315 * aarch64-asm-2.c: Regenerated.
2316 * aarch64-dis-2.c: Regenerated.
2317 * aarch64-opc-2.c: Regenerated.
2318
20a4ca55
SD		 23192019-01-25 Sudakshina Das <sudi.das@arm.com>
2320
2321 * aarch64-asm-2.c: Regenerated.
2322 * aarch64-dis-2.c: Likewise.
2323 * aarch64-opc-2.c: Likewise.
2324 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2325
550fd7bf
SD		 23262019-01-25 Sudakshina Das <sudi.das@arm.com>
2327 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2328
2329 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2330 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2331 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2332 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2333 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2334 case for ldstgv_indexed.
2335 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2336 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2337 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2338 * aarch64-asm-2.c: Regenerated.
2339 * aarch64-dis-2.c: Regenerated.
2340 * aarch64-opc-2.c: Regenerated.
2341
d9938630
NC		 23422019-01-23 Nick Clifton <nickc@redhat.com>
2343
2344 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2345
375cd423
NC		 23462019-01-21 Nick Clifton <nickc@redhat.com>
2347
2348 * po/de.po: Updated German translation.
2349 * po/uk.po: Updated Ukranian translation.
2350
57299f48
CX		 23512019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2352 * mips-dis.c (mips_arch_choices): Fix typo in
2353 gs464, gs464e and gs264e descriptors.
2354
f48dfe41
NC		 23552019-01-19 Nick Clifton <nickc@redhat.com>
2356
2357 * configure: Regenerate.
2358 * po/opcodes.pot: Regenerate.
2359
f974f26c
NC		 23602018-06-24 Nick Clifton <nickc@redhat.com>
2361
2362 2.32 branch created.
2363
39f286cd
JD		 23642019-01-09 John Darrington <john@darrington.wattle.id.au>
2365
448b8ca8
JD		 2366 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2367 if it is null.
2368 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2369 zero.
2370
3107326d
AP		 23712019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2372
2373 * configure: Regenerate.
2374
7e9ca91e
AM		 23752019-01-07 Alan Modra <amodra@gmail.com>
2376
2377 * configure: Regenerate.
2378 * po/POTFILES.in: Regenerate.
2379
ef1ad42b
JD		 23802019-01-03 John Darrington <john@darrington.wattle.id.au>
2381
2382 * s12z-opc.c: New file.
2383 * s12z-opc.h: New file.
2384 * s12z-dis.c: Removed all code not directly related to display
2385 of instructions. Used the interface provided by the new files
2386 instead.
2387 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2388 * Makefile.in: Regenerate.
ef1ad42b 2389 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2390 * configure: Regenerate.
ef1ad42b 2391
82704155
AM		 23922019-01-01 Alan Modra <amodra@gmail.com>
2393
2394 Update year range in copyright notice of all files.
2395
d5c04e1b 2396For older changes see ChangeLog-2018
3499769a 2397\f
d5c04e1b 2398Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2399
2400Copying and distribution of this file, with or without modification,
2401are permitted in any medium without royalty provided the copyright
2402notice and this notice are preserved.
2403
2404Local Variables:
2405mode: change-log
2406left-margin: 8
2407fill-column: 74
2408version-control: never
2409End:
GDB Binutils - Deliverables
This page took 0.330417 seconds and 4 git commands to generate.