* config/alpha/tm-nbsd.h: Remove file.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
e8b42ce4
JB
12006-07-05 Julian Brown <julian@codesourcery.com>
2
3 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
4
15965411
L
52006-06-12 H.J. Lu <hongjiu.lu@intel.com>
6
7 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
8 (twobyte_has_modrm): Set 1 for 0x1f.
9
46e883c5
L
102006-06-12 H.J. Lu <hongjiu.lu@intel.com>
11
12 * i386-dis.c (NOP_Fixup): Removed.
13 (NOP_Fixup1): New.
14 (NOP_Fixup2): Likewise.
15 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
16
4e9d3b81
JB
172006-06-12 Julian Brown <julian@codesourcery.com>
18
19 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
20 on 64-bit hosts.
21
b3882df9
L
222006-06-10 H.J. Lu <hongjiu.lu@intel.com>
23
24 * i386.c (GRP10): Renamed to ...
25 (GRP12): This.
26 (GRP11): Renamed to ...
27 (GRP13): This.
28 (GRP12): Renamed to ...
29 (GRP14): This.
30 (GRP13): Renamed to ...
31 (GRP15): This.
32 (GRP14): Renamed to ...
33 (GRP16): This.
34 (dis386_twobyte): Updated.
35 (grps): Likewise.
36
5f4df3dd
NC
372006-06-09 Nick Clifton <nickc@redhat.com>
38
39 * po/fi.po: Updated Finnish translation.
40
6648b7cf
JM
412006-06-07 Joseph S. Myers <joseph@codesourcery.com>
42
43 * po/Make-in (pdf, ps): New dummy targets.
44
c22aaad1
PB
452006-06-06 Paul Brook <paul@codesourcery.com>
46
47 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
48 instructions.
49 (neon_opcodes): Add conditional execution specifiers.
50 (thumb_opcodes): Ditto.
51 (thumb32_opcodes): Ditto.
52 (arm_conditional): Change 0xe to "al" and add "" to end.
53 (ifthen_state, ifthen_next_state, ifthen_address): New.
54 (IFTHEN_COND): Define.
55 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
56 (print_insn_arm): Change %c to use new values of arm_conditional.
57 (print_insn_thumb16): Print thumb conditions. Add %I.
58 (print_insn_thumb32): Print thumb conditions.
59 (find_ifthen_state): New function.
60 (print_insn): Track IT block state.
61
9622b051
AM
622006-06-06 Ben Elliston <bje@au.ibm.com>
63 Anton Blanchard <anton@samba.org>
64 Peter Bergner <bergner@vnet.ibm.com>
65
66 * ppc-dis.c (powerpc_dialect): Handle power6 option.
67 (print_ppc_disassembler_options): Mention power6.
68
65263ce3
TS
692006-06-06 Thiemo Seufer <ths@mips.com>
70 Chao-ying Fu <fu@mips.com>
71
72 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
73 * mips-opc.c: Add DSP64 instructions.
74
92ce91bb
AM
752006-06-06 Alan Modra <amodra@bigpond.net.au>
76
77 * m68hc11-dis.c (print_insn): Warning fix.
78
4cfe2c59
DJ
792006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
80
81 * po/Make-in (top_builddir): Define.
82
7ff1a5b5
AM
832006-06-05 Alan Modra <amodra@bigpond.net.au>
84
85 * Makefile.am: Run "make dep-am".
86 * Makefile.in: Regenerate.
87 * config.in: Regenerate.
88
20e95c23
DJ
892006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
90
91 * Makefile.am (INCLUDES): Use @INCINTL@.
92 * acinclude.m4: Include new gettext macros.
93 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
94 Remove local code for po/Makefile.
95 * Makefile.in, aclocal.m4, configure: Regenerated.
96
eebf07fb
NC
972006-05-30 Nick Clifton <nickc@redhat.com>
98
99 * po/es.po: Updated Spanish translation.
100
a596001e
RS
1012006-05-25 Richard Sandiford <richard@codesourcery.com>
102
103 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
104 and fmovem entries. Put register list entries before immediate
105 mask entries. Use "l" rather than "L" in the fmovem entries.
106 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
107 out from INFO.
108 (m68k_scan_mask): New function, split out from...
109 (print_insn_m68k): ...here. If no architecture has been set,
110 first try printing an m680x0 instruction, then try a Coldfire one.
111
4a4d496a
NC
1122006-05-24 Nick Clifton <nickc@redhat.com>
113
114 * po/ga.po: Updated Irish translation.
115
a854efa3
NC
1162006-05-22 Nick Clifton <nickc@redhat.com>
117
118 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
119
0bd79061
NC
1202006-05-22 Nick Clifton <nickc@redhat.com>
121
122 * po/nl.po: Updated translation.
123
00988f49
AM
1242006-05-18 Alan Modra <amodra@bigpond.net.au>
125
126 * avr-dis.c: Formatting fix.
127
9b3f89ee
TS
1282006-05-14 Thiemo Seufer <ths@mips.com>
129
130 * mips16-opc.c (I1, I32, I64): New shortcut defines.
131 (mips16_opcodes): Change membership of instructions to their
132 lowest baseline ISA.
133
cb6d3433
L
1342006-05-09 H.J. Lu <hongjiu.lu@intel.com>
135
136 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
137
1f3c39b9
JB
1382006-05-05 Julian Brown <julian@codesourcery.com>
139
140 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
141 vldm/vstm.
142
d43b4baf
TS
1432006-05-05 Thiemo Seufer <ths@mips.com>
144 David Ung <davidu@mips.com>
145
146 * mips-opc.c: Add macro for cache instruction.
147
39a7806d
TS
1482006-05-04 Thiemo Seufer <ths@mips.com>
149 Nigel Stephens <nigel@mips.com>
150 David Ung <davidu@mips.com>
151
152 * mips-dis.c (mips_arch_choices): Add smartmips instruction
153 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
154 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
155 MIPS64R2.
156 * mips-opc.c: fix random typos in comments.
157 (INSN_SMARTMIPS): New defines.
158 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
159 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
160 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
161 FP_S and FP_D flags to denote single and double register
162 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
163 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
164 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
165 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
166 release 2 ISAs.
167 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
168
104b4fab
TS
1692006-05-03 Thiemo Seufer <ths@mips.com>
170
171 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
172
022fac6d
TS
1732006-05-02 Thiemo Seufer <ths@mips.com>
174 Nigel Stephens <nigel@mips.com>
175 David Ung <davidu@mips.com>
176
177 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
178 (print_mips16_insn_arg): Force mips16 to odd addresses.
179
9bcd4f99
TS
1802006-04-30 Thiemo Seufer <ths@mips.com>
181 David Ung <davidu@mips.com>
182
183 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
184 "udi0" to "udi15".
185 * mips-dis.c (print_insn_args): Adds udi argument handling.
186
f095b97b
JW
1872006-04-28 James E Wilson <wilson@specifix.com>
188
189 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
190 error message.
191
59c455b3
TS
1922006-04-28 Thiemo Seufer <ths@mips.com>
193 David Ung <davidu@mips.com>
bdb09db1 194 Nigel Stephens <nigel@mips.com>
59c455b3
TS
195
196 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
197 names.
198
cc0ca239 1992006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 200 Nigel Stephens <nigel@mips.com>
cc0ca239
TS
201 David Ung <davidu@mips.com>
202
203 * mips-dis.c (print_insn_args): Add mips_opcode argument.
204 (print_insn_mips): Adjust print_insn_args call.
205
0d09bfe6 2062006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 207 Nigel Stephens <nigel@mips.com>
0d09bfe6
TS
208
209 * mips-dis.c (print_insn_args): Print $fcc only for FP
210 instructions, use $cc elsewise.
211
654c225a 2122006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 213 Nigel Stephens <nigel@mips.com>
654c225a
TS
214
215 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
216 Map MIPS16 registers to O32 names.
217 (print_mips16_insn_arg): Use mips16_reg_names.
218
0dbde4cf
JB
2192006-04-26 Julian Brown <julian@codesourcery.com>
220
221 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
222 VMOV.
223
16980d0b
JB
2242006-04-26 Nathan Sidwell <nathan@codesourcery.com>
225 Julian Brown <julian@codesourcery.com>
226
227 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
228 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
229 Add unified load/store instruction names.
230 (neon_opcode_table): New.
231 (arm_opcodes): Expand meaning of %<bitfield>['`?].
232 (arm_decode_bitfield): New.
233 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
234 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
235 (print_insn_neon): New.
236 (print_insn_arm): Adjust print_insn_coprocessor call. Call
237 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
238 (print_insn_thumb32): Likewise.
239
ec3fcc56
AM
2402006-04-19 Alan Modra <amodra@bigpond.net.au>
241
242 * Makefile.am: Run "make dep-am".
243 * Makefile.in: Regenerate.
244
241a6c40
AM
2452006-04-19 Alan Modra <amodra@bigpond.net.au>
246
7c6646cd
AM
247 * avr-dis.c (avr_operand): Warning fix.
248
241a6c40
AM
249 * configure: Regenerate.
250
e7403566
DJ
2512006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
252
253 * po/POTFILES.in: Regenerated.
254
52f16a0e
NC
2552006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
256
257 PR binutils/2454
258 * avr-dis.c (avr_operand): Arrange for a comment to appear before
259 the symolic form of an address, so that the output of objdump -d
260 can be reassembled.
261
e78efa90
DD
2622006-04-10 DJ Delorie <dj@redhat.com>
263
264 * m32c-asm.c: Regenerate.
265
108a6f8e
CD
2662006-04-06 Carlos O'Donell <carlos@codesourcery.com>
267
268 * Makefile.am: Add install-html target.
269 * Makefile.in: Regenerate.
270
a135cb2c
NC
2712006-04-06 Nick Clifton <nickc@redhat.com>
272
273 * po/vi/po: Updated Vietnamese translation.
274
47426b41
AM
2752006-03-31 Paul Koning <ni1d@arrl.net>
276
277 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
278
331f1cbe
BS
2792006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
280
281 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
282 logic to identify halfword shifts.
283
c16d2bf0
PB
2842006-03-16 Paul Brook <paul@codesourcery.com>
285
286 * arm-dis.c (arm_opcodes): Rename swi to svc.
287 (thumb_opcodes): Ditto.
288
5348b81e
DD
2892006-03-13 DJ Delorie <dj@redhat.com>
290
5398310a
DD
291 * m32c-asm.c: Regenerate.
292 * m32c-desc.c: Likewise.
293 * m32c-desc.h: Likewise.
294 * m32c-dis.c: Likewise.
295 * m32c-ibld.c: Likewise.
5348b81e
DD
296 * m32c-opc.c: Likewise.
297 * m32c-opc.h: Likewise.
298
253d272c
DD
2992006-03-10 DJ Delorie <dj@redhat.com>
300
301 * m32c-desc.c: Regenerate with mul.l, mulu.l.
302 * m32c-opc.c: Likewise.
303 * m32c-opc.h: Likewise.
304
305
f530741d
NC
3062006-03-09 Nick Clifton <nickc@redhat.com>
307
308 * po/sv.po: Updated Swedish translation.
309
35c52694
L
3102006-03-07 H.J. Lu <hongjiu.lu@intel.com>
311
312 PR binutils/2428
313 * i386-dis.c (REP_Fixup): New function.
314 (AL): Remove duplicate.
315 (Xbr): New.
316 (Xvr): Likewise.
317 (Ybr): Likewise.
318 (Yvr): Likewise.
319 (indirDXr): Likewise.
320 (ALr): Likewise.
321 (eAXr): Likewise.
322 (dis386): Updated entries of ins, outs, movs, lods and stos.
323
ed963e2d
NC
3242006-03-05 Nick Clifton <nickc@redhat.com>
325
326 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
327 signed 32-bit value into an unsigned 32-bit field when the host is
328 a 64-bit machine.
329 * fr30-ibld.c: Regenerate.
330 * frv-ibld.c: Regenerate.
331 * ip2k-ibld.c: Regenerate.
332 * iq2000-asm.c: Regenerate.
333 * iq2000-ibld.c: Regenerate.
334 * m32c-ibld.c: Regenerate.
335 * m32r-ibld.c: Regenerate.
336 * openrisc-ibld.c: Regenerate.
337 * xc16x-ibld.c: Regenerate.
338 * xstormy16-ibld.c: Regenerate.
339
c7d41dc5
NC
3402006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
341
342 * xc16x-asm.c: Regenerate.
343 * xc16x-dis.c: Regenerate.
c7d41dc5 344
f7d9e5c3
CD
3452006-02-27 Carlos O'Donell <carlos@codesourcery.com>
346
347 * po/Make-in: Add html target.
348
331d2d0d
L
3492006-02-27 H.J. Lu <hongjiu.lu@intel.com>
350
351 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
352 Intel Merom New Instructions.
353 (THREE_BYTE_0): Likewise.
354 (THREE_BYTE_1): Likewise.
355 (three_byte_table): Likewise.
356 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
357 THREE_BYTE_1 for entry 0x3a.
358 (twobyte_has_modrm): Updated.
359 (twobyte_uses_SSE_prefix): Likewise.
360 (print_insn): Handle 3-byte opcodes used by Intel Merom New
361 Instructions.
362
ff3f9d5b
DM
3632006-02-24 David S. Miller <davem@sunset.davemloft.net>
364
365 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
366 (v9_hpriv_reg_names): New table.
367 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
368 New cases '$' and '%' for read/write hyperprivileged register.
369 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
370 window handling and rdhpr/wrhpr instructions.
371
6772dd07
DD
3722006-02-24 DJ Delorie <dj@redhat.com>
373
374 * m32c-desc.c: Regenerate with linker relaxation attributes.
375 * m32c-desc.h: Likewise.
376 * m32c-dis.c: Likewise.
377 * m32c-opc.c: Likewise.
378
62b3e311
PB
3792006-02-24 Paul Brook <paul@codesourcery.com>
380
381 * arm-dis.c (arm_opcodes): Add V7 instructions.
382 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
383 (print_arm_address): New function.
384 (print_insn_arm): Use it. Add 'P' and 'U' cases.
385 (psr_name): New function.
386 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
387
59cf82fe
L
3882006-02-23 H.J. Lu <hongjiu.lu@intel.com>
389
390 * ia64-opc-i.c (bXc): New.
391 (mXc): Likewise.
392 (OpX2TaTbYaXcC): Likewise.
393 (TF). Likewise.
394 (TFCM). Likewise.
395 (ia64_opcodes_i): Add instructions for tf.
396
397 * ia64-opc.h (IMMU5b): New.
398
399 * ia64-asmtab.c: Regenerated.
400
19a7219f
L
4012006-02-23 H.J. Lu <hongjiu.lu@intel.com>
402
403 * ia64-gen.c: Update copyright years.
404 * ia64-opc-b.c: Likewise.
405
7f3dfb9c
L
4062006-02-22 H.J. Lu <hongjiu.lu@intel.com>
407
408 * ia64-gen.c (lookup_regindex): Handle ".vm".
409 (print_dependency_table): Handle '\"'.
410
411 * ia64-ic.tbl: Updated from SDM 2.2.
412 * ia64-raw.tbl: Likewise.
413 * ia64-waw.tbl: Likewise.
414 * ia64-asmtab.c: Regenerated.
415
416 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
417
d70c5fc7
NC
4182006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
419 Anil Paranjape <anilp1@kpitcummins.com>
420 Shilin Shakti <shilins@kpitcummins.com>
421
422 * xc16x-desc.h: New file
423 * xc16x-desc.c: New file
424 * xc16x-opc.h: New file
425 * xc16x-opc.c: New file
426 * xc16x-ibld.c: New file
427 * xc16x-asm.c: New file
428 * xc16x-dis.c: New file
429 * Makefile.am: Entries for xc16x
430 * Makefile.in: Regenerate
431 * cofigure.in: Add xc16x target information.
432 * configure: Regenerate.
433 * disassemble.c: Add xc16x target information.
434
a1cfb73e
L
4352006-02-11 H.J. Lu <hongjiu.lu@intel.com>
436
437 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
438 moves.
439
6dd5059a
L
4402006-02-11 H.J. Lu <hongjiu.lu@intel.com>
441
442 * i386-dis.c ('Z'): Add a new macro.
443 (dis386_twobyte): Use "movZ" for control register moves.
444
8536c657
NC
4452006-02-10 Nick Clifton <nickc@redhat.com>
446
447 * iq2000-asm.c: Regenerate.
448
266abb8f
NS
4492006-02-07 Nathan Sidwell <nathan@codesourcery.com>
450
451 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
452
f1a64f49
DU
4532006-01-26 David Ung <davidu@mips.com>
454
455 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
456 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
457 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
458 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
459 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
460
9e919b5f
AM
4612006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
462
463 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
464 ld_d_r, pref_xd_cb): Use signed char to hold data to be
465 disassembled.
466 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
467 buffer overflows when disassembling instructions like
468 ld (ix+123),0x23
469 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
470 operand, if the offset is negative.
471
c9021189
AM
4722006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
473
474 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
475 unsigned char to hold data to be disassembled.
476
d99b6465
AS
4772006-01-17 Andreas Schwab <schwab@suse.de>
478
479 PR binutils/1486
480 * disassemble.c (disassemble_init_for_target): Set
481 disassembler_needs_relocs for bfd_arch_arm.
482
c2fe9327
PB
4832006-01-16 Paul Brook <paul@codesourcery.com>
484
e88d958a 485 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327
PB
486 f?add?, and f?sub? instructions.
487
32fba81d
NC
4882006-01-16 Nick Clifton <nickc@redhat.com>
489
490 * po/zh_CN.po: New Chinese (simplified) translation.
491 * configure.in (ALL_LINGUAS): Add "zh_CH".
492 * configure: Regenerate.
493
1b3a26b5
PB
4942006-01-05 Paul Brook <paul@codesourcery.com>
495
496 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
497
db313fa6
DD
4982006-01-06 DJ Delorie <dj@redhat.com>
499
500 * m32c-desc.c: Regenerate.
501 * m32c-opc.c: Regenerate.
502 * m32c-opc.h: Regenerate.
503
54d46aca
DD
5042006-01-03 DJ Delorie <dj@redhat.com>
505
506 * cgen-ibld.in (extract_normal): Avoid memory range errors.
507 * m32c-ibld.c: Regenerated.
508
e88d958a 509For older changes see ChangeLog-2005
252b5132
RH
510\f
511Local Variables:
2f6d2f85
NC
512mode: change-log
513left-margin: 8
514fill-column: 74
252b5132
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515version-control: never
516End:
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