[deliverable/binutils-gdb.git] / opcodes / ChangeLog

2015-06-19  Peter Bergner  <bergner@vnet.ibm.com>

        * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	* ppc-opc.c (FXM4): Add non-zero optional value.
	(TBR): Likewise.
	(SXL): Likewise.
	(insert_fxm): Handle new default operand value.
	(extract_fxm): Likewise.
	(insert_tbr): Likewise.
	(extract_tbr): Likewise.

2015-06-16  Matthew Wahab  <matthew.wahab@arm.com>

	* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".

2015-06-16  Szabolcs Nagy  <szabolcs.nagy@arm.com>

	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.

2015-06-12  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c: Add comment accidentally removed by old commit.
	(MTMSRD_L): Delete.

2015-06-04  Nick Clifton  <nickc@redhat.com>

	PR 18474
	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (arm_opcodes): Add "setpan".
	(thumb_opcodes): Add "setpan".

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	macros.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_rdma): New.
	(RDMA): New.
	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-02  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-tbl.h (aarch64_feature_lor): New.
	(LOR): New.
	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	"stllrb", "stllrh".
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Regenerate.
	* aarch64-opc-2.c: Regenerate.

2015-06-01  Matthew Wahab  <matthew.wahab@arm.com>

	* aarch64-opc.c (F_ARCHEXT): New.
	(aarch64_sys_regs): Add "pan".
	(aarch64_sys_reg_supported_p): New.
	(aarch64_pstatefields): Add "pan".
	(aarch64_pstatefield_supported_p): New.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-tbl.h: Regenerate.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (print_insn): Swap rounding mode specifier and
	general purpose register in Intel mode.

2015-06-01  Jan Beulich  <jbeulich@suse.com>

	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	* i386-tbl.h: Regenerate.

2015-05-18  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	* i386-init.h: Regenerated.

2015-05-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c: Add comments for '@'.
	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	(enum x86_64_isa): New.
	(isa64): Likewise.
	(print_i386_disassembler_options): Add amd64 and intel64.
	(print_insn): Handle amd64 and intel64.
	(putop): Handle '@'.
	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	* i386-opc.h (AMD64): New.
	(CpuIntel64): Likewise.
	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	* i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
	Mark direct call/jmp without Disp16|Disp32 as Intel64.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.

2015-05-14  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (IH) New define.
	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	<tlbie>: Add RS operand for POWER7.
	<slbia>: Add IH operand for POWER6.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
	direct branch.
	(jmp): Likewise.
	* i386-tbl.h: Regenerated.

2015-05-11  H.J. Lu  <hongjiu.lu@intel.com>

	* configure.ac: Support bfd_iamcu_arch.
	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	CPU_IAMCU_COMPAT_FLAGS.
	(cpu_flags): Add CpuIAMCU.
	* i386-opc.h (CpuIAMCU): New.
	(i386_cpu_flags): Add cpuiamcu.
	* configure: Regenerated.
	* i386-init.h: Likewise.
	* i386-tbl.h: Likewise.

2015-05-08  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutis/18386
	* i386-dis.c (X86_64_E8): New.
	(X86_64_E9): Likewise.
	Update comments on 'T', 'U', 'V'.  Add comments for '^'.
	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	(mod_table): Replace {T|} with ^ on Jcall/Jmp.
	(putop): Handle '^'.
	(OP_J): Ignore the operand size prefix in 64-bit.  Don't check
	REX_W.

2015-04-30  DJ Delorie  <dj@redhat.com>

	* disassemble.c (disassembler): Choose suitable disassembler based
	on E_ABI.
	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter.  Use
	it to decode mul/div insns.
	* rl78-decode.c: Regenerate.
	* rl78-dis.c (print_insn_rl78): Rename to...
	(print_insn_rl78_common): ...this, take ISA parameter.
	(print_insn_rl78): New.
	(print_insn_rl78_g10): New.
	(print_insn_rl78_g13): New.
	(print_insn_rl78_g14): New.
	(rl78_get_disassembler): New.

2015-04-29  Nick Clifton  <nickc@redhat.com>

	* po/fr.po: Updated French translation.

2015-04-27  Peter Bergner  <bergner@vnet.ibm.com>

	* ppc-opc.c (DCBT_EO): New define.
	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	<lharx>: Likewise.
	<stbcx.>: Likewise.
	<sthcx.>: Likewise.
	<waitrsv>: Do not enable for POWER7 and later.
	<waitimpl>: Likewise.
	<dcbt>: Default to the two operand form of the instruction for all
	"old" cpus.  For "new" cpus, use the operand ordering that matches
	whether the cpu is server or embedded.
	<dcbtst>: Likewise.

2015-04-27  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: New instruction type VV0UU2.
	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	and WFC.

2015-04-23  Jan Beulich  <jbeulich@suse.com>

	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	(vfpclasspd, vfpclassps): Add %XZ.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	(PREFIX_UD_REPZ): Likewise.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (prefix_requirement): Removed.
	(print_insn): Don't set prefix_requirement.  Check
	dp->prefix_requirement instead of prefix_requirement.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	PR binutils/17898
	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	(PREFIX_MOD_0_0FC7_REG_6): This.
	(PREFIX_MOD_3_0FC7_REG_6): New.
	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Add PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.
	(mod_table): Replace PREFIX_0FC7_REG_6 with
	PREFIX_MOD_0_0FC7_REG_6.  Use PREFIX_MOD_3_0FC7_REG_6 and
	PREFIX_MOD_3_0FC7_REG_7.

2015-04-15  H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	(PREFIX_MANDATORY_REPNZ): Likewise.
	(PREFIX_MANDATORY_DATA): Likewise.
	(PREFIX_MANDATORY_ADDR): Likewise.
	(PREFIX_MANDATORY_LOCK): Likewise.
	(PREFIX_MANDATORY): Likewise.
	(PREFIX_UD_SHIFT): Set to 8
	(PREFIX_UD_REPZ): Updated.
	(PREFIX_UD_REPNZ): Likewise.
	(PREFIX_UD_DATA): Likewise.
	(PREFIX_UD_ADDR): Likewise.
	(PREFIX_UD_LOCK): Likewise.
	(PREFIX_IGNORED_SHIFT): New.
	(PREFIX_IGNORED_REPZ): Likewise.
	(PREFIX_IGNORED_REPNZ): Likewise.
	(PREFIX_IGNORED_DATA): Likewise.
	(PREFIX_IGNORED_ADDR): Likewise.
	(PREFIX_IGNORED_LOCK): Likewise.
	(PREFIX_OPCODE): Likewise.
	(PREFIX_IGNORED): Likewise.
	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	(three_byte_table): Likewise.
	(mod_table): Likewise.
	(mandatory_prefix): Renamed to ...
	(prefix_requirement): This.
	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	Update PREFIX_90 entry.
	(get_valid_dis386): Check prefix_requirement to see if a prefix
	should be ignored.
	(print_insn): Replace mandatory_prefix with prefix_requirement.

2015-04-15  Renlin Li  <renlin.li@arm.com>

	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	use it for ssat and ssat16.
	(print_insn_thumb32): Add handle case for 'D' control code.

2015-04-06  Ilya Tocar  <ilya.tocar@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>

	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	Fill prefix_requirement field.
	(struct dis386): Add prefix_requirement field.
	(dis386): Fill prefix_requirement field.
	(dis386_twobyte): Ditto.
	(twobyte_has_mandatory_prefix_: Remove.
	(reg_table): Fill prefix_requirement field.
	(prefix_table): Ditto.
	(x86_64_table): Ditto.
	(three_byte_table): Ditto.
	(xop_table): Ditto.
	(vex_table): Ditto.
	(vex_len_table): Ditto.
	(vex_w_table): Ditto.
	(mod_table): Ditto.
	(bad_opcode): Ditto.
	(print_insn): Use prefix_requirement.
	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	(float_reg): Ditto.

2015-03-30  Mike Frysinger  <vapier@gentoo.org>

	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.

2015-03-29  H.J. Lu  <hongjiu.lu@intel.com>

	* Makefile.in: Regenerated.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	powerpc_opcd_indices and vle_opcd_indices once.

2015-03-25  Anton Blanchard  <anton@samba.org>

	* ppc-opc.c (powerpc_opcodes): Add slbfee.

2015-03-24  Terry Guo  <terry.guo@arm.com>

	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	(opcode16): Likewise.
	(coprocessor_opcodes): Replace bit with feature struct.
	(neon_opcodes): Likewise.
	(arm_opcodes): Likewise.
	(thumb_opcodes): Likewise.
	(thumb32_opcodes): Likewise.
	(print_insn_coprocessor): Likewise.
	(print_insn_arm): Likewise.
	(select_arm_features): Follow new feature struct.

2015-03-17  Ganesh Gopalasubramanian  <Ganesh.Gopalasubramanian@amd.com>

	* i386-dis.c (rm_table): Add clzero.
	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	Add CPU_CLZERO_FLAGS.
	(cpu_flags): Add CpuCLZERO.
	* i386-opc.h: Add CpuCLZERO.
	* i386-opc.tbl: Add clzero.
	* i386-init.h: Re-generated.
	* i386-tbl.h: Re-generated.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (decode_mips_operand): Fix constraint issues
	with u and y operands.

2015-03-13  Andrew Bennett  <andrew.bennett@imgtec.com>

	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.

2015-03-10  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-opc.c: Add new IBM z13 instructions.
	* s390-opc.txt: Likewise.

2015-03-10  Renlin Li  <renlin.li@arm.com>

	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	related alias.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis-2.c: Likewise.
	* aarch64-opc-2.c: Likewise.

2015-03-03  Jiong Wang  <jiong.wang@arm.com>

	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.

2015-02-25  Oleg Endo  <olegendo@gcc.gnu.org>

	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	arch_sh_up.
	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.

2015-02-23  Vinay  <Vinay.G@kpit.com>

	* rl78-decode.opc (MOV): Added space between two operands for
	'mov' instruction in index addressing mode.
	* rl78-decode.c: Regenerate.

2015-02-19  Pedro Alves  <palves@redhat.com>

	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".

2015-02-10  Pedro Alves  <palves@redhat.com>
	    Tom Tromey  <tromey@redhat.com>

	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	microblaze_and, microblaze_xor.
	* microblaze-opc.h (opcodes): Adjust.

2015-01-28  James Bowman  <james.bowman@ftdichip.com>

	* Makefile.am: Add FT32 files.
	* configure.ac: Handle FT32.
	* disassemble.c (disassembler): Call print_insn_ft32.
	* ft32-dis.c: New file.
	* ft32-opc.c: New file.
	* Makefile.in: Regenerate.
	* configure: Regenerate.
	* po/POTFILES.in: Regenerate.

2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>

	* nds32-asm.c (keyword_sr): Add new system registers.

2015-01-16  Andreas Krebbel  <krebbel@linux.vnet.ibm.com>

	* s390-dis.c (s390_extract_operand): Support vector register
	operands.
	(s390_print_insn_with_opcode): Support new operands types and add
	new handling of optional operands.
	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	and include opcode/s390.h instead.
	(struct op_struct): New field `flags'.
	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	(dumpTable): Dump flags.
	(main): Parse flags from the s390-opc.txt file.  Add z13 as cpu
	string.
	* s390-opc.c: Add new operands types, instruction formats, and
	instruction masks.
	(s390_opformats): Add new formats for .insn.
	* s390-opc.txt: Add new instructions.

2015-01-01  Alan Modra  <amodra@gmail.com>

	Update year range in copyright notice of all files.

For older changes see ChangeLog-2014
\f
Copyright (C) 2015 Free Software Foundation, Inc.

Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved.

Local Variables:
mode: change-log
left-margin: 8
fill-column: 74
version-control: never
End:
Commit	Line	Data
11a0cf2e PB	1	2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
	2
	3	* ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
	4	* ppc-opc.c (FXM4): Add non-zero optional value.
	5	(TBR): Likewise.
	6	(SXL): Likewise.
	7	(insert_fxm): Handle new default operand value.
	8	(extract_fxm): Likewise.
	9	(insert_tbr): Likewise.
	10	(extract_tbr): Likewise.
	11
bdfa8b95 MW	12	2015-06-16 Matthew Wahab <matthew.wahab@arm.com>
	13
	14	* arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
	15
24b4cf66 SN	16	2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
	17
	18	* arm-dis.c (print_insn_coprocessor): Avoid negative shift.
	19
99a2c561 PB	20	2015-06-12 Peter Bergner <bergner@vnet.ibm.com>
	21
	22	* ppc-opc.c: Add comment accidentally removed by old commit.
	23	(MTMSRD_L): Delete.
	24
13be46a2 NC	25	2015-06-04 Nick Clifton <nickc@redhat.com>
	26
	27	PR 18474
	28	* msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
	29
ddfded2f MW	30	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	31
	32	* arm-dis.c (arm_opcodes): Add "setpan".
	33	(thumb_opcodes): Add "setpan".
	34
1af1dd51 MW	35	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	36
	37	* arm-dis.c (select_arm_features): Rework to avoid used of redefined
	38	macros.
	39
9e1f0fa7 MW	40	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	41
	42	* aarch64-tbl.h (aarch64_feature_rdma): New.
	43	(RDMA): New.
	44	(aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
	45	* aarch64-asm-2.c: Regenerate.
	46	* aarch64-dis-2.c: Regenerate.
	47	* aarch64-opc-2.c: Regenerate.
	48
290806fd MW	49	2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
	50
	51	* aarch64-tbl.h (aarch64_feature_lor): New.
	52	(LOR): New.
	53	(aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
	54	"stllrb", "stllrh".
	55	* aarch64-asm-2.c: Regenerate.
	56	* aarch64-dis-2.c: Regenerate.
	57	* aarch64-opc-2.c: Regenerate.
	58
f21cce2c MW	59	2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
	60
	61	* aarch64-opc.c (F_ARCHEXT): New.
	62	(aarch64_sys_regs): Add "pan".
	63	(aarch64_sys_reg_supported_p): New.
	64	(aarch64_pstatefields): Add "pan".
	65	(aarch64_pstatefield_supported_p): New.
	66
d194d186 JB	67	2015-06-01 Jan Beulich <jbeulich@suse.com>
	68
	69	* i386-tbl.h: Regenerate.
	70
3a8547d2 JB	71	2015-06-01 Jan Beulich <jbeulich@suse.com>
	72
	73	* i386-dis.c (print_insn): Swap rounding mode specifier and
	74	general purpose register in Intel mode.
	75
015c54d5 JB	76	2015-06-01 Jan Beulich <jbeulich@suse.com>
	77
	78	* i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
	79	* i386-tbl.h: Regenerate.
	80
071f0063 L	81	2015-05-18 H.J. Lu <hongjiu.lu@intel.com>
	82
	83	* i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
	84	* i386-init.h: Regenerated.
	85
5db04b09 L	86	2015-05-15 H.J. Lu <hongjiu.lu@intel.com>
	87
	88	PR binutis/18386
	89	* i386-dis.c: Add comments for '@'.
	90	(x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
	91	(enum x86_64_isa): New.
	92	(isa64): Likewise.
	93	(print_i386_disassembler_options): Add amd64 and intel64.
	94	(print_insn): Handle amd64 and intel64.
	95	(putop): Handle '@'.
	96	(OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
	97	* i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
	98	* i386-opc.h (AMD64): New.
	99	(CpuIntel64): Likewise.
	100	(i386_cpu_flags): Add cpuamd64 and cpuintel64.
	101	* i386-opc.tbl: Add direct call/jmp with Disp16\|Disp32 for AMD64.
	102	Mark direct call/jmp without Disp16\|Disp32 as Intel64.
	103	* i386-init.h: Regenerated.
	104	* i386-tbl.h: Likewise.
	105
4bc0608a PB	106	2015-05-14 Peter Bergner <bergner@vnet.ibm.com>
	107
	108	* ppc-opc.c (IH) New define.
	109	(powerpc_opcodes) <wait>: Do not enable for POWER7.
	110	<tlbie>: Add RS operand for POWER7.
	111	<slbia>: Add IH operand for POWER6.
	112
70cead07 L	113	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	114
	115	* opcodes/i386-opc.tbl (call): Remove Disp16\|Disp32 from 64-bit
	116	direct branch.
	117	(jmp): Likewise.
	118	* i386-tbl.h: Regenerated.
	119
7b6d09fb L	120	2015-05-11 H.J. Lu <hongjiu.lu@intel.com>
	121
	122	* configure.ac: Support bfd_iamcu_arch.
	123	* disassemble.c (disassembler): Support bfd_iamcu_arch.
	124	* i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
	125	CPU_IAMCU_COMPAT_FLAGS.
	126	(cpu_flags): Add CpuIAMCU.
	127	* i386-opc.h (CpuIAMCU): New.
	128	(i386_cpu_flags): Add cpuiamcu.
	129	* configure: Regenerated.
	130	* i386-init.h: Likewise.
	131	* i386-tbl.h: Likewise.
	132
31955f99 L	133	2015-05-08 H.J. Lu <hongjiu.lu@intel.com>
	134
	135	PR binutis/18386
	136	* i386-dis.c (X86_64_E8): New.
	137	(X86_64_E9): Likewise.
	138	Update comments on 'T', 'U', 'V'. Add comments for '^'.
	139	(dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
	140	(x86_64_table): Add X86_64_E8 and X86_64_E9.
	141	(mod_table): Replace {T\|} with ^ on Jcall/Jmp.
	142	(putop): Handle '^'.
	143	(OP_J): Ignore the operand size prefix in 64-bit. Don't check
	144	REX_W.
	145
0952813b DD	146	2015-04-30 DJ Delorie <dj@redhat.com>
	147
	148	* disassemble.c (disassembler): Choose suitable disassembler based
	149	on E_ABI.
	150	* rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
	151	it to decode mul/div insns.
	152	* rl78-decode.c: Regenerate.
	153	* rl78-dis.c (print_insn_rl78): Rename to...
	154	(print_insn_rl78_common): ...this, take ISA parameter.
	155	(print_insn_rl78): New.
	156	(print_insn_rl78_g10): New.
	157	(print_insn_rl78_g13): New.
	158	(print_insn_rl78_g14): New.
	159	(rl78_get_disassembler): New.
	160
f9d3ecaa NC	161	2015-04-29 Nick Clifton <nickc@redhat.com>
	162
	163	* po/fr.po: Updated French translation.
	164
4fff86c5 PB	165	2015-04-27 Peter Bergner <bergner@vnet.ibm.com>
	166
	167	* ppc-opc.c (DCBT_EO): New define.
	168	(powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
	169	<lharx>: Likewise.
	170	<stbcx.>: Likewise.
	171	<sthcx.>: Likewise.
	172	<waitrsv>: Do not enable for POWER7 and later.
	173	<waitimpl>: Likewise.
	174	<dcbt>: Default to the two operand form of the instruction for all
	175	"old" cpus. For "new" cpus, use the operand ordering that matches
	176	whether the cpu is server or embedded.
	177	<dcbtst>: Likewise.
	178
3b78cfe1 AK	179	2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	180
	181	* s390-opc.c: New instruction type VV0UU2.
	182	* s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
	183	and WFC.
	184
04d824a4 JB	185	2015-04-23 Jan Beulich <jbeulich@suse.com>
	186
	187	* i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
	188	* i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
	189	vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
	190	(vfpclasspd, vfpclassps): Add %XZ.
	191
09708981 L	192	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	193
	194	* i386-dis.c (PREFIX_UD_SHIFT): Removed.
	195	(PREFIX_UD_REPZ): Likewise.
	196	(PREFIX_UD_REPNZ): Likewise.
	197	(PREFIX_UD_DATA): Likewise.
	198	(PREFIX_UD_ADDR): Likewise.
	199	(PREFIX_UD_LOCK): Likewise.
	200
3888916d L	201	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	202
	203	* i386-dis.c (prefix_requirement): Removed.
	204	(print_insn): Don't set prefix_requirement. Check
	205	dp->prefix_requirement instead of prefix_requirement.
	206
f24bcbaa L	207	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	208
	209	PR binutils/17898
	210	* i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
	211	(PREFIX_MOD_0_0FC7_REG_6): This.
	212	(PREFIX_MOD_3_0FC7_REG_6): New.
	213	(PREFIX_MOD_3_0FC7_REG_7): Likewise.
	214	(prefix_table): Replace PREFIX_0FC7_REG_6 with
	215	PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
	216	PREFIX_MOD_3_0FC7_REG_7.
	217	(mod_table): Replace PREFIX_0FC7_REG_6 with
	218	PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
	219	PREFIX_MOD_3_0FC7_REG_7.
	220
507bd325 L	221	2015-04-15 H.J. Lu <hongjiu.lu@intel.com>
	222
	223	* i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
	224	(PREFIX_MANDATORY_REPNZ): Likewise.
	225	(PREFIX_MANDATORY_DATA): Likewise.
	226	(PREFIX_MANDATORY_ADDR): Likewise.
	227	(PREFIX_MANDATORY_LOCK): Likewise.
	228	(PREFIX_MANDATORY): Likewise.
	229	(PREFIX_UD_SHIFT): Set to 8
	230	(PREFIX_UD_REPZ): Updated.
	231	(PREFIX_UD_REPNZ): Likewise.
	232	(PREFIX_UD_DATA): Likewise.
	233	(PREFIX_UD_ADDR): Likewise.
	234	(PREFIX_UD_LOCK): Likewise.
	235	(PREFIX_IGNORED_SHIFT): New.
	236	(PREFIX_IGNORED_REPZ): Likewise.
	237	(PREFIX_IGNORED_REPNZ): Likewise.
	238	(PREFIX_IGNORED_DATA): Likewise.
	239	(PREFIX_IGNORED_ADDR): Likewise.
	240	(PREFIX_IGNORED_LOCK): Likewise.
	241	(PREFIX_OPCODE): Likewise.
	242	(PREFIX_IGNORED): Likewise.
	243	(Bad_Opcode): Replace PREFIX_MANDATORY with 0.
	244	(dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	245	(three_byte_table): Likewise.
	246	(mod_table): Likewise.
	247	(mandatory_prefix): Renamed to ...
	248	(prefix_requirement): This.
	249	(prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
	250	Update PREFIX_90 entry.
	251	(get_valid_dis386): Check prefix_requirement to see if a prefix
	252	should be ignored.
	253	(print_insn): Replace mandatory_prefix with prefix_requirement.
	254
f0fba320 RL	255	2015-04-15 Renlin Li <renlin.li@arm.com>
	256
	257	* arm-dis.c (thumb32_opcodes): Define 'D' format control code,
	258	use it for ssat and ssat16.
	259	(print_insn_thumb32): Add handle case for 'D' control code.
	260
bf890a93 IT	261	2015-04-06 Ilya Tocar <ilya.tocar@intel.com>
	262	H.J. Lu <hongjiu.lu@intel.com>
	263
	264	* i386-dis-evex.h (evex_table): Fill prefix_requirement field.
	265	* i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
	266	PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
	267	PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
	268	PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
	269	(Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
	270	Fill prefix_requirement field.
	271	(struct dis386): Add prefix_requirement field.
	272	(dis386): Fill prefix_requirement field.
	273	(dis386_twobyte): Ditto.
	274	(twobyte_has_mandatory_prefix_: Remove.
	275	(reg_table): Fill prefix_requirement field.
	276	(prefix_table): Ditto.
	277	(x86_64_table): Ditto.
	278	(three_byte_table): Ditto.
	279	(xop_table): Ditto.
	280	(vex_table): Ditto.
	281	(vex_len_table): Ditto.
	282	(vex_w_table): Ditto.
	283	(mod_table): Ditto.
	284	(bad_opcode): Ditto.
	285	(print_insn): Use prefix_requirement.
	286	(FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
	287	FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
	288	(float_reg): Ditto.
	289
2f783c1f MF	290	2015-03-30 Mike Frysinger <vapier@gentoo.org>
	291
	292	* d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
	293
b9d94d62 L	294	2015-03-29 H.J. Lu <hongjiu.lu@intel.com>
	295
	296	* Makefile.in: Regenerated.
	297
27c49e9a AB	298	2015-03-25 Anton Blanchard <anton@samba.org>
	299
	300	* ppc-dis.c (disassemble_init_powerpc): Only initialise
	301	powerpc_opcd_indices and vle_opcd_indices once.
	302
c4e676f1 AB	303	2015-03-25 Anton Blanchard <anton@samba.org>
	304
	305	* ppc-opc.c (powerpc_opcodes): Add slbfee.
	306
823d2571 TG	307	2015-03-24 Terry Guo <terry.guo@arm.com>
	308
	309	* arm-dis.c (opcode32): Updated to use new arm feature struct.
	310	(opcode16): Likewise.
	311	(coprocessor_opcodes): Replace bit with feature struct.
	312	(neon_opcodes): Likewise.
	313	(arm_opcodes): Likewise.
	314	(thumb_opcodes): Likewise.
	315	(thumb32_opcodes): Likewise.
	316	(print_insn_coprocessor): Likewise.
	317	(print_insn_arm): Likewise.
	318	(select_arm_features): Follow new feature struct.
	319
029f3522 GG	320	2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
	321
	322	* i386-dis.c (rm_table): Add clzero.
	323	* i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
	324	Add CPU_CLZERO_FLAGS.
	325	(cpu_flags): Add CpuCLZERO.
	326	* i386-opc.h: Add CpuCLZERO.
	327	* i386-opc.tbl: Add clzero.
	328	* i386-init.h: Re-generated.
	329	* i386-tbl.h: Re-generated.
	330
6914869a AB	331	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	332
	333	* mips-opc.c (decode_mips_operand): Fix constraint issues
	334	with u and y operands.
	335
21e20815 AB	336	2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
	337
	338	* mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
	339
6b1d7593 AK	340	2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	341
	342	* s390-opc.c: Add new IBM z13 instructions.
	343	* s390-opc.txt: Likewise.
	344
c8f89a34 JW	345	2015-03-10 Renlin Li <renlin.li@arm.com>
	346
	347	* aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
	348	stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
	349	related alias.
	350	* aarch64-asm-2.c: Regenerate.
	351	* aarch64-dis-2.c: Likewise.
	352	* aarch64-opc-2.c: Likewise.
	353
d8282f0e JW	354	2015-03-03 Jiong Wang <jiong.wang@arm.com>
	355
	356	* arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
	357
ac994365 OE	358	2015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
	359
	360	* sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
	361	arch_sh_up.
	362	(pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
	363	arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
	364
fd63f640 V	365	2015-02-23 Vinay <Vinay.G@kpit.com>
	366
	367	* rl78-decode.opc (MOV): Added space between two operands for
	368	'mov' instruction in index addressing mode.
	369	* rl78-decode.c: Regenerate.
	370
f63c1776 PA	371	2015-02-19 Pedro Alves <palves@redhat.com>
	372
	373	* microblaze-dis.h [__cplusplus]: Wrap in extern "C".
	374
07774fcc PA	375	2015-02-10 Pedro Alves <palves@redhat.com>
	376	Tom Tromey <tromey@redhat.com>
	377
	378	* microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
	379	microblaze_and, microblaze_xor.
	380	* microblaze-opc.h (opcodes): Adjust.
	381
3f8107ab AM	382	2015-01-28 James Bowman <james.bowman@ftdichip.com>
	383
	384	* Makefile.am: Add FT32 files.
	385	* configure.ac: Handle FT32.
	386	* disassemble.c (disassembler): Call print_insn_ft32.
	387	* ft32-dis.c: New file.
	388	* ft32-opc.c: New file.
	389	* Makefile.in: Regenerate.
	390	* configure: Regenerate.
	391	* po/POTFILES.in: Regenerate.
	392
e5fe4957 KLC	393	2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
	394
	395	* nds32-asm.c (keyword_sr): Add new system registers.
	396
1e2e8c52 AK	397	2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
	398
	399	* s390-dis.c (s390_extract_operand): Support vector register
	400	operands.
	401	(s390_print_insn_with_opcode): Support new operands types and add
	402	new handling of optional operands.
	403	* s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
	404	and include opcode/s390.h instead.
	405	(struct op_struct): New field `flags'.
	406	(insertOpcode, insertExpandedMnemonic): New parameter `flags'.
	407	(dumpTable): Dump flags.
	408	(main): Parse flags from the s390-opc.txt file. Add z13 as cpu
	409	string.
	410	* s390-opc.c: Add new operands types, instruction formats, and
	411	instruction masks.
	412	(s390_opformats): Add new formats for .insn.
	413	* s390-opc.txt: Add new instructions.
	414
b90efa5b	415	2015-01-01 Alan Modra <amodra@gmail.com>
bffb6004	416
b90efa5b	417	Update year range in copyright notice of all files.
bffb6004	418
b90efa5b	419	For older changes see ChangeLog-2014
252b5132	420	\f
b90efa5b	421	Copyright (C) 2015 Free Software Foundation, Inc.
752937aa NC	422
	423	Copying and distribution of this file, with or without modification,
	424	are permitted in any medium without royalty provided the copyright
	425	notice and this notice are preserved.
	426
252b5132	427	Local Variables:
2f6d2f85 NC	428	mode: change-log
	429	left-margin: 8
	430	fill-column: 74
252b5132 RH	431	version-control: never
252b5132 RH	432	End: