Commit | Line | Data |
---|---|---|
25499ac7 MR |
1 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
2 | Matthew Fortune <matthew.fortune@imgtec.com> | |
3 | ||
4 | * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and | |
5 | ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. | |
6 | (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. | |
7 | (print_insn_arg) <OP_REG28>: Add handler. | |
8 | (validate_insn_args) <OP_REG28>: Handle. | |
9 | (print_mips16_insn_arg): Handle MIPS16 instructions that require | |
10 | 32-bit encoding and 9-bit immediates. | |
11 | (print_insn_mips16): Handle MIPS16 instructions that require | |
12 | 32-bit encoding and MFC0/MTC0 operand decoding. | |
13 | * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> | |
14 | <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. | |
15 | (RD_C0, WR_C0, E2, E2MT): New macros. | |
16 | (mips16_opcodes): Add entries for MIPS16e2 instructions: | |
17 | GP-relative "addiu" and its "addu" spelling, "andi", "cache", | |
18 | "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", | |
19 | "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", | |
20 | "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", | |
21 | "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" | |
22 | instructions, "swl", "swr", "sync" and its "sync_acquire", | |
23 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, | |
24 | "xori", "dmt", "dvpe", "emt" and "evpe". Add split | |
25 | regular/extended entries for original MIPS16 ISA revision | |
26 | instructions whose extended forms are subdecoded in the MIPS16e2 | |
27 | ISA revision: "li", "sll" and "srl". | |
28 | ||
fdfb4752 MR |
29 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
30 | ||
31 | * mips-dis.c (print_insn_args) <default>: Remove an MT ASE | |
32 | reference in CP0 move operand decoding. | |
33 | ||
a4f89915 MR |
34 | 2017-05-12 Maciej W. Rozycki <macro@imgtec.com> |
35 | ||
36 | * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand | |
37 | type to hexadecimal. | |
38 | (mips16_opcodes): Add operandless "break" and "sdbbp" entries. | |
39 | ||
99e2d67a MR |
40 | 2017-05-11 Maciej W. Rozycki <macro@imgtec.com> |
41 | ||
42 | * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", | |
43 | "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release", | |
44 | "sync_rmb" and "sync_wmb" as aliases. | |
45 | * micromips-opc.c (micromips_opcodes): Mark "sync_acquire", | |
46 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. | |
47 | ||
53a346d8 CZ |
48 | 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> |
49 | ||
50 | * arc-dis.c (parse_option): Update quarkse_em option.. | |
51 | * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to | |
52 | QUARKSE1. | |
53 | (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. | |
54 | ||
f91d48de KC |
55 | 2017-05-03 Kito Cheng <kito.cheng@gmail.com> |
56 | ||
57 | * riscv-dis.c (print_insn_args): Handle 'Co' operands. | |
58 | ||
43e379d7 MC |
59 | 2017-05-01 Michael Clark <michaeljclark@mac.com> |
60 | ||
61 | * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary | |
62 | register. | |
63 | ||
a4ddc54e MR |
64 | 2017-05-02 Maciej W. Rozycki <macro@imgtec.com> |
65 | ||
66 | * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps | |
67 | and branches and not synthetic data instructions. | |
68 | ||
fe50e98c BE |
69 | 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de> |
70 | ||
71 | * arm-dis.c (print_insn_thumb32): Fix value_in_comment. | |
72 | ||
126124cc CZ |
73 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
74 | ||
75 | * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. | |
76 | * arc-opc.c (insert_r13el): New function. | |
77 | (R13_EL): Define. | |
78 | * arc-tbl.h: Add new enter/leave variants. | |
79 | ||
be6a24d8 CZ |
80 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
81 | ||
82 | * arc-tbl.h: Reorder NOP entry to be before MOV instructions. | |
83 | ||
0348fd79 MR |
84 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
85 | ||
86 | * mips-dis.c (print_mips_disassembler_options): Add | |
87 | `no-aliases'. | |
88 | ||
6e3d1f07 MR |
89 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
90 | ||
91 | * mips16-opc.c (AL): New macro. | |
92 | (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms | |
93 | of "ld" and "lw" as aliases. | |
94 | ||
957f6b39 TC |
95 | 2017-04-24 Tamar Christina <tamar.christina@arm.com> |
96 | ||
97 | * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE | |
98 | arguments. | |
99 | ||
a8cc8a54 AM |
100 | 2017-04-22 Alexander Fedotov <alfedotov@gmail.com> |
101 | Alan Modra <amodra@gmail.com> | |
102 | ||
103 | * ppc-opc.c (ELEV): Define. | |
104 | (vle_opcodes): Add se_rfgi and e_sc. | |
105 | (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx | |
106 | for E200Z4. | |
107 | ||
3ab87b68 JM |
108 | 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com> |
109 | ||
110 | * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9. | |
111 | ||
792f174f NC |
112 | 2017-04-21 Nick Clifton <nickc@redhat.com> |
113 | ||
114 | PR binutils/21380 | |
115 | * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R, | |
116 | LD3R and LD4R. | |
117 | ||
42742084 AM |
118 | 2017-04-13 Alan Modra <amodra@gmail.com> |
119 | ||
120 | * epiphany-desc.c: Regenerate. | |
121 | * fr30-desc.c: Regenerate. | |
122 | * frv-desc.c: Regenerate. | |
123 | * ip2k-desc.c: Regenerate. | |
124 | * iq2000-desc.c: Regenerate. | |
125 | * lm32-desc.c: Regenerate. | |
126 | * m32c-desc.c: Regenerate. | |
127 | * m32r-desc.c: Regenerate. | |
128 | * mep-desc.c: Regenerate. | |
129 | * mt-desc.c: Regenerate. | |
130 | * or1k-desc.c: Regenerate. | |
131 | * xc16x-desc.c: Regenerate. | |
132 | * xstormy16-desc.c: Regenerate. | |
133 | ||
9a85b496 AM |
134 | 2017-04-11 Alan Modra <amodra@gmail.com> |
135 | ||
ef85eab0 | 136 | * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2, |
c03dc33b AM |
137 | PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set |
138 | PPC_OPCODE_TMR for e6500. | |
9a85b496 AM |
139 | * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. |
140 | (PPCVEC3): Define as PPC_OPCODE_POWER9. | |
9570835e AM |
141 | (PPCVSX2): Define as PPC_OPCODE_POWER8. |
142 | (PPCVSX3): Define as PPC_OPCODE_POWER9. | |
ef85eab0 | 143 | (PPCHTM): Define as PPC_OPCODE_POWER8. |
c03dc33b | 144 | (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
9a85b496 | 145 | |
62adc510 AM |
146 | 2017-04-10 Alan Modra <amodra@gmail.com> |
147 | ||
148 | * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440. | |
149 | * ppc-opc.c (MULHW): Add PPC_OPCODE_476. | |
150 | (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit | |
151 | removal of PPC_OPCODE_440 from ppc476 cpu selection bits. | |
152 | ||
aa808707 PC |
153 | 2017-04-09 Pip Cet <pipcet@gmail.com> |
154 | ||
155 | * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify | |
156 | appropriate floating-point precision directly. | |
157 | ||
ac8f0f72 AM |
158 | 2017-04-07 Alan Modra <amodra@gmail.com> |
159 | ||
160 | * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl, | |
161 | lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx, | |
162 | lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx, | |
163 | lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only | |
164 | vector instructions with E6500 not PPCVEC2. | |
165 | ||
62ecb94c PC |
166 | 2017-04-06 Pip Cet <pipcet@gmail.com> |
167 | ||
168 | * Makefile.am: Add wasm32-dis.c. | |
169 | * configure.ac: Add wasm32-dis.c to wasm32 target. | |
170 | * disassemble.c: Add wasm32 disassembler code. | |
171 | * wasm32-dis.c: New file. | |
172 | * Makefile.in: Regenerate. | |
173 | * configure: Regenerate. | |
174 | * po/POTFILES.in: Regenerate. | |
175 | * po/opcodes.pot: Regenerate. | |
176 | ||
f995bbe8 PA |
177 | 2017-04-05 Pedro Alves <palves@redhat.com> |
178 | ||
179 | * arc-dis.c (parse_option, parse_disassembler_options): Constify. | |
180 | * arm-dis.c (parse_arm_disassembler_options): Constify. | |
181 | * ppc-dis.c (powerpc_init_dialect): Constify local. | |
182 | * vax-dis.c (parse_disassembler_options): Constify. | |
183 | ||
b5292032 PD |
184 | 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> |
185 | ||
186 | * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to | |
187 | RISCV_GP_SYMBOL. | |
188 | ||
f96bd6c2 PC |
189 | 2017-03-30 Pip Cet <pipcet@gmail.com> |
190 | ||
191 | * configure.ac: Add (empty) bfd_wasm32_arch target. | |
192 | * configure: Regenerate | |
193 | * po/opcodes.pot: Regenerate. | |
194 | ||
f7c514a3 JM |
195 | 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com> |
196 | ||
197 | Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, & | |
198 | OSA2015. | |
199 | * opcodes/sparc-opc.c (asi_table): New ASIs. | |
200 | ||
52be03fd AM |
201 | 2017-03-29 Alan Modra <amodra@gmail.com> |
202 | ||
203 | * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add | |
204 | "raw" option. | |
205 | (lookup_powerpc): Don't special case -1 dialect. Handle | |
206 | PPC_OPCODE_RAW. | |
207 | (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first | |
208 | lookup_powerpc call, pass it on second. | |
209 | ||
9b753937 AM |
210 | 2017-03-27 Alan Modra <amodra@gmail.com> |
211 | ||
212 | PR 21303 | |
213 | * ppc-dis.c (struct ppc_mopt): Comment. | |
214 | (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. | |
215 | ||
c0c31e91 RZ |
216 | 2017-03-27 Rinat Zelig <rinat@mellanox.com> |
217 | ||
218 | * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. | |
219 | * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, | |
220 | F_NPS_M, F_NPS_CORE, F_NPS_ALL. | |
221 | (insert_nps_misc_imm_offset): New function. | |
222 | (extract_nps_misc imm_offset): New function. | |
223 | (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. | |
224 | (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. | |
225 | ||
2253c8f0 AK |
226 | 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
227 | ||
228 | * s390-mkopc.c (main): Remove vx2 check. | |
229 | * s390-opc.txt: Remove vx2 instruction flags. | |
230 | ||
645d3342 RZ |
231 | 2017-03-21 Rinat Zelig <rinat@mellanox.com> |
232 | ||
233 | * arc-nps400-tbl.h: Add cp32/cp16 instructions format. | |
234 | * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. | |
235 | (insert_nps_imm_offset): New function. | |
236 | (extract_nps_imm_offset): New function. | |
237 | (insert_nps_imm_entry): New function. | |
238 | (extract_nps_imm_entry): New function. | |
239 | ||
4b94dd2d AM |
240 | 2017-03-17 Alan Modra <amodra@gmail.com> |
241 | ||
242 | PR 21248 | |
243 | * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33, | |
244 | mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after | |
245 | those spr mnemonics they alias. Similarly for mtibatl, mtibatu. | |
246 | ||
b416fe87 KC |
247 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
248 | ||
249 | * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. | |
250 | <c.andi>: Likewise. | |
251 | <c.addiw> Likewise. | |
252 | ||
03b039a5 KC |
253 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
254 | ||
255 | * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode. | |
256 | ||
2c232b83 AW |
257 | 2017-03-13 Andrew Waterman <andrew@sifive.com> |
258 | ||
259 | * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. | |
260 | <srl> Likewise. | |
261 | <srai> Likewise. | |
262 | <sra> Likewise. | |
263 | ||
86fa6981 L |
264 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
265 | ||
266 | * i386-gen.c (opcode_modifiers): Replace S with Load. | |
267 | * i386-opc.h (S): Removed. | |
268 | (Load): New. | |
269 | (i386_opcode_modifier): Replace s with load. | |
270 | * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} | |
271 | and {evex}. Replace S with Load. | |
272 | * i386-tbl.h: Regenerated. | |
273 | ||
c1fe188b L |
274 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
275 | ||
276 | * i386-opc.tbl: Use CpuCET on rdsspq. | |
277 | * i386-tbl.h: Regenerated. | |
278 | ||
4b8b687e PB |
279 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
280 | ||
281 | * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; | |
282 | <vsx>: Do not use PPC_OPCODE_VSX3; | |
283 | ||
1437d063 PB |
284 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
285 | ||
286 | * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. | |
287 | ||
603555e5 L |
288 | 2017-03-06 H.J. Lu <hongjiu.lu@intel.com> |
289 | ||
290 | * i386-dis.c (REG_0F1E_MOD_3): New enum. | |
291 | (MOD_0F1E_PREFIX_1): Likewise. | |
292 | (MOD_0F38F5_PREFIX_2): Likewise. | |
293 | (MOD_0F38F6_PREFIX_0): Likewise. | |
294 | (RM_0F1E_MOD_3_REG_7): Likewise. | |
295 | (PREFIX_MOD_0_0F01_REG_5): Likewise. | |
296 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. | |
297 | (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. | |
298 | (PREFIX_0F1E): Likewise. | |
299 | (PREFIX_MOD_0_0FAE_REG_5): Likewise. | |
300 | (PREFIX_0F38F5): Likewise. | |
301 | (dis386_twobyte): Use PREFIX_0F1E. | |
302 | (reg_table): Add REG_0F1E_MOD_3. | |
303 | (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, | |
304 | PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, | |
305 | PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update | |
306 | PREFIX_0FAE_REG_6 and PREFIX_0F38F6. | |
307 | (three_byte_table): Use PREFIX_0F38F5. | |
308 | (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. | |
309 | Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. | |
310 | (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, | |
311 | RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and | |
312 | PREFIX_MOD_3_0F01_REG_5_RM_2. | |
313 | * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. | |
314 | (cpu_flags): Add CpuCET. | |
315 | * i386-opc.h (CpuCET): New enum. | |
316 | (CpuUnused): Commented out. | |
317 | (i386_cpu_flags): Add cpucet. | |
318 | * i386-opc.tbl: Add Intel CET instructions. | |
319 | * i386-init.h: Regenerated. | |
320 | * i386-tbl.h: Likewise. | |
321 | ||
73f07bff AM |
322 | 2017-03-06 Alan Modra <amodra@gmail.com> |
323 | ||
324 | PR 21124 | |
325 | * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) | |
326 | (extract_raq, extract_ras, extract_rbx): New functions. | |
327 | (powerpc_operands): Use opposite corresponding insert function. | |
328 | (Q_MASK): Define. | |
329 | (powerpc_opcodes): Apply Q_MASK to all quad insns with even | |
330 | register restriction. | |
331 | ||
65b48a81 PB |
332 | 2017-02-28 Peter Bergner <bergner@vnet.ibm.com> |
333 | ||
334 | * disassemble.c Include "safe-ctype.h". | |
335 | (disassemble_init_for_target): Handle s390 init. | |
336 | (remove_whitespace_and_extra_commas): New function. | |
337 | (disassembler_options_cmp): Likewise. | |
338 | * arm-dis.c: Include "libiberty.h". | |
339 | (NUM_ELEM): Delete. | |
340 | (regnames): Use long disassembler style names. | |
341 | Add force-thumb and no-force-thumb options. | |
342 | (NUM_ARM_REGNAMES): Rename from this... | |
343 | (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. | |
344 | (get_arm_regname_num_options): Delete. | |
345 | (set_arm_regname_option): Likewise. | |
346 | (get_arm_regnames): Likewise. | |
347 | (parse_disassembler_options): Likewise. | |
348 | (parse_arm_disassembler_option): Rename from this... | |
349 | (parse_arm_disassembler_options): ...to this. Make static. | |
350 | Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. | |
351 | (print_insn): Use parse_arm_disassembler_options. | |
352 | (disassembler_options_arm): New function. | |
353 | (print_arm_disassembler_options): Handle updated regnames. | |
354 | * ppc-dis.c: Include "libiberty.h". | |
355 | (ppc_opts): Add "32" and "64" entries. | |
356 | (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. | |
357 | (powerpc_init_dialect): Add break to switch statement. | |
358 | Use new FOR_EACH_DISASSEMBLER_OPTION macro. | |
359 | (disassembler_options_powerpc): New function. | |
360 | (print_ppc_disassembler_options): Use ARRAY_SIZE. | |
361 | Remove printing of "32" and "64". | |
362 | * s390-dis.c: Include "libiberty.h". | |
363 | (init_flag): Remove unneeded variable. | |
364 | (struct s390_options_t): New structure type. | |
365 | (options): New structure. | |
366 | (init_disasm): Rename from this... | |
367 | (disassemble_init_s390): ...to this. Add initializations for | |
368 | current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. | |
369 | (print_insn_s390): Delete call to init_disasm. | |
370 | (disassembler_options_s390): New function. | |
371 | (print_s390_disassembler_options): Print using information from | |
372 | struct 'options'. | |
373 | * po/opcodes.pot: Regenerate. | |
374 | ||
15c7c1d8 JB |
375 | 2017-02-28 Jan Beulich <jbeulich@suse.com> |
376 | ||
377 | * i386-dis.c (PCMPESTR_Fixup): New. | |
378 | (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete. | |
379 | (prefix_table): Use PCMPESTR_Fixup. | |
380 | (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use | |
381 | PCMPESTR_Fixup. | |
382 | (vex_w_table): Delete VPCMPESTR{I,M} entries. | |
383 | * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm): | |
384 | Split 64-bit and non-64-bit variants. | |
385 | * opcodes/i386-tbl.h: Re-generate. | |
386 | ||
582e12bf RS |
387 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
388 | ||
389 | * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) | |
390 | (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) | |
391 | (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) | |
392 | (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) | |
393 | (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) | |
394 | (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) | |
395 | (OP_SVE_V_HSD): New macros. | |
396 | (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) | |
397 | (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) | |
398 | (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. | |
399 | (aarch64_opcode_table): Add new SVE instructions. | |
400 | (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate | |
401 | for rotation operands. Add new SVE operands. | |
402 | * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. | |
403 | (ins_sve_quad_index): Likewise. | |
404 | (ins_imm_rotate): Split into... | |
405 | (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. | |
406 | * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... | |
407 | (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two | |
408 | functions. | |
409 | (aarch64_ins_sve_addr_ri_s4): New function. | |
410 | (aarch64_ins_sve_quad_index): Likewise. | |
411 | (do_misc_encoding): Handle "MOV Zn.Q, Qm". | |
412 | * aarch64-asm-2.c: Regenerate. | |
413 | * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. | |
414 | (ext_sve_quad_index): Likewise. | |
415 | (ext_imm_rotate): Split into... | |
416 | (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. | |
417 | * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... | |
418 | (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two | |
419 | functions. | |
420 | (aarch64_ext_sve_addr_ri_s4): New function. | |
421 | (aarch64_ext_sve_quad_index): Likewise. | |
422 | (aarch64_ext_sve_index): Allow quad indices. | |
423 | (do_misc_decoding): Likewise. | |
424 | * aarch64-dis-2.c: Regenerate. | |
425 | * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New | |
426 | aarch64_field_kinds. | |
427 | (OPD_F_OD_MASK): Widen by one bit. | |
428 | (OPD_F_NO_ZR): Bump accordingly. | |
429 | (get_operand_field_width): New function. | |
430 | * aarch64-opc.c (fields): Add new SVE fields. | |
431 | (operand_general_constraint_met_p): Handle new SVE operands. | |
432 | (aarch64_print_operand): Likewise. | |
433 | * aarch64-opc-2.c: Regenerate. | |
434 | ||
f482d304 RS |
435 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
436 | ||
437 | * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... | |
438 | (aarch64_feature_compnum): ...this. | |
439 | (SIMD_V8_3): Replace with... | |
440 | (COMPNUM): ...this. | |
441 | (CNUM_INSN): New macro. | |
442 | (aarch64_opcode_table): Use it for the complex number instructions. | |
443 | ||
7db2c588 JB |
444 | 2017-02-24 Jan Beulich <jbeulich@suse.com> |
445 | ||
446 | * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST. | |
447 | ||
1e9d41d4 SL |
448 | 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com> |
449 | ||
450 | Add support for associating SPARC ASIs with an architecture level. | |
451 | * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. | |
452 | * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ | |
453 | decoding of SPARC ASIs. | |
454 | ||
53c4d625 JB |
455 | 2017-02-23 Jan Beulich <jbeulich@suse.com> |
456 | ||
457 | * i386-dis.c (get_valid_dis386): Don't special case VEX opcode | |
458 | 82. For 3-byte VEX only special case opcode 77 in VEX_0F space. | |
459 | ||
11648de5 JB |
460 | 2017-02-21 Jan Beulich <jbeulich@suse.com> |
461 | ||
462 | * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand | |
463 | 1 (instead of to itself). Correct typo. | |
464 | ||
f98d33be AW |
465 | 2017-02-14 Andrew Waterman <andrew@sifive.com> |
466 | ||
467 | * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and | |
468 | pseudoinstructions. | |
469 | ||
773fb663 RS |
470 | 2017-02-15 Richard Sandiford <richard.sandiford@arm.com> |
471 | ||
472 | * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. | |
473 | (aarch64_sys_reg_supported_p): Handle them. | |
474 | ||
cc07cda6 CZ |
475 | 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> |
476 | ||
477 | * arc-opc.c (UIMM6_20R): Define. | |
478 | (SIMM12_20): Use above. | |
479 | (SIMM12_20R): Define. | |
480 | (SIMM3_5_S): Use above. | |
481 | (UIMM7_A32_11R_S): Define. | |
482 | (UIMM7_9_S): Use above. | |
483 | (UIMM3_13R_S): Define. | |
484 | (SIMM11_A32_7_S): Use above. | |
485 | (SIMM9_8R): Define. | |
486 | (UIMM10_A32_8_S): Use above. | |
487 | (UIMM8_8R_S): Define. | |
488 | (W6): Use above. | |
489 | (arc_relax_opcodes): Use all above defines. | |
490 | ||
66a5a740 VG |
491 | 2017-02-15 Vineet Gupta <vgupta@synopsys.com> |
492 | ||
493 | * arc-regs.h: Distinguish some of the registers different on | |
494 | ARC700 and HS38 cpus. | |
495 | ||
7e0de605 AM |
496 | 2017-02-14 Alan Modra <amodra@gmail.com> |
497 | ||
498 | PR 21118 | |
499 | * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries | |
500 | with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR. | |
501 | ||
54064fdb AM |
502 | 2017-02-11 Stafford Horne <shorne@gmail.com> |
503 | Alan Modra <amodra@gmail.com> | |
504 | ||
505 | * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. | |
506 | Use insn_bytes_value and insn_int_value directly instead. Don't | |
507 | free allocated memory until function exit. | |
508 | ||
dce75bf9 NP |
509 | 2017-02-10 Nicholas Piggin <npiggin@gmail.com> |
510 | ||
511 | * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. | |
512 | ||
1b7e3d2f NC |
513 | 2017-02-03 Nick Clifton <nickc@redhat.com> |
514 | ||
515 | PR 21096 | |
516 | * aarch64-opc.c (print_register_list): Ensure that the register | |
517 | list index will fir into the tb buffer. | |
518 | (print_register_offset_address): Likewise. | |
519 | * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf. | |
520 | ||
8ec5cf65 AD |
521 | 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com> |
522 | ||
523 | PR 21056 | |
524 | * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel | |
525 | instructions when the previous fetch packet ends with a 32-bit | |
526 | instruction. | |
527 | ||
a1aa5e81 DD |
528 | 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu> |
529 | ||
530 | * pru-opc.c: Remove vague reference to a future GDB port. | |
531 | ||
add3afb2 NC |
532 | 2017-01-20 Nick Clifton <nickc@redhat.com> |
533 | ||
534 | * po/ga.po: Updated Irish translation. | |
535 | ||
c13a63b0 SN |
536 | 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com> |
537 | ||
538 | * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. | |
539 | ||
9608051a YQ |
540 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
541 | ||
542 | * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 | |
543 | if FETCH_DATA returns 0. | |
544 | (m68k_scan_mask): Likewise. | |
545 | (print_insn_m68k): Update code to handle -1 return value. | |
546 | ||
f622ea96 YQ |
547 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
548 | ||
549 | * m68k-dis.c (enum print_insn_arg_error): New. | |
550 | (NEXTBYTE): Replace -3 with | |
551 | PRINT_INSN_ARG_MEMORY_ERROR. | |
552 | (NEXTULONG): Likewise. | |
553 | (NEXTSINGLE): Likewise. | |
554 | (NEXTDOUBLE): Likewise. | |
555 | (NEXTDOUBLE): Likewise. | |
556 | (NEXTPACKED): Likewise. | |
557 | (FETCH_ARG): Likewise. | |
558 | (FETCH_DATA): Update comments. | |
559 | (print_insn_arg): Update comments. Replace magic numbers with | |
560 | enum. | |
561 | (match_insn_m68k): Likewise. | |
562 | ||
620214f7 IT |
563 | 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
564 | ||
565 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. | |
566 | * i386-dis-evex.h (evex_table): Updated. | |
567 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, | |
568 | CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. | |
569 | (cpu_flags): Add CpuAVX512_VPOPCNTDQ. | |
570 | * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. | |
571 | (i386_cpu_flags): Add cpuavx512_vpopcntdq. | |
572 | * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. | |
573 | * i386-init.h: Regenerate. | |
574 | * i386-tbl.h: Ditto. | |
575 | ||
d95014a2 YQ |
576 | 2017-01-12 Yao Qi <yao.qi@linaro.org> |
577 | ||
578 | * msp430-dis.c (msp430_singleoperand): Return -1 if | |
579 | msp430dis_opcode_signed returns false. | |
580 | (msp430_doubleoperand): Likewise. | |
581 | (msp430_branchinstr): Return -1 if | |
582 | msp430dis_opcode_unsigned returns false. | |
583 | (msp430x_calla_instr): Likewise. | |
584 | (print_insn_msp430): Likewise. | |
585 | ||
0ae60c3e NC |
586 | 2017-01-05 Nick Clifton <nickc@redhat.com> |
587 | ||
588 | PR 20946 | |
589 | * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name | |
590 | could not be matched. | |
591 | (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning | |
592 | NULL. | |
593 | ||
d74d4880 SN |
594 | 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> |
595 | ||
596 | * aarch64-tbl.h (RCPC, RCPC_INSN): Define. | |
597 | (aarch64_opcode_table): Use RCPC_INSN. | |
598 | ||
cc917fd9 KC |
599 | 2017-01-03 Kito Cheng <kito.cheng@gmail.com> |
600 | ||
601 | * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA | |
602 | extension. | |
603 | * riscv-opcodes/all-opcodes: Likewise. | |
604 | ||
b52d3cfc DP |
605 | 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org> |
606 | ||
607 | * riscv-dis.c (print_insn_args): Add fall through comment. | |
608 | ||
f90c58d5 NC |
609 | 2017-01-03 Nick Clifton <nickc@redhat.com> |
610 | ||
611 | * po/sr.po: New Serbian translation. | |
612 | * configure.ac (ALL_LINGUAS): Add sr. | |
613 | * configure: Regenerate. | |
614 | ||
f47b0d4a AM |
615 | 2017-01-02 Alan Modra <amodra@gmail.com> |
616 | ||
617 | * epiphany-desc.h: Regenerate. | |
618 | * epiphany-opc.h: Regenerate. | |
619 | * fr30-desc.h: Regenerate. | |
620 | * fr30-opc.h: Regenerate. | |
621 | * frv-desc.h: Regenerate. | |
622 | * frv-opc.h: Regenerate. | |
623 | * ip2k-desc.h: Regenerate. | |
624 | * ip2k-opc.h: Regenerate. | |
625 | * iq2000-desc.h: Regenerate. | |
626 | * iq2000-opc.h: Regenerate. | |
627 | * lm32-desc.h: Regenerate. | |
628 | * lm32-opc.h: Regenerate. | |
629 | * m32c-desc.h: Regenerate. | |
630 | * m32c-opc.h: Regenerate. | |
631 | * m32r-desc.h: Regenerate. | |
632 | * m32r-opc.h: Regenerate. | |
633 | * mep-desc.h: Regenerate. | |
634 | * mep-opc.h: Regenerate. | |
635 | * mt-desc.h: Regenerate. | |
636 | * mt-opc.h: Regenerate. | |
637 | * or1k-desc.h: Regenerate. | |
638 | * or1k-opc.h: Regenerate. | |
639 | * xc16x-desc.h: Regenerate. | |
640 | * xc16x-opc.h: Regenerate. | |
641 | * xstormy16-desc.h: Regenerate. | |
642 | * xstormy16-opc.h: Regenerate. | |
643 | ||
2571583a AM |
644 | 2017-01-02 Alan Modra <amodra@gmail.com> |
645 | ||
646 | Update year range in copyright notice of all files. | |
647 | ||
5c1ad6b5 | 648 | For older changes see ChangeLog-2016 |
3499769a | 649 | \f |
5c1ad6b5 | 650 | Copyright (C) 2017 Free Software Foundation, Inc. |
3499769a AM |
651 | |
652 | Copying and distribution of this file, with or without modification, | |
653 | are permitted in any medium without royalty provided the copyright | |
654 | notice and this notice are preserved. | |
655 | ||
656 | Local Variables: | |
657 | mode: change-log | |
658 | left-margin: 8 | |
659 | fill-column: 74 | |
660 | version-control: never | |
661 | End: |