projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| fe4e2a3c IT |
1 | 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 2 | ||
| 3 | * i386-init.h: Regenerate | |
| 4 | * i386-tbl.h: Likewise | |
| 5 | ||
| 2739ef6d IT |
6 | 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 7 | ||
| 8 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F. | |
| 9 | (enum): Add EVEX_W_0F3854_P_2. | |
| 10 | * i386-dis-evex.h (evex_table): Updated. | |
| 11 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG, | |
| 12 | CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS. | |
| 13 | (cpu_flags): Add CpuAVX512_BITALG. | |
| 14 | * i386-opc.h (enum): Add CpuAVX512_BITALG. | |
| 15 | (i386_cpu_flags): Add cpuavx512_bitalg.. | |
| 16 | * i386-opc.tbl: Add Intel AVX512_BITALG instructions. | |
| 17 | * i386-init.h: Regenerate. | |
| 18 | * i386-tbl.h: Likewise. | |
| 19 | ||
| 20 | 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> | |
| 21 | ||
| 22 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851. | |
| 23 | * i386-dis-evex.h (evex_table): Updated. | |
| 24 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI, | |
| 25 | CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS. | |
| 26 | (cpu_flags): Add CpuAVX512_VNNI. | |
| 27 | * i386-opc.h (enum): Add CpuAVX512_VNNI. | |
| 28 | (i386_cpu_flags): Add cpuavx512_vnni. | |
| 29 | * i386-opc.tbl Add Intel AVX512_VNNI instructions. | |
| 30 | * i386-init.h: Regenerate. | |
| 31 | * i386-tbl.h: Likewise. | |
| 32 | ||
| 33 | 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> | |
| 34 | ||
| 35 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44. | |
| 36 | (enum): Remove VEX_LEN_0F3A44_P_2. | |
| 37 | (vex_len_table): Ditto. | |
| 38 | (enum): Remove VEX_W_0F3A44_P_2. | |
| 39 | (vew_w_table): Ditto. | |
| 40 | (prefix_table): Adjust instructions (see prefixes above). | |
| 41 | * i386-dis-evex.h (evex_table): | |
| 42 | Add new instructions (see prefixes above). | |
| 43 | * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ. | |
| 44 | (bitfield_cpu_flags): Ditto. | |
| 45 | * i386-opc.h (enum): Ditto. | |
| 46 | (i386_cpu_flags): Ditto. | |
| 47 | (CpuUnused): Comment out to avoid zero-width field problem. | |
| 48 | * i386-opc.tbl (vpclmulqdq): New instruction. | |
| 49 | * i386-init.h: Regenerate. | |
| 50 | * i386-tbl.h: Ditto. | |
| 51 | ||
| 52 | 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> | |
| 53 | ||
| 54 | * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, | |
| 55 | PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF. | |
| 56 | (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2, | |
| 57 | VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2. | |
| 58 | (vex_len_table): Ditto. | |
| 59 | (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2, | |
| 60 | VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2. | |
| 61 | (vew_w_table): Ditto. | |
| 62 | (prefix_table): Adjust instructions (see prefixes above). | |
| 63 | * i386-dis-evex.h (evex_table): | |
| 64 | Add new instructions (see prefixes above). | |
| 65 | * i386-gen.c (cpu_flag_init): Add VAES. | |
| 66 | (bitfield_cpu_flags): Ditto. | |
| 67 | * i386-opc.h (enum): Ditto. | |
| 68 | (i386_cpu_flags): Ditto. | |
| 69 | * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions. | |
| 70 | * i386-init.h: Regenerate. | |
| 71 | * i386-tbl.h: Ditto. | |
| 72 | ||
| 73 | 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> | |
| 74 | ||
| 75 | * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF, | |
| 76 | PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, | |
| 77 | PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF. | |
| 78 | (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, | |
| 79 | EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2. | |
| 80 | (prefix_table): Updated (see prefixes above). | |
| 81 | (three_byte_table): Likewise. | |
| 82 | (vex_w_table): Likewise. | |
| 83 | * i386-dis-evex.h: Likewise. | |
| 84 | * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI. | |
| 85 | (cpu_flags): Add CpuGFNI. | |
| 86 | * i386-opc.h (enum): Add CpuGFNI. | |
| 87 | (i386_cpu_flags): Add cpugfni. | |
| 88 | * i386-opc.tbl: Add Intel GFNI instructions. | |
| 89 | * i386-init.h: Regenerate. | |
| 90 | * i386-tbl.h: Likewise. | |
| 91 | ||
| 92 | 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com> | |
| 93 | ||
| 94 | * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode. | |
| 95 | Define EXbScalar and EXwScalar for OP_EX. | |
| 96 | (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, | |
| 97 | PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872, | |
| 98 | PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71, | |
| 99 | PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73. | |
| 100 | (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2, | |
| 101 | EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2, | |
| 102 | EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2, | |
| 103 | EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2. | |
| 104 | (intel_operand_size): Handle b_scalar_mode and w_scalar_mode. | |
| 105 | (OP_E_memory): Likewise. | |
| 106 | * i386-dis-evex.h: Updated. | |
| 107 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2, | |
| 108 | CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS. | |
| 109 | (cpu_flags): Add CpuAVX512_VBMI2. | |
| 110 | * i386-opc.h (enum): Add CpuAVX512_VBMI2. | |
| 111 | (i386_cpu_flags): Add cpuavx512_vbmi2. | |
| 112 | * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions. | |
| 113 | * i386-init.h: Regenerate. | |
| 114 | * i386-tbl.h: Likewise. | |
| 115 | ||
| 2a6969e1 EB |
116 | 2017-10-18 Eric Botcazou <ebotcazou@adacore.com> |
| 117 | ||
| 118 | * visium-dis.c (disassem_class1) <case 0>: Print the operands. | |
| 119 | ||
| 3b4b0a62 JB |
120 | 2017-10-12 James Bowman <james.bowman@ftdichip.com> |
| 121 | ||
| 122 | * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15. | |
| 123 | * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with | |
| 124 | K15. Add jmpix pattern. | |
| 125 | ||
| 8e464506 AK |
126 | 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 127 | ||
| 128 | * s390-opc.txt (prno, tpei, irbm): New instructions added. | |
| 129 | ||
| ee6767da AK |
130 | 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com> |
| 131 | ||
| 132 | * s390-opc.c (INSTR_SI_RD): New macro. | |
| 133 | (INSTR_S_RD): Adjust example instruction. | |
| 134 | * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to | |
| 135 | SI_RD. | |
| 136 | ||
| d2e6c9a3 AF |
137 | 2017-10-01 Alexander Fedotov <alfedotov@gmail.com> |
| 138 | ||
| 139 | * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw, | |
| 140 | e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for | |
| 141 | VLE multimple load/store instructions. Old e_ldm* variants are | |
| 142 | kept as aliases. | |
| 143 | Add missing e_lmvmcsrrw and e_stmvmcsrrw. | |
| 144 | ||
| 8e43602e NC |
145 | 2017-09-27 Nick Clifton <nickc@redhat.com> |
| 146 | ||
| 147 | PR 22179 | |
| 148 | * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new | |
| 149 | names for the fmv.x.s and fmv.s.x instructions respectively. | |
| 150 | ||
| 58a0b827 NC |
151 | 2017-09-26 do <do@nerilex.org> |
| 152 | ||
| 153 | PR 22123 | |
| 154 | * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to | |
| 155 | be used on CPUs that have emacs support. | |
| 156 | ||
| 57a024f4 SDJ |
157 | 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com> |
| 158 | ||
| 159 | * aarch64-opc.c (expand_fp_imm): Initialize 'imm'. | |
| 160 | ||
| 4ec521f2 KLC |
161 | 2017-09-09 Kamil Rytarowski <n54@gmx.com> |
| 162 | ||
| 163 | * nds32-asm.c: Rename __BIT() to N32_BIT(). | |
| 164 | * nds32-asm.h: Likewise. | |
| 165 | * nds32-dis.c: Likewise. | |
| 166 | ||
| 4e9ac44a L |
167 | 2017-09-09 H.J. Lu <hongjiu.lu@intel.com> |
| 168 | ||
| 169 | * i386-dis.c (last_active_prefix): Removed. | |
| 170 | (ckprefix): Don't set last_active_prefix. | |
| 171 | (NOTRACK_Fixup): Don't check last_active_prefix. | |
| 172 | ||
| b55f3386 NC |
173 | 2017-08-31 Nick Clifton <nickc@redhat.com> |
| 174 | ||
| 175 | * po/fr.po: Updated French translation. | |
| 176 | ||
| 59e8523b JB |
177 | 2017-08-31 James Bowman <james.bowman@ftdichip.com> |
| 178 | ||
| 179 | * ft32-dis.c (print_insn_ft32): Correct display of non-address | |
| 180 | fields. | |
| 181 | ||
| 74081948 AF |
182 | 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com> |
| 183 | Edmar Wienskoski <edmar.wienskoski@nxp.com> | |
| 184 | ||
| 185 | * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and | |
| 186 | PPC_OPCODE_EFS2 flag to "e200z4" entry. | |
| 187 | New entries efs2 and spe2. | |
| 188 | Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry. | |
| 189 | (SPE2_OPCD_SEGS): New macro. | |
| 190 | (spe2_opcd_indices): New. | |
| 191 | (disassemble_init_powerpc): Handle SPE2 opcodes. | |
| 192 | (lookup_spe2): New function. | |
| 193 | (print_insn_powerpc): call lookup_spe2. | |
| 194 | * ppc-opc.c (insert_evuimm1_ex0): New function. | |
| 195 | (extract_evuimm1_ex0): Likewise. | |
| 196 | (insert_evuimm_lt8): Likewise. | |
| 197 | (extract_evuimm_lt8): Likewise. | |
| 198 | (insert_off_spe2): Likewise. | |
| 199 | (extract_off_spe2): Likewise. | |
| 200 | (insert_Ddd): Likewise. | |
| 201 | (extract_Ddd): Likewise. | |
| 202 | (DD): New operand. | |
| 203 | (EVUIMM_LT8): Likewise. | |
| 204 | (EVUIMM_LT16): Adjust. | |
| 205 | (MMMM): New operand. | |
| 206 | (EVUIMM_1): Likewise. | |
| 207 | (EVUIMM_1_EX0): Likewise. | |
| 208 | (EVUIMM_2): Adjust. | |
| 209 | (NNN): New operand. | |
| 210 | (VX_OFF_SPE2): Likewise. | |
| 211 | (BBB): Likewise. | |
| 212 | (DDD): Likewise. | |
| 213 | (VX_MASK_DDD): New mask. | |
| 214 | (HH): New operand. | |
| 215 | (VX_RA_CONST): New macro. | |
| 216 | (VX_RA_CONST_MASK): Likewise. | |
| 217 | (VX_RB_CONST): Likewise. | |
| 218 | (VX_RB_CONST_MASK): Likewise. | |
| 219 | (VX_OFF_SPE2_MASK): Likewise. | |
| 220 | (VX_SPE_CRFD): Likewise. | |
| 221 | (VX_SPE_CRFD_MASK VX): Likewise. | |
| 222 | (VX_SPE2_CLR): Likewise. | |
| 223 | (VX_SPE2_CLR_MASK): Likewise. | |
| 224 | (VX_SPE2_SPLATB): Likewise. | |
| 225 | (VX_SPE2_SPLATB_MASK): Likewise. | |
| 226 | (VX_SPE2_OCTET): Likewise. | |
| 227 | (VX_SPE2_OCTET_MASK): Likewise. | |
| 228 | (VX_SPE2_DDHH): Likewise. | |
| 229 | (VX_SPE2_DDHH_MASK): Likewise. | |
| 230 | (VX_SPE2_HH): Likewise. | |
| 231 | (VX_SPE2_HH_MASK): Likewise. | |
| 232 | (VX_SPE2_EVMAR): Likewise. | |
| 233 | (VX_SPE2_EVMAR_MASK): Likewise. | |
| 234 | (PPCSPE2): Likewise. | |
| 235 | (PPCEFS2): Likewise. | |
| 236 | (vle_opcodes): Add EFS2 and some missing SPE opcodes. | |
| 237 | (powerpc_macros): Map old SPE instructions have new names | |
| 238 | with the same opcodes. Add SPE2 instructions which just are | |
| 239 | mapped to SPE2. | |
| 240 | (spe2_opcodes): Add SPE2 opcodes. | |
| 241 | ||
| b80c7270 AM |
242 | 2017-08-23 Alan Modra <amodra@gmail.com> |
| 243 | ||
| 244 | * ppc-opc.c: Formatting and comment fixes. Move insert and | |
| 245 | extract functions earlier, deleting forward declarations. | |
| 246 | (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and | |
| 247 | RA_MASK. | |
| 248 | ||
| 67d888f5 PD |
249 | 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com> |
| 250 | ||
| 251 | * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias. | |
| 252 | ||
| e3c2f928 AF |
253 | 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com> |
| 254 | Edmar Wienskoski <edmar.wienskoski@nxp.com> | |
| 255 | ||
| 256 | * ppc-opc.c (insert_evuimm2_ex0): New function. | |
| 257 | (extract_evuimm2_ex0): Likewise. | |
| 258 | (insert_evuimm4_ex0): Likewise. | |
| 259 | (extract_evuimm4_ex0): Likewise. | |
| 260 | (insert_evuimm8_ex0): Likewise. | |
| 261 | (extract_evuimm8_ex0): Likewise. | |
| 262 | (insert_evuimm_lt16): Likewise. | |
| 263 | (extract_evuimm_lt16): Likewise. | |
| 264 | (insert_rD_rS_even): Likewise. | |
| 265 | (extract_rD_rS_even): Likewise. | |
| 266 | (insert_off_lsp): Likewise. | |
| 267 | (extract_off_lsp): Likewise. | |
| 268 | (RD_EVEN): New operand. | |
| 269 | (RS_EVEN): Likewise. | |
| 270 | (RSQ): Adjust. | |
| 271 | (EVUIMM_LT16): New operand. | |
| 272 | (HTM_SI): Adjust. | |
| 273 | (EVUIMM_2_EX0): New operand. | |
| 274 | (EVUIMM_4): Adjust. | |
| 275 | (EVUIMM_4_EX0): New operand. | |
| 276 | (EVUIMM_8): Adjust. | |
| 277 | (EVUIMM_8_EX0): New operand. | |
| 278 | (WS): Adjust. | |
| 279 | (VX_OFF): New operand. | |
| 280 | (VX_LSP): New macro. | |
| 281 | (VX_LSP_MASK): Likewise. | |
| 282 | (VX_LSP_OFF_MASK): Likewise. | |
| 283 | (PPC_OPCODE_LSP): Likewise. | |
| 284 | (vle_opcodes): Add LSP opcodes. | |
| 285 | * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry. | |
| 286 | ||
| cc4a945a JW |
287 | 2017-08-09 Jiong Wang <jiong.wang@arm.com> |
| 288 | ||
| 289 | * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for | |
| 290 | register operands in CRC instructions. | |
| 291 | (print_insn_thumb32): Remove "<bitfield>S" support. Updated the | |
| 292 | comments. | |
| 293 | ||
| b28b8b5e L |
294 | 2017-08-07 H.J. Lu <hongjiu.lu@intel.com> |
| 295 | ||
| 296 | * disassemble.c (disassembler): Mark big and mach with | |
| 297 | ATTRIBUTE_UNUSED. | |
| 298 | ||
| e347efc3 MR |
299 | 2017-08-07 Maciej W. Rozycki <macro@imgtec.com> |
| 300 | ||
| 301 | * disassemble.c (disassembler): Remove arch/mach/endian | |
| 302 | assertions. | |
| 303 | ||
| 7cbc739c NC |
304 | 2017-07-25 Nick Clifton <nickc@redhat.com> |
| 305 | ||
| 306 | PR 21739 | |
| 307 | * arc-opc.c (insert_rhv2): Use lower case first letter in error | |
| 308 | message. | |
| 309 | (insert_r0): Likewise. | |
| 310 | (insert_r1): Likewise. | |
| 311 | (insert_r2): Likewise. | |
| 312 | (insert_r3): Likewise. | |
| 313 | (insert_sp): Likewise. | |
| 314 | (insert_gp): Likewise. | |
| 315 | (insert_pcl): Likewise. | |
| 316 | (insert_blink): Likewise. | |
| 317 | (insert_ilink1): Likewise. | |
| 318 | (insert_ilink2): Likewise. | |
| 319 | (insert_ras): Likewise. | |
| 320 | (insert_rbs): Likewise. | |
| 321 | (insert_rcs): Likewise. | |
| 322 | (insert_simm3s): Likewise. | |
| 323 | (insert_rrange): Likewise. | |
| 324 | (insert_r13el): Likewise. | |
| 325 | (insert_fpel): Likewise. | |
| 326 | (insert_blinkel): Likewise. | |
| 327 | (insert_pclel): Likewise. | |
| 328 | (insert_nps_bitop_size_2b): Likewise. | |
| 329 | (insert_nps_imm_offset): Likewise. | |
| 330 | (insert_nps_imm_entry): Likewise. | |
| 331 | (insert_nps_size_16bit): Likewise. | |
| 332 | (insert_nps_##NAME##_pos): Likewise. | |
| 333 | (insert_nps_##NAME): Likewise. | |
| 334 | (insert_nps_bitop_ins_ext): Likewise. | |
| 335 | (insert_nps_##NAME): Likewise. | |
| 336 | (insert_nps_min_hofs): Likewise. | |
| 337 | (insert_nps_##NAME): Likewise. | |
| 338 | (insert_nps_rbdouble_64): Likewise. | |
| 339 | (insert_nps_misc_imm_offset): Likewise. | |
| 340 | * riscv-dis.c (print_riscv_disassembler_options): Fix typo in | |
| 341 | option description. | |
| 342 | ||
| 7684e580 JW |
343 | 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com> |
| 344 | Jiong Wang <jiong.wang@arm.com> | |
| 345 | ||
| 346 | * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to | |
| 347 | correct the print. | |
| 348 | * aarch64-dis-2.c: Regenerated. | |
| 349 | ||
| 47826cdb AK |
350 | 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 351 | ||
| 352 | * s390-mkopc.c (main): Enable z14 as CPU string in the opcode | |
| 353 | table. | |
| 354 | ||
| 2d2dbad0 NC |
355 | 2017-07-20 Nick Clifton <nickc@redhat.com> |
| 356 | ||
| 357 | * po/de.po: Updated German translation. | |
| 358 | ||
| 70b448ba | 359 | 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> |
| 360 | ||
| 361 | * arc-regs.h (sec_stat): New aux register. | |
| 362 | (aux_kernel_sp): Likewise. | |
| 363 | (aux_sec_u_sp): Likewise. | |
| 364 | (aux_sec_k_sp): Likewise. | |
| 365 | (sec_vecbase_build): Likewise. | |
| 366 | (nsc_table_top): Likewise. | |
| 367 | (nsc_table_base): Likewise. | |
| 368 | (ersec_stat): Likewise. | |
| 369 | (aux_sec_except): Likewise. | |
| 370 | ||
| 7179e0e6 CZ |
371 | 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> |
| 372 | ||
| 373 | * arc-opc.c (extract_uimm12_20): New function. | |
| 374 | (UIMM12_20): New operand. | |
| 375 | (SIMM3_5_S): Adjust. | |
| 376 | * arc-tbl.h (sjli): Add new instruction. | |
| 377 | ||
| 684d5a10 JEM |
378 | 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> |
| 379 | John Eric Martin <John.Martin@emmicro-us.com> | |
| 380 | ||
| 381 | * arc-opc.c (UIMM10_6_S_JLIOFF): Define. | |
| 382 | (UIMM3_23): Adjust accordingly. | |
| 383 | * arc-regs.h: Add/correct jli_base register. | |
| 384 | * arc-tbl.h (jli_s): Likewise. | |
| 385 | ||
| de194d85 YC |
386 | 2017-07-18 Nick Clifton <nickc@redhat.com> |
| 387 | ||
| 388 | PR 21775 | |
| 389 | * aarch64-opc.c: Fix spelling typos. | |
| 390 | * i386-dis.c: Likewise. | |
| 391 | ||
| 0f6329bd RB |
392 | 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> |
| 393 | ||
| 394 | * dis-buf.c (buffer_read_memory): Change type of end_addr_offset, | |
| 395 | max_addr_offset and octets variables to size_t. | |
| 396 | ||
| 429d795d AM |
397 | 2017-07-12 Alan Modra <amodra@gmail.com> |
| 398 | ||
| 399 | * po/da.po: Update from translationproject.org/latest/opcodes/. | |
| 400 | * po/de.po: Likewise. | |
| 401 | * po/es.po: Likewise. | |
| 402 | * po/fi.po: Likewise. | |
| 403 | * po/fr.po: Likewise. | |
| 404 | * po/id.po: Likewise. | |
| 405 | * po/it.po: Likewise. | |
| 406 | * po/nl.po: Likewise. | |
| 407 | * po/pt_BR.po: Likewise. | |
| 408 | * po/ro.po: Likewise. | |
| 409 | * po/sv.po: Likewise. | |
| 410 | * po/tr.po: Likewise. | |
| 411 | * po/uk.po: Likewise. | |
| 412 | * po/vi.po: Likewise. | |
| 413 | * po/zh_CN.po: Likewise. | |
| 414 | ||
| 4162bb66 AM |
415 | 2017-07-11 Yao Qi <yao.qi@linaro.org> |
| 416 | Alan Modra <amodra@gmail.com> | |
| 417 | ||
| 418 | * cgen.sh: Mark generated files read-only. | |
| 419 | * epiphany-asm.c: Regenerate. | |
| 420 | * epiphany-desc.c: Regenerate. | |
| 421 | * epiphany-desc.h: Regenerate. | |
| 422 | * epiphany-dis.c: Regenerate. | |
| 423 | * epiphany-ibld.c: Regenerate. | |
| 424 | * epiphany-opc.c: Regenerate. | |
| 425 | * epiphany-opc.h: Regenerate. | |
| 426 | * fr30-asm.c: Regenerate. | |
| 427 | * fr30-desc.c: Regenerate. | |
| 428 | * fr30-desc.h: Regenerate. | |
| 429 | * fr30-dis.c: Regenerate. | |
| 430 | * fr30-ibld.c: Regenerate. | |
| 431 | * fr30-opc.c: Regenerate. | |
| 432 | * fr30-opc.h: Regenerate. | |
| 433 | * frv-asm.c: Regenerate. | |
| 434 | * frv-desc.c: Regenerate. | |
| 435 | * frv-desc.h: Regenerate. | |
| 436 | * frv-dis.c: Regenerate. | |
| 437 | * frv-ibld.c: Regenerate. | |
| 438 | * frv-opc.c: Regenerate. | |
| 439 | * frv-opc.h: Regenerate. | |
| 440 | * ip2k-asm.c: Regenerate. | |
| 441 | * ip2k-desc.c: Regenerate. | |
| 442 | * ip2k-desc.h: Regenerate. | |
| 443 | * ip2k-dis.c: Regenerate. | |
| 444 | * ip2k-ibld.c: Regenerate. | |
| 445 | * ip2k-opc.c: Regenerate. | |
| 446 | * ip2k-opc.h: Regenerate. | |
| 447 | * iq2000-asm.c: Regenerate. | |
| 448 | * iq2000-desc.c: Regenerate. | |
| 449 | * iq2000-desc.h: Regenerate. | |
| 450 | * iq2000-dis.c: Regenerate. | |
| 451 | * iq2000-ibld.c: Regenerate. | |
| 452 | * iq2000-opc.c: Regenerate. | |
| 453 | * iq2000-opc.h: Regenerate. | |
| 454 | * lm32-asm.c: Regenerate. | |
| 455 | * lm32-desc.c: Regenerate. | |
| 456 | * lm32-desc.h: Regenerate. | |
| 457 | * lm32-dis.c: Regenerate. | |
| 458 | * lm32-ibld.c: Regenerate. | |
| 459 | * lm32-opc.c: Regenerate. | |
| 460 | * lm32-opc.h: Regenerate. | |
| 461 | * lm32-opinst.c: Regenerate. | |
| 462 | * m32c-asm.c: Regenerate. | |
| 463 | * m32c-desc.c: Regenerate. | |
| 464 | * m32c-desc.h: Regenerate. | |
| 465 | * m32c-dis.c: Regenerate. | |
| 466 | * m32c-ibld.c: Regenerate. | |
| 467 | * m32c-opc.c: Regenerate. | |
| 468 | * m32c-opc.h: Regenerate. | |
| 469 | * m32r-asm.c: Regenerate. | |
| 470 | * m32r-desc.c: Regenerate. | |
| 471 | * m32r-desc.h: Regenerate. | |
| 472 | * m32r-dis.c: Regenerate. | |
| 473 | * m32r-ibld.c: Regenerate. | |
| 474 | * m32r-opc.c: Regenerate. | |
| 475 | * m32r-opc.h: Regenerate. | |
| 476 | * m32r-opinst.c: Regenerate. | |
| 477 | * mep-asm.c: Regenerate. | |
| 478 | * mep-desc.c: Regenerate. | |
| 479 | * mep-desc.h: Regenerate. | |
| 480 | * mep-dis.c: Regenerate. | |
| 481 | * mep-ibld.c: Regenerate. | |
| 482 | * mep-opc.c: Regenerate. | |
| 483 | * mep-opc.h: Regenerate. | |
| 484 | * mt-asm.c: Regenerate. | |
| 485 | * mt-desc.c: Regenerate. | |
| 486 | * mt-desc.h: Regenerate. | |
| 487 | * mt-dis.c: Regenerate. | |
| 488 | * mt-ibld.c: Regenerate. | |
| 489 | * mt-opc.c: Regenerate. | |
| 490 | * mt-opc.h: Regenerate. | |
| 491 | * or1k-asm.c: Regenerate. | |
| 492 | * or1k-desc.c: Regenerate. | |
| 493 | * or1k-desc.h: Regenerate. | |
| 494 | * or1k-dis.c: Regenerate. | |
| 495 | * or1k-ibld.c: Regenerate. | |
| 496 | * or1k-opc.c: Regenerate. | |
| 497 | * or1k-opc.h: Regenerate. | |
| 498 | * or1k-opinst.c: Regenerate. | |
| 499 | * xc16x-asm.c: Regenerate. | |
| 500 | * xc16x-desc.c: Regenerate. | |
| 501 | * xc16x-desc.h: Regenerate. | |
| 502 | * xc16x-dis.c: Regenerate. | |
| 503 | * xc16x-ibld.c: Regenerate. | |
| 504 | * xc16x-opc.c: Regenerate. | |
| 505 | * xc16x-opc.h: Regenerate. | |
| 506 | * xstormy16-asm.c: Regenerate. | |
| 507 | * xstormy16-desc.c: Regenerate. | |
| 508 | * xstormy16-desc.h: Regenerate. | |
| 509 | * xstormy16-dis.c: Regenerate. | |
| 510 | * xstormy16-ibld.c: Regenerate. | |
| 511 | * xstormy16-opc.c: Regenerate. | |
| 512 | * xstormy16-opc.h: Regenerate. | |
| 513 | ||
| 7639175c AM |
514 | 2017-07-07 Alan Modra <amodra@gmail.com> |
| 515 | ||
| 516 | * cgen-dis.in: Include disassemble.h, not dis-asm.h. | |
| 517 | * m32c-dis.c: Regenerate. | |
| 518 | * mep-dis.c: Regenerate. | |
| 519 | ||
| e4bdd679 BP |
520 | 2017-07-05 Borislav Petkov <bp@suse.de> |
| 521 | ||
| 522 | * i386-dis.c: Enable ModRM.reg /6 aliases. | |
| 523 | ||
| 60c96dbf RR |
524 | 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> |
| 525 | ||
| 526 | * opcodes/arm-dis.c: Support MVFR2 in disassembly | |
| 527 | with vmrs and vmsr. | |
| 528 | ||
| 0d702cfe TG |
529 | 2017-07-04 Tristan Gingold <gingold@adacore.com> |
| 530 | ||
| 531 | * configure: Regenerate. | |
| 532 | ||
| 15e6ed8c TG |
533 | 2017-07-03 Tristan Gingold <gingold@adacore.com> |
| 534 | ||
| 535 | * po/opcodes.pot: Regenerate. | |
| 536 | ||
| b1d3c886 MR |
537 | 2017-06-30 Maciej W. Rozycki <macro@imgtec.com> |
| 538 | ||
| 539 | * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa" | |
| 540 | entries to the MSA ASE instruction block. | |
| 541 | ||
| 909b4e3d MR |
542 | 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com> |
| 543 | Maciej W. Rozycki <macro@imgtec.com> | |
| 544 | ||
| 545 | * micromips-opc.c (XPA, XPAVZ): New macros. | |
| 546 | (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and | |
| 547 | "mthgc0". | |
| 548 | ||
| f5b2fd52 MR |
549 | 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com> |
| 550 | Maciej W. Rozycki <macro@imgtec.com> | |
| 551 | ||
| 552 | * micromips-opc.c (I36): New macro. | |
| 553 | (micromips_opcodes): Add "eretnc". | |
| 554 | ||
| 9785fc2a MR |
555 | 2017-06-30 Maciej W. Rozycki <macro@imgtec.com> |
| 556 | Andrew Bennett <andrew.bennett@imgtec.com> | |
| 557 | ||
| 558 | * mips-dis.c (mips_calculate_combination_ases): Handle the | |
| 559 | ASE_XPA_VIRT flag. | |
| 560 | (parse_mips_ase_option): New function. | |
| 561 | (parse_mips_dis_option): Factor out ASE option handling to the | |
| 562 | new function. Call `mips_calculate_combination_ases'. | |
| 563 | * mips-opc.c (XPAVZ): New macro. | |
| 564 | (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", | |
| 565 | "mfhgc0", "mthc0" and "mthgc0". | |
| 566 | ||
| 60804c53 MR |
567 | 2017-06-29 Maciej W. Rozycki <macro@imgtec.com> |
| 568 | ||
| 569 | * mips-dis.c (mips_calculate_combination_ases): New function. | |
| 570 | (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT | |
| 571 | calculation to the new function. | |
| 572 | (set_default_mips_dis_options): Call the new function. | |
| 573 | ||
| 2e74f9dd AK |
574 | 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com> |
| 575 | ||
| 576 | * arc-dis.c (parse_disassembler_options): Use | |
| 577 | FOR_EACH_DISASSEMBLER_OPTION. | |
| 578 | ||
| e1e94c49 AK |
579 | 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com> |
| 580 | ||
| 581 | * arc-dis.c (parse_option): Use disassembler_options_cmp to compare | |
| 582 | disassembler option strings. | |
| 583 | (parse_cpu_option): Likewise. | |
| 584 | ||
| 65a55fbb TC |
585 | 2017-06-28 Tamar Christina <tamar.christina@arm.com> |
| 586 | ||
| 587 | * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. | |
| 588 | * aarch64-dis.c (aarch64_ext_reglane): Likewise. | |
| 589 | * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. | |
| 590 | (aarch64_feature_dotprod, DOT_INSN): New. | |
| 591 | (udot, sdot): New. | |
| 592 | * aarch64-dis-2.c: Regenerated. | |
| 593 | ||
| c604a79a JW |
594 | 2017-06-28 Jiong Wang <jiong.wang@arm.com> |
| 595 | ||
| 596 | * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot. | |
| 597 | ||
| 38bf472a MR |
598 | 2017-06-28 Maciej W. Rozycki <macro@imgtec.com> |
| 599 | Matthew Fortune <matthew.fortune@imgtec.com> | |
| 4151f684 | 600 | Andrew Bennett <andrew.bennett@imgtec.com> |
| 38bf472a MR |
601 | |
| 602 | * mips-formats.h (INT_BIAS): New macro. | |
| 603 | (INT_ADJ): Redefine in INT_BIAS terms. | |
| 604 | * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. | |
| 605 | (mips_print_save_restore): New function. | |
| 606 | (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. | |
| 607 | (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' | |
| 608 | call. | |
| 609 | (print_insn_args): Handle OP_SAVE_RESTORE_LIST. | |
| 610 | (print_mips16_insn_arg): Call `mips_print_save_restore' for | |
| 611 | OP_SAVE_RESTORE_LIST handling, factored out from here. | |
| 612 | * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. | |
| 613 | (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. | |
| 614 | (mips_builtin_opcodes): Add "restore" and "save" entries. | |
| 615 | * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. | |
| 616 | (IAMR2): New macro. | |
| 617 | (mips16_opcodes): Add "copyw" and "ucopyw" entries. | |
| 618 | ||
| 9bdfdbf9 AW |
619 | 2017-06-23 Andrew Waterman <andrew@sifive.com> |
| 620 | ||
| 621 | * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an | |
| 622 | alias; do not mark SLTI instruction as an alias. | |
| 623 | ||
| 2234eee6 L |
624 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| 625 | ||
| 626 | * i386-dis.c (RM_0FAE_REG_5): Removed. | |
| 627 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. | |
| 628 | (PREFIX_MOD_3_0F01_REG_5_RM_0): New. | |
| 629 | (PREFIX_MOD_3_0FAE_REG_5): Likewise. | |
| 630 | (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add | |
| 631 | PREFIX_MOD_3_0F01_REG_5_RM_0. | |
| 632 | (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add | |
| 633 | PREFIX_MOD_3_0FAE_REG_5. | |
| 634 | (mod_table): Update MOD_0FAE_REG_5. | |
| 635 | (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. | |
| 636 | * i386-opc.tbl: Update incsspd, incsspq and setssbsy. | |
| 637 | * i386-tbl.h: Regenerated. | |
| 638 | ||
| c2f76402 L |
639 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| 640 | ||
| 641 | * i386-dis.c (prefix_table): Replace savessp with saveprevssp. | |
| 642 | * i386-opc.tbl: Likewise. | |
| 643 | * i386-tbl.h: Regenerated. | |
| 644 | ||
| 9fef80d6 L |
645 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| 646 | ||
| 647 | * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}" | |
| 648 | and "jmp{&|}". | |
| 649 | (NOTRACK_Fixup): Support memory indirect branch with NOTRACK | |
| 650 | prefix. | |
| 651 | ||
| 0f6d864d NC |
652 | 2017-06-19 Nick Clifton <nickc@redhat.com> |
| 653 | ||
| 654 | PR binutils/21614 | |
| 655 | * score-dis.c (score_opcodes): Add sentinel. | |
| 656 | ||
| e197589b AM |
657 | 2017-06-16 Alan Modra <amodra@gmail.com> |
| 658 | ||
| 659 | * rx-decode.c: Regenerate. | |
| 660 | ||
| 0d96e4df L |
661 | 2017-06-15 H.J. Lu <hongjiu.lu@intel.com> |
| 662 | ||
| 663 | PR binutils/21594 | |
| 664 | * i386-dis.c (OP_E_register): Check valid bnd register. | |
| 665 | (OP_G): Likewise. | |
| 666 | ||
| cd3ea7c6 NC |
667 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| 668 | ||
| 669 | PR binutils/21595 | |
| 670 | * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of | |
| 671 | range value. | |
| 672 | ||
| 63323b5b NC |
673 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| 674 | ||
| 675 | PR binutils/21588 | |
| 676 | * rl78-decode.opc (OP_BUF_LEN): Define. | |
| 677 | (GETBYTE): Check for the index exceeding OP_BUF_LEN. | |
| 678 | (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf | |
| 679 | array. | |
| 680 | * rl78-decode.c: Regenerate. | |
| 681 | ||
| 08c7881b NC |
682 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| 683 | ||
| 684 | PR binutils/21586 | |
| 685 | * bfin-dis.c (gregs): Clip index to prevent overflow. | |
| 686 | (regs): Likewise. | |
| 687 | (regs_lo): Likewise. | |
| 688 | (regs_hi): Likewise. | |
| 689 | ||
| e64519d1 NC |
690 | 2017-06-14 Nick Clifton <nickc@redhat.com> |
| 691 | ||
| 692 | PR binutils/21576 | |
| 693 | * score7-dis.c (score_opcodes): Add sentinel. | |
| 694 | ||
| 6394c606 YQ |
695 | 2017-06-14 Yao Qi <yao.qi@linaro.org> |
| 696 | ||
| 697 | * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. | |
| 698 | * arm-dis.c: Likewise. | |
| 699 | * ia64-dis.c: Likewise. | |
| 700 | * mips-dis.c: Likewise. | |
| 701 | * spu-dis.c: Likewise. | |
| 702 | * disassemble.h (print_insn_aarch64): New declaration, moved from | |
| 703 | include/dis-asm.h. | |
| 704 | (print_insn_big_arm, print_insn_big_mips): Likewise. | |
| 705 | (print_insn_i386, print_insn_ia64): Likewise. | |
| 706 | (print_insn_little_arm, print_insn_little_mips): Likewise. | |
| 707 | ||
| db5fa770 NC |
708 | 2017-06-14 Nick Clifton <nickc@redhat.com> |
| 709 | ||
| 710 | PR binutils/21587 | |
| 711 | * rx-decode.opc: Include libiberty.h | |
| 712 | (GET_SCALE): New macro - validates access to SCALE array. | |
| 713 | (GET_PSCALE): New macro - validates access to PSCALE array. | |
| 714 | (DIs, SIs, S2Is, rx_disp): Use new macros. | |
| 715 | * rx-decode.c: Regenerate. | |
| 716 | ||
| 05c966f3 AV |
717 | 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 718 | ||
| 719 | * arm-dis.c (print_insn_arm): Remove bogus entry for bx. | |
| 720 | ||
| 10045478 AK |
721 | 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com> |
| 722 | ||
| 723 | * arc-dis.c (enforced_isa_mask): Declare. | |
| 724 | (cpu_types): Likewise. | |
| 725 | (parse_cpu_option): New function. | |
| 726 | (parse_disassembler_options): Use it. | |
| 727 | (print_insn_arc): Use enforced_isa_mask. | |
| 728 | (print_arc_disassembler_options): Document new options. | |
| 729 | ||
| 88c1242d YQ |
730 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 731 | ||
| 732 | * alpha-dis.c: Include disassemble.h, don't include | |
| 733 | dis-asm.h. | |
| 734 | * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. | |
| 735 | * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. | |
| 736 | * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. | |
| 737 | * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. | |
| 738 | * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. | |
| 739 | * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. | |
| 740 | * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. | |
| 741 | * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. | |
| 742 | * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. | |
| 743 | * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. | |
| 744 | * moxie-dis.c, msp430-dis.c, mt-dis.c: | |
| 745 | * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. | |
| 746 | * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. | |
| 747 | * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. | |
| 748 | * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. | |
| 749 | * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. | |
| 750 | * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. | |
| 751 | * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. | |
| 752 | * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. | |
| 753 | * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. | |
| 754 | * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. | |
| 755 | * z80-dis.c, z8k-dis.c: Likewise. | |
| 756 | * disassemble.h: New file. | |
| 757 | ||
| ab20fa4a YQ |
758 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 759 | ||
| 760 | * rl78-dis.c (rl78_get_disassembler): If parameter abfd | |
| 761 | is NULL, set cpu to E_FLAG_RL78_ANY_CPU. | |
| 762 | ||
| 003ca0fd YQ |
763 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 764 | ||
| 765 | * disassemble.c (disassembler): Add arguments a, big and mach. | |
| 766 | Use them. | |
| 767 | ||
| 04ef582a L |
768 | 2017-05-22 H.J. Lu <hongjiu.lu@intel.com> |
| 769 | ||
| 770 | * i386-dis.c (NOTRACK_Fixup): New. | |
| 771 | (NOTRACK): Likewise. | |
| 772 | (NOTRACK_PREFIX): Likewise. | |
| 773 | (last_active_prefix): Likewise. | |
| 774 | (reg_table): Use NOTRACK on indirect call and jmp. | |
| 775 | (ckprefix): Set last_active_prefix. | |
| 776 | (prefix_name): Return "notrack" for NOTRACK_PREFIX. | |
| 777 | * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. | |
| 778 | * i386-opc.h (NoTrackPrefixOk): New. | |
| 779 | (i386_opcode_modifier): Add notrackprefixok. | |
| 780 | * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. | |
| 781 | Add notrack. | |
| 782 | * i386-tbl.h: Regenerated. | |
| 783 | ||
| 64517994 JM |
784 | 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 785 | ||
| 786 | * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. | |
| 787 | (X_IMM2): Define. | |
| 788 | (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and | |
| 789 | bfd_mach_sparc_v9m8. | |
| 790 | (print_insn_sparc): Handle new operand types. | |
| 791 | * sparc-opc.c (MASK_M8): Define. | |
| 792 | (v6): Add MASK_M8. | |
| 793 | (v6notlet): Likewise. | |
| 794 | (v7): Likewise. | |
| 795 | (v8): Likewise. | |
| 796 | (v9): Likewise. | |
| 797 | (v9a): Likewise. | |
| 798 | (v9b): Likewise. | |
| 799 | (v9c): Likewise. | |
| 800 | (v9d): Likewise. | |
| 801 | (v9e): Likewise. | |
| 802 | (v9v): Likewise. | |
| 803 | (v9m): Likewise. | |
| 804 | (v9andleon): Likewise. | |
| 805 | (m8): Define. | |
| 806 | (HWS_VM8): Define. | |
| 807 | (HWS2_VM8): Likewise. | |
| 808 | (sparc_opcode_archs): Add entry for "m8". | |
| 809 | (sparc_opcodes): Add OSA2017 and M8 instructions | |
| 810 | dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, | |
| 811 | fpx{ll,ra,rl}64x, | |
| 812 | ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, | |
| 813 | ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, | |
| 814 | revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, | |
| 815 | stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. | |
| 816 | (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, | |
| 817 | ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, | |
| 818 | ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, | |
| 819 | ASI_CORE_SELECT_COMMIT_NHT. | |
| 820 | ||
| 535b785f AM |
821 | 2017-05-18 Alan Modra <amodra@gmail.com> |
| 822 | ||
| 823 | * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE. | |
| 824 | * aarch64-dis.c: Likewise. | |
| 825 | * aarch64-gen.c: Likewise. | |
| 826 | * aarch64-opc.c: Likewise. | |
| 827 | ||
| 25499ac7 MR |
828 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
| 829 | Matthew Fortune <matthew.fortune@imgtec.com> | |
| 830 | ||
| 831 | * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and | |
| 832 | ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. | |
| 833 | (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. | |
| 834 | (print_insn_arg) <OP_REG28>: Add handler. | |
| 835 | (validate_insn_args) <OP_REG28>: Handle. | |
| 836 | (print_mips16_insn_arg): Handle MIPS16 instructions that require | |
| 837 | 32-bit encoding and 9-bit immediates. | |
| 838 | (print_insn_mips16): Handle MIPS16 instructions that require | |
| 839 | 32-bit encoding and MFC0/MTC0 operand decoding. | |
| 840 | * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> | |
| 841 | <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. | |
| 842 | (RD_C0, WR_C0, E2, E2MT): New macros. | |
| 843 | (mips16_opcodes): Add entries for MIPS16e2 instructions: | |
| 844 | GP-relative "addiu" and its "addu" spelling, "andi", "cache", | |
| 845 | "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", | |
| 846 | "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", | |
| 847 | "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", | |
| 848 | "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" | |
| 849 | instructions, "swl", "swr", "sync" and its "sync_acquire", | |
| 850 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, | |
| 851 | "xori", "dmt", "dvpe", "emt" and "evpe". Add split | |
| 852 | regular/extended entries for original MIPS16 ISA revision | |
| 853 | instructions whose extended forms are subdecoded in the MIPS16e2 | |
| 854 | ISA revision: "li", "sll" and "srl". | |
| 855 | ||
| fdfb4752 MR |
856 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
| 857 | ||
| 858 | * mips-dis.c (print_insn_args) <default>: Remove an MT ASE | |
| 859 | reference in CP0 move operand decoding. | |
| 860 | ||
| a4f89915 MR |
861 | 2017-05-12 Maciej W. Rozycki <macro@imgtec.com> |
| 862 | ||
| 863 | * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand | |
| 864 | type to hexadecimal. | |
| 865 | (mips16_opcodes): Add operandless "break" and "sdbbp" entries. | |
| 866 | ||
| 99e2d67a MR |
867 | 2017-05-11 Maciej W. Rozycki <macro@imgtec.com> |
| 868 | ||
| 869 | * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", | |
| 870 | "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release", | |
| 871 | "sync_rmb" and "sync_wmb" as aliases. | |
| 872 | * micromips-opc.c (micromips_opcodes): Mark "sync_acquire", | |
| 873 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. | |
| 874 | ||
| 53a346d8 CZ |
875 | 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> |
| 876 | ||
| 877 | * arc-dis.c (parse_option): Update quarkse_em option.. | |
| 878 | * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to | |
| 879 | QUARKSE1. | |
| 880 | (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. | |
| 881 | ||
| f91d48de KC |
882 | 2017-05-03 Kito Cheng <kito.cheng@gmail.com> |
| 883 | ||
| 884 | * riscv-dis.c (print_insn_args): Handle 'Co' operands. | |
| 885 | ||
| 43e379d7 MC |
886 | 2017-05-01 Michael Clark <michaeljclark@mac.com> |
| 887 | ||
| 888 | * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary | |
| 889 | register. | |
| 890 | ||
| a4ddc54e MR |
891 | 2017-05-02 Maciej W. Rozycki <macro@imgtec.com> |
| 892 | ||
| 893 | * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps | |
| 894 | and branches and not synthetic data instructions. | |
| 895 | ||
| fe50e98c BE |
896 | 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de> |
| 897 | ||
| 898 | * arm-dis.c (print_insn_thumb32): Fix value_in_comment. | |
| 899 | ||
| 126124cc CZ |
900 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| 901 | ||
| 902 | * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. | |
| 903 | * arc-opc.c (insert_r13el): New function. | |
| 904 | (R13_EL): Define. | |
| 905 | * arc-tbl.h: Add new enter/leave variants. | |
| 906 | ||
| be6a24d8 CZ |
907 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| 908 | ||
| 909 | * arc-tbl.h: Reorder NOP entry to be before MOV instructions. | |
| 910 | ||
| 0348fd79 MR |
911 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| 912 | ||
| 913 | * mips-dis.c (print_mips_disassembler_options): Add | |
| 914 | `no-aliases'. | |
| 915 | ||
| 6e3d1f07 MR |
916 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| 917 | ||
| 918 | * mips16-opc.c (AL): New macro. | |
| 919 | (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms | |
| 920 | of "ld" and "lw" as aliases. | |
| 921 | ||
| 957f6b39 TC |
922 | 2017-04-24 Tamar Christina <tamar.christina@arm.com> |
| 923 | ||
| 924 | * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE | |
| 925 | arguments. | |
| 926 | ||
| a8cc8a54 AM |
927 | 2017-04-22 Alexander Fedotov <alfedotov@gmail.com> |
| 928 | Alan Modra <amodra@gmail.com> | |
| 929 | ||
| 930 | * ppc-opc.c (ELEV): Define. | |
| 931 | (vle_opcodes): Add se_rfgi and e_sc. | |
| 932 | (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx | |
| 933 | for E200Z4. | |
| 934 | ||
| 3ab87b68 JM |
935 | 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 936 | ||
| 937 | * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9. | |
| 938 | ||
| 792f174f NC |
939 | 2017-04-21 Nick Clifton <nickc@redhat.com> |
| 940 | ||
| 941 | PR binutils/21380 | |
| 942 | * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R, | |
| 943 | LD3R and LD4R. | |
| 944 | ||
| 42742084 AM |
945 | 2017-04-13 Alan Modra <amodra@gmail.com> |
| 946 | ||
| 947 | * epiphany-desc.c: Regenerate. | |
| 948 | * fr30-desc.c: Regenerate. | |
| 949 | * frv-desc.c: Regenerate. | |
| 950 | * ip2k-desc.c: Regenerate. | |
| 951 | * iq2000-desc.c: Regenerate. | |
| 952 | * lm32-desc.c: Regenerate. | |
| 953 | * m32c-desc.c: Regenerate. | |
| 954 | * m32r-desc.c: Regenerate. | |
| 955 | * mep-desc.c: Regenerate. | |
| 956 | * mt-desc.c: Regenerate. | |
| 957 | * or1k-desc.c: Regenerate. | |
| 958 | * xc16x-desc.c: Regenerate. | |
| 959 | * xstormy16-desc.c: Regenerate. | |
| 960 | ||
| 9a85b496 AM |
961 | 2017-04-11 Alan Modra <amodra@gmail.com> |
| 962 | ||
| ef85eab0 | 963 | * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2, |
| c03dc33b AM |
964 | PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set |
| 965 | PPC_OPCODE_TMR for e6500. | |
| 9a85b496 AM |
966 | * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. |
| 967 | (PPCVEC3): Define as PPC_OPCODE_POWER9. | |
| 9570835e AM |
968 | (PPCVSX2): Define as PPC_OPCODE_POWER8. |
| 969 | (PPCVSX3): Define as PPC_OPCODE_POWER9. | |
| ef85eab0 | 970 | (PPCHTM): Define as PPC_OPCODE_POWER8. |
| c03dc33b | 971 | (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
| 9a85b496 | 972 | |
| 62adc510 AM |
973 | 2017-04-10 Alan Modra <amodra@gmail.com> |
| 974 | ||
| 975 | * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440. | |
| 976 | * ppc-opc.c (MULHW): Add PPC_OPCODE_476. | |
| 977 | (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit | |
| 978 | removal of PPC_OPCODE_440 from ppc476 cpu selection bits. | |
| 979 | ||
| aa808707 PC |
980 | 2017-04-09 Pip Cet <pipcet@gmail.com> |
| 981 | ||
| 982 | * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify | |
| 983 | appropriate floating-point precision directly. | |
| 984 | ||
| ac8f0f72 AM |
985 | 2017-04-07 Alan Modra <amodra@gmail.com> |
| 986 | ||
| 987 | * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl, | |
| 988 | lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx, | |
| 989 | lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx, | |
| 990 | lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only | |
| 991 | vector instructions with E6500 not PPCVEC2. | |
| 992 | ||
| 62ecb94c PC |
993 | 2017-04-06 Pip Cet <pipcet@gmail.com> |
| 994 | ||
| 995 | * Makefile.am: Add wasm32-dis.c. | |
| 996 | * configure.ac: Add wasm32-dis.c to wasm32 target. | |
| 997 | * disassemble.c: Add wasm32 disassembler code. | |
| 998 | * wasm32-dis.c: New file. | |
| 999 | * Makefile.in: Regenerate. | |
| 1000 | * configure: Regenerate. | |
| 1001 | * po/POTFILES.in: Regenerate. | |
| 1002 | * po/opcodes.pot: Regenerate. | |
| 1003 | ||
| f995bbe8 PA |
1004 | 2017-04-05 Pedro Alves <palves@redhat.com> |
| 1005 | ||
| 1006 | * arc-dis.c (parse_option, parse_disassembler_options): Constify. | |
| 1007 | * arm-dis.c (parse_arm_disassembler_options): Constify. | |
| 1008 | * ppc-dis.c (powerpc_init_dialect): Constify local. | |
| 1009 | * vax-dis.c (parse_disassembler_options): Constify. | |
| 1010 | ||
| b5292032 PD |
1011 | 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> |
| 1012 | ||
| 1013 | * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to | |
| 1014 | RISCV_GP_SYMBOL. | |
| 1015 | ||
| f96bd6c2 PC |
1016 | 2017-03-30 Pip Cet <pipcet@gmail.com> |
| 1017 | ||
| 1018 | * configure.ac: Add (empty) bfd_wasm32_arch target. | |
| 1019 | * configure: Regenerate | |
| 1020 | * po/opcodes.pot: Regenerate. | |
| 1021 | ||
| f7c514a3 JM |
1022 | 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com> |
| 1023 | ||
| 1024 | Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, & | |
| 1025 | OSA2015. | |
| 1026 | * opcodes/sparc-opc.c (asi_table): New ASIs. | |
| 1027 | ||
| 52be03fd AM |
1028 | 2017-03-29 Alan Modra <amodra@gmail.com> |
| 1029 | ||
| 1030 | * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add | |
| 1031 | "raw" option. | |
| 1032 | (lookup_powerpc): Don't special case -1 dialect. Handle | |
| 1033 | PPC_OPCODE_RAW. | |
| 1034 | (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first | |
| 1035 | lookup_powerpc call, pass it on second. | |
| 1036 | ||
| 9b753937 AM |
1037 | 2017-03-27 Alan Modra <amodra@gmail.com> |
| 1038 | ||
| 1039 | PR 21303 | |
| 1040 | * ppc-dis.c (struct ppc_mopt): Comment. | |
| 1041 | (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. | |
| 1042 | ||
| c0c31e91 RZ |
1043 | 2017-03-27 Rinat Zelig <rinat@mellanox.com> |
| 1044 | ||
| 1045 | * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. | |
| 1046 | * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, | |
| 1047 | F_NPS_M, F_NPS_CORE, F_NPS_ALL. | |
| 1048 | (insert_nps_misc_imm_offset): New function. | |
| 1049 | (extract_nps_misc imm_offset): New function. | |
| 1050 | (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. | |
| 1051 | (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. | |
| 1052 | ||
| 2253c8f0 AK |
1053 | 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 1054 | ||
| 1055 | * s390-mkopc.c (main): Remove vx2 check. | |
| 1056 | * s390-opc.txt: Remove vx2 instruction flags. | |
| 1057 | ||
| 645d3342 RZ |
1058 | 2017-03-21 Rinat Zelig <rinat@mellanox.com> |
| 1059 | ||
| 1060 | * arc-nps400-tbl.h: Add cp32/cp16 instructions format. | |
| 1061 | * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. | |
| 1062 | (insert_nps_imm_offset): New function. | |
| 1063 | (extract_nps_imm_offset): New function. | |
| 1064 | (insert_nps_imm_entry): New function. | |
| 1065 | (extract_nps_imm_entry): New function. | |
| 1066 | ||
| 4b94dd2d AM |
1067 | 2017-03-17 Alan Modra <amodra@gmail.com> |
| 1068 | ||
| 1069 | PR 21248 | |
| 1070 | * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33, | |
| 1071 | mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after | |
| 1072 | those spr mnemonics they alias. Similarly for mtibatl, mtibatu. | |
| 1073 | ||
| b416fe87 KC |
1074 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 1075 | ||
| 1076 | * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. | |
| 1077 | <c.andi>: Likewise. | |
| 1078 | <c.addiw> Likewise. | |
| 1079 | ||
| 03b039a5 KC |
1080 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 1081 | ||
| 1082 | * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode. | |
| 1083 | ||
| 2c232b83 AW |
1084 | 2017-03-13 Andrew Waterman <andrew@sifive.com> |
| 1085 | ||
| 1086 | * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. | |
| 1087 | <srl> Likewise. | |
| 1088 | <srai> Likewise. | |
| 1089 | <sra> Likewise. | |
| 1090 | ||
| 86fa6981 L |
1091 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 1092 | ||
| 1093 | * i386-gen.c (opcode_modifiers): Replace S with Load. | |
| 1094 | * i386-opc.h (S): Removed. | |
| 1095 | (Load): New. | |
| 1096 | (i386_opcode_modifier): Replace s with load. | |
| 1097 | * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} | |
| 1098 | and {evex}. Replace S with Load. | |
| 1099 | * i386-tbl.h: Regenerated. | |
| 1100 | ||
| c1fe188b L |
1101 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 1102 | ||
| 1103 | * i386-opc.tbl: Use CpuCET on rdsspq. | |
| 1104 | * i386-tbl.h: Regenerated. | |
| 1105 | ||
| 4b8b687e PB |
1106 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| 1107 | ||
| 1108 | * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; | |
| 1109 | <vsx>: Do not use PPC_OPCODE_VSX3; | |
| 1110 | ||
| 1437d063 PB |
1111 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| 1112 | ||
| 1113 | * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. | |
| 1114 | ||
| 603555e5 L |
1115 | 2017-03-06 H.J. Lu <hongjiu.lu@intel.com> |
| 1116 | ||
| 1117 | * i386-dis.c (REG_0F1E_MOD_3): New enum. | |
| 1118 | (MOD_0F1E_PREFIX_1): Likewise. | |
| 1119 | (MOD_0F38F5_PREFIX_2): Likewise. | |
| 1120 | (MOD_0F38F6_PREFIX_0): Likewise. | |
| 1121 | (RM_0F1E_MOD_3_REG_7): Likewise. | |
| 1122 | (PREFIX_MOD_0_0F01_REG_5): Likewise. | |
| 1123 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. | |
| 1124 | (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. | |
| 1125 | (PREFIX_0F1E): Likewise. | |
| 1126 | (PREFIX_MOD_0_0FAE_REG_5): Likewise. | |
| 1127 | (PREFIX_0F38F5): Likewise. | |
| 1128 | (dis386_twobyte): Use PREFIX_0F1E. | |
| 1129 | (reg_table): Add REG_0F1E_MOD_3. | |
| 1130 | (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, | |
| 1131 | PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, | |
| 1132 | PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update | |
| 1133 | PREFIX_0FAE_REG_6 and PREFIX_0F38F6. | |
| 1134 | (three_byte_table): Use PREFIX_0F38F5. | |
| 1135 | (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. | |
| 1136 | Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. | |
| 1137 | (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, | |
| 1138 | RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and | |
| 1139 | PREFIX_MOD_3_0F01_REG_5_RM_2. | |
| 1140 | * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. | |
| 1141 | (cpu_flags): Add CpuCET. | |
| 1142 | * i386-opc.h (CpuCET): New enum. | |
| 1143 | (CpuUnused): Commented out. | |
| 1144 | (i386_cpu_flags): Add cpucet. | |
| 1145 | * i386-opc.tbl: Add Intel CET instructions. | |
| 1146 | * i386-init.h: Regenerated. | |
| 1147 | * i386-tbl.h: Likewise. | |
| 1148 | ||
| 73f07bff AM |
1149 | 2017-03-06 Alan Modra <amodra@gmail.com> |
| 1150 | ||
| 1151 | PR 21124 | |
| 1152 | * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) | |
| 1153 | (extract_raq, extract_ras, extract_rbx): New functions. | |
| 1154 | (powerpc_operands): Use opposite corresponding insert function. | |
| 1155 | (Q_MASK): Define. | |
| 1156 | (powerpc_opcodes): Apply Q_MASK to all quad insns with even | |
| 1157 | register restriction. | |
| 1158 | ||
| 65b48a81 PB |
1159 | 2017-02-28 Peter Bergner <bergner@vnet.ibm.com> |
| 1160 | ||
| 1161 | * disassemble.c Include "safe-ctype.h". | |
| 1162 | (disassemble_init_for_target): Handle s390 init. | |
| 1163 | (remove_whitespace_and_extra_commas): New function. | |
| 1164 | (disassembler_options_cmp): Likewise. | |
| 1165 | * arm-dis.c: Include "libiberty.h". | |
| 1166 | (NUM_ELEM): Delete. | |
| 1167 | (regnames): Use long disassembler style names. | |
| 1168 | Add force-thumb and no-force-thumb options. | |
| 1169 | (NUM_ARM_REGNAMES): Rename from this... | |
| 1170 | (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. | |
| 1171 | (get_arm_regname_num_options): Delete. | |
| 1172 | (set_arm_regname_option): Likewise. | |
| 1173 | (get_arm_regnames): Likewise. | |
| 1174 | (parse_disassembler_options): Likewise. | |
| 1175 | (parse_arm_disassembler_option): Rename from this... | |
| 1176 | (parse_arm_disassembler_options): ...to this. Make static. | |
| 1177 | Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. | |
| 1178 | (print_insn): Use parse_arm_disassembler_options. | |
| 1179 | (disassembler_options_arm): New function. | |
| 1180 | (print_arm_disassembler_options): Handle updated regnames. | |
| 1181 | * ppc-dis.c: Include "libiberty.h". | |
| 1182 | (ppc_opts): Add "32" and "64" entries. | |
| 1183 | (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. | |
| 1184 | (powerpc_init_dialect): Add break to switch statement. | |
| 1185 | Use new FOR_EACH_DISASSEMBLER_OPTION macro. | |
| 1186 | (disassembler_options_powerpc): New function. | |
| 1187 | (print_ppc_disassembler_options): Use ARRAY_SIZE. | |
| 1188 | Remove printing of "32" and "64". | |
| 1189 | * s390-dis.c: Include "libiberty.h". | |
| 1190 | (init_flag): Remove unneeded variable. | |
| 1191 | (struct s390_options_t): New structure type. | |
| 1192 | (options): New structure. | |
| 1193 | (init_disasm): Rename from this... | |
| 1194 | (disassemble_init_s390): ...to this. Add initializations for | |
| 1195 | current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. | |
| 1196 | (print_insn_s390): Delete call to init_disasm. | |
| 1197 | (disassembler_options_s390): New function. | |
| 1198 | (print_s390_disassembler_options): Print using information from | |
| 1199 | struct 'options'. | |
| 1200 | * po/opcodes.pot: Regenerate. | |
| 1201 | ||
| 15c7c1d8 JB |
1202 | 2017-02-28 Jan Beulich <jbeulich@suse.com> |
| 1203 | ||
| 1204 | * i386-dis.c (PCMPESTR_Fixup): New. | |
| 1205 | (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete. | |
| 1206 | (prefix_table): Use PCMPESTR_Fixup. | |
| 1207 | (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use | |
| 1208 | PCMPESTR_Fixup. | |
| 1209 | (vex_w_table): Delete VPCMPESTR{I,M} entries. | |
| 1210 | * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm): | |
| 1211 | Split 64-bit and non-64-bit variants. | |
| 1212 | * opcodes/i386-tbl.h: Re-generate. | |
| 1213 | ||
| 582e12bf RS |
1214 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| 1215 | ||
| 1216 | * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) | |
| 1217 | (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) | |
| 1218 | (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) | |
| 1219 | (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) | |
| 1220 | (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) | |
| 1221 | (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) | |
| 1222 | (OP_SVE_V_HSD): New macros. | |
| 1223 | (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) | |
| 1224 | (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) | |
| 1225 | (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. | |
| 1226 | (aarch64_opcode_table): Add new SVE instructions. | |
| 1227 | (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate | |
| 1228 | for rotation operands. Add new SVE operands. | |
| 1229 | * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. | |
| 1230 | (ins_sve_quad_index): Likewise. | |
| 1231 | (ins_imm_rotate): Split into... | |
| 1232 | (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. | |
| 1233 | * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... | |
| 1234 | (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two | |
| 1235 | functions. | |
| 1236 | (aarch64_ins_sve_addr_ri_s4): New function. | |
| 1237 | (aarch64_ins_sve_quad_index): Likewise. | |
| 1238 | (do_misc_encoding): Handle "MOV Zn.Q, Qm". | |
| 1239 | * aarch64-asm-2.c: Regenerate. | |
| 1240 | * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. | |
| 1241 | (ext_sve_quad_index): Likewise. | |
| 1242 | (ext_imm_rotate): Split into... | |
| 1243 | (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. | |
| 1244 | * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... | |
| 1245 | (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two | |
| 1246 | functions. | |
| 1247 | (aarch64_ext_sve_addr_ri_s4): New function. | |
| 1248 | (aarch64_ext_sve_quad_index): Likewise. | |
| 1249 | (aarch64_ext_sve_index): Allow quad indices. | |
| 1250 | (do_misc_decoding): Likewise. | |
| 1251 | * aarch64-dis-2.c: Regenerate. | |
| 1252 | * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New | |
| 1253 | aarch64_field_kinds. | |
| 1254 | (OPD_F_OD_MASK): Widen by one bit. | |
| 1255 | (OPD_F_NO_ZR): Bump accordingly. | |
| 1256 | (get_operand_field_width): New function. | |
| 1257 | * aarch64-opc.c (fields): Add new SVE fields. | |
| 1258 | (operand_general_constraint_met_p): Handle new SVE operands. | |
| 1259 | (aarch64_print_operand): Likewise. | |
| 1260 | * aarch64-opc-2.c: Regenerate. | |
| 1261 | ||
| f482d304 RS |
1262 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| 1263 | ||
| 1264 | * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... | |
| 1265 | (aarch64_feature_compnum): ...this. | |
| 1266 | (SIMD_V8_3): Replace with... | |
| 1267 | (COMPNUM): ...this. | |
| 1268 | (CNUM_INSN): New macro. | |
| 1269 | (aarch64_opcode_table): Use it for the complex number instructions. | |
| 1270 | ||
| 7db2c588 JB |
1271 | 2017-02-24 Jan Beulich <jbeulich@suse.com> |
| 1272 | ||
| 1273 | * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST. | |
| 1274 | ||
| 1e9d41d4 SL |
1275 | 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com> |
| 1276 | ||
| 1277 | Add support for associating SPARC ASIs with an architecture level. | |
| 1278 | * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. | |
| 1279 | * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ | |
| 1280 | decoding of SPARC ASIs. | |
| 1281 | ||
| 53c4d625 JB |
1282 | 2017-02-23 Jan Beulich <jbeulich@suse.com> |
| 1283 | ||
| 1284 | * i386-dis.c (get_valid_dis386): Don't special case VEX opcode | |
| 1285 | 82. For 3-byte VEX only special case opcode 77 in VEX_0F space. | |
| 1286 | ||
| 11648de5 JB |
1287 | 2017-02-21 Jan Beulich <jbeulich@suse.com> |
| 1288 | ||
| 1289 | * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand | |
| 1290 | 1 (instead of to itself). Correct typo. | |
| 1291 | ||
| f98d33be AW |
1292 | 2017-02-14 Andrew Waterman <andrew@sifive.com> |
| 1293 | ||
| 1294 | * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and | |
| 1295 | pseudoinstructions. | |
| 1296 | ||
| 773fb663 RS |
1297 | 2017-02-15 Richard Sandiford <richard.sandiford@arm.com> |
| 1298 | ||
| 1299 | * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. | |
| 1300 | (aarch64_sys_reg_supported_p): Handle them. | |
| 1301 | ||
| cc07cda6 CZ |
1302 | 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> |
| 1303 | ||
| 1304 | * arc-opc.c (UIMM6_20R): Define. | |
| 1305 | (SIMM12_20): Use above. | |
| 1306 | (SIMM12_20R): Define. | |
| 1307 | (SIMM3_5_S): Use above. | |
| 1308 | (UIMM7_A32_11R_S): Define. | |
| 1309 | (UIMM7_9_S): Use above. | |
| 1310 | (UIMM3_13R_S): Define. | |
| 1311 | (SIMM11_A32_7_S): Use above. | |
| 1312 | (SIMM9_8R): Define. | |
| 1313 | (UIMM10_A32_8_S): Use above. | |
| 1314 | (UIMM8_8R_S): Define. | |
| 1315 | (W6): Use above. | |
| 1316 | (arc_relax_opcodes): Use all above defines. | |
| 1317 | ||
| 66a5a740 VG |
1318 | 2017-02-15 Vineet Gupta <vgupta@synopsys.com> |
| 1319 | ||
| 1320 | * arc-regs.h: Distinguish some of the registers different on | |
| 1321 | ARC700 and HS38 cpus. | |
| 1322 | ||
| 7e0de605 AM |
1323 | 2017-02-14 Alan Modra <amodra@gmail.com> |
| 1324 | ||
| 1325 | PR 21118 | |
| 1326 | * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries | |
| 1327 | with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR. | |
| 1328 | ||
| 54064fdb AM |
1329 | 2017-02-11 Stafford Horne <shorne@gmail.com> |
| 1330 | Alan Modra <amodra@gmail.com> | |
| 1331 | ||
| 1332 | * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. | |
| 1333 | Use insn_bytes_value and insn_int_value directly instead. Don't | |
| 1334 | free allocated memory until function exit. | |
| 1335 | ||
| dce75bf9 NP |
1336 | 2017-02-10 Nicholas Piggin <npiggin@gmail.com> |
| 1337 | ||
| 1338 | * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. | |
| 1339 | ||
| 1b7e3d2f NC |
1340 | 2017-02-03 Nick Clifton <nickc@redhat.com> |
| 1341 | ||
| 1342 | PR 21096 | |
| 1343 | * aarch64-opc.c (print_register_list): Ensure that the register | |
| 1344 | list index will fir into the tb buffer. | |
| 1345 | (print_register_offset_address): Likewise. | |
| 1346 | * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf. | |
| 1347 | ||
| 8ec5cf65 AD |
1348 | 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com> |
| 1349 | ||
| 1350 | PR 21056 | |
| 1351 | * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel | |
| 1352 | instructions when the previous fetch packet ends with a 32-bit | |
| 1353 | instruction. | |
| 1354 | ||
| a1aa5e81 DD |
1355 | 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu> |
| 1356 | ||
| 1357 | * pru-opc.c: Remove vague reference to a future GDB port. | |
| 1358 | ||
| add3afb2 NC |
1359 | 2017-01-20 Nick Clifton <nickc@redhat.com> |
| 1360 | ||
| 1361 | * po/ga.po: Updated Irish translation. | |
| 1362 | ||
| c13a63b0 SN |
1363 | 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 1364 | ||
| 1365 | * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. | |
| 1366 | ||
| 9608051a YQ |
1367 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| 1368 | ||
| 1369 | * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 | |
| 1370 | if FETCH_DATA returns 0. | |
| 1371 | (m68k_scan_mask): Likewise. | |
| 1372 | (print_insn_m68k): Update code to handle -1 return value. | |
| 1373 | ||
| f622ea96 YQ |
1374 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| 1375 | ||
| 1376 | * m68k-dis.c (enum print_insn_arg_error): New. | |
| 1377 | (NEXTBYTE): Replace -3 with | |
| 1378 | PRINT_INSN_ARG_MEMORY_ERROR. | |
| 1379 | (NEXTULONG): Likewise. | |
| 1380 | (NEXTSINGLE): Likewise. | |
| 1381 | (NEXTDOUBLE): Likewise. | |
| 1382 | (NEXTDOUBLE): Likewise. | |
| 1383 | (NEXTPACKED): Likewise. | |
| 1384 | (FETCH_ARG): Likewise. | |
| 1385 | (FETCH_DATA): Update comments. | |
| 1386 | (print_insn_arg): Update comments. Replace magic numbers with | |
| 1387 | enum. | |
| 1388 | (match_insn_m68k): Likewise. | |
| 1389 | ||
| 620214f7 IT |
1390 | 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 1391 | ||
| 1392 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. | |
| 1393 | * i386-dis-evex.h (evex_table): Updated. | |
| 1394 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, | |
| 1395 | CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. | |
| 1396 | (cpu_flags): Add CpuAVX512_VPOPCNTDQ. | |
| 1397 | * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. | |
| 1398 | (i386_cpu_flags): Add cpuavx512_vpopcntdq. | |
| 1399 | * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. | |
| 1400 | * i386-init.h: Regenerate. | |
| 1401 | * i386-tbl.h: Ditto. | |
| 1402 | ||
| d95014a2 YQ |
1403 | 2017-01-12 Yao Qi <yao.qi@linaro.org> |
| 1404 | ||
| 1405 | * msp430-dis.c (msp430_singleoperand): Return -1 if | |
| 1406 | msp430dis_opcode_signed returns false. | |
| 1407 | (msp430_doubleoperand): Likewise. | |
| 1408 | (msp430_branchinstr): Return -1 if | |
| 1409 | msp430dis_opcode_unsigned returns false. | |
| 1410 | (msp430x_calla_instr): Likewise. | |
| 1411 | (print_insn_msp430): Likewise. | |
| 1412 | ||
| 0ae60c3e NC |
1413 | 2017-01-05 Nick Clifton <nickc@redhat.com> |
| 1414 | ||
| 1415 | PR 20946 | |
| 1416 | * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name | |
| 1417 | could not be matched. | |
| 1418 | (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning | |
| 1419 | NULL. | |
| 1420 | ||
| d74d4880 SN |
1421 | 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 1422 | ||
| 1423 | * aarch64-tbl.h (RCPC, RCPC_INSN): Define. | |
| 1424 | (aarch64_opcode_table): Use RCPC_INSN. | |
| 1425 | ||
| cc917fd9 KC |
1426 | 2017-01-03 Kito Cheng <kito.cheng@gmail.com> |
| 1427 | ||
| 1428 | * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA | |
| 1429 | extension. | |
| 1430 | * riscv-opcodes/all-opcodes: Likewise. | |
| 1431 | ||
| b52d3cfc DP |
1432 | 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org> |
| 1433 | ||
| 1434 | * riscv-dis.c (print_insn_args): Add fall through comment. | |
| 1435 | ||
| f90c58d5 NC |
1436 | 2017-01-03 Nick Clifton <nickc@redhat.com> |
| 1437 | ||
| 1438 | * po/sr.po: New Serbian translation. | |
| 1439 | * configure.ac (ALL_LINGUAS): Add sr. | |
| 1440 | * configure: Regenerate. | |
| 1441 | ||
| f47b0d4a AM |
1442 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| 1443 | ||
| 1444 | * epiphany-desc.h: Regenerate. | |
| 1445 | * epiphany-opc.h: Regenerate. | |
| 1446 | * fr30-desc.h: Regenerate. | |
| 1447 | * fr30-opc.h: Regenerate. | |
| 1448 | * frv-desc.h: Regenerate. | |
| 1449 | * frv-opc.h: Regenerate. | |
| 1450 | * ip2k-desc.h: Regenerate. | |
| 1451 | * ip2k-opc.h: Regenerate. | |
| 1452 | * iq2000-desc.h: Regenerate. | |
| 1453 | * iq2000-opc.h: Regenerate. | |
| 1454 | * lm32-desc.h: Regenerate. | |
| 1455 | * lm32-opc.h: Regenerate. | |
| 1456 | * m32c-desc.h: Regenerate. | |
| 1457 | * m32c-opc.h: Regenerate. | |
| 1458 | * m32r-desc.h: Regenerate. | |
| 1459 | * m32r-opc.h: Regenerate. | |
| 1460 | * mep-desc.h: Regenerate. | |
| 1461 | * mep-opc.h: Regenerate. | |
| 1462 | * mt-desc.h: Regenerate. | |
| 1463 | * mt-opc.h: Regenerate. | |
| 1464 | * or1k-desc.h: Regenerate. | |
| 1465 | * or1k-opc.h: Regenerate. | |
| 1466 | * xc16x-desc.h: Regenerate. | |
| 1467 | * xc16x-opc.h: Regenerate. | |
| 1468 | * xstormy16-desc.h: Regenerate. | |
| 1469 | * xstormy16-opc.h: Regenerate. | |
| 1470 | ||
| 2571583a AM |
1471 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| 1472 | ||
| 1473 | Update year range in copyright notice of all files. | |
| 1474 | ||
| 5c1ad6b5 | 1475 | For older changes see ChangeLog-2016 |
| 3499769a | 1476 | \f |
| 5c1ad6b5 | 1477 | Copyright (C) 2017 Free Software Foundation, Inc. |
| 3499769a AM |
1478 | |
| 1479 | Copying and distribution of this file, with or without modification, | |
| 1480 | are permitted in any medium without royalty provided the copyright | |
| 1481 | notice and this notice are preserved. | |
| 1482 | ||
| 1483 | Local Variables: | |
| 1484 | mode: change-log | |
| 1485 | left-margin: 8 | |
| 1486 | fill-column: 74 | |
| 1487 | version-control: never | |
| 1488 | End: |