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gdbarch: Use an anonymous union for target data in `gdbarch_info'
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7cbc739c
NC		 12017-07-25 Nick Clifton <nickc@redhat.com>
2
3 PR 21739
4 * arc-opc.c (insert_rhv2): Use lower case first letter in error
5 message.
6 (insert_r0): Likewise.
7 (insert_r1): Likewise.
8 (insert_r2): Likewise.
9 (insert_r3): Likewise.
10 (insert_sp): Likewise.
11 (insert_gp): Likewise.
12 (insert_pcl): Likewise.
13 (insert_blink): Likewise.
14 (insert_ilink1): Likewise.
15 (insert_ilink2): Likewise.
16 (insert_ras): Likewise.
17 (insert_rbs): Likewise.
18 (insert_rcs): Likewise.
19 (insert_simm3s): Likewise.
20 (insert_rrange): Likewise.
21 (insert_r13el): Likewise.
22 (insert_fpel): Likewise.
23 (insert_blinkel): Likewise.
24 (insert_pclel): Likewise.
25 (insert_nps_bitop_size_2b): Likewise.
26 (insert_nps_imm_offset): Likewise.
27 (insert_nps_imm_entry): Likewise.
28 (insert_nps_size_16bit): Likewise.
29 (insert_nps_##NAME##_pos): Likewise.
30 (insert_nps_##NAME): Likewise.
31 (insert_nps_bitop_ins_ext): Likewise.
32 (insert_nps_##NAME): Likewise.
33 (insert_nps_min_hofs): Likewise.
34 (insert_nps_##NAME): Likewise.
35 (insert_nps_rbdouble_64): Likewise.
36 (insert_nps_misc_imm_offset): Likewise.
37 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
38 option description.
39
7684e580
JW		 402017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
41 Jiong Wang <jiong.wang@arm.com>
42
43 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
44 correct the print.
45 * aarch64-dis-2.c: Regenerated.
46
47826cdb
AK		 472017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
48
49 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
50 table.
51
2d2dbad0
NC		 522017-07-20 Nick Clifton <nickc@redhat.com>
53
54 * po/de.po: Updated German translation.
55
70b448ba 562017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
57
58 * arc-regs.h (sec_stat): New aux register.
59 (aux_kernel_sp): Likewise.
60 (aux_sec_u_sp): Likewise.
61 (aux_sec_k_sp): Likewise.
62 (sec_vecbase_build): Likewise.
63 (nsc_table_top): Likewise.
64 (nsc_table_base): Likewise.
65 (ersec_stat): Likewise.
66 (aux_sec_except): Likewise.
67
7179e0e6
CZ		 682017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
69
70 * arc-opc.c (extract_uimm12_20): New function.
71 (UIMM12_20): New operand.
72 (SIMM3_5_S): Adjust.
73 * arc-tbl.h (sjli): Add new instruction.
74
684d5a10
JEM		 752017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
76 John Eric Martin <John.Martin@emmicro-us.com>
77
78 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
79 (UIMM3_23): Adjust accordingly.
80 * arc-regs.h: Add/correct jli_base register.
81 * arc-tbl.h (jli_s): Likewise.
82
de194d85
YC		 832017-07-18 Nick Clifton <nickc@redhat.com>
84
85 PR 21775
86 * aarch64-opc.c: Fix spelling typos.
87 * i386-dis.c: Likewise.
88
0f6329bd
RB		 892017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
90
91 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
92 max_addr_offset and octets variables to size_t.
93
429d795d
AM		 942017-07-12 Alan Modra <amodra@gmail.com>
95
96 * po/da.po: Update from translationproject.org/latest/opcodes/.
97 * po/de.po: Likewise.
98 * po/es.po: Likewise.
99 * po/fi.po: Likewise.
100 * po/fr.po: Likewise.
101 * po/id.po: Likewise.
102 * po/it.po: Likewise.
103 * po/nl.po: Likewise.
104 * po/pt_BR.po: Likewise.
105 * po/ro.po: Likewise.
106 * po/sv.po: Likewise.
107 * po/tr.po: Likewise.
108 * po/uk.po: Likewise.
109 * po/vi.po: Likewise.
110 * po/zh_CN.po: Likewise.
111
4162bb66
AM		 1122017-07-11 Yao Qi <yao.qi@linaro.org>
113 Alan Modra <amodra@gmail.com>
114
115 * cgen.sh: Mark generated files read-only.
116 * epiphany-asm.c: Regenerate.
117 * epiphany-desc.c: Regenerate.
118 * epiphany-desc.h: Regenerate.
119 * epiphany-dis.c: Regenerate.
120 * epiphany-ibld.c: Regenerate.
121 * epiphany-opc.c: Regenerate.
122 * epiphany-opc.h: Regenerate.
123 * fr30-asm.c: Regenerate.
124 * fr30-desc.c: Regenerate.
125 * fr30-desc.h: Regenerate.
126 * fr30-dis.c: Regenerate.
127 * fr30-ibld.c: Regenerate.
128 * fr30-opc.c: Regenerate.
129 * fr30-opc.h: Regenerate.
130 * frv-asm.c: Regenerate.
131 * frv-desc.c: Regenerate.
132 * frv-desc.h: Regenerate.
133 * frv-dis.c: Regenerate.
134 * frv-ibld.c: Regenerate.
135 * frv-opc.c: Regenerate.
136 * frv-opc.h: Regenerate.
137 * ip2k-asm.c: Regenerate.
138 * ip2k-desc.c: Regenerate.
139 * ip2k-desc.h: Regenerate.
140 * ip2k-dis.c: Regenerate.
141 * ip2k-ibld.c: Regenerate.
142 * ip2k-opc.c: Regenerate.
143 * ip2k-opc.h: Regenerate.
144 * iq2000-asm.c: Regenerate.
145 * iq2000-desc.c: Regenerate.
146 * iq2000-desc.h: Regenerate.
147 * iq2000-dis.c: Regenerate.
148 * iq2000-ibld.c: Regenerate.
149 * iq2000-opc.c: Regenerate.
150 * iq2000-opc.h: Regenerate.
151 * lm32-asm.c: Regenerate.
152 * lm32-desc.c: Regenerate.
153 * lm32-desc.h: Regenerate.
154 * lm32-dis.c: Regenerate.
155 * lm32-ibld.c: Regenerate.
156 * lm32-opc.c: Regenerate.
157 * lm32-opc.h: Regenerate.
158 * lm32-opinst.c: Regenerate.
159 * m32c-asm.c: Regenerate.
160 * m32c-desc.c: Regenerate.
161 * m32c-desc.h: Regenerate.
162 * m32c-dis.c: Regenerate.
163 * m32c-ibld.c: Regenerate.
164 * m32c-opc.c: Regenerate.
165 * m32c-opc.h: Regenerate.
166 * m32r-asm.c: Regenerate.
167 * m32r-desc.c: Regenerate.
168 * m32r-desc.h: Regenerate.
169 * m32r-dis.c: Regenerate.
170 * m32r-ibld.c: Regenerate.
171 * m32r-opc.c: Regenerate.
172 * m32r-opc.h: Regenerate.
173 * m32r-opinst.c: Regenerate.
174 * mep-asm.c: Regenerate.
175 * mep-desc.c: Regenerate.
176 * mep-desc.h: Regenerate.
177 * mep-dis.c: Regenerate.
178 * mep-ibld.c: Regenerate.
179 * mep-opc.c: Regenerate.
180 * mep-opc.h: Regenerate.
181 * mt-asm.c: Regenerate.
182 * mt-desc.c: Regenerate.
183 * mt-desc.h: Regenerate.
184 * mt-dis.c: Regenerate.
185 * mt-ibld.c: Regenerate.
186 * mt-opc.c: Regenerate.
187 * mt-opc.h: Regenerate.
188 * or1k-asm.c: Regenerate.
189 * or1k-desc.c: Regenerate.
190 * or1k-desc.h: Regenerate.
191 * or1k-dis.c: Regenerate.
192 * or1k-ibld.c: Regenerate.
193 * or1k-opc.c: Regenerate.
194 * or1k-opc.h: Regenerate.
195 * or1k-opinst.c: Regenerate.
196 * xc16x-asm.c: Regenerate.
197 * xc16x-desc.c: Regenerate.
198 * xc16x-desc.h: Regenerate.
199 * xc16x-dis.c: Regenerate.
200 * xc16x-ibld.c: Regenerate.
201 * xc16x-opc.c: Regenerate.
202 * xc16x-opc.h: Regenerate.
203 * xstormy16-asm.c: Regenerate.
204 * xstormy16-desc.c: Regenerate.
205 * xstormy16-desc.h: Regenerate.
206 * xstormy16-dis.c: Regenerate.
207 * xstormy16-ibld.c: Regenerate.
208 * xstormy16-opc.c: Regenerate.
209 * xstormy16-opc.h: Regenerate.
210
7639175c
AM		 2112017-07-07 Alan Modra <amodra@gmail.com>
212
213 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
214 * m32c-dis.c: Regenerate.
215 * mep-dis.c: Regenerate.
216
e4bdd679
BP		 2172017-07-05 Borislav Petkov <bp@suse.de>
218
219 * i386-dis.c: Enable ModRM.reg /6 aliases.
220
60c96dbf
RR		 2212017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
222
223 * opcodes/arm-dis.c: Support MVFR2 in disassembly
224 with vmrs and vmsr.
225
0d702cfe
TG		 2262017-07-04 Tristan Gingold <gingold@adacore.com>
227
228 * configure: Regenerate.
229
15e6ed8c
TG		 2302017-07-03 Tristan Gingold <gingold@adacore.com>
231
232 * po/opcodes.pot: Regenerate.
233
b1d3c886
MR		 2342017-06-30 Maciej W. Rozycki <macro@imgtec.com>
235
236 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
237 entries to the MSA ASE instruction block.
238
909b4e3d
MR		 2392017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
240 Maciej W. Rozycki <macro@imgtec.com>
241
242 * micromips-opc.c (XPA, XPAVZ): New macros.
243 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
244 "mthgc0".
245
f5b2fd52
MR		 2462017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
247 Maciej W. Rozycki <macro@imgtec.com>
248
249 * micromips-opc.c (I36): New macro.
250 (micromips_opcodes): Add "eretnc".
251
9785fc2a
MR		 2522017-06-30 Maciej W. Rozycki <macro@imgtec.com>
253 Andrew Bennett <andrew.bennett@imgtec.com>
254
255 * mips-dis.c (mips_calculate_combination_ases): Handle the
256 ASE_XPA_VIRT flag.
257 (parse_mips_ase_option): New function.
258 (parse_mips_dis_option): Factor out ASE option handling to the
259 new function. Call `mips_calculate_combination_ases'.
260 * mips-opc.c (XPAVZ): New macro.
261 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
262 "mfhgc0", "mthc0" and "mthgc0".
263
60804c53
MR		 2642017-06-29 Maciej W. Rozycki <macro@imgtec.com>
265
266 * mips-dis.c (mips_calculate_combination_ases): New function.
267 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
268 calculation to the new function.
269 (set_default_mips_dis_options): Call the new function.
270
2e74f9dd
AK		 2712017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
272
273 * arc-dis.c (parse_disassembler_options): Use
274 FOR_EACH_DISASSEMBLER_OPTION.
275
e1e94c49
AK		 2762017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
277
278 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
279 disassembler option strings.
280 (parse_cpu_option): Likewise.
281
65a55fbb
TC		 2822017-06-28 Tamar Christina <tamar.christina@arm.com>
283
284 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
285 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
286 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
287 (aarch64_feature_dotprod, DOT_INSN): New.
288 (udot, sdot): New.
289 * aarch64-dis-2.c: Regenerated.
290
c604a79a
JW		 2912017-06-28 Jiong Wang <jiong.wang@arm.com>
292
293 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
294
38bf472a
MR		 2952017-06-28 Maciej W. Rozycki <macro@imgtec.com>
296 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 297 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 298
299 * mips-formats.h (INT_BIAS): New macro.
300 (INT_ADJ): Redefine in INT_BIAS terms.
301 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
302 (mips_print_save_restore): New function.
303 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
304 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
305 call.
306 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
307 (print_mips16_insn_arg): Call `mips_print_save_restore' for
308 OP_SAVE_RESTORE_LIST handling, factored out from here.
309 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
310 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
311 (mips_builtin_opcodes): Add "restore" and "save" entries.
312 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
313 (IAMR2): New macro.
314 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
315
9bdfdbf9
AW		 3162017-06-23 Andrew Waterman <andrew@sifive.com>
317
318 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
319 alias; do not mark SLTI instruction as an alias.
320
2234eee6
L		 3212017-06-21 H.J. Lu <hongjiu.lu@intel.com>
322
323 * i386-dis.c (RM_0FAE_REG_5): Removed.
324 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
325 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
326 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
327 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
328 PREFIX_MOD_3_0F01_REG_5_RM_0.
329 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
330 PREFIX_MOD_3_0FAE_REG_5.
331 (mod_table): Update MOD_0FAE_REG_5.
332 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
333 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
334 * i386-tbl.h: Regenerated.
335
c2f76402
L		 3362017-06-21 H.J. Lu <hongjiu.lu@intel.com>
337
338 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
339 * i386-opc.tbl: Likewise.
340 * i386-tbl.h: Regenerated.
341
9fef80d6
L		 3422017-06-21 H.J. Lu <hongjiu.lu@intel.com>
343
344 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
345 and "jmp{&|}".
346 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
347 prefix.
348
0f6d864d
NC		 3492017-06-19 Nick Clifton <nickc@redhat.com>
350
351 PR binutils/21614
352 * score-dis.c (score_opcodes): Add sentinel.
353
e197589b
AM		 3542017-06-16 Alan Modra <amodra@gmail.com>
355
356 * rx-decode.c: Regenerate.
357
0d96e4df
L		 3582017-06-15 H.J. Lu <hongjiu.lu@intel.com>
359
360 PR binutils/21594
361 * i386-dis.c (OP_E_register): Check valid bnd register.
362 (OP_G): Likewise.
363
cd3ea7c6
NC		 3642017-06-15 Nick Clifton <nickc@redhat.com>
365
366 PR binutils/21595
367 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
368 range value.
369
63323b5b
NC		 3702017-06-15 Nick Clifton <nickc@redhat.com>
371
372 PR binutils/21588
373 * rl78-decode.opc (OP_BUF_LEN): Define.
374 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
375 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
376 array.
377 * rl78-decode.c: Regenerate.
378
08c7881b
NC		 3792017-06-15 Nick Clifton <nickc@redhat.com>
380
381 PR binutils/21586
382 * bfin-dis.c (gregs): Clip index to prevent overflow.
383 (regs): Likewise.
384 (regs_lo): Likewise.
385 (regs_hi): Likewise.
386
e64519d1
NC		 3872017-06-14 Nick Clifton <nickc@redhat.com>
388
389 PR binutils/21576
390 * score7-dis.c (score_opcodes): Add sentinel.
391
6394c606
YQ		 3922017-06-14 Yao Qi <yao.qi@linaro.org>
393
394 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
395 * arm-dis.c: Likewise.
396 * ia64-dis.c: Likewise.
397 * mips-dis.c: Likewise.
398 * spu-dis.c: Likewise.
399 * disassemble.h (print_insn_aarch64): New declaration, moved from
400 include/dis-asm.h.
401 (print_insn_big_arm, print_insn_big_mips): Likewise.
402 (print_insn_i386, print_insn_ia64): Likewise.
403 (print_insn_little_arm, print_insn_little_mips): Likewise.
404
db5fa770
NC		 4052017-06-14 Nick Clifton <nickc@redhat.com>
406
407 PR binutils/21587
408 * rx-decode.opc: Include libiberty.h
409 (GET_SCALE): New macro - validates access to SCALE array.
410 (GET_PSCALE): New macro - validates access to PSCALE array.
411 (DIs, SIs, S2Is, rx_disp): Use new macros.
412 * rx-decode.c: Regenerate.
413
05c966f3
AV		 4142017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
415
416 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
417
10045478
AK		 4182017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
419
420 * arc-dis.c (enforced_isa_mask): Declare.
421 (cpu_types): Likewise.
422 (parse_cpu_option): New function.
423 (parse_disassembler_options): Use it.
424 (print_insn_arc): Use enforced_isa_mask.
425 (print_arc_disassembler_options): Document new options.
426
88c1242d
YQ		 4272017-05-24 Yao Qi <yao.qi@linaro.org>
428
429 * alpha-dis.c: Include disassemble.h, don't include
430 dis-asm.h.
431 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
432 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
433 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
434 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
435 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
436 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
437 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
438 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
439 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
440 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
441 * moxie-dis.c, msp430-dis.c, mt-dis.c:
442 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
443 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
444 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
445 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
446 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
447 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
448 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
449 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
450 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
451 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
452 * z80-dis.c, z8k-dis.c: Likewise.
453 * disassemble.h: New file.
454
ab20fa4a
YQ		 4552017-05-24 Yao Qi <yao.qi@linaro.org>
456
457 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
458 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
459
003ca0fd
YQ		 4602017-05-24 Yao Qi <yao.qi@linaro.org>
461
462 * disassemble.c (disassembler): Add arguments a, big and mach.
463 Use them.
464
04ef582a
L		 4652017-05-22 H.J. Lu <hongjiu.lu@intel.com>
466
467 * i386-dis.c (NOTRACK_Fixup): New.
468 (NOTRACK): Likewise.
469 (NOTRACK_PREFIX): Likewise.
470 (last_active_prefix): Likewise.
471 (reg_table): Use NOTRACK on indirect call and jmp.
472 (ckprefix): Set last_active_prefix.
473 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
474 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
475 * i386-opc.h (NoTrackPrefixOk): New.
476 (i386_opcode_modifier): Add notrackprefixok.
477 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
478 Add notrack.
479 * i386-tbl.h: Regenerated.
480
64517994
JM		 4812017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
482
483 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
484 (X_IMM2): Define.
485 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
486 bfd_mach_sparc_v9m8.
487 (print_insn_sparc): Handle new operand types.
488 * sparc-opc.c (MASK_M8): Define.
489 (v6): Add MASK_M8.
490 (v6notlet): Likewise.
491 (v7): Likewise.
492 (v8): Likewise.
493 (v9): Likewise.
494 (v9a): Likewise.
495 (v9b): Likewise.
496 (v9c): Likewise.
497 (v9d): Likewise.
498 (v9e): Likewise.
499 (v9v): Likewise.
500 (v9m): Likewise.
501 (v9andleon): Likewise.
502 (m8): Define.
503 (HWS_VM8): Define.
504 (HWS2_VM8): Likewise.
505 (sparc_opcode_archs): Add entry for "m8".
506 (sparc_opcodes): Add OSA2017 and M8 instructions
507 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
508 fpx{ll,ra,rl}64x,
509 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
510 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
511 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
512 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
513 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
514 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
515 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
516 ASI_CORE_SELECT_COMMIT_NHT.
517
535b785f
AM		 5182017-05-18 Alan Modra <amodra@gmail.com>
519
520 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
521 * aarch64-dis.c: Likewise.
522 * aarch64-gen.c: Likewise.
523 * aarch64-opc.c: Likewise.
524
25499ac7
MR		 5252017-05-15 Maciej W. Rozycki <macro@imgtec.com>
526 Matthew Fortune <matthew.fortune@imgtec.com>
527
528 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
529 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
530 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
531 (print_insn_arg) <OP_REG28>: Add handler.
532 (validate_insn_args) <OP_REG28>: Handle.
533 (print_mips16_insn_arg): Handle MIPS16 instructions that require
534 32-bit encoding and 9-bit immediates.
535 (print_insn_mips16): Handle MIPS16 instructions that require
536 32-bit encoding and MFC0/MTC0 operand decoding.
537 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
538 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
539 (RD_C0, WR_C0, E2, E2MT): New macros.
540 (mips16_opcodes): Add entries for MIPS16e2 instructions:
541 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
542 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
543 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
544 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
545 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
546 instructions, "swl", "swr", "sync" and its "sync_acquire",
547 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
548 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
549 regular/extended entries for original MIPS16 ISA revision
550 instructions whose extended forms are subdecoded in the MIPS16e2
551 ISA revision: "li", "sll" and "srl".
552
fdfb4752
MR		 5532017-05-15 Maciej W. Rozycki <macro@imgtec.com>
554
555 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
556 reference in CP0 move operand decoding.
557
a4f89915
MR		 5582017-05-12 Maciej W. Rozycki <macro@imgtec.com>
559
560 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
561 type to hexadecimal.
562 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
563
99e2d67a
MR		 5642017-05-11 Maciej W. Rozycki <macro@imgtec.com>
565
566 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
567 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
568 "sync_rmb" and "sync_wmb" as aliases.
569 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
570 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
571
53a346d8
CZ		 5722017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
573
574 * arc-dis.c (parse_option): Update quarkse_em option..
575 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
576 QUARKSE1.
577 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
578
f91d48de
KC		 5792017-05-03 Kito Cheng <kito.cheng@gmail.com>
580
581 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
582
43e379d7
MC		 5832017-05-01 Michael Clark <michaeljclark@mac.com>
584
585 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
586 register.
587
a4ddc54e
MR		 5882017-05-02 Maciej W. Rozycki <macro@imgtec.com>
589
590 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
591 and branches and not synthetic data instructions.
592
fe50e98c
BE		 5932017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
594
595 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
596
126124cc
CZ		 5972017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
598
599 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
600 * arc-opc.c (insert_r13el): New function.
601 (R13_EL): Define.
602 * arc-tbl.h: Add new enter/leave variants.
603
be6a24d8
CZ		 6042017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
605
606 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
607
0348fd79
MR		 6082017-04-25 Maciej W. Rozycki <macro@imgtec.com>
609
610 * mips-dis.c (print_mips_disassembler_options): Add
611 `no-aliases'.
612
6e3d1f07
MR		 6132017-04-25 Maciej W. Rozycki <macro@imgtec.com>
614
615 * mips16-opc.c (AL): New macro.
616 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
617 of "ld" and "lw" as aliases.
618
957f6b39
TC		 6192017-04-24 Tamar Christina <tamar.christina@arm.com>
620
621 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
622 arguments.
623
a8cc8a54
AM		 6242017-04-22 Alexander Fedotov <alfedotov@gmail.com>
625 Alan Modra <amodra@gmail.com>
626
627 * ppc-opc.c (ELEV): Define.
628 (vle_opcodes): Add se_rfgi and e_sc.
629 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
630 for E200Z4.
631
3ab87b68
JM		 6322017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
633
634 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
635
792f174f
NC		 6362017-04-21 Nick Clifton <nickc@redhat.com>
637
638 PR binutils/21380
639 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
640 LD3R and LD4R.
641
42742084
AM		 6422017-04-13 Alan Modra <amodra@gmail.com>
643
644 * epiphany-desc.c: Regenerate.
645 * fr30-desc.c: Regenerate.
646 * frv-desc.c: Regenerate.
647 * ip2k-desc.c: Regenerate.
648 * iq2000-desc.c: Regenerate.
649 * lm32-desc.c: Regenerate.
650 * m32c-desc.c: Regenerate.
651 * m32r-desc.c: Regenerate.
652 * mep-desc.c: Regenerate.
653 * mt-desc.c: Regenerate.
654 * or1k-desc.c: Regenerate.
655 * xc16x-desc.c: Regenerate.
656 * xstormy16-desc.c: Regenerate.
657
9a85b496
AM		 6582017-04-11 Alan Modra <amodra@gmail.com>
659
ef85eab0 660 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 661 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
662 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 663 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
664 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 665 (PPCVSX2): Define as PPC_OPCODE_POWER8.
666 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 667 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 668 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 669
62adc510
AM		 6702017-04-10 Alan Modra <amodra@gmail.com>
671
672 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
673 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
674 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
675 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
676
aa808707
PC		 6772017-04-09 Pip Cet <pipcet@gmail.com>
678
679 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
680 appropriate floating-point precision directly.
681
ac8f0f72
AM		 6822017-04-07 Alan Modra <amodra@gmail.com>
683
684 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
685 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
686 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
687 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
688 vector instructions with E6500 not PPCVEC2.
689
62ecb94c
PC		 6902017-04-06 Pip Cet <pipcet@gmail.com>
691
692 * Makefile.am: Add wasm32-dis.c.
693 * configure.ac: Add wasm32-dis.c to wasm32 target.
694 * disassemble.c: Add wasm32 disassembler code.
695 * wasm32-dis.c: New file.
696 * Makefile.in: Regenerate.
697 * configure: Regenerate.
698 * po/POTFILES.in: Regenerate.
699 * po/opcodes.pot: Regenerate.
700
f995bbe8
PA		 7012017-04-05 Pedro Alves <palves@redhat.com>
702
703 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
704 * arm-dis.c (parse_arm_disassembler_options): Constify.
705 * ppc-dis.c (powerpc_init_dialect): Constify local.
706 * vax-dis.c (parse_disassembler_options): Constify.
707
b5292032
PD		 7082017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
709
710 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
711 RISCV_GP_SYMBOL.
712
f96bd6c2
PC		 7132017-03-30 Pip Cet <pipcet@gmail.com>
714
715 * configure.ac: Add (empty) bfd_wasm32_arch target.
716 * configure: Regenerate
717 * po/opcodes.pot: Regenerate.
718
f7c514a3
JM		 7192017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
720
721 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
722 OSA2015.
723 * opcodes/sparc-opc.c (asi_table): New ASIs.
724
52be03fd
AM		 7252017-03-29 Alan Modra <amodra@gmail.com>
726
727 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
728 "raw" option.
729 (lookup_powerpc): Don't special case -1 dialect. Handle
730 PPC_OPCODE_RAW.
731 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
732 lookup_powerpc call, pass it on second.
733
9b753937
AM		 7342017-03-27 Alan Modra <amodra@gmail.com>
735
736 PR 21303
737 * ppc-dis.c (struct ppc_mopt): Comment.
738 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
739
c0c31e91
RZ		 7402017-03-27 Rinat Zelig <rinat@mellanox.com>
741
742 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
743 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
744 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
745 (insert_nps_misc_imm_offset): New function.
746 (extract_nps_misc imm_offset): New function.
747 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
748 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
749
2253c8f0
AK		 7502017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
751
752 * s390-mkopc.c (main): Remove vx2 check.
753 * s390-opc.txt: Remove vx2 instruction flags.
754
645d3342
RZ		 7552017-03-21 Rinat Zelig <rinat@mellanox.com>
756
757 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
758 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
759 (insert_nps_imm_offset): New function.
760 (extract_nps_imm_offset): New function.
761 (insert_nps_imm_entry): New function.
762 (extract_nps_imm_entry): New function.
763
4b94dd2d
AM		 7642017-03-17 Alan Modra <amodra@gmail.com>
765
766 PR 21248
767 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
768 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
769 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
770
b416fe87
KC		 7712017-03-14 Kito Cheng <kito.cheng@gmail.com>
772
773 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
774 <c.andi>: Likewise.
775 <c.addiw> Likewise.
776
03b039a5
KC		 7772017-03-14 Kito Cheng <kito.cheng@gmail.com>
778
779 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
780
2c232b83
AW		 7812017-03-13 Andrew Waterman <andrew@sifive.com>
782
783 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
784 <srl> Likewise.
785 <srai> Likewise.
786 <sra> Likewise.
787
86fa6981
L		 7882017-03-09 H.J. Lu <hongjiu.lu@intel.com>
789
790 * i386-gen.c (opcode_modifiers): Replace S with Load.
791 * i386-opc.h (S): Removed.
792 (Load): New.
793 (i386_opcode_modifier): Replace s with load.
794 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
795 and {evex}. Replace S with Load.
796 * i386-tbl.h: Regenerated.
797
c1fe188b
L		 7982017-03-09 H.J. Lu <hongjiu.lu@intel.com>
799
800 * i386-opc.tbl: Use CpuCET on rdsspq.
801 * i386-tbl.h: Regenerated.
802
4b8b687e
PB		 8032017-03-08 Peter Bergner <bergner@vnet.ibm.com>
804
805 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
806 <vsx>: Do not use PPC_OPCODE_VSX3;
807
1437d063
PB		 8082017-03-08 Peter Bergner <bergner@vnet.ibm.com>
809
810 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
811
603555e5
L		 8122017-03-06 H.J. Lu <hongjiu.lu@intel.com>
813
814 * i386-dis.c (REG_0F1E_MOD_3): New enum.
815 (MOD_0F1E_PREFIX_1): Likewise.
816 (MOD_0F38F5_PREFIX_2): Likewise.
817 (MOD_0F38F6_PREFIX_0): Likewise.
818 (RM_0F1E_MOD_3_REG_7): Likewise.
819 (PREFIX_MOD_0_0F01_REG_5): Likewise.
820 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
821 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
822 (PREFIX_0F1E): Likewise.
823 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
824 (PREFIX_0F38F5): Likewise.
825 (dis386_twobyte): Use PREFIX_0F1E.
826 (reg_table): Add REG_0F1E_MOD_3.
827 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
828 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
829 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
830 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
831 (three_byte_table): Use PREFIX_0F38F5.
832 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
833 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
834 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
835 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
836 PREFIX_MOD_3_0F01_REG_5_RM_2.
837 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
838 (cpu_flags): Add CpuCET.
839 * i386-opc.h (CpuCET): New enum.
840 (CpuUnused): Commented out.
841 (i386_cpu_flags): Add cpucet.
842 * i386-opc.tbl: Add Intel CET instructions.
843 * i386-init.h: Regenerated.
844 * i386-tbl.h: Likewise.
845
73f07bff
AM		 8462017-03-06 Alan Modra <amodra@gmail.com>
847
848 PR 21124
849 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
850 (extract_raq, extract_ras, extract_rbx): New functions.
851 (powerpc_operands): Use opposite corresponding insert function.
852 (Q_MASK): Define.
853 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
854 register restriction.
855
65b48a81
PB		 8562017-02-28 Peter Bergner <bergner@vnet.ibm.com>
857
858 * disassemble.c Include "safe-ctype.h".
859 (disassemble_init_for_target): Handle s390 init.
860 (remove_whitespace_and_extra_commas): New function.
861 (disassembler_options_cmp): Likewise.
862 * arm-dis.c: Include "libiberty.h".
863 (NUM_ELEM): Delete.
864 (regnames): Use long disassembler style names.
865 Add force-thumb and no-force-thumb options.
866 (NUM_ARM_REGNAMES): Rename from this...
867 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
868 (get_arm_regname_num_options): Delete.
869 (set_arm_regname_option): Likewise.
870 (get_arm_regnames): Likewise.
871 (parse_disassembler_options): Likewise.
872 (parse_arm_disassembler_option): Rename from this...
873 (parse_arm_disassembler_options): ...to this. Make static.
874 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
875 (print_insn): Use parse_arm_disassembler_options.
876 (disassembler_options_arm): New function.
877 (print_arm_disassembler_options): Handle updated regnames.
878 * ppc-dis.c: Include "libiberty.h".
879 (ppc_opts): Add "32" and "64" entries.
880 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
881 (powerpc_init_dialect): Add break to switch statement.
882 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
883 (disassembler_options_powerpc): New function.
884 (print_ppc_disassembler_options): Use ARRAY_SIZE.
885 Remove printing of "32" and "64".
886 * s390-dis.c: Include "libiberty.h".
887 (init_flag): Remove unneeded variable.
888 (struct s390_options_t): New structure type.
889 (options): New structure.
890 (init_disasm): Rename from this...
891 (disassemble_init_s390): ...to this. Add initializations for
892 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
893 (print_insn_s390): Delete call to init_disasm.
894 (disassembler_options_s390): New function.
895 (print_s390_disassembler_options): Print using information from
896 struct 'options'.
897 * po/opcodes.pot: Regenerate.
898
15c7c1d8
JB		 8992017-02-28 Jan Beulich <jbeulich@suse.com>
900
901 * i386-dis.c (PCMPESTR_Fixup): New.
902 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
903 (prefix_table): Use PCMPESTR_Fixup.
904 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
905 PCMPESTR_Fixup.
906 (vex_w_table): Delete VPCMPESTR{I,M} entries.
907 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
908 Split 64-bit and non-64-bit variants.
909 * opcodes/i386-tbl.h: Re-generate.
910
582e12bf
RS		 9112017-02-24 Richard Sandiford <richard.sandiford@arm.com>
912
913 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
914 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
915 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
916 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
917 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
918 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
919 (OP_SVE_V_HSD): New macros.
920 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
921 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
922 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
923 (aarch64_opcode_table): Add new SVE instructions.
924 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
925 for rotation operands. Add new SVE operands.
926 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
927 (ins_sve_quad_index): Likewise.
928 (ins_imm_rotate): Split into...
929 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
930 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
931 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
932 functions.
933 (aarch64_ins_sve_addr_ri_s4): New function.
934 (aarch64_ins_sve_quad_index): Likewise.
935 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
936 * aarch64-asm-2.c: Regenerate.
937 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
938 (ext_sve_quad_index): Likewise.
939 (ext_imm_rotate): Split into...
940 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
941 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
942 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
943 functions.
944 (aarch64_ext_sve_addr_ri_s4): New function.
945 (aarch64_ext_sve_quad_index): Likewise.
946 (aarch64_ext_sve_index): Allow quad indices.
947 (do_misc_decoding): Likewise.
948 * aarch64-dis-2.c: Regenerate.
949 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
950 aarch64_field_kinds.
951 (OPD_F_OD_MASK): Widen by one bit.
952 (OPD_F_NO_ZR): Bump accordingly.
953 (get_operand_field_width): New function.
954 * aarch64-opc.c (fields): Add new SVE fields.
955 (operand_general_constraint_met_p): Handle new SVE operands.
956 (aarch64_print_operand): Likewise.
957 * aarch64-opc-2.c: Regenerate.
958
f482d304
RS		 9592017-02-24 Richard Sandiford <richard.sandiford@arm.com>
960
961 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
962 (aarch64_feature_compnum): ...this.
963 (SIMD_V8_3): Replace with...
964 (COMPNUM): ...this.
965 (CNUM_INSN): New macro.
966 (aarch64_opcode_table): Use it for the complex number instructions.
967
7db2c588
JB		 9682017-02-24 Jan Beulich <jbeulich@suse.com>
969
970 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
971
1e9d41d4
SL		 9722017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
973
974 Add support for associating SPARC ASIs with an architecture level.
975 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
976 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
977 decoding of SPARC ASIs.
978
53c4d625
JB		 9792017-02-23 Jan Beulich <jbeulich@suse.com>
980
981 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
982 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
983
11648de5
JB		 9842017-02-21 Jan Beulich <jbeulich@suse.com>
985
986 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
987 1 (instead of to itself). Correct typo.
988
f98d33be
AW		 9892017-02-14 Andrew Waterman <andrew@sifive.com>
990
991 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
992 pseudoinstructions.
993
773fb663
RS		 9942017-02-15 Richard Sandiford <richard.sandiford@arm.com>
995
996 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
997 (aarch64_sys_reg_supported_p): Handle them.
998
cc07cda6
CZ		 9992017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1000
1001 * arc-opc.c (UIMM6_20R): Define.
1002 (SIMM12_20): Use above.
1003 (SIMM12_20R): Define.
1004 (SIMM3_5_S): Use above.
1005 (UIMM7_A32_11R_S): Define.
1006 (UIMM7_9_S): Use above.
1007 (UIMM3_13R_S): Define.
1008 (SIMM11_A32_7_S): Use above.
1009 (SIMM9_8R): Define.
1010 (UIMM10_A32_8_S): Use above.
1011 (UIMM8_8R_S): Define.
1012 (W6): Use above.
1013 (arc_relax_opcodes): Use all above defines.
1014
66a5a740
VG		 10152017-02-15 Vineet Gupta <vgupta@synopsys.com>
1016
1017 * arc-regs.h: Distinguish some of the registers different on
1018 ARC700 and HS38 cpus.
1019
7e0de605
AM		 10202017-02-14 Alan Modra <amodra@gmail.com>
1021
1022 PR 21118
1023 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1024 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1025
54064fdb
AM		 10262017-02-11 Stafford Horne <shorne@gmail.com>
1027 Alan Modra <amodra@gmail.com>
1028
1029 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1030 Use insn_bytes_value and insn_int_value directly instead. Don't
1031 free allocated memory until function exit.
1032
dce75bf9
NP		 10332017-02-10 Nicholas Piggin <npiggin@gmail.com>
1034
1035 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1036
1b7e3d2f
NC		 10372017-02-03 Nick Clifton <nickc@redhat.com>
1038
1039 PR 21096
1040 * aarch64-opc.c (print_register_list): Ensure that the register
1041 list index will fir into the tb buffer.
1042 (print_register_offset_address): Likewise.
1043 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1044
8ec5cf65
AD		 10452017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1046
1047 PR 21056
1048 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1049 instructions when the previous fetch packet ends with a 32-bit
1050 instruction.
1051
a1aa5e81
DD		 10522017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1053
1054 * pru-opc.c: Remove vague reference to a future GDB port.
1055
add3afb2
NC		 10562017-01-20 Nick Clifton <nickc@redhat.com>
1057
1058 * po/ga.po: Updated Irish translation.
1059
c13a63b0
SN		 10602017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1061
1062 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1063
9608051a
YQ		 10642017-01-13 Yao Qi <yao.qi@linaro.org>
1065
1066 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1067 if FETCH_DATA returns 0.
1068 (m68k_scan_mask): Likewise.
1069 (print_insn_m68k): Update code to handle -1 return value.
1070
f622ea96
YQ		 10712017-01-13 Yao Qi <yao.qi@linaro.org>
1072
1073 * m68k-dis.c (enum print_insn_arg_error): New.
1074 (NEXTBYTE): Replace -3 with
1075 PRINT_INSN_ARG_MEMORY_ERROR.
1076 (NEXTULONG): Likewise.
1077 (NEXTSINGLE): Likewise.
1078 (NEXTDOUBLE): Likewise.
1079 (NEXTDOUBLE): Likewise.
1080 (NEXTPACKED): Likewise.
1081 (FETCH_ARG): Likewise.
1082 (FETCH_DATA): Update comments.
1083 (print_insn_arg): Update comments. Replace magic numbers with
1084 enum.
1085 (match_insn_m68k): Likewise.
1086
620214f7
IT		 10872017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1088
1089 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1090 * i386-dis-evex.h (evex_table): Updated.
1091 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1092 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1093 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1094 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1095 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1096 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1097 * i386-init.h: Regenerate.
1098 * i386-tbl.h: Ditto.
1099
d95014a2
YQ		 11002017-01-12 Yao Qi <yao.qi@linaro.org>
1101
1102 * msp430-dis.c (msp430_singleoperand): Return -1 if
1103 msp430dis_opcode_signed returns false.
1104 (msp430_doubleoperand): Likewise.
1105 (msp430_branchinstr): Return -1 if
1106 msp430dis_opcode_unsigned returns false.
1107 (msp430x_calla_instr): Likewise.
1108 (print_insn_msp430): Likewise.
1109
0ae60c3e
NC		 11102017-01-05 Nick Clifton <nickc@redhat.com>
1111
1112 PR 20946
1113 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1114 could not be matched.
1115 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1116 NULL.
1117
d74d4880
SN		 11182017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1119
1120 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1121 (aarch64_opcode_table): Use RCPC_INSN.
1122
cc917fd9
KC		 11232017-01-03 Kito Cheng <kito.cheng@gmail.com>
1124
1125 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1126 extension.
1127 * riscv-opcodes/all-opcodes: Likewise.
1128
b52d3cfc
DP		 11292017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1130
1131 * riscv-dis.c (print_insn_args): Add fall through comment.
1132
f90c58d5
NC		 11332017-01-03 Nick Clifton <nickc@redhat.com>
1134
1135 * po/sr.po: New Serbian translation.
1136 * configure.ac (ALL_LINGUAS): Add sr.
1137 * configure: Regenerate.
1138
f47b0d4a
AM		 11392017-01-02 Alan Modra <amodra@gmail.com>
1140
1141 * epiphany-desc.h: Regenerate.
1142 * epiphany-opc.h: Regenerate.
1143 * fr30-desc.h: Regenerate.
1144 * fr30-opc.h: Regenerate.
1145 * frv-desc.h: Regenerate.
1146 * frv-opc.h: Regenerate.
1147 * ip2k-desc.h: Regenerate.
1148 * ip2k-opc.h: Regenerate.
1149 * iq2000-desc.h: Regenerate.
1150 * iq2000-opc.h: Regenerate.
1151 * lm32-desc.h: Regenerate.
1152 * lm32-opc.h: Regenerate.
1153 * m32c-desc.h: Regenerate.
1154 * m32c-opc.h: Regenerate.
1155 * m32r-desc.h: Regenerate.
1156 * m32r-opc.h: Regenerate.
1157 * mep-desc.h: Regenerate.
1158 * mep-opc.h: Regenerate.
1159 * mt-desc.h: Regenerate.
1160 * mt-opc.h: Regenerate.
1161 * or1k-desc.h: Regenerate.
1162 * or1k-opc.h: Regenerate.
1163 * xc16x-desc.h: Regenerate.
1164 * xc16x-opc.h: Regenerate.
1165 * xstormy16-desc.h: Regenerate.
1166 * xstormy16-opc.h: Regenerate.
1167
2571583a
AM		 11682017-01-02 Alan Modra <amodra@gmail.com>
1169
1170 Update year range in copyright notice of all files.
1171
5c1ad6b5 1172For older changes see ChangeLog-2016
3499769a 1173\f
5c1ad6b5 1174Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1175
1176Copying and distribution of this file, with or without modification,
1177are permitted in any medium without royalty provided the copyright
1178notice and this notice are preserved.
1179
1180Local Variables:
1181mode: change-log
1182left-margin: 8
1183fill-column: 74
1184version-control: never
1185End:
GDB Binutils - Deliverables
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