2004-03-12 Michal Ludvig <mludvig@suse.cz>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
0f10071e
ML
12004-03-12 Michal Ludvig <mludvig@suse.cz>
2
3 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
4 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
5 (padlock_table): New struct with PadLock instructions.
6 (print_insn): Handle PADLOCK_SPECIAL.
7
c02908d2
AM
82004-03-12 Alan Modra <amodra@bigpond.net.au>
9
10 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
11 (OP_E): Twiddle clflush to sfence here.
12
d5bb7600
NC
132004-03-08 Nick Clifton <nickc@redhat.com>
14
15 * po/de.po: Updated German translation.
16
ae51a426
JR
172003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
18
19 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
20 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
21 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
22 accordingly.
23
676a64f4
RS
242004-03-01 Richard Sandiford <rsandifo@redhat.com>
25
26 * frv-asm.c: Regenerate.
27 * frv-desc.c: Regenerate.
28 * frv-desc.h: Regenerate.
29 * frv-dis.c: Regenerate.
30 * frv-ibld.c: Regenerate.
31 * frv-opc.c: Regenerate.
32 * frv-opc.h: Regenerate.
33
c7a48b9a
RS
342004-03-01 Richard Sandiford <rsandifo@redhat.com>
35
36 * frv-desc.c, frv-opc.c: Regenerate.
37
8ae0baa2
RS
382004-03-01 Richard Sandiford <rsandifo@redhat.com>
39
40 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
41
ce11586c
JR
422004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
43
44 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
45 Also correct mistake in the comment.
46
6a5709a5
JR
472004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
48
49 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
50 ensure that double registers have even numbers.
51 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
52 that reserved instruction 0xfffd does not decode the same
53 as 0xfdfd (ftrv).
54 * sh-opc.h: Add REG_N_D nibble type and use it whereever
55 REG_N refers to a double register.
56 Add REG_N_B01 nibble type and use it instead of REG_NM
57 in ftrv.
58 Adjust the bit patterns in a few comments.
59
e5d2b64f
AH
602004-02-25 Aldy Hernandez <aldyh@redhat.com>
61
62 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
63
1f04b05f
AH
642004-02-20 Aldy Hernandez <aldyh@redhat.com>
65
66 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
67
2f3b8700
AH
682004-02-20 Aldy Hernandez <aldyh@redhat.com>
69
70 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
71
f0b26da6
AH
722004-02-20 Aldy Hernandez <aldyh@redhat.com>
73
74 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
75 mtivor32, mtivor33, mtivor34.
76
23d59c56
AH
772004-02-19 Aldy Hernandez <aldyh@redhat.com>
78
f0b26da6 79 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 80
34920d91
NC
812004-02-10 Petko Manolov <petkan@nucleusys.com>
82
83 * arm-opc.h Maverick accumulator register opcode fixes.
84
44d86481
BE
852004-02-13 Ben Elliston <bje@wasabisystems.com>
86
87 * m32r-dis.c: Regenerate.
88
17707c23
MS
892004-01-27 Michael Snyder <msnyder@redhat.com>
90
91 * sh-opc.h (sh_table): "fsrra", not "fssra".
92
fe3a9bc4
NC
932004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
94
95 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
96 contraints.
97
ff24f124
JJ
982004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
99
100 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
101
a02a862a
AM
1022004-01-19 Alan Modra <amodra@bigpond.net.au>
103
104 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
105 1. Don't print scale factor on AT&T mode when index missing.
106
d164ea7f
AO
1072004-01-16 Alexandre Oliva <aoliva@redhat.com>
108
109 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
110 when loaded into XR registers.
111
cb10e79a
RS
1122004-01-14 Richard Sandiford <rsandifo@redhat.com>
113
114 * frv-desc.h: Regenerate.
115 * frv-desc.c: Regenerate.
116 * frv-opc.c: Regenerate.
117
f532f3fa
MS
1182004-01-13 Michael Snyder <msnyder@redhat.com>
119
120 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
121
e45d0630
PB
1222004-01-09 Paul Brook <paul@codesourcery.com>
123
124 * arm-opc.h (arm_opcodes): Move generic mcrr after known
125 specific opcodes.
126
3ba7a1aa
DJ
1272004-01-07 Daniel Jacobowitz <drow@mvista.com>
128
129 * Makefile.am (libopcodes_la_DEPENDENCIES)
130 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
131 comment about the problem.
132 * Makefile.in: Regenerate.
133
ba2d3f07
AO
1342004-01-06 Alexandre Oliva <aoliva@redhat.com>
135
136 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
137 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
138 cut&paste errors in shifting/truncating numerical operands.
139 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
140 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
141 (parse_uslo16): Likewise.
142 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
143 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
144 (parse_s12): Likewise.
145 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
146 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
147 (parse_uslo16): Likewise.
148 (parse_uhi16): Parse gothi and gotfuncdeschi.
149 (parse_d12): Parse got12 and gotfuncdesc12.
150 (parse_s12): Likewise.
151
3ab48931
NC
1522004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
153
154 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
155 instruction which looks similar to an 'rla' instruction.
a0bd404e 156
c9e214e5 157For older changes see ChangeLog-0203
252b5132
RH
158\f
159Local Variables:
2f6d2f85
NC
160mode: change-log
161left-margin: 8
162fill-column: 74
252b5132
RH
163version-control: never
164End:
This page took 0.229559 seconds and 4 git commands to generate.