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Use disassemble_info.private_data in place of insn_sets
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
103ebbc3
AM		 12019-12-10 Alan Modra <amodra@gmail.com>
2
3 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
4 * disassemble.c (disassemble_init_for_target): Likewise.
5 * bpf-dis.c: Regenerate.
6 * epiphany-dis.c: Regenerate.
7 * fr30-dis.c: Regenerate.
8 * frv-dis.c: Regenerate.
9 * ip2k-dis.c: Regenerate.
10 * iq2000-dis.c: Regenerate.
11 * lm32-dis.c: Regenerate.
12 * m32c-dis.c: Regenerate.
13 * m32r-dis.c: Regenerate.
14 * mep-dis.c: Regenerate.
15 * mt-dis.c: Regenerate.
16 * or1k-dis.c: Regenerate.
17 * xc16x-dis.c: Regenerate.
18 * xstormy16-dis.c: Regenerate.
19
6f0e0752
AM		 202019-12-10 Alan Modra <amodra@gmail.com>
21
22 * ppc-dis.c (private): Delete variable.
23 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
24 (powerpc_init_dialect): Don't use global private.
25
e7c22a69
AM		 262019-12-10 Alan Modra <amodra@gmail.com>
27
28 * s12z-opc.c: Formatting.
29
0a6aef6b
AM		 302019-12-08 Alan Modra <amodra@gmail.com>
31
32 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
33 registers.
34
2dc4b12f
JB		 352019-12-05 Jan Beulich <jbeulich@suse.com>
36
37 * aarch64-tbl.h (aarch64_feature_crypto,
38 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
39 CRYPTO_V8_2_INSN): Delete.
40
378fd436
AM		 412019-12-05 Alan Modra <amodra@gmail.com>
42
43 PR 25249
44 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
45 (struct string_buf): New.
46 (strbuf): New function.
47 (get_field): Use strbuf rather than strdup of local temp.
48 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
49 (get_field_rfsl, get_field_imm15): Likewise.
50 (get_field_rd, get_field_r1, get_field_r2): Update macros.
51 (get_field_special): Likewise. Don't strcpy spr. Formatting.
52 (print_insn_microblaze): Formatting. Init and pass string_buf to
53 get_field functions.
54
0ba59a29
JB		 552019-12-04 Jan Beulich <jbeulich@suse.com>
56
57 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
58 * i386-tbl.h: Re-generate.
59
77ad8092
JB		 602019-12-04 Jan Beulich <jbeulich@suse.com>
61
62 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
63
3036c899
JB		 642019-12-04 Jan Beulich <jbeulich@suse.com>
65
66 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
67 forms.
68 (xbegin): Drop DefaultSize.
69 * i386-tbl.h: Re-generate.
70
8b301fbb
MI		 712019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
72
73 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
74 Change the coproc CRC conditions to use the extension
75 feature set, second word, base on ARM_EXT2_CRC.
76
6aa385b9
JB		 772019-11-14 Jan Beulich <jbeulich@suse.com>
78
79 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
80 * i386-tbl.h: Re-generate.
81
0cfa3eb3
JB		 822019-11-14 Jan Beulich <jbeulich@suse.com>
83
84 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
85 JumpInterSegment, and JumpAbsolute entries.
86 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
87 JUMP_ABSOLUTE): Define.
88 (struct i386_opcode_modifier): Extend jump field to 3 bits.
89 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
90 fields.
91 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
92 JumpInterSegment): Define.
93 * i386-tbl.h: Re-generate.
94
6f2f06be
JB		 952019-11-14 Jan Beulich <jbeulich@suse.com>
96
97 * i386-gen.c (operand_type_init): Remove
98 OPERAND_TYPE_JUMPABSOLUTE entry.
99 (opcode_modifiers): Add JumpAbsolute entry.
100 (operand_types): Remove JumpAbsolute entry.
101 * i386-opc.h (JumpAbsolute): Move between enums.
102 (struct i386_opcode_modifier): Add jumpabsolute field.
103 (union i386_operand_type): Remove jumpabsolute field.
104 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
105 * i386-init.h, i386-tbl.h: Re-generate.
106
601e8564
JB		 1072019-11-14 Jan Beulich <jbeulich@suse.com>
108
109 * i386-gen.c (opcode_modifiers): Add AnySize entry.
110 (operand_types): Remove AnySize entry.
111 * i386-opc.h (AnySize): Move between enums.
112 (struct i386_opcode_modifier): Add anysize field.
113 (OTUnused): Un-comment.
114 (union i386_operand_type): Remove anysize field.
115 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
116 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
117 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
118 AnySize.
119 * i386-tbl.h: Re-generate.
120
7722d40a
JW		 1212019-11-12 Nelson Chu <nelson.chu@sifive.com>
122
123 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
124 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
125 use the floating point register (FPR).
126
ce760a76
MI		 1272019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
128
129 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
130 cmode 1101.
131 (is_mve_encoding_conflict): Update cmode conflict checks for
132 MVE_VMVN_IMM.
133
51c8edf6
JB		 1342019-11-12 Jan Beulich <jbeulich@suse.com>
135
136 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
137 entry.
138 (operand_types): Remove EsSeg entry.
139 (main): Replace stale use of OTMax.
140 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
141 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
142 (EsSeg): Delete.
143 (OTUnused): Comment out.
144 (union i386_operand_type): Remove esseg field.
145 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
146 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
147 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
148 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
149 * i386-init.h, i386-tbl.h: Re-generate.
150
474da251
JB		 1512019-11-12 Jan Beulich <jbeulich@suse.com>
152
153 * i386-gen.c (operand_instances): Add RegB entry.
154 * i386-opc.h (enum operand_instance): Add RegB.
155 * i386-opc.tbl (RegC, RegD, RegB): Define.
156 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
157 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
158 monitorx, mwaitx): Drop ImmExt and convert encodings
159 accordingly.
160 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
161 (edx, rdx): Add Instance=RegD.
162 (ebx, rbx): Add Instance=RegB.
163 * i386-tbl.h: Re-generate.
164
75e5731b
JB		 1652019-11-12 Jan Beulich <jbeulich@suse.com>
166
167 * i386-gen.c (operand_type_init): Adjust
168 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
169 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
170 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
171 (operand_instances): New.
172 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
173 (output_operand_type): New parameter "instance". Process it.
174 (process_i386_operand_type): New local variable "instance".
175 (main): Adjust static assertions.
176 * i386-opc.h (INSTANCE_WIDTH): Define.
177 (enum operand_instance): New.
178 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
179 (union i386_operand_type): Replace acc, inoutportreg, and
180 shiftcount by instance.
181 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
182 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
183 Add Instance=.
184 * i386-init.h, i386-tbl.h: Re-generate.
185
91802f3c
JB		 1862019-11-11 Jan Beulich <jbeulich@suse.com>
187
188 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
189 smaxp/sminp entries' "tied_operand" field to 2.
190
4f5fc85d
JB		 1912019-11-11 Jan Beulich <jbeulich@suse.com>
192
193 * aarch64-opc.c (operand_general_constraint_met_p): Replace
194 "index" local variable by that of the already existing "num".
195
dc2be329
L		 1962019-11-08 H.J. Lu <hongjiu.lu@intel.com>
197
198 PR gas/25167
199 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
200 * i386-tbl.h: Regenerated.
201
f74a6307
JB		 2022019-11-08 Jan Beulich <jbeulich@suse.com>
203
204 * i386-gen.c (operand_type_init): Add Class= to
205 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
206 OPERAND_TYPE_REGBND entry.
207 (operand_classes): Add RegMask and RegBND entries.
208 (operand_types): Drop RegMask and RegBND entry.
209 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
210 (RegMask, RegBND): Delete.
211 (union i386_operand_type): Remove regmask and regbnd fields.
212 * i386-opc.tbl (RegMask, RegBND): Define.
213 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
214 Class=RegBND.
215 * i386-init.h, i386-tbl.h: Re-generate.
216
3528c362
JB		 2172019-11-08 Jan Beulich <jbeulich@suse.com>
218
219 * i386-gen.c (operand_type_init): Add Class= to
220 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
221 OPERAND_TYPE_REGZMM entries.
222 (operand_classes): Add RegMMX and RegSIMD entries.
223 (operand_types): Drop RegMMX and RegSIMD entries.
224 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
225 (RegMMX, RegSIMD): Delete.
226 (union i386_operand_type): Remove regmmx and regsimd fields.
227 * i386-opc.tbl (RegMMX): Define.
228 (RegXMM, RegYMM, RegZMM): Add Class=.
229 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
230 Class=RegSIMD.
231 * i386-init.h, i386-tbl.h: Re-generate.
232
4a5c67ed
JB		 2332019-11-08 Jan Beulich <jbeulich@suse.com>
234
235 * i386-gen.c (operand_type_init): Add Class= to
236 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
237 entries.
238 (operand_classes): Add RegCR, RegDR, and RegTR entries.
239 (operand_types): Drop Control, Debug, and Test entries.
240 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
241 (Control, Debug, Test): Delete.
242 (union i386_operand_type): Remove control, debug, and test
243 fields.
244 * i386-opc.tbl (Control, Debug, Test): Define.
245 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
246 Class=RegDR, and Test by Class=RegTR.
247 * i386-init.h, i386-tbl.h: Re-generate.
248
00cee14f
JB		 2492019-11-08 Jan Beulich <jbeulich@suse.com>
250
251 * i386-gen.c (operand_type_init): Add Class= to
252 OPERAND_TYPE_SREG entry.
253 (operand_classes): Add SReg entry.
254 (operand_types): Drop SReg entry.
255 * i386-opc.h (enum operand_class): Add SReg.
256 (SReg): Delete.
257 (union i386_operand_type): Remove sreg field.
258 * i386-opc.tbl (SReg): Define.
259 * i386-reg.tbl: Replace SReg by Class=SReg.
260 * i386-init.h, i386-tbl.h: Re-generate.
261
bab6aec1
JB		 2622019-11-08 Jan Beulich <jbeulich@suse.com>
263
264 * i386-gen.c (operand_type_init): Add Class=. New
265 OPERAND_TYPE_ANYIMM entry.
266 (operand_classes): New.
267 (operand_types): Drop Reg entry.
268 (output_operand_type): New parameter "class". Process it.
269 (process_i386_operand_type): New local variable "class".
270 (main): Adjust static assertions.
271 * i386-opc.h (CLASS_WIDTH): Define.
272 (enum operand_class): New.
273 (Reg): Replace by Class. Adjust comment.
274 (union i386_operand_type): Replace reg by class.
275 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
276 Class=.
277 * i386-reg.tbl: Replace Reg by Class=Reg.
278 * i386-init.h: Re-generate.
279
1f4cd317
MM		 2802019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
281
282 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
283 (aarch64_opcode_table): Add data gathering hint mnemonic.
284 * opcodes/aarch64-dis-2.c: Account for new instruction.
285
616ce08e
MM		 2862019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
287
288 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
289
290
8382113f
MM		 2912019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
292
293 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
294 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
295 aarch64_feature_f64mm): New feature sets.
296 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
297 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
298 instructions.
299 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
300 macros.
301 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
302 (OP_SVE_QQQ): New qualifier.
303 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
304 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
305 the movprfx constraint.
306 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
307 (aarch64_opcode_table): Define new instructions smmla,
308 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
309 uzip{1/2}, trn{1/2}.
310 * aarch64-opc.c (operand_general_constraint_met_p): Handle
311 AARCH64_OPND_SVE_ADDR_RI_S4x32.
312 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
313 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
314 Account for new instructions.
315 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
316 S4x32 operand.
317 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
318
aab2c27d
MM		 3192019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3202019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
321
322 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
323 Armv8.6-A.
324 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
325 (neon_opcodes): Add bfloat SIMD instructions.
326 (print_insn_coprocessor): Add new control character %b to print
327 condition code without checking cp_num.
328 (print_insn_neon): Account for BFloat16 instructions that have no
329 special top-byte handling.
330
33593eaf
MM		 3312019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3322019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
333
334 * arm-dis.c (print_insn_coprocessor,
335 print_insn_generic_coprocessor): Create wrapper functions around
336 the implementation of the print_insn_coprocessor control codes.
337 (print_insn_coprocessor_1): Original print_insn_coprocessor
338 function that now takes which array to look at as an argument.
339 (print_insn_arm): Use both print_insn_coprocessor and
340 print_insn_generic_coprocessor.
341 (print_insn_thumb32): As above.
342
df678013
MM		 3432019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3442019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
345
346 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
347 in reglane special case.
348 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
349 aarch64_find_next_opcode): Account for new instructions.
350 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
351 in reglane special case.
352 * aarch64-opc.c (struct operand_qualifier_data): Add data for
353 new AARCH64_OPND_QLF_S_2H qualifier.
354 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
355 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
356 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
357 sets.
358 (BFLOAT_SVE, BFLOAT): New feature set macros.
359 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
360 instructions.
361 (aarch64_opcode_table): Define new instructions bfdot,
362 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
363 bfcvtn2, bfcvt.
364
8ae2d3d9
MM		 3652019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3662019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
367
368 * aarch64-tbl.h (ARMV8_6): New macro.
369
142861df
JB		 3702019-11-07 Jan Beulich <jbeulich@suse.com>
371
372 * i386-dis.c (prefix_table): Add mcommit.
373 (rm_table): Add rdpru.
374 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
375 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
376 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
377 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
378 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
379 * i386-opc.tbl (mcommit, rdpru): New.
380 * i386-init.h, i386-tbl.h: Re-generate.
381
081e283f
JB		 3822019-11-07 Jan Beulich <jbeulich@suse.com>
383
384 * i386-dis.c (OP_Mwait): Drop local variable "names", use
385 "names32" instead.
386 (OP_Monitor): Drop local variable "op1_names", re-purpose
387 "names" for it instead, and replace former "names" uses by
388 "names32" ones.
389
c050c89a
JB		 3902019-11-07 Jan Beulich <jbeulich@suse.com>
391
392 PR/gas 25167
393 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
394 operand-less forms.
395 * opcodes/i386-tbl.h: Re-generate.
396
7abb8d81
JB		 3972019-11-05 Jan Beulich <jbeulich@suse.com>
398
399 * i386-dis.c (OP_Mwaitx): Delete.
400 (prefix_table): Use OP_Mwait for mwaitx entry.
401 (OP_Mwait): Also handle mwaitx.
402
267b8516
JB		 4032019-11-05 Jan Beulich <jbeulich@suse.com>
404
405 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
406 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
407 (prefix_table): Add respective entries.
408 (rm_table): Link to those entries.
409
f8687e93
JB		 4102019-11-05 Jan Beulich <jbeulich@suse.com>
411
412 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
413 (REG_0F1C_P_0_MOD_0): ... this.
414 (REG_0F1E_MOD_3): Rename to ...
415 (REG_0F1E_P_1_MOD_3): ... this.
416 (RM_0F01_REG_5): Rename to ...
417 (RM_0F01_REG_5_MOD_3): ... this.
418 (RM_0F01_REG_7): Rename to ...
419 (RM_0F01_REG_7_MOD_3): ... this.
420 (RM_0F1E_MOD_3_REG_7): Rename to ...
421 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
422 (RM_0FAE_REG_6): Rename to ...
423 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
424 (RM_0FAE_REG_7): Rename to ...
425 (RM_0FAE_REG_7_MOD_3): ... this.
426 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
427 (PREFIX_0F01_REG_5_MOD_0): ... this.
428 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
429 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
430 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
431 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
432 (PREFIX_0FAE_REG_0): Rename to ...
433 (PREFIX_0FAE_REG_0_MOD_3): ... this.
434 (PREFIX_0FAE_REG_1): Rename to ...
435 (PREFIX_0FAE_REG_1_MOD_3): ... this.
436 (PREFIX_0FAE_REG_2): Rename to ...
437 (PREFIX_0FAE_REG_2_MOD_3): ... this.
438 (PREFIX_0FAE_REG_3): Rename to ...
439 (PREFIX_0FAE_REG_3_MOD_3): ... this.
440 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
441 (PREFIX_0FAE_REG_4_MOD_0): ... this.
442 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
443 (PREFIX_0FAE_REG_4_MOD_3): ... this.
444 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
445 (PREFIX_0FAE_REG_5_MOD_0): ... this.
446 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
447 (PREFIX_0FAE_REG_5_MOD_3): ... this.
448 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
449 (PREFIX_0FAE_REG_6_MOD_0): ... this.
450 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
451 (PREFIX_0FAE_REG_6_MOD_3): ... this.
452 (PREFIX_0FAE_REG_7): Rename to ...
453 (PREFIX_0FAE_REG_7_MOD_0): ... this.
454 (PREFIX_MOD_0_0FC3): Rename to ...
455 (PREFIX_0FC3_MOD_0): ... this.
456 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
457 (PREFIX_0FC7_REG_6_MOD_0): ... this.
458 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
459 (PREFIX_0FC7_REG_6_MOD_3): ... this.
460 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
461 (PREFIX_0FC7_REG_7_MOD_3): ... this.
462 (reg_table, prefix_table, mod_table, rm_table): Adjust
463 accordingly.
464
5103274f
NC		 4652019-11-04 Nick Clifton <nickc@redhat.com>
466
467 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
468 of a v850 system register. Move the v850_sreg_names array into
469 this function.
470 (get_v850_reg_name): Likewise for ordinary register names.
471 (get_v850_vreg_name): Likewise for vector register names.
472 (get_v850_cc_name): Likewise for condition codes.
473 * get_v850_float_cc_name): Likewise for floating point condition
474 codes.
475 (get_v850_cacheop_name): Likewise for cache-ops.
476 (get_v850_prefop_name): Likewise for pref-ops.
477 (disassemble): Use the new accessor functions.
478
1820262b
DB		 4792019-10-30 Delia Burduv <delia.burduv@arm.com>
480
481 * aarch64-opc.c (print_immediate_offset_address): Don't print the
482 immediate for the writeback form of ldraa/ldrab if it is 0.
483 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
484 * aarch64-opc-2.c: Regenerated.
485
3cc17af5
JB		 4862019-10-30 Jan Beulich <jbeulich@suse.com>
487
488 * i386-gen.c (operand_type_shorthands): Delete.
489 (operand_type_init): Expand previous shorthands.
490 (set_bitfield_from_shorthand): Rename back to ...
491 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
492 of operand_type_init[].
493 (set_bitfield): Adjust call to the above function.
494 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
495 RegXMM, RegYMM, RegZMM): Define.
496 * i386-reg.tbl: Expand prior shorthands.
497
a2cebd03
JB		 4982019-10-30 Jan Beulich <jbeulich@suse.com>
499
500 * i386-gen.c (output_i386_opcode): Change order of fields
501 emitted to output.
502 * i386-opc.h (struct insn_template): Move operands field.
503 Convert extension_opcode field to unsigned short.
504 * i386-tbl.h: Re-generate.
505
507916b8
JB		 5062019-10-30 Jan Beulich <jbeulich@suse.com>
507
508 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
509 of W.
510 * i386-opc.h (W): Extend comment.
511 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
512 general purpose variants not allowing for byte operands.
513 * i386-tbl.h: Re-generate.
514
efea62b4
NC		 5152019-10-29 Nick Clifton <nickc@redhat.com>
516
517 * tic30-dis.c (print_branch): Correct size of operand array.
518
9adb2591
NC		 5192019-10-29 Nick Clifton <nickc@redhat.com>
520
521 * d30v-dis.c (print_insn): Check that operand index is valid
522 before attempting to access the operands array.
523
993a00a9
NC		 5242019-10-29 Nick Clifton <nickc@redhat.com>
525
526 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
527 locating the bit to be tested.
528
66a66a17
NC		 5292019-10-29 Nick Clifton <nickc@redhat.com>
530
531 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
532 values.
533 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
534 (print_insn_s12z): Check for illegal size values.
535
1ee3542c
NC		 5362019-10-28 Nick Clifton <nickc@redhat.com>
537
538 * csky-dis.c (csky_chars_to_number): Check for a negative
539 count. Use an unsigned integer to construct the return value.
540
bbf9a0b5
NC		 5412019-10-28 Nick Clifton <nickc@redhat.com>
542
543 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
544 operand buffer. Set value to 15 not 13.
545 (get_register_operand): Use OPERAND_BUFFER_LEN.
546 (get_indirect_operand): Likewise.
547 (print_two_operand): Likewise.
548 (print_three_operand): Likewise.
549 (print_oar_insn): Likewise.
550
d1e304bc
NC		 5512019-10-28 Nick Clifton <nickc@redhat.com>
552
553 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
554 (bit_extract_simple): Likewise.
555 (bit_copy): Likewise.
556 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
557 index_offset array are not accessed.
558
dee33451
NC		 5592019-10-28 Nick Clifton <nickc@redhat.com>
560
561 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
562 operand.
563
27cee81d
NC		 5642019-10-25 Nick Clifton <nickc@redhat.com>
565
566 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
567 access to opcodes.op array element.
568
de6d8dc2
NC		 5692019-10-23 Nick Clifton <nickc@redhat.com>
570
571 * rx-dis.c (get_register_name): Fix spelling typo in error
572 message.
573 (get_condition_name, get_flag_name, get_double_register_name)
574 (get_double_register_high_name, get_double_register_low_name)
575 (get_double_control_register_name, get_double_condition_name)
576 (get_opsize_name, get_size_name): Likewise.
577
6207ed28
NC		 5782019-10-22 Nick Clifton <nickc@redhat.com>
579
580 * rx-dis.c (get_size_name): New function. Provides safe
581 access to name array.
582 (get_opsize_name): Likewise.
583 (print_insn_rx): Use the accessor functions.
584
12234dfd
NC		 5852019-10-16 Nick Clifton <nickc@redhat.com>
586
587 * rx-dis.c (get_register_name): New function. Provides safe
588 access to name array.
589 (get_condition_name, get_flag_name, get_double_register_name)
590 (get_double_register_high_name, get_double_register_low_name)
591 (get_double_control_register_name, get_double_condition_name):
592 Likewise.
593 (print_insn_rx): Use the accessor functions.
594
1d378749
NC		 5952019-10-09 Nick Clifton <nickc@redhat.com>
596
597 PR 25041
598 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
599 instructions.
600
d241b910
JB		 6012019-10-07 Jan Beulich <jbeulich@suse.com>
602
603 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
604 (cmpsd): Likewise. Move EsSeg to other operand.
605 * opcodes/i386-tbl.h: Re-generate.
606
f5c5b7c1
AM		 6072019-09-23 Alan Modra <amodra@gmail.com>
608
609 * m68k-dis.c: Include cpu-m68k.h
610
7beeaeb8
AM		 6112019-09-23 Alan Modra <amodra@gmail.com>
612
613 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
614 "elf/mips.h" earlier.
615
3f9aad11
JB		 6162018-09-20 Jan Beulich <jbeulich@suse.com>
617
618 PR gas/25012
619 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
620 with SReg operand.
621 * i386-tbl.h: Re-generate.
622
fd361982
AM		 6232019-09-18 Alan Modra <amodra@gmail.com>
624
625 * arc-ext.c: Update throughout for bfd section macro changes.
626
e0b2a78c
SM		 6272019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
628
629 * Makefile.in: Re-generate.
630 * configure: Re-generate.
631
7e9ad3a3
JW		 6322019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
633
634 * riscv-opc.c (riscv_opcodes): Change subset field
635 to insn_class field for all instructions.
636 (riscv_insn_types): Likewise.
637
bb695960
PB		 6382019-09-16 Phil Blundell <pb@pbcl.net>
639
640 * configure: Regenerated.
641
8063ab7e
MV		 6422019-09-10 Miod Vallat <miod@online.fr>
643
644 PR 24982
645 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
646
60391a25
PB		 6472019-09-09 Phil Blundell <pb@pbcl.net>
648
649 binutils 2.33 branch created.
650
f44b758d
NC		 6512019-09-03 Nick Clifton <nickc@redhat.com>
652
653 PR 24961
654 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
655 greater than zero before indexing via (bufcnt -1).
656
1e4b5e7d
NC		 6572019-09-03 Nick Clifton <nickc@redhat.com>
658
659 PR 24958
660 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
661 (MAX_SPEC_REG_NAME_LEN): Define.
662 (struct mmix_dis_info): Use defined constants for array lengths.
663 (get_reg_name): New function.
664 (get_sprec_reg_name): New function.
665 (print_insn_mmix): Use new functions.
666
c4a23bf8
SP		 6672019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
668
669 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
670 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
671 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
672
a051e2f3
KT		 6732019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
674
675 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
676 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
677 (aarch64_sys_reg_supported_p): Update checks for the above.
678
08132bdd
SP		 6792019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
680
681 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
682 cases MVE_SQRSHRL and MVE_UQRSHLL.
683 (print_insn_mve): Add case for specifier 'k' to check
684 specific bit of the instruction.
685
d88bdcb4
PA		 6862019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
687
688 PR 24854
689 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
690 encountering an unknown machine type.
691 (print_insn_arc): Handle arc_insn_length returning 0. In error
692 cases return -1 rather than calling abort.
693
bc750500
JB		 6942019-08-07 Jan Beulich <jbeulich@suse.com>
695
696 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
697 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
698 IgnoreSize.
699 * i386-tbl.h: Re-generate.
700
23d188c7
BW		 7012019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
702
703 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
704 instructions.
705
c0d6f62f
JW		 7062019-07-30 Mel Chen <mel.chen@sifive.com>
707
708 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
709 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
710
711 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
712 fscsr.
713
0f3f7167
CZ		 7142019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
715
716 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
717 and MPY class instructions.
718 (parse_option): Add nps400 option.
719 (print_arc_disassembler_options): Add nps400 info.
720
7e126ba3
CZ		 7212019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
722
723 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
724 (bspop): Likewise.
725 (modapp): Likewise.
726 * arc-opc.c (RAD_CHK): Add.
727 * arc-tbl.h: Regenerate.
728
a028026d
KT		 7292019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
730
731 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
732 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
733
ac79ff9e
NC		 7342019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
735
736 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
737 instructions as UNPREDICTABLE.
738
231097b0
JM		 7392019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
740
741 * bpf-desc.c: Regenerated.
742
1d942ae9
JB		 7432019-07-17 Jan Beulich <jbeulich@suse.com>
744
745 * i386-gen.c (static_assert): Define.
746 (main): Use it.
747 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
748 (Opcode_Modifier_Num): ... this.
749 (Mem): Delete.
750
dfd69174
JB		 7512019-07-16 Jan Beulich <jbeulich@suse.com>
752
753 * i386-gen.c (operand_types): Move RegMem ...
754 (opcode_modifiers): ... here.
755 * i386-opc.h (RegMem): Move to opcode modifer enum.
756 (union i386_operand_type): Move regmem field ...
757 (struct i386_opcode_modifier): ... here.
758 * i386-opc.tbl (RegMem): Define.
759 (mov, movq): Move RegMem on segment, control, debug, and test
760 register flavors.
761 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
762 to non-SSE2AVX flavor.
763 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
764 Move RegMem on register only flavors. Drop IgnoreSize from
765 legacy encoding flavors.
766 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
767 flavors.
768 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
769 register only flavors.
770 (vmovd): Move RegMem and drop IgnoreSize on register only
771 flavor. Change opcode and operand order to store form.
772 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
773
21df382b
JB		 7742019-07-16 Jan Beulich <jbeulich@suse.com>
775
776 * i386-gen.c (operand_type_init, operand_types): Replace SReg
777 entries.
778 * i386-opc.h (SReg2, SReg3): Replace by ...
779 (SReg): ... this.
780 (union i386_operand_type): Replace sreg fields.
781 * i386-opc.tbl (mov, ): Use SReg.
782 (push, pop): Likewies. Drop i386 and x86-64 specific segment
783 register flavors.
784 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
785 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
786
3719fd55
JM		 7872019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
788
789 * bpf-desc.c: Regenerate.
790 * bpf-opc.c: Likewise.
791 * bpf-opc.h: Likewise.
792
92434a14
JM		 7932019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
794
795 * bpf-desc.c: Regenerate.
796 * bpf-opc.c: Likewise.
797
43dd7626
HPN		 7982019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
799
800 * arm-dis.c (print_insn_coprocessor): Rename index to
801 index_operand.
802
98602811
JW		 8032019-07-05 Kito Cheng <kito.cheng@sifive.com>
804
805 * riscv-opc.c (riscv_insn_types): Add r4 type.
806
807 * riscv-opc.c (riscv_insn_types): Add b and j type.
808
809 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
810 format for sb type and correct s type.
811
01c1ee4a
RS		 8122019-07-02 Richard Sandiford <richard.sandiford@arm.com>
813
814 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
815 SVE FMOV alias of FCPY.
816
83adff69
RS		 8172019-07-02 Richard Sandiford <richard.sandiford@arm.com>
818
819 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
820 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
821
89418844
RS		 8222019-07-02 Richard Sandiford <richard.sandiford@arm.com>
823
824 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
825 registers in an instruction prefixed by MOVPRFX.
826
41be57ca
MM		 8272019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
828
829 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
830 sve_size_13 icode to account for variant behaviour of
831 pmull{t,b}.
832 * aarch64-dis-2.c: Regenerate.
833 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
834 sve_size_13 icode to account for variant behaviour of
835 pmull{t,b}.
836 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
837 (OP_SVE_VVV_Q_D): Add new qualifier.
838 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
839 (struct aarch64_opcode): Split pmull{t,b} into those requiring
840 AES and those not.
841
9d3bf266
JB		 8422019-07-01 Jan Beulich <jbeulich@suse.com>
843
844 * opcodes/i386-gen.c (operand_type_init): Remove
845 OPERAND_TYPE_VEC_IMM4 entry.
846 (operand_types): Remove Vec_Imm4.
847 * opcodes/i386-opc.h (Vec_Imm4): Delete.
848 (union i386_operand_type): Remove vec_imm4.
849 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
850 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
851
c3949f43
JB		 8522019-07-01 Jan Beulich <jbeulich@suse.com>
853
854 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
855 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
856 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
857 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
858 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
859 monitorx, mwaitx): Drop ImmExt from operand-less forms.
860 * i386-tbl.h: Re-generate.
861
5641ec01
JB		 8622019-07-01 Jan Beulich <jbeulich@suse.com>
863
864 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
865 register operands.
866 * i386-tbl.h: Re-generate.
867
79dec6b7
JB		 8682019-07-01 Jan Beulich <jbeulich@suse.com>
869
870 * i386-opc.tbl (C): New.
871 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
872 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
873 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
874 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
875 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
876 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
877 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
878 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
879 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
880 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
881 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
882 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
883 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
884 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
885 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
886 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
887 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
888 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
889 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
890 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
891 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
892 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
893 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
894 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
895 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
896 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
897 flavors.
898 * i386-tbl.h: Re-generate.
899
a0a1771e
JB		 9002019-07-01 Jan Beulich <jbeulich@suse.com>
901
902 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
903 register operands.
904 * i386-tbl.h: Re-generate.
905
cd546e7b
JB		 9062019-07-01 Jan Beulich <jbeulich@suse.com>
907
908 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
909 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
910 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
911 * i386-tbl.h: Re-generate.
912
e3bba3fc
JB		 9132019-07-01 Jan Beulich <jbeulich@suse.com>
914
915 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
916 Disp8MemShift from register only templates.
917 * i386-tbl.h: Re-generate.
918
36cc073e
JB		 9192019-07-01 Jan Beulich <jbeulich@suse.com>
920
921 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
922 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
923 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
924 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
925 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
926 EVEX_W_0F11_P_3_M_1): Delete.
927 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
928 EVEX_W_0F11_P_3): New.
929 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
930 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
931 MOD_EVEX_0F11_PREFIX_3 table entries.
932 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
933 PREFIX_EVEX_0F11 table entries.
934 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
935 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
936 EVEX_W_0F11_P_3_M_{0,1} table entries.
937
219920a7
JB		 9382019-07-01 Jan Beulich <jbeulich@suse.com>
939
940 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
941 Delete.
942
e395f487
L		 9432019-06-27 H.J. Lu <hongjiu.lu@intel.com>
944
945 PR binutils/24719
946 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
947 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
948 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
949 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
950 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
951 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
952 EVEX_LEN_0F38C7_R_6_P_2_W_1.
953 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
954 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
955 PREFIX_EVEX_0F38C6_REG_6 entries.
956 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
957 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
958 EVEX_W_0F38C7_R_6_P_2 entries.
959 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
960 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
961 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
962 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
963 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
964 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
965 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
966
2b7bcc87
JB		 9672019-06-27 Jan Beulich <jbeulich@suse.com>
968
969 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
970 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
971 VEX_LEN_0F2D_P_3): Delete.
972 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
973 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
974 (prefix_table): ... here.
975
c1dc7af5
JB		 9762019-06-27 Jan Beulich <jbeulich@suse.com>
977
978 * i386-dis.c (Iq): Delete.
979 (Id): New.
980 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
981 TBM insns.
982 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
983 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
984 (OP_E_memory): Also honor needindex when deciding whether an
985 address size prefix needs printing.
986 (OP_I): Remove handling of q_mode. Add handling of d_mode.
987
d7560e2d
JW		 9882019-06-26 Jim Wilson <jimw@sifive.com>
989
990 PR binutils/24739
991 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
992 Set info->display_endian to info->endian_code.
993
2c703856
JB		 9942019-06-25 Jan Beulich <jbeulich@suse.com>
995
996 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
997 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
998 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
999 OPERAND_TYPE_ACC64 entries.
1000 * i386-init.h: Re-generate.
1001
54fbadc0
JB		 10022019-06-25 Jan Beulich <jbeulich@suse.com>
1003
1004 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1005 Delete.
1006 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1007 of dqa_mode.
1008 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1009 entries here.
1010 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1011 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1012
a280ab8e
JB		 10132019-06-25 Jan Beulich <jbeulich@suse.com>
1014
1015 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1016 variables.
1017
e1a1babd
JB		 10182019-06-25 Jan Beulich <jbeulich@suse.com>
1019
1020 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1021 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1022 movnti.
d7560e2d 1023 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1024 * i386-tbl.h: Re-generate.
1025
b8364fa7
JB		 10262019-06-25 Jan Beulich <jbeulich@suse.com>
1027
1028 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1029 * i386-tbl.h: Re-generate.
1030
ad692897
L		 10312019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1032
1033 * i386-dis-evex.h: Break into ...
1034 * i386-dis-evex-len.h: New file.
1035 * i386-dis-evex-mod.h: Likewise.
1036 * i386-dis-evex-prefix.h: Likewise.
1037 * i386-dis-evex-reg.h: Likewise.
1038 * i386-dis-evex-w.h: Likewise.
1039 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1040 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1041 i386-dis-evex-mod.h.
1042
f0a6222e
L		 10432019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1044
1045 PR binutils/24700
1046 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1047 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1048 EVEX_W_0F385B_P_2.
1049 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1050 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1051 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1052 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1053 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1054 EVEX_LEN_0F385B_P_2_W_1.
1055 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1056 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1057 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1058 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1059 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1060 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1061 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1062 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1063 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1064 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1065
6e1c90b7
L		 10662019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1067
1068 PR binutils/24691
1069 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1070 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1071 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1072 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1073 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1074 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1075 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1076 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1077 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1078 EVEX_LEN_0F3A43_P_2_W_1.
1079 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1080 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1081 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1082 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1083 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1084 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1085 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1086 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1087 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1088 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1089 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1090 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1091
bcc5a6eb
NC		 10922019-06-14 Nick Clifton <nickc@redhat.com>
1093
1094 * po/fr.po; Updated French translation.
1095
e4c4ac46
SH		 10962019-06-13 Stafford Horne <shorne@gmail.com>
1097
1098 * or1k-asm.c: Regenerated.
1099 * or1k-desc.c: Regenerated.
1100 * or1k-desc.h: Regenerated.
1101 * or1k-dis.c: Regenerated.
1102 * or1k-ibld.c: Regenerated.
1103 * or1k-opc.c: Regenerated.
1104 * or1k-opc.h: Regenerated.
1105 * or1k-opinst.c: Regenerated.
1106
a0e44ef5
PB		 11072019-06-12 Peter Bergner <bergner@linux.ibm.com>
1108
1109 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1110
12efd68d
L		 11112019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1112
1113 PR binutils/24633
1114 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1115 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1116 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1117 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1118 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1119 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1120 EVEX_LEN_0F3A1B_P_2_W_1.
1121 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1122 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1123 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1124 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1125 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1126 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1127 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1128 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1129
63c6fc6c
L		 11302019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1131
1132 PR binutils/24626
1133 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1134 EVEX.vvvv when disassembling VEX and EVEX instructions.
1135 (OP_VEX): Set vex.register_specifier to 0 after readding
1136 vex.register_specifier.
1137 (OP_Vex_2src_1): Likewise.
1138 (OP_Vex_2src_2): Likewise.
1139 (OP_LWP_E): Likewise.
1140 (OP_EX_Vex): Don't check vex.register_specifier.
1141 (OP_XMM_Vex): Likewise.
1142
9186c494
L		 11432019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1144 Lili Cui <lili.cui@intel.com>
1145
1146 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1147 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1148 instructions.
1149 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1150 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1151 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1152 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1153 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1154 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1155 * i386-init.h: Regenerated.
1156 * i386-tbl.h: Likewise.
1157
5d79adc4
L		 11582019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1159 Lili Cui <lili.cui@intel.com>
1160
1161 * doc/c-i386.texi: Document enqcmd.
1162 * testsuite/gas/i386/enqcmd-intel.d: New file.
1163 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1164 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1165 * testsuite/gas/i386/enqcmd.d: Likewise.
1166 * testsuite/gas/i386/enqcmd.s: Likewise.
1167 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1168 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1169 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1170 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1171 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1172 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1173 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1174 and x86-64-enqcmd.
1175
a9d96ab9
AH		 11762019-06-04 Alan Hayward <alan.hayward@arm.com>
1177
1178 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1179
4f6d070a
AM		 11802019-06-03 Alan Modra <amodra@gmail.com>
1181
1182 * ppc-dis.c (prefix_opcd_indices): Correct size.
1183
a2f4b66c
L		 11842019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1185
1186 PR gas/24625
1187 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1188 Disp8ShiftVL.
1189 * i386-tbl.h: Regenerated.
1190
405b5bd8
AM		 11912019-05-24 Alan Modra <amodra@gmail.com>
1192
1193 * po/POTFILES.in: Regenerate.
1194
8acf1435
PB		 11952019-05-24 Peter Bergner <bergner@linux.ibm.com>
1196 Alan Modra <amodra@gmail.com>
1197
1198 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1199 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1200 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1201 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1202 XTOP>): Define and add entries.
1203 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1204 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1205 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1206 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1207
dd7efa79
PB		 12082019-05-24 Peter Bergner <bergner@linux.ibm.com>
1209 Alan Modra <amodra@gmail.com>
1210
1211 * ppc-dis.c (ppc_opts): Add "future" entry.
1212 (PREFIX_OPCD_SEGS): Define.
1213 (prefix_opcd_indices): New array.
1214 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1215 (lookup_prefix): New function.
1216 (print_insn_powerpc): Handle 64-bit prefix instructions.
1217 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1218 (PMRR, POWERXX): Define.
1219 (prefix_opcodes): New instruction table.
1220 (prefix_num_opcodes): New constant.
1221
79472b45
JM		 12222019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1223
1224 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1225 * configure: Regenerated.
1226 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1227 and cpu/bpf.opc.
1228 (HFILES): Add bpf-desc.h and bpf-opc.h.
1229 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1230 bpf-ibld.c and bpf-opc.c.
1231 (BPF_DEPS): Define.
1232 * Makefile.in: Regenerated.
1233 * disassemble.c (ARCH_bpf): Define.
1234 (disassembler): Add case for bfd_arch_bpf.
1235 (disassemble_init_for_target): Likewise.
1236 (enum epbf_isa_attr): Define.
1237 * disassemble.h: extern print_insn_bpf.
1238 * bpf-asm.c: Generated.
1239 * bpf-opc.h: Likewise.
1240 * bpf-opc.c: Likewise.
1241 * bpf-ibld.c: Likewise.
1242 * bpf-dis.c: Likewise.
1243 * bpf-desc.h: Likewise.
1244 * bpf-desc.c: Likewise.
1245
ba6cd17f
SD		 12462019-05-21 Sudakshina Das <sudi.das@arm.com>
1247
1248 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1249 and VMSR with the new operands.
1250
e39c1607
SD		 12512019-05-21 Sudakshina Das <sudi.das@arm.com>
1252
1253 * arm-dis.c (enum mve_instructions): New enum
1254 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1255 and cneg.
1256 (mve_opcodes): New instructions as above.
1257 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1258 csneg and csel.
1259 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1260
23d00a41
SD		 12612019-05-21 Sudakshina Das <sudi.das@arm.com>
1262
1263 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1264 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1265 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1266 uqshl, urshrl and urshr.
1267 (is_mve_okay_in_it): Add new instructions to TRUE list.
1268 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1269 (print_insn_mve): Updated to accept new %j,
1270 %<bitfield>m and %<bitfield>n patterns.
1271
cd4797ee
FS		 12722019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1273
1274 * mips-opc.c (mips_builtin_opcodes): Change source register
1275 constraint for DAUI.
1276
999b073b
NC		 12772019-05-20 Nick Clifton <nickc@redhat.com>
1278
1279 * po/fr.po: Updated French translation.
1280
14b456f2
AV		 12812019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1282 Michael Collison <michael.collison@arm.com>
1283
1284 * arm-dis.c (thumb32_opcodes): Add new instructions.
1285 (enum mve_instructions): Likewise.
1286 (enum mve_undefined): Add new reasons.
1287 (is_mve_encoding_conflict): Handle new instructions.
1288 (is_mve_undefined): Likewise.
1289 (is_mve_unpredictable): Likewise.
1290 (print_mve_undefined): Likewise.
1291 (print_mve_size): Likewise.
1292
f49bb598
AV		 12932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1294 Michael Collison <michael.collison@arm.com>
1295
1296 * arm-dis.c (thumb32_opcodes): Add new instructions.
1297 (enum mve_instructions): Likewise.
1298 (is_mve_encoding_conflict): Handle new instructions.
1299 (is_mve_undefined): Likewise.
1300 (is_mve_unpredictable): Likewise.
1301 (print_mve_size): Likewise.
1302
56858bea
AV		 13032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1304 Michael Collison <michael.collison@arm.com>
1305
1306 * arm-dis.c (thumb32_opcodes): Add new instructions.
1307 (enum mve_instructions): Likewise.
1308 (is_mve_encoding_conflict): Likewise.
1309 (is_mve_unpredictable): Likewise.
1310 (print_mve_size): Likewise.
1311
e523f101
AV		 13122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1313 Michael Collison <michael.collison@arm.com>
1314
1315 * arm-dis.c (thumb32_opcodes): Add new instructions.
1316 (enum mve_instructions): Likewise.
1317 (is_mve_encoding_conflict): Handle new instructions.
1318 (is_mve_undefined): Likewise.
1319 (is_mve_unpredictable): Likewise.
1320 (print_mve_size): Likewise.
1321
66dcaa5d
AV		 13222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1323 Michael Collison <michael.collison@arm.com>
1324
1325 * arm-dis.c (thumb32_opcodes): Add new instructions.
1326 (enum mve_instructions): Likewise.
1327 (is_mve_encoding_conflict): Handle new instructions.
1328 (is_mve_undefined): Likewise.
1329 (is_mve_unpredictable): Likewise.
1330 (print_mve_size): Likewise.
1331 (print_insn_mve): Likewise.
1332
d052b9b7
AV		 13332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1334 Michael Collison <michael.collison@arm.com>
1335
1336 * arm-dis.c (thumb32_opcodes): Add new instructions.
1337 (print_insn_thumb32): Handle new instructions.
1338
ed63aa17
AV		 13392019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1340 Michael Collison <michael.collison@arm.com>
1341
1342 * arm-dis.c (enum mve_instructions): Add new instructions.
1343 (enum mve_undefined): Add new reasons.
1344 (is_mve_encoding_conflict): Handle new instructions.
1345 (is_mve_undefined): Likewise.
1346 (is_mve_unpredictable): Likewise.
1347 (print_mve_undefined): Likewise.
1348 (print_mve_size): Likewise.
1349 (print_mve_shift_n): Likewise.
1350 (print_insn_mve): Likewise.
1351
897b9bbc
AV		 13522019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1353 Michael Collison <michael.collison@arm.com>
1354
1355 * arm-dis.c (enum mve_instructions): Add new instructions.
1356 (is_mve_encoding_conflict): Handle new instructions.
1357 (is_mve_unpredictable): Likewise.
1358 (print_mve_rotate): Likewise.
1359 (print_mve_size): Likewise.
1360 (print_insn_mve): Likewise.
1361
1c8f2df8
AV		 13622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1363 Michael Collison <michael.collison@arm.com>
1364
1365 * arm-dis.c (enum mve_instructions): Add new instructions.
1366 (is_mve_encoding_conflict): Handle new instructions.
1367 (is_mve_unpredictable): Likewise.
1368 (print_mve_size): Likewise.
1369 (print_insn_mve): Likewise.
1370
d3b63143
AV		 13712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1372 Michael Collison <michael.collison@arm.com>
1373
1374 * arm-dis.c (enum mve_instructions): Add new instructions.
1375 (enum mve_undefined): Add new reasons.
1376 (is_mve_encoding_conflict): Handle new instructions.
1377 (is_mve_undefined): Likewise.
1378 (is_mve_unpredictable): Likewise.
1379 (print_mve_undefined): Likewise.
1380 (print_mve_size): Likewise.
1381 (print_insn_mve): Likewise.
1382
14925797
AV		 13832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1384 Michael Collison <michael.collison@arm.com>
1385
1386 * arm-dis.c (enum mve_instructions): Add new instructions.
1387 (is_mve_encoding_conflict): Handle new instructions.
1388 (is_mve_undefined): Likewise.
1389 (is_mve_unpredictable): Likewise.
1390 (print_mve_size): Likewise.
1391 (print_insn_mve): Likewise.
1392
c507f10b
AV		 13932019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1394 Michael Collison <michael.collison@arm.com>
1395
1396 * arm-dis.c (enum mve_instructions): Add new instructions.
1397 (enum mve_unpredictable): Add new reasons.
1398 (enum mve_undefined): Likewise.
1399 (is_mve_okay_in_it): Handle new isntructions.
1400 (is_mve_encoding_conflict): Likewise.
1401 (is_mve_undefined): Likewise.
1402 (is_mve_unpredictable): Likewise.
1403 (print_mve_vmov_index): Likewise.
1404 (print_simd_imm8): Likewise.
1405 (print_mve_undefined): Likewise.
1406 (print_mve_unpredictable): Likewise.
1407 (print_mve_size): Likewise.
1408 (print_insn_mve): Likewise.
1409
bf0b396d
AV		 14102019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1411 Michael Collison <michael.collison@arm.com>
1412
1413 * arm-dis.c (enum mve_instructions): Add new instructions.
1414 (enum mve_unpredictable): Add new reasons.
1415 (enum mve_undefined): Likewise.
1416 (is_mve_encoding_conflict): Handle new instructions.
1417 (is_mve_undefined): Likewise.
1418 (is_mve_unpredictable): Likewise.
1419 (print_mve_undefined): Likewise.
1420 (print_mve_unpredictable): Likewise.
1421 (print_mve_rounding_mode): Likewise.
1422 (print_mve_vcvt_size): Likewise.
1423 (print_mve_size): Likewise.
1424 (print_insn_mve): Likewise.
1425
ef1576a1
AV		 14262019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1427 Michael Collison <michael.collison@arm.com>
1428
1429 * arm-dis.c (enum mve_instructions): Add new instructions.
1430 (enum mve_unpredictable): Add new reasons.
1431 (enum mve_undefined): Likewise.
1432 (is_mve_undefined): Handle new instructions.
1433 (is_mve_unpredictable): Likewise.
1434 (print_mve_undefined): Likewise.
1435 (print_mve_unpredictable): Likewise.
1436 (print_mve_size): Likewise.
1437 (print_insn_mve): Likewise.
1438
aef6d006
AV		 14392019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1440 Michael Collison <michael.collison@arm.com>
1441
1442 * arm-dis.c (enum mve_instructions): Add new instructions.
1443 (enum mve_undefined): Add new reasons.
1444 (insns): Add new instructions.
1445 (is_mve_encoding_conflict):
1446 (print_mve_vld_str_addr): New print function.
1447 (is_mve_undefined): Handle new instructions.
1448 (is_mve_unpredictable): Likewise.
1449 (print_mve_undefined): Likewise.
1450 (print_mve_size): Likewise.
1451 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1452 (print_insn_mve): Handle new operands.
1453
04d54ace
AV		 14542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1455 Michael Collison <michael.collison@arm.com>
1456
1457 * arm-dis.c (enum mve_instructions): Add new instructions.
1458 (enum mve_unpredictable): Add new reasons.
1459 (is_mve_encoding_conflict): Handle new instructions.
1460 (is_mve_unpredictable): Likewise.
1461 (mve_opcodes): Add new instructions.
1462 (print_mve_unpredictable): Handle new reasons.
1463 (print_mve_register_blocks): New print function.
1464 (print_mve_size): Handle new instructions.
1465 (print_insn_mve): Likewise.
1466
9743db03
AV		 14672019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1468 Michael Collison <michael.collison@arm.com>
1469
1470 * arm-dis.c (enum mve_instructions): Add new instructions.
1471 (enum mve_unpredictable): Add new reasons.
1472 (enum mve_undefined): Likewise.
1473 (is_mve_encoding_conflict): Handle new instructions.
1474 (is_mve_undefined): Likewise.
1475 (is_mve_unpredictable): Likewise.
1476 (coprocessor_opcodes): Move NEON VDUP from here...
1477 (neon_opcodes): ... to here.
1478 (mve_opcodes): Add new instructions.
1479 (print_mve_undefined): Handle new reasons.
1480 (print_mve_unpredictable): Likewise.
1481 (print_mve_size): Handle new instructions.
1482 (print_insn_neon): Handle vdup.
1483 (print_insn_mve): Handle new operands.
1484
143275ea
AV		 14852019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1486 Michael Collison <michael.collison@arm.com>
1487
1488 * arm-dis.c (enum mve_instructions): Add new instructions.
1489 (enum mve_unpredictable): Add new values.
1490 (mve_opcodes): Add new instructions.
1491 (vec_condnames): New array with vector conditions.
1492 (mve_predicatenames): New array with predicate suffixes.
1493 (mve_vec_sizename): New array with vector sizes.
1494 (enum vpt_pred_state): New enum with vector predication states.
1495 (struct vpt_block): New struct type for vpt blocks.
1496 (vpt_block_state): Global struct to keep track of state.
1497 (mve_extract_pred_mask): New helper function.
1498 (num_instructions_vpt_block): Likewise.
1499 (mark_outside_vpt_block): Likewise.
1500 (mark_inside_vpt_block): Likewise.
1501 (invert_next_predicate_state): Likewise.
1502 (update_next_predicate_state): Likewise.
1503 (update_vpt_block_state): Likewise.
1504 (is_vpt_instruction): Likewise.
1505 (is_mve_encoding_conflict): Add entries for new instructions.
1506 (is_mve_unpredictable): Likewise.
1507 (print_mve_unpredictable): Handle new cases.
1508 (print_instruction_predicate): Likewise.
1509 (print_mve_size): New function.
1510 (print_vec_condition): New function.
1511 (print_insn_mve): Handle vpt blocks and new print operands.
1512
f08d8ce3
AV		 15132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1514
1515 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1516 8, 14 and 15 for Armv8.1-M Mainline.
1517
73cd51e5
AV		 15182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1519 Michael Collison <michael.collison@arm.com>
1520
1521 * arm-dis.c (enum mve_instructions): New enum.
1522 (enum mve_unpredictable): Likewise.
1523 (enum mve_undefined): Likewise.
1524 (struct mopcode32): New struct.
1525 (is_mve_okay_in_it): New function.
1526 (is_mve_architecture): Likewise.
1527 (arm_decode_field): Likewise.
1528 (arm_decode_field_multiple): Likewise.
1529 (is_mve_encoding_conflict): Likewise.
1530 (is_mve_undefined): Likewise.
1531 (is_mve_unpredictable): Likewise.
1532 (print_mve_undefined): Likewise.
1533 (print_mve_unpredictable): Likewise.
1534 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1535 (print_insn_mve): New function.
1536 (print_insn_thumb32): Handle MVE architecture.
1537 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1538
3076e594
NC		 15392019-05-10 Nick Clifton <nickc@redhat.com>
1540
1541 PR 24538
1542 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1543 end of the table prematurely.
1544
387e7624
FS		 15452019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1546
1547 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1548 macros for R6.
1549
0067be51
AM		 15502019-05-11 Alan Modra <amodra@gmail.com>
1551
1552 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1553 when -Mraw is in effect.
1554
42e6288f
MM		 15552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1556
1557 * aarch64-dis-2.c: Regenerate.
1558 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1559 (OP_SVE_BBB): New variant set.
1560 (OP_SVE_DDDD): New variant set.
1561 (OP_SVE_HHH): New variant set.
1562 (OP_SVE_HHHU): New variant set.
1563 (OP_SVE_SSS): New variant set.
1564 (OP_SVE_SSSU): New variant set.
1565 (OP_SVE_SHH): New variant set.
1566 (OP_SVE_SBBU): New variant set.
1567 (OP_SVE_DSS): New variant set.
1568 (OP_SVE_DHHU): New variant set.
1569 (OP_SVE_VMV_HSD_BHS): New variant set.
1570 (OP_SVE_VVU_HSD_BHS): New variant set.
1571 (OP_SVE_VVVU_SD_BH): New variant set.
1572 (OP_SVE_VVVU_BHSD): New variant set.
1573 (OP_SVE_VVV_QHD_DBS): New variant set.
1574 (OP_SVE_VVV_HSD_BHS): New variant set.
1575 (OP_SVE_VVV_HSD_BHS2): New variant set.
1576 (OP_SVE_VVV_BHS_HSD): New variant set.
1577 (OP_SVE_VV_BHS_HSD): New variant set.
1578 (OP_SVE_VVV_SD): New variant set.
1579 (OP_SVE_VVU_BHS_HSD): New variant set.
1580 (OP_SVE_VZVV_SD): New variant set.
1581 (OP_SVE_VZVV_BH): New variant set.
1582 (OP_SVE_VZV_SD): New variant set.
1583 (aarch64_opcode_table): Add sve2 instructions.
1584
28ed815a
MM		 15852019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1586
1587 * aarch64-asm-2.c: Regenerated.
1588 * aarch64-dis-2.c: Regenerated.
1589 * aarch64-opc-2.c: Regenerated.
1590 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1591 for SVE_SHLIMM_UNPRED_22.
1592 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1593 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1594 operand.
1595
fd1dc4a0
MM		 15962019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1597
1598 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1599 sve_size_tsz_bhs iclass encode.
1600 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1601 sve_size_tsz_bhs iclass decode.
1602
31e36ab3
MM		 16032019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1604
1605 * aarch64-asm-2.c: Regenerated.
1606 * aarch64-dis-2.c: Regenerated.
1607 * aarch64-opc-2.c: Regenerated.
1608 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1609 for SVE_Zm4_11_INDEX.
1610 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1611 (fields): Handle SVE_i2h field.
1612 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1613 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1614
1be5f94f
MM		 16152019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1616
1617 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1618 sve_shift_tsz_bhsd iclass encode.
1619 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1620 sve_shift_tsz_bhsd iclass decode.
1621
3c17238b
MM		 16222019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1623
1624 * aarch64-asm-2.c: Regenerated.
1625 * aarch64-dis-2.c: Regenerated.
1626 * aarch64-opc-2.c: Regenerated.
1627 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1628 (aarch64_encode_variant_using_iclass): Handle
1629 sve_shift_tsz_hsd iclass encode.
1630 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1631 sve_shift_tsz_hsd iclass decode.
1632 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1633 for SVE_SHRIMM_UNPRED_22.
1634 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1635 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1636 operand.
1637
cd50a87a
MM		 16382019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1639
1640 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1641 sve_size_013 iclass encode.
1642 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1643 sve_size_013 iclass decode.
1644
3c705960
MM		 16452019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1646
1647 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1648 sve_size_bh iclass encode.
1649 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1650 sve_size_bh iclass decode.
1651
0a57e14f
MM		 16522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1653
1654 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1655 sve_size_sd2 iclass encode.
1656 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1657 sve_size_sd2 iclass decode.
1658 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1659 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1660
c469c864
MM		 16612019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1662
1663 * aarch64-asm-2.c: Regenerated.
1664 * aarch64-dis-2.c: Regenerated.
1665 * aarch64-opc-2.c: Regenerated.
1666 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1667 for SVE_ADDR_ZX.
1668 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1669 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1670
116adc27
MM		 16712019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1672
1673 * aarch64-asm-2.c: Regenerated.
1674 * aarch64-dis-2.c: Regenerated.
1675 * aarch64-opc-2.c: Regenerated.
1676 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1677 for SVE_Zm3_11_INDEX.
1678 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1679 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1680 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1681 fields.
1682 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1683
3bd82c86
MM		 16842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1685
1686 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1687 sve_size_hsd2 iclass encode.
1688 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1689 sve_size_hsd2 iclass decode.
1690 * aarch64-opc.c (fields): Handle SVE_size field.
1691 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1692
adccc507
MM		 16932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1694
1695 * aarch64-asm-2.c: Regenerated.
1696 * aarch64-dis-2.c: Regenerated.
1697 * aarch64-opc-2.c: Regenerated.
1698 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1699 for SVE_IMM_ROT3.
1700 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1701 (fields): Handle SVE_rot3 field.
1702 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1703 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1704
5cd99750
MM		 17052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1706
1707 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1708 instructions.
1709
7ce2460a
MM		 17102019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1711
1712 * aarch64-tbl.h
1713 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1714 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1715 aarch64_feature_sve2bitperm): New feature sets.
1716 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1717 for feature set addresses.
1718 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1719 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1720
41cee089
FS		 17212019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1722 Faraz Shahbazker <fshahbazker@wavecomp.com>
1723
1724 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1725 argument and set ASE_EVA_R6 appropriately.
1726 (set_default_mips_dis_options): Pass ISA to above.
1727 (parse_mips_dis_option): Likewise.
1728 * mips-opc.c (EVAR6): New macro.
1729 (mips_builtin_opcodes): Add llwpe, scwpe.
1730
b83b4b13
SD		 17312019-05-01 Sudakshina Das <sudi.das@arm.com>
1732
1733 * aarch64-asm-2.c: Regenerated.
1734 * aarch64-dis-2.c: Regenerated.
1735 * aarch64-opc-2.c: Regenerated.
1736 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1737 AARCH64_OPND_TME_UIMM16.
1738 (aarch64_print_operand): Likewise.
1739 * aarch64-tbl.h (QL_IMM_NIL): New.
1740 (TME): New.
1741 (_TME_INSN): New.
1742 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1743
4a90ce95
JD		 17442019-04-29 John Darrington <john@darrington.wattle.id.au>
1745
1746 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1747
a45328b9
AB		 17482019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1749 Faraz Shahbazker <fshahbazker@wavecomp.com>
1750
1751 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1752
d10be0cb
JD		 17532019-04-24 John Darrington <john@darrington.wattle.id.au>
1754
1755 * s12z-opc.h: Add extern "C" bracketing to help
1756 users who wish to use this interface in c++ code.
1757
a679f24e
JD		 17582019-04-24 John Darrington <john@darrington.wattle.id.au>
1759
1760 * s12z-opc.c (bm_decode): Handle bit map operations with the
1761 "reserved0" mode.
1762
32c36c3c
AV		 17632019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1764
1765 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1766 specifier. Add entries for VLDR and VSTR of system registers.
1767 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1768 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1769 of %J and %K format specifier.
1770
efd6b359
AV		 17712019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1772
1773 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1774 Add new entries for VSCCLRM instruction.
1775 (print_insn_coprocessor): Handle new %C format control code.
1776
6b0dd094
AV		 17772019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1778
1779 * arm-dis.c (enum isa): New enum.
1780 (struct sopcode32): New structure.
1781 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1782 set isa field of all current entries to ANY.
1783 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1784 Only match an entry if its isa field allows the current mode.
1785
4b5a202f
AV		 17862019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1787
1788 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1789 CLRM.
1790 (print_insn_thumb32): Add logic to print %n CLRM register list.
1791
60f993ce
AV		 17922019-04-15 Sudakshina Das <sudi.das@arm.com>
1793
1794 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1795 and %Q patterns.
1796
f6b2b12d
AV		 17972019-04-15 Sudakshina Das <sudi.das@arm.com>
1798
1799 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1800 (print_insn_thumb32): Edit the switch case for %Z.
1801
1889da70
AV		 18022019-04-15 Sudakshina Das <sudi.das@arm.com>
1803
1804 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1805
65d1bc05
AV		 18062019-04-15 Sudakshina Das <sudi.das@arm.com>
1807
1808 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1809
1caf72a5
AV		 18102019-04-15 Sudakshina Das <sudi.das@arm.com>
1811
1812 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1813
f1c7f421
AV		 18142019-04-15 Sudakshina Das <sudi.das@arm.com>
1815
1816 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1817 Arm register with r13 and r15 unpredictable.
1818 (thumb32_opcodes): New instructions for bfx and bflx.
1819
4389b29a
AV		 18202019-04-15 Sudakshina Das <sudi.das@arm.com>
1821
1822 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1823
e5d6e09e
AV		 18242019-04-15 Sudakshina Das <sudi.das@arm.com>
1825
1826 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1827
e12437dc
AV		 18282019-04-15 Sudakshina Das <sudi.das@arm.com>
1829
1830 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1831
031254f2
AV		 18322019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1833
1834 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1835
e5a557ac
JD		 18362019-04-12 John Darrington <john@darrington.wattle.id.au>
1837
1838 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1839 "optr". ("operator" is a reserved word in c++).
1840
bd7ceb8d
SD		 18412019-04-11 Sudakshina Das <sudi.das@arm.com>
1842
1843 * aarch64-opc.c (aarch64_print_operand): Add case for
1844 AARCH64_OPND_Rt_SP.
1845 (verify_constraints): Likewise.
1846 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1847 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1848 to accept Rt|SP as first operand.
1849 (AARCH64_OPERANDS): Add new Rt_SP.
1850 * aarch64-asm-2.c: Regenerated.
1851 * aarch64-dis-2.c: Regenerated.
1852 * aarch64-opc-2.c: Regenerated.
1853
e54010f1
SD		 18542019-04-11 Sudakshina Das <sudi.das@arm.com>
1855
1856 * aarch64-asm-2.c: Regenerated.
1857 * aarch64-dis-2.c: Likewise.
1858 * aarch64-opc-2.c: Likewise.
1859 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1860
7e96e219
RS		 18612019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1862
1863 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1864
6f2791d5
L		 18652019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1866
1867 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1868 * i386-init.h: Regenerated.
1869
e392bad3
AM		 18702019-04-07 Alan Modra <amodra@gmail.com>
1871
1872 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1873 op_separator to control printing of spaces, comma and parens
1874 rather than need_comma, need_paren and spaces vars.
1875
dffaa15c
AM		 18762019-04-07 Alan Modra <amodra@gmail.com>
1877
1878 PR 24421
1879 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1880 (print_insn_neon, print_insn_arm): Likewise.
1881
d6aab7a1
XG		 18822019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1883
1884 * i386-dis-evex.h (evex_table): Updated to support BF16
1885 instructions.
1886 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1887 and EVEX_W_0F3872_P_3.
1888 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1889 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1890 * i386-opc.h (enum): Add CpuAVX512_BF16.
1891 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1892 * i386-opc.tbl: Add AVX512 BF16 instructions.
1893 * i386-init.h: Regenerated.
1894 * i386-tbl.h: Likewise.
1895
66e85460
AM		 18962019-04-05 Alan Modra <amodra@gmail.com>
1897
1898 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1899 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1900 to favour printing of "-" branch hint when using the "y" bit.
1901 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1902
c2b1c275
AM		 19032019-04-05 Alan Modra <amodra@gmail.com>
1904
1905 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1906 opcode until first operand is output.
1907
aae9718e
PB		 19082019-04-04 Peter Bergner <bergner@linux.ibm.com>
1909
1910 PR gas/24349
1911 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1912 (valid_bo_post_v2): Add support for 'at' branch hints.
1913 (insert_bo): Only error on branch on ctr.
1914 (get_bo_hint_mask): New function.
1915 (insert_boe): Add new 'branch_taken' formal argument. Add support
1916 for inserting 'at' branch hints.
1917 (extract_boe): Add new 'branch_taken' formal argument. Add support
1918 for extracting 'at' branch hints.
1919 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1920 (BOE): Delete operand.
1921 (BOM, BOP): New operands.
1922 (RM): Update value.
1923 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1924 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1925 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1926 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1927 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1928 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1929 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1930 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1931 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1932 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1933 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1934 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1935 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1936 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1937 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1938 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1939 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1940 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1941 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1942 bttarl+>: New extended mnemonics.
1943
96a86c01
AM		 19442019-03-28 Alan Modra <amodra@gmail.com>
1945
1946 PR 24390
1947 * ppc-opc.c (BTF): Define.
1948 (powerpc_opcodes): Use for mtfsb*.
1949 * ppc-dis.c (print_insn_powerpc): Print fields with both
1950 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1951
796d6298
TC		 19522019-03-25 Tamar Christina <tamar.christina@arm.com>
1953
1954 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1955 (mapping_symbol_for_insn): Implement new algorithm.
1956 (print_insn): Remove duplicate code.
1957
60df3720
TC		 19582019-03-25 Tamar Christina <tamar.christina@arm.com>
1959
1960 * aarch64-dis.c (print_insn_aarch64):
1961 Implement override.
1962
51457761
TC		 19632019-03-25 Tamar Christina <tamar.christina@arm.com>
1964
1965 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1966 order.
1967
53b2f36b
TC		 19682019-03-25 Tamar Christina <tamar.christina@arm.com>
1969
1970 * aarch64-dis.c (last_stop_offset): New.
1971 (print_insn_aarch64): Use stop_offset.
1972
89199bb5
L		 19732019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1974
1975 PR gas/24359
1976 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1977 CPU_ANY_AVX2_FLAGS.
1978 * i386-init.h: Regenerated.
1979
97ed31ae
L		 19802019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1981
1982 PR gas/24348
1983 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1984 vmovdqu16, vmovdqu32 and vmovdqu64.
1985 * i386-tbl.h: Regenerated.
1986
0919bfe9
AK		 19872019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1988
1989 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1990 from vstrszb, vstrszh, and vstrszf.
1991
19922019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1993
1994 * s390-opc.txt: Add instruction descriptions.
1995
21820ebe
JW		 19962019-02-08 Jim Wilson <jimw@sifive.com>
1997
1998 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1999 <bne>: Likewise.
2000
f7dd2fb2
TC		 20012019-02-07 Tamar Christina <tamar.christina@arm.com>
2002
2003 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2004
6456d318
TC		 20052019-02-07 Tamar Christina <tamar.christina@arm.com>
2006
2007 PR binutils/23212
2008 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2009 * aarch64-opc.c (verify_elem_sd): New.
2010 (fields): Add FLD_sz entr.
2011 * aarch64-tbl.h (_SIMD_INSN): New.
2012 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2013 fmulx scalar and vector by element isns.
2014
4a83b610
NC		 20152019-02-07 Nick Clifton <nickc@redhat.com>
2016
2017 * po/sv.po: Updated Swedish translation.
2018
fc60b8c8
AK		 20192019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2020
2021 * s390-mkopc.c (main): Accept arch13 as cpu string.
2022 * s390-opc.c: Add new instruction formats and instruction opcode
2023 masks.
2024 * s390-opc.txt: Add new arch13 instructions.
2025
e10620d3
TC		 20262019-01-25 Sudakshina Das <sudi.das@arm.com>
2027
2028 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2029 (aarch64_opcode): Change encoding for stg, stzg
2030 st2g and st2zg.
2031 * aarch64-asm-2.c: Regenerated.
2032 * aarch64-dis-2.c: Regenerated.
2033 * aarch64-opc-2.c: Regenerated.
2034
20a4ca55
SD		 20352019-01-25 Sudakshina Das <sudi.das@arm.com>
2036
2037 * aarch64-asm-2.c: Regenerated.
2038 * aarch64-dis-2.c: Likewise.
2039 * aarch64-opc-2.c: Likewise.
2040 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2041
550fd7bf
SD		 20422019-01-25 Sudakshina Das <sudi.das@arm.com>
2043 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2044
2045 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2046 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2047 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2048 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2049 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2050 case for ldstgv_indexed.
2051 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2052 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2053 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2054 * aarch64-asm-2.c: Regenerated.
2055 * aarch64-dis-2.c: Regenerated.
2056 * aarch64-opc-2.c: Regenerated.
2057
d9938630
NC		 20582019-01-23 Nick Clifton <nickc@redhat.com>
2059
2060 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2061
375cd423
NC		 20622019-01-21 Nick Clifton <nickc@redhat.com>
2063
2064 * po/de.po: Updated German translation.
2065 * po/uk.po: Updated Ukranian translation.
2066
57299f48
CX		 20672019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2068 * mips-dis.c (mips_arch_choices): Fix typo in
2069 gs464, gs464e and gs264e descriptors.
2070
f48dfe41
NC		 20712019-01-19 Nick Clifton <nickc@redhat.com>
2072
2073 * configure: Regenerate.
2074 * po/opcodes.pot: Regenerate.
2075
f974f26c
NC		 20762018-06-24 Nick Clifton <nickc@redhat.com>
2077
2078 2.32 branch created.
2079
39f286cd
JD		 20802019-01-09 John Darrington <john@darrington.wattle.id.au>
2081
448b8ca8
JD		 2082 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2083 if it is null.
2084 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2085 zero.
2086
3107326d
AP		 20872019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2088
2089 * configure: Regenerate.
2090
7e9ca91e
AM		 20912019-01-07 Alan Modra <amodra@gmail.com>
2092
2093 * configure: Regenerate.
2094 * po/POTFILES.in: Regenerate.
2095
ef1ad42b
JD		 20962019-01-03 John Darrington <john@darrington.wattle.id.au>
2097
2098 * s12z-opc.c: New file.
2099 * s12z-opc.h: New file.
2100 * s12z-dis.c: Removed all code not directly related to display
2101 of instructions. Used the interface provided by the new files
2102 instead.
2103 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2104 * Makefile.in: Regenerate.
ef1ad42b 2105 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2106 * configure: Regenerate.
ef1ad42b 2107
82704155
AM		 21082019-01-01 Alan Modra <amodra@gmail.com>
2109
2110 Update year range in copyright notice of all files.
2111
d5c04e1b 2112For older changes see ChangeLog-2018
3499769a 2113\f
d5c04e1b 2114Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2115
2116Copying and distribution of this file, with or without modification,
2117are permitted in any medium without royalty provided the copyright
2118notice and this notice are preserved.
2119
2120Local Variables:
2121mode: change-log
2122left-margin: 8
2123fill-column: 74
2124version-control: never
2125End:
GDB Binutils - Deliverables
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