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RISC-V: Accept version, supervisor ext and more than one NSE for -march.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
1080bf78
JW		 12018-12-03 Kito Cheng <kito@andestech.com>
2
3 * riscv-opc.c: Change the type of xlen, because type of
4 xlen_requirement changed.
5
57b64c41
EB		 62018-12-03 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
7
8 PR 23193
9 PR 19721
10 * aarch64-tbl.h (aarch64_opcode_table): Only disassemble an ORR
11 encoding as MOV if the shift operation is a left shift of zero.
12
12951a2f
JW		 132018-11-29 Jim Wilson <jimw@sifive.com>
14
15 * riscv-opc.c (unimp): Mark compressed unimp as INSN_ALIAS.
16 (c.unimp): New.
17
4765cd61
JW		 182018-11-27 Jim Wilson <jimw@sifive.com>
19
20 * riscv-opc.c (ciw): Fix whitespace to align columns.
21 (ca): New.
22
27f42a4d
JD		 232018-11-21 John Darrington <john@darrington.wattle.id.au>
24
25 * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
26 if the postbyte matches the appropriate pattern.
27
97b3f392
FT		 282018-11-13 Francois H. Theron <francois.theron@netronome.com>
29
30 * nfp-dis.c: Fix crc[] disassembly if operands are swapped.
31
3a0f69be
SD		 322018-11-12 Sudakshina Das <sudi.das@arm.com>
33
34 * aarch64-opc.c (aarch64_sys_regs_dc): New entries for
35 IGVAC, IGSW, CGSW, CIGSW, CGVAC, CGVAP, CGVADP, CIGVAC, GVA,
36 IGDVAC, IGDSW, CGDSW, CIGDSW, CGDVAC, CGDVAP, CGDVADP,
37 CIGDVAC and GZVA.
38 (aarch64_sys_ins_reg_supported_p): New check for above.
39
70f3d23a
SD		 402018-11-12 Sudakshina Das <sudi.das@arm.com>
41
42 * aarch64-opc.c (aarch64_sys_regs): New entries for TCO,
43 TFSRE0_SL1, TFSR_EL1, TFSR_EL2, TFSR_EL3, TFSR_EL12,
44 RGSR_EL1 and GCR_EL1.
45 (aarch64_sys_reg_supported_p): New check for above.
46 (aarch64_pstatefields): New entry for TCO.
47 (aarch64_pstatefield_supported_p): New check for above.
48
503ba600
SD		 492018-11-12 Sudakshina Das <sudi.das@arm.com>
50
51 * aarch64-asm.c (aarch64_ins_addr_simple_2): New.
52 * aarch64-asm.h (ins_addr_simple_2): Declare the above.
53 * aarch64-dis.c (aarch64_ext_addr_simple_2): New.
54 * aarch64-dis.h (ext_addr_simple_2): Declare the above.
55 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
56 AARCH64_OPND_ADDR_SIMPLE_2 and ldstgv_indexed.
57 (aarch64_print_operand): Add case for AARCH64_OPND_ADDR_SIMPLE_2.
58 * aarch64-tbl.h (aarch64_opcode_table): Add stgv and ldgv.
59 (AARCH64_OPERANDS): Define ADDR_SIMPLE_2.
60 * aarch64-asm-2.c: Regenerated.
61 * aarch64-dis-2.c: Regenerated.
62 * aarch64-opc-2.c: Regenerated.
63
e6025b54
SD		 642018-11-12 Sudakshina Das <sudi.das@arm.com>
65
66 * aarch64-tbl.h (QL_LDG): New.
67 (aarch64_opcode_table): Add ldg.
68 * aarch64-asm-2.c: Regenerated.
69 * aarch64-dis-2.c: Regenerated.
70 * aarch64-opc-2.c: Regenerated.
71
fb3265b3
SD		 722018-11-12 Sudakshina Das <sudi.das@arm.com>
73
74 * aarch64-opc.c (aarch64_opnd_qualifiers): Add new data
75 for AARCH64_OPND_QLF_imm_tag.
76 (operand_general_constraint_met_p): Add case for
77 AARCH64_OPND_ADDR_SIMM11 and AARCH64_OPND_ADDR_SIMM13.
78 (aarch64_print_operand): Likewise.
79 * aarch64-tbl.h (QL_LDST_AT, QL_STGP): New.
80 (aarch64_opcode_table): Add stg, stzg, st2g, stz2g and stgp
81 for both offset and pre/post indexed versions.
82 (AARCH64_OPERANDS): Define ADDR_SIMM11 and ADDR_SIMM13.
83 * aarch64-asm-2.c: Regenerated.
84 * aarch64-dis-2.c: Regenerated.
85 * aarch64-opc-2.c: Regenerated.
86
b731bc3b
SD		 872018-11-12 Sudakshina Das <sudi.das@arm.com>
88
89 * aarch64-tbl.h (aarch64_opcode_table): Add subp, subps and cmpp.
90 * aarch64-asm-2.c: Regenerated.
91 * aarch64-dis-2.c: Regenerated.
92 * aarch64-opc-2.c: Regenerated.
93
193614f2
SD		 942018-11-12 Sudakshina Das <sudi.das@arm.com>
95
96 * aarch64-opc.h (aarch64_field_kind): New FLD_imm4_3.
97 (OPD_F_SHIFT_BY_4, operand_need_shift_by_four): New.
98 * aarch64-opc.c (fields): Add entry for imm4_3.
99 (operand_general_constraint_met_p): Add cases for
100 AARCH64_OPND_UIMM4_ADDG and AARCH64_OPND_UIMM10.
101 (aarch64_print_operand): Likewise.
102 * aarch64-tbl.h (QL_ADDG): New.
103 (aarch64_opcode_table): Add addg, subg, irg and gmi.
104 (AARCH64_OPERANDS): Define UIMM4_ADDG and UIMM10.
105 * aarch64-asm.c (aarch64_ins_imm): Add case for
106 operand_need_shift_by_four.
107 * aarch64-asm-2.c: Regenerated.
108 * aarch64-dis-2.c: Regenerated.
109 * aarch64-opc-2.c: Regenerated.
110
73b605ec
SD		 1112018-11-12 Sudakshina Das <sudi.das@arm.com>
112
113 * aarch64-tbl.h (aarch64_feature_memtag): New.
114 (MEMTAG, MEMTAG_INSN): New.
115
0632eeea
SD		 1162018-11-06 Sudakshina Das <sudi.das@arm.com>
117
118 * arm-dis.c (select_arm_features): Update bfd_mach_arm_8
119 with Armv8.5-A. Remove reduntant ARM_EXT2_FP16_FML.
120
71553718
AM		 1212018-11-06 Alan Modra <amodra@gmail.com>
122
123 * ppc-opc.c (insert_arx, insert_ary, insert_rx, insert_ry, insert_ls),
124 (insert_evuimm1_ex0, insert_evuimm2_ex0, insert_evuimm4_ex0),
125 (insert_evuimm8_ex0, insert_evuimm_lt8, insert_evuimm_lt16),
126 (insert_rD_rS_even, insert_off_lsp, insert_off_spe2, insert_Ddd):
127 Don't return zero on error, insert mask bits instead.
128 (insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w): Delete.
129 (insert_sh6, extract_sh6): Delete dead code.
130 (insert_sprbat, insert_sprg): Use unsigned comparisions.
131 (powerpc_operands <OIMM>): Set shift count rather than using
132 PPC_OPSHIFT_INV.
133 <SE_SDH, SE_SDW>: Likewise. Don't use insert/extract functions.
134
4dd4e639
JB		 1352018-11-06 Jan Beulich <jbeulich@suse.com>
136
137 * i386-dis-evex.h (evex_table): Use K suffix instead of %LW for
138 vpbroadcast{d,q} with GPR operand.
139
9819647a
JB		 1402018-11-06 Jan Beulich <jbeulich@suse.com>
141
142 * i386-dis.c (EVEX_W_0F6E_P_2, EVEX_W_0F7E_P_2): Delete.
143 * i386-dis-evex.h (evex_table): Move vmov[dq} with GPR operand
144 cases up one level in the hierarchy.
145
58a211d2
JB		 1462018-11-06 Jan Beulich <jbeulich@suse.com>
147
148 * i386-dis.c (MOD_VEX_W_0_0F92_P_3_LEN_0,
149 MOD_VEX_W_1_0F92_P_3_LEN_0): Fold into MOD_VEX_0F92_P_3_LEN_0.
150 (MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0): Fold
151 into MOD_VEX_0F93_P_3_LEN_0.
152 (vex_len_table, vex_w_table, mod_table): Move kmov[dq} with GPR
153 operand cases up one level in the hierarchy.
154
b50c9f31
JB		 1552018-11-06 Jan Beulich <jbeulich@suse.com>
156
157 * i386-dis.c (VEX_W_0FC4_P_2, VEX_W_0FC5_P_2, VEX_W_0F3A14_P_2,
158 VEX_W_0F3A15_P_2, VEX_W_0F3A20_P_2, EVEX_W_0F3A16_P_2,
159 EVEX_W_0F3A22_P_2): Delete.
160 (vex_len_table, vex_w_table): Move vpextr{b,w} and vpinsr{b,w}
161 entries up one level in the hierarchy.
162 (OP_E_memory): Handle dq_mode when determining Disp8 shift
163 value.
164 * i386-dis-evex.h (evex_table): Move vpextr{d,q} and vpinsr{d,q}
165 entries up one level in the hierarchy.
166 * i386-opc.tbl (vpextrb, vpextrw, vpinsrb, vpinsrw): Change to
167 VexWIG for AVX flavors.
168 * i386-tbl.h: Re-generate.
169
931d03b7
JB		 1702018-11-06 Jan Beulich <jbeulich@suse.com>
171
172 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vmovd, vpcmpestri,
173 vpcmpestrm, vpextrd, vpinsrd, vpbroadcastd, vcvtusi2sd,
174 vcvtusi2ss, kmovd): Drop VexW=1.
175 * i386-tbl.h: Re-generate.
176
fd71a375
JB		 1772018-11-06 Jan Beulich <jbeulich@suse.com>
178
179 * i386-opc.tbl (Vex128, Vex256, VexLIG, EVex128, EVex256,
180 EVex512, EVexLIG, EVexDYN): New.
181 (ldmxcsr, stmxcsr, vldmxcsr, vstmxcsr, all BMI, BMI2, and TBM
182 insns): Use Vex128 instead of Vex=3 (aka VexLIG).
183 (vextractps, vinsertps, vpextr*, vpinsr*): Use EVex128 instead
184 of EVex=4 (aka EVexLIG).
185 * i386-tbl.h: Re-generate.
186
563c7eef
JB		 1872018-11-06 Jan Beulich <jbeulich@suse.com>
188
189 * i386-opc.tbl (pextrw, vpextrw): Add Load to 0F C5 forms.
190 (vpmaxub): Re-order attributes on AVX512BW flavor.
191 * i386-tbl.h: Re-generate.
192
0aaca1d9
JB		 1932018-11-06 Jan Beulich <jbeulich@suse.com>
194
195 * i386-opc.tbl (vandnp*, vandp*, vcmp*, vcvtss2sd, vorp*,
196 vpmaxub, vmovntdqa, vmpsadbw, vphsub*): Use VexWIG instead of
197 Vex=1 on AVX / AVX2 flavors.
198 (vpmaxub): Re-order attributes on AVX512BW flavor.
199 * i386-tbl.h: Re-generate.
200
bbae6b11
JB		 2012018-11-06 Jan Beulich <jbeulich@suse.com>
202
203 * i386-opc.tbl (VexW0, VexW1): New.
204 (vphadd*, vphsub*): Use VexW0 on XOP variants.
205 * i386-tbl.h: Re-generate.
206
192c2bfb
JD		 2072018-10-22 John Darrington <john@darrington.wattle.id.au>
208
209 * s12z-dis.c (decode_possible_symbol): Add fallback case.
210 (rel_15_7): Likewise.
211
0b347048
TC		 2122018-10-19 Tamar Christina <tamar.christina@arm.com>
213
214 * arm-dis.c (UNKNOWN_INSTRUCTION_32BIT): Format specifier for arm mode.
215 (UNKNOWN_INSTRUCTION_16BIT): Format specifier for thumb mode.
216 (print_insn_arm, print_insn_thumb16, print_insn_thumb32): Use them.
217
66e6f0b7
MM		 2182018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
219
220 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
221 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
222
673fe0f0
JB		 2232018-10-10 Jan Beulich <jbeulich@suse.com>
224
225 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
226 Size64. Add Size.
227 * i386-opc.h (Size16, Size32, Size64): Delete.
228 (Size): New.
229 (SIZE16, SIZE32, SIZE64): Define.
230 (struct i386_opcode_modifier): Drop size16, size32, and size64.
231 Add size.
232 * i386-opc.tbl (Size16, Size32, Size64): Define.
233 * i386-tbl.h: Re-generate.
234
104fefee
SD		 2352018-10-09 Sudakshina Das <sudi.das@arm.com>
236
237 * aarch64-opc.c (operand_general_constraint_met_p): Add
238 SSBS in the check for one-bit immediate.
239 (aarch64_sys_regs): New entry for SSBS.
240 (aarch64_sys_reg_supported_p): New check for above.
241 (aarch64_pstatefields): New entry for SSBS.
242 (aarch64_pstatefield_supported_p): New check for above.
243
a97330e7
SD		 2442018-10-09 Sudakshina Das <sudi.das@arm.com>
245
246 * aarch64-opc.c (aarch64_sys_regs): New entries for
247 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
248 (aarch64_sys_reg_supported_p): New checks for above.
249
ff605452
SD		 2502018-10-09 Sudakshina Das <sudi.das@arm.com>
251
252 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
253 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
254 with the hint immediate.
255 * aarch64-opc.c (aarch64_hint_options): New entries for
256 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
257 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
258 while checking for HINT_OPD_F_NOPRINT flag.
259 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
260 extract value.
261 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
262 (aarch64_opcode_table): Add entry for BTI.
263 (AARCH64_OPERANDS): Add new description for BTI targets.
264 * aarch64-asm-2.c: Regenerate.
265 * aarch64-dis-2.c: Regenerate.
266 * aarch64-opc-2.c: Regenerate.
267
af4bcb4c
SD		 2682018-10-09 Sudakshina Das <sudi.das@arm.com>
269
270 * aarch64-opc.c (aarch64_sys_regs): New entries for
271 rndr and rndrrs.
272 (aarch64_sys_reg_supported_p): New check for above.
273
3fd229a4
SD		 2742018-10-09 Sudakshina Das <sudi.das@arm.com>
275
276 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
277 (aarch64_sys_ins_reg_supported_p): New check for above.
278
2ac435d4
SD		 2792018-10-09 Sudakshina Das <sudi.das@arm.com>
280
281 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
282 AARCH64_OPND_SYSREG_SR.
283 * aarch64-opc.c (aarch64_print_operand): Likewise.
284 (aarch64_sys_regs_sr): Define table.
285 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
286 AARCH64_FEATURE_PREDRES.
287 * aarch64-tbl.h (aarch64_feature_predres): New.
288 (PREDRES, PREDRES_INSN): New.
289 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
290 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
291 * aarch64-asm-2.c: Regenerate.
292 * aarch64-dis-2.c: Regenerate.
293 * aarch64-opc-2.c: Regenerate.
294
68dfbb92
SD		 2952018-10-09 Sudakshina Das <sudi.das@arm.com>
296
297 * aarch64-tbl.h (aarch64_feature_sb): New.
298 (SB, SB_INSN): New.
299 (aarch64_opcode_table): Add entry for sb.
300 * aarch64-asm-2.c: Regenerate.
301 * aarch64-dis-2.c: Regenerate.
302 * aarch64-opc-2.c: Regenerate.
303
13c60ad7
SD		 3042018-10-09 Sudakshina Das <sudi.das@arm.com>
305
306 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
307 (aarch64_feature_frintts): New.
308 (FLAGMANIP, FRINTTS): New.
309 (aarch64_opcode_table): Add entries for xaflag, axflag
310 and frint[32,64][x,z] instructions.
311 * aarch64-asm-2.c: Regenerate.
312 * aarch64-dis-2.c: Regenerate.
313 * aarch64-opc-2.c: Regenerate.
314
70d56181
SD		 3152018-10-09 Sudakshina Das <sudi.das@arm.com>
316
317 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
318 (ARMV8_5, V8_5_INSN): New.
319
780f601c
TC		 3202018-10-08 Tamar Christina <tamar.christina@arm.com>
321
322 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
323
a4e78aa5
L		 3242018-10-05 H.J. Lu <hongjiu.lu@intel.com>
325
326 * i386-dis.c (rm_table): Add enclv.
327 * i386-opc.tbl: Add enclv.
328 * i386-tbl.h: Regenerated.
329
7fadb25d
SD		 3302018-10-05 Sudakshina Das <sudi.das@arm.com>
331
332 * arm-dis.c (arm_opcodes): Add sb.
333 (thumb32_opcodes): Likewise.
334
07f5f4c6
RH		 3352018-10-05 Richard Henderson <rth@twiddle.net>
336 Stafford Horne <shorne@gmail.com>
337
338 * or1k-desc.c: Regenerate.
339 * or1k-desc.h: Regenerate.
340 * or1k-opc.c: Regenerate.
341 * or1k-opc.h: Regenerate.
342 * or1k-opinst.c: Regenerate.
343
c8e98e36
SH		 3442018-10-05 Richard Henderson <rth@twiddle.net>
345
346 * or1k-asm.c: Regenerated.
347 * or1k-desc.c: Regenerated.
348 * or1k-desc.h: Regenerated.
349 * or1k-dis.c: Regenerated.
350 * or1k-ibld.c: Regenerated.
351 * or1k-opc.c: Regenerated.
352 * or1k-opc.h: Regenerated.
353 * or1k-opinst.c: Regenerated.
354
1c4f3780
RH		 3552018-10-05 Richard Henderson <rth@twiddle.net>
356
357 * or1k-asm.c: Regenerate.
358
bde90be2
TC		 3592018-10-03 Tamar Christina <tamar.christina@arm.com>
360
361 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
362 * aarch64-dis.c (print_operands): Refactor to take notes.
363 (print_verifier_notes): New.
364 (print_aarch64_insn): Apply constraint verifier.
365 (print_insn_aarch64_word): Update call to print_aarch64_insn.
366 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
367
a68f4cd2
TC		 3682018-10-03 Tamar Christina <tamar.christina@arm.com>
369
370 * aarch64-opc.c (init_insn_block): New.
371 (verify_constraints, aarch64_is_destructive_by_operands): New.
372 * aarch64-opc.h (verify_constraints): New.
373
755b748f
TC		 3742018-10-03 Tamar Christina <tamar.christina@arm.com>
375
376 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
377 * aarch64-opc.c (verify_ldpsw): Update arguments.
378
1d482394
TC		 3792018-10-03 Tamar Christina <tamar.christina@arm.com>
380
381 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
382 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
383
7e84b55d
TC		 3842018-10-03 Tamar Christina <tamar.christina@arm.com>
385
386 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
387 * aarch64-dis.c (insn_sequence): New.
388
eae424ae
TC		 3892018-10-03 Tamar Christina <tamar.christina@arm.com>
390
391 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
392 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
393 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
394 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
395 constraints.
396 (_SVE_INSNC): New.
397 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
398 constraints.
399 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
400 F_SCAN flags.
401 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
402 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
403 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
404 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
405 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
406 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
407 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
408
64a336ac
PD		 4092018-10-02 Palmer Dabbelt <palmer@sifive.com>
410
411 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
412
6031ac35
SL		 4132018-09-23 Sandra Loosemore <sandra@codesourcery.com>
414
415 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
416 are used when extracting signed fields and converting them to
417 potentially 64-bit types.
418
f24ff6e9
SM		 4192018-09-21 Simon Marchi <simon.marchi@ericsson.com>
420
421 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
422 * Makefile.in: Re-generate.
423 * aclocal.m4: Re-generate.
424 * configure: Re-generate.
425 * configure.ac: Remove check for -Wno-missing-field-initializers.
426 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
427 (csky_v2_opcodes): Likewise.
428
53b6d6f5
MR		 4292018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
430
431 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
432
fbaf61ad
NC		 4332018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
434
435 * nds32-asm.c (operand_fields): Remove the unused fields.
436 (nds32_opcodes): Remove the unused instructions.
437 * nds32-dis.c (nds32_ex9_info): Removed.
438 (nds32_parse_opcode): Updated.
439 (print_insn_nds32): Likewise.
440 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
441 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
442 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
443 build_opcode_hash_table): New functions.
444 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
445 nds32_opcode_table): New.
446 (hw_ktabs): Declare it to a pointer rather than an array.
447 (build_hash_table): Removed.
448 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
449 SYN_ROPT and upadte HW_GPR and HW_INT.
450 * nds32-dis.c (keywords): Remove const.
451 (match_field): New function.
452 (nds32_parse_opcode): Updated.
453 * disassemble.c (disassemble_init_for_target):
454 Add disassemble_init_nds32.
455 * nds32-dis.c (eum map_type): New.
456 (nds32_private_data): Likewise.
457 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
458 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
459 (print_insn_nds32): Updated.
460 * nds32-asm.c (parse_aext_reg): Add new parameter.
461 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
462 are allowed to use.
463 All callers changed.
464 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
465 (operand_fields): Add new fields.
466 (nds32_opcodes): Add new instructions.
467 (keyword_aridxi_mx): New keyword.
468 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
469 and NASM_ATTR_ZOL.
470 (ALU2_1, ALU2_2, ALU2_3): New macros.
471 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
472
4e2b1898
JW		 4732018-09-17 Kito Cheng <kito@andestech.com>
474
475 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
476
04e2a182
L		 4772018-09-17 H.J. Lu <hongjiu.lu@intel.com>
478
479 PR gas/23670
480 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
481 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
482 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
483 (EVEX_LEN_0F7E_P_1): Likewise.
484 (EVEX_LEN_0F7E_P_2): Likewise.
485 (EVEX_LEN_0FD6_P_2): Likewise.
486 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
487 (EVEX_LEN_TABLE): Likewise.
488 (EVEX_LEN_0F6E_P_2): New enum.
489 (EVEX_LEN_0F7E_P_1): Likewise.
490 (EVEX_LEN_0F7E_P_2): Likewise.
491 (EVEX_LEN_0FD6_P_2): Likewise.
492 (evex_len_table): New.
493 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
494 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
495 * i386-tbl.h: Regenerated.
496
d5f787c2
L		 4972018-09-17 H.J. Lu <hongjiu.lu@intel.com>
498
499 PR gas/23665
500 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
501 VEX_LEN_0F7E_P_2 entries.
502 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
503 * i386-tbl.h: Regenerated.
504
ec6f095a
L		 5052018-09-17 H.J. Lu <hongjiu.lu@intel.com>
506
507 * i386-dis.c (VZERO_Fixup): Removed.
508 (VZERO): Likewise.
509 (VEX_LEN_0F10_P_1): Likewise.
510 (VEX_LEN_0F10_P_3): Likewise.
511 (VEX_LEN_0F11_P_1): Likewise.
512 (VEX_LEN_0F11_P_3): Likewise.
513 (VEX_LEN_0F2E_P_0): Likewise.
514 (VEX_LEN_0F2E_P_2): Likewise.
515 (VEX_LEN_0F2F_P_0): Likewise.
516 (VEX_LEN_0F2F_P_2): Likewise.
517 (VEX_LEN_0F51_P_1): Likewise.
518 (VEX_LEN_0F51_P_3): Likewise.
519 (VEX_LEN_0F52_P_1): Likewise.
520 (VEX_LEN_0F53_P_1): Likewise.
521 (VEX_LEN_0F58_P_1): Likewise.
522 (VEX_LEN_0F58_P_3): Likewise.
523 (VEX_LEN_0F59_P_1): Likewise.
524 (VEX_LEN_0F59_P_3): Likewise.
525 (VEX_LEN_0F5A_P_1): Likewise.
526 (VEX_LEN_0F5A_P_3): Likewise.
527 (VEX_LEN_0F5C_P_1): Likewise.
528 (VEX_LEN_0F5C_P_3): Likewise.
529 (VEX_LEN_0F5D_P_1): Likewise.
530 (VEX_LEN_0F5D_P_3): Likewise.
531 (VEX_LEN_0F5E_P_1): Likewise.
532 (VEX_LEN_0F5E_P_3): Likewise.
533 (VEX_LEN_0F5F_P_1): Likewise.
534 (VEX_LEN_0F5F_P_3): Likewise.
535 (VEX_LEN_0FC2_P_1): Likewise.
536 (VEX_LEN_0FC2_P_3): Likewise.
537 (VEX_LEN_0F3A0A_P_2): Likewise.
538 (VEX_LEN_0F3A0B_P_2): Likewise.
539 (VEX_W_0F10_P_0): Likewise.
540 (VEX_W_0F10_P_1): Likewise.
541 (VEX_W_0F10_P_2): Likewise.
542 (VEX_W_0F10_P_3): Likewise.
543 (VEX_W_0F11_P_0): Likewise.
544 (VEX_W_0F11_P_1): Likewise.
545 (VEX_W_0F11_P_2): Likewise.
546 (VEX_W_0F11_P_3): Likewise.
547 (VEX_W_0F12_P_0_M_0): Likewise.
548 (VEX_W_0F12_P_0_M_1): Likewise.
549 (VEX_W_0F12_P_1): Likewise.
550 (VEX_W_0F12_P_2): Likewise.
551 (VEX_W_0F12_P_3): Likewise.
552 (VEX_W_0F13_M_0): Likewise.
553 (VEX_W_0F14): Likewise.
554 (VEX_W_0F15): Likewise.
555 (VEX_W_0F16_P_0_M_0): Likewise.
556 (VEX_W_0F16_P_0_M_1): Likewise.
557 (VEX_W_0F16_P_1): Likewise.
558 (VEX_W_0F16_P_2): Likewise.
559 (VEX_W_0F17_M_0): Likewise.
560 (VEX_W_0F28): Likewise.
561 (VEX_W_0F29): Likewise.
562 (VEX_W_0F2B_M_0): Likewise.
563 (VEX_W_0F2E_P_0): Likewise.
564 (VEX_W_0F2E_P_2): Likewise.
565 (VEX_W_0F2F_P_0): Likewise.
566 (VEX_W_0F2F_P_2): Likewise.
567 (VEX_W_0F50_M_0): Likewise.
568 (VEX_W_0F51_P_0): Likewise.
569 (VEX_W_0F51_P_1): Likewise.
570 (VEX_W_0F51_P_2): Likewise.
571 (VEX_W_0F51_P_3): Likewise.
572 (VEX_W_0F52_P_0): Likewise.
573 (VEX_W_0F52_P_1): Likewise.
574 (VEX_W_0F53_P_0): Likewise.
575 (VEX_W_0F53_P_1): Likewise.
576 (VEX_W_0F58_P_0): Likewise.
577 (VEX_W_0F58_P_1): Likewise.
578 (VEX_W_0F58_P_2): Likewise.
579 (VEX_W_0F58_P_3): Likewise.
580 (VEX_W_0F59_P_0): Likewise.
581 (VEX_W_0F59_P_1): Likewise.
582 (VEX_W_0F59_P_2): Likewise.
583 (VEX_W_0F59_P_3): Likewise.
584 (VEX_W_0F5A_P_0): Likewise.
585 (VEX_W_0F5A_P_1): Likewise.
586 (VEX_W_0F5A_P_3): Likewise.
587 (VEX_W_0F5B_P_0): Likewise.
588 (VEX_W_0F5B_P_1): Likewise.
589 (VEX_W_0F5B_P_2): Likewise.
590 (VEX_W_0F5C_P_0): Likewise.
591 (VEX_W_0F5C_P_1): Likewise.
592 (VEX_W_0F5C_P_2): Likewise.
593 (VEX_W_0F5C_P_3): Likewise.
594 (VEX_W_0F5D_P_0): Likewise.
595 (VEX_W_0F5D_P_1): Likewise.
596 (VEX_W_0F5D_P_2): Likewise.
597 (VEX_W_0F5D_P_3): Likewise.
598 (VEX_W_0F5E_P_0): Likewise.
599 (VEX_W_0F5E_P_1): Likewise.
600 (VEX_W_0F5E_P_2): Likewise.
601 (VEX_W_0F5E_P_3): Likewise.
602 (VEX_W_0F5F_P_0): Likewise.
603 (VEX_W_0F5F_P_1): Likewise.
604 (VEX_W_0F5F_P_2): Likewise.
605 (VEX_W_0F5F_P_3): Likewise.
606 (VEX_W_0F60_P_2): Likewise.
607 (VEX_W_0F61_P_2): Likewise.
608 (VEX_W_0F62_P_2): Likewise.
609 (VEX_W_0F63_P_2): Likewise.
610 (VEX_W_0F64_P_2): Likewise.
611 (VEX_W_0F65_P_2): Likewise.
612 (VEX_W_0F66_P_2): Likewise.
613 (VEX_W_0F67_P_2): Likewise.
614 (VEX_W_0F68_P_2): Likewise.
615 (VEX_W_0F69_P_2): Likewise.
616 (VEX_W_0F6A_P_2): Likewise.
617 (VEX_W_0F6B_P_2): Likewise.
618 (VEX_W_0F6C_P_2): Likewise.
619 (VEX_W_0F6D_P_2): Likewise.
620 (VEX_W_0F6F_P_1): Likewise.
621 (VEX_W_0F6F_P_2): Likewise.
622 (VEX_W_0F70_P_1): Likewise.
623 (VEX_W_0F70_P_2): Likewise.
624 (VEX_W_0F70_P_3): Likewise.
625 (VEX_W_0F71_R_2_P_2): Likewise.
626 (VEX_W_0F71_R_4_P_2): Likewise.
627 (VEX_W_0F71_R_6_P_2): Likewise.
628 (VEX_W_0F72_R_2_P_2): Likewise.
629 (VEX_W_0F72_R_4_P_2): Likewise.
630 (VEX_W_0F72_R_6_P_2): Likewise.
631 (VEX_W_0F73_R_2_P_2): Likewise.
632 (VEX_W_0F73_R_3_P_2): Likewise.
633 (VEX_W_0F73_R_6_P_2): Likewise.
634 (VEX_W_0F73_R_7_P_2): Likewise.
635 (VEX_W_0F74_P_2): Likewise.
636 (VEX_W_0F75_P_2): Likewise.
637 (VEX_W_0F76_P_2): Likewise.
638 (VEX_W_0F77_P_0): Likewise.
639 (VEX_W_0F7C_P_2): Likewise.
640 (VEX_W_0F7C_P_3): Likewise.
641 (VEX_W_0F7D_P_2): Likewise.
642 (VEX_W_0F7D_P_3): Likewise.
643 (VEX_W_0F7E_P_1): Likewise.
644 (VEX_W_0F7F_P_1): Likewise.
645 (VEX_W_0F7F_P_2): Likewise.
646 (VEX_W_0FAE_R_2_M_0): Likewise.
647 (VEX_W_0FAE_R_3_M_0): Likewise.
648 (VEX_W_0FC2_P_0): Likewise.
649 (VEX_W_0FC2_P_1): Likewise.
650 (VEX_W_0FC2_P_2): Likewise.
651 (VEX_W_0FC2_P_3): Likewise.
652 (VEX_W_0FD0_P_2): Likewise.
653 (VEX_W_0FD0_P_3): Likewise.
654 (VEX_W_0FD1_P_2): Likewise.
655 (VEX_W_0FD2_P_2): Likewise.
656 (VEX_W_0FD3_P_2): Likewise.
657 (VEX_W_0FD4_P_2): Likewise.
658 (VEX_W_0FD5_P_2): Likewise.
659 (VEX_W_0FD6_P_2): Likewise.
660 (VEX_W_0FD7_P_2_M_1): Likewise.
661 (VEX_W_0FD8_P_2): Likewise.
662 (VEX_W_0FD9_P_2): Likewise.
663 (VEX_W_0FDA_P_2): Likewise.
664 (VEX_W_0FDB_P_2): Likewise.
665 (VEX_W_0FDC_P_2): Likewise.
666 (VEX_W_0FDD_P_2): Likewise.
667 (VEX_W_0FDE_P_2): Likewise.
668 (VEX_W_0FDF_P_2): Likewise.
669 (VEX_W_0FE0_P_2): Likewise.
670 (VEX_W_0FE1_P_2): Likewise.
671 (VEX_W_0FE2_P_2): Likewise.
672 (VEX_W_0FE3_P_2): Likewise.
673 (VEX_W_0FE4_P_2): Likewise.
674 (VEX_W_0FE5_P_2): Likewise.
675 (VEX_W_0FE6_P_1): Likewise.
676 (VEX_W_0FE6_P_2): Likewise.
677 (VEX_W_0FE6_P_3): Likewise.
678 (VEX_W_0FE7_P_2_M_0): Likewise.
679 (VEX_W_0FE8_P_2): Likewise.
680 (VEX_W_0FE9_P_2): Likewise.
681 (VEX_W_0FEA_P_2): Likewise.
682 (VEX_W_0FEB_P_2): Likewise.
683 (VEX_W_0FEC_P_2): Likewise.
684 (VEX_W_0FED_P_2): Likewise.
685 (VEX_W_0FEE_P_2): Likewise.
686 (VEX_W_0FEF_P_2): Likewise.
687 (VEX_W_0FF0_P_3_M_0): Likewise.
688 (VEX_W_0FF1_P_2): Likewise.
689 (VEX_W_0FF2_P_2): Likewise.
690 (VEX_W_0FF3_P_2): Likewise.
691 (VEX_W_0FF4_P_2): Likewise.
692 (VEX_W_0FF5_P_2): Likewise.
693 (VEX_W_0FF6_P_2): Likewise.
694 (VEX_W_0FF7_P_2): Likewise.
695 (VEX_W_0FF8_P_2): Likewise.
696 (VEX_W_0FF9_P_2): Likewise.
697 (VEX_W_0FFA_P_2): Likewise.
698 (VEX_W_0FFB_P_2): Likewise.
699 (VEX_W_0FFC_P_2): Likewise.
700 (VEX_W_0FFD_P_2): Likewise.
701 (VEX_W_0FFE_P_2): Likewise.
702 (VEX_W_0F3800_P_2): Likewise.
703 (VEX_W_0F3801_P_2): Likewise.
704 (VEX_W_0F3802_P_2): Likewise.
705 (VEX_W_0F3803_P_2): Likewise.
706 (VEX_W_0F3804_P_2): Likewise.
707 (VEX_W_0F3805_P_2): Likewise.
708 (VEX_W_0F3806_P_2): Likewise.
709 (VEX_W_0F3807_P_2): Likewise.
710 (VEX_W_0F3808_P_2): Likewise.
711 (VEX_W_0F3809_P_2): Likewise.
712 (VEX_W_0F380A_P_2): Likewise.
713 (VEX_W_0F380B_P_2): Likewise.
714 (VEX_W_0F3817_P_2): Likewise.
715 (VEX_W_0F381C_P_2): Likewise.
716 (VEX_W_0F381D_P_2): Likewise.
717 (VEX_W_0F381E_P_2): Likewise.
718 (VEX_W_0F3820_P_2): Likewise.
719 (VEX_W_0F3821_P_2): Likewise.
720 (VEX_W_0F3822_P_2): Likewise.
721 (VEX_W_0F3823_P_2): Likewise.
722 (VEX_W_0F3824_P_2): Likewise.
723 (VEX_W_0F3825_P_2): Likewise.
724 (VEX_W_0F3828_P_2): Likewise.
725 (VEX_W_0F3829_P_2): Likewise.
726 (VEX_W_0F382A_P_2_M_0): Likewise.
727 (VEX_W_0F382B_P_2): Likewise.
728 (VEX_W_0F3830_P_2): Likewise.
729 (VEX_W_0F3831_P_2): Likewise.
730 (VEX_W_0F3832_P_2): Likewise.
731 (VEX_W_0F3833_P_2): Likewise.
732 (VEX_W_0F3834_P_2): Likewise.
733 (VEX_W_0F3835_P_2): Likewise.
734 (VEX_W_0F3837_P_2): Likewise.
735 (VEX_W_0F3838_P_2): Likewise.
736 (VEX_W_0F3839_P_2): Likewise.
737 (VEX_W_0F383A_P_2): Likewise.
738 (VEX_W_0F383B_P_2): Likewise.
739 (VEX_W_0F383C_P_2): Likewise.
740 (VEX_W_0F383D_P_2): Likewise.
741 (VEX_W_0F383E_P_2): Likewise.
742 (VEX_W_0F383F_P_2): Likewise.
743 (VEX_W_0F3840_P_2): Likewise.
744 (VEX_W_0F3841_P_2): Likewise.
745 (VEX_W_0F38DB_P_2): Likewise.
746 (VEX_W_0F3A08_P_2): Likewise.
747 (VEX_W_0F3A09_P_2): Likewise.
748 (VEX_W_0F3A0A_P_2): Likewise.
749 (VEX_W_0F3A0B_P_2): Likewise.
750 (VEX_W_0F3A0C_P_2): Likewise.
751 (VEX_W_0F3A0D_P_2): Likewise.
752 (VEX_W_0F3A0E_P_2): Likewise.
753 (VEX_W_0F3A0F_P_2): Likewise.
754 (VEX_W_0F3A21_P_2): Likewise.
755 (VEX_W_0F3A40_P_2): Likewise.
756 (VEX_W_0F3A41_P_2): Likewise.
757 (VEX_W_0F3A42_P_2): Likewise.
758 (VEX_W_0F3A62_P_2): Likewise.
759 (VEX_W_0F3A63_P_2): Likewise.
760 (VEX_W_0F3ADF_P_2): Likewise.
761 (VEX_LEN_0F77_P_0): New.
762 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
763 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
764 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
765 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
766 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
767 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
768 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
769 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
770 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
771 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
772 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
773 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
774 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
775 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
776 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
777 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
778 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
779 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
780 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
781 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
782 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
783 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
784 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
785 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
786 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
787 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
788 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
789 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
790 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
791 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
792 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
793 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
794 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
795 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
796 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
797 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
798 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
799 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
800 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
801 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
802 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
803 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
804 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
805 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
806 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
807 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
808 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
809 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
810 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
811 (vex_table): Update VEX 0F28 and 0F29 entries.
812 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
813 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
814 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
815 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
816 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
817 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
818 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
819 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
820 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
821 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
822 VEX_LEN_0F3A0B_P_2 entries.
823 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
824 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
825 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
826 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
827 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
828 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
829 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
830 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
831 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
832 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
833 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
834 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
835 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
836 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
837 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
838 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
839 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
840 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
841 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
842 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
843 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
844 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
845 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
846 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
847 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
848 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
849 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
850 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
851 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
852 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
853 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
854 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
855 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
856 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
857 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
858 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
859 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
860 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
861 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
862 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
863 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
864 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
865 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
866 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
867 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
868 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
869 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
870 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
871 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
872 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
873 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
874 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
875 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
876 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
877 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
878 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
879 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
880 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
881 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
882 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
883 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
884 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
885 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
886 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
887 VEX_W_0F3ADF_P_2 entries.
888 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
889 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
890 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
891
6fa52824
L		 8922018-09-17 H.J. Lu <hongjiu.lu@intel.com>
893
894 * i386-opc.tbl (VexWIG): New.
895 Replace VexW=3 with VexWIG.
896
db4cc665
L		 8972018-09-15 H.J. Lu <hongjiu.lu@intel.com>
898
899 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
900 * i386-tbl.h: Regenerated.
901
3c374143
L		 9022018-09-15 H.J. Lu <hongjiu.lu@intel.com>
903
904 PR gas/23665
905 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
906 VEX_LEN_0FD6_P_2 entries.
907 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
908 * i386-tbl.h: Regenerated.
909
6865c043
L		 9102018-09-14 H.J. Lu <hongjiu.lu@intel.com>
911
912 PR gas/23642
913 * i386-opc.h (VEXWIG): New.
914 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
915 * i386-tbl.h: Regenerated.
916
70df6fc9
L		 9172018-09-14 H.J. Lu <hongjiu.lu@intel.com>
918
919 PR binutils/23655
920 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
921 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
922 * i386-dis.c (EXxEVexR64): New.
923 (evex_rounding_64_mode): Likewise.
924 (OP_Rounding): Handle evex_rounding_64_mode.
925
d20dee9e
L		 9262018-09-14 H.J. Lu <hongjiu.lu@intel.com>
927
928 PR binutils/23655
929 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
930 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
931 * i386-dis.c (Edqa): New.
932 (dqa_mode): Likewise.
933 (intel_operand_size): Handle dqa_mode as m_mode.
934 (OP_E_register): Handle dqa_mode as dq_mode.
935 (OP_E_memory): Set shift for dqa_mode based on address_mode.
936
5074ad8a
L		 9372018-09-14 H.J. Lu <hongjiu.lu@intel.com>
938
939 * i386-dis.c (OP_E_memory): Reformat.
940
556059dd
JB		 9412018-09-14 Jan Beulich <jbeulich@suse.com>
942
943 * i386-opc.tbl (crc32): Fold byte and word forms.
944 * i386-tbl.h: Re-generate.
945
41d1ab6a
L		 9462018-09-13 H.J. Lu <hongjiu.lu@intel.com>
947
948 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
949 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
950 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
951 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
952 * i386-tbl.h: Regenerated.
953
57f6375e
JB		 9542018-09-13 Jan Beulich <jbeulich@suse.com>
955
956 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
957 meaningless.
958 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
959 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
960 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
961 * i386-tbl.h: Re-generate.
962
2589a7e5
JB		 9632018-09-13 Jan Beulich <jbeulich@suse.com>
964
965 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
966 AVX512_4VNNIW insns.
967 * i386-tbl.h: Re-generate.
968
a760eb41
JB		 9692018-09-13 Jan Beulich <jbeulich@suse.com>
970
971 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
972 meaningless.
973 * i386-tbl.h: Re-generate.
974
e9042658
JB		 9752018-09-13 Jan Beulich <jbeulich@suse.com>
976
977 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
978 meaningless.
979 * i386-tbl.h: Re-generate.
980
9caa306f
JB		 9812018-09-13 Jan Beulich <jbeulich@suse.com>
982
983 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
984 meaningless.
985 * i386-tbl.h: Re-generate.
986
fb6ce599
JB		 9872018-09-13 Jan Beulich <jbeulich@suse.com>
988
989 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
990 meaningless.
991 * i386-tbl.h: Re-generate.
992
6a8da886
JB		 9932018-09-13 Jan Beulich <jbeulich@suse.com>
994
995 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
996 meaningless.
997 * i386-tbl.h: Re-generate.
998
c7f27919
JB		 9992018-09-13 Jan Beulich <jbeulich@suse.com>
1000
1001 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
1002 * i386-tbl.h: Re-generate.
1003
0f407ee9
JB		 10042018-09-13 Jan Beulich <jbeulich@suse.com>
1005
1006 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
1007 * i386-tbl.h: Re-generate.
1008
2fbbbee5
JB		 10092018-09-13 Jan Beulich <jbeulich@suse.com>
1010
1011 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
1012 meaningless.
1013 * i386-tbl.h: Re-generate.
1014
2b02b9a2
JB		 10152018-09-13 Jan Beulich <jbeulich@suse.com>
1016
1017 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
1018 meaningless.
1019 * i386-tbl.h: Re-generate.
1020
963c68aa
JB		 10212018-09-13 Jan Beulich <jbeulich@suse.com>
1022
1023 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
1024 * i386-tbl.h: Re-generate.
1025
64e025c3
JB		 10262018-09-13 Jan Beulich <jbeulich@suse.com>
1027
1028 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
1029 * i386-tbl.h: Re-generate.
1030
47603f88
JB		 10312018-09-13 Jan Beulich <jbeulich@suse.com>
1032
1033 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
1034 * i386-tbl.h: Re-generate.
1035
0001cfd0
JB		 10362018-09-13 Jan Beulich <jbeulich@suse.com>
1037
1038 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
1039 meaningless.
1040 * i386-tbl.h: Re-generate.
1041
be4b452e
JB		 10422018-09-13 Jan Beulich <jbeulich@suse.com>
1043
1044 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
1045 meaningless.
1046 * i386-tbl.h: Re-generate.
1047
d09a1394
JB		 10482018-09-13 Jan Beulich <jbeulich@suse.com>
1049
1050 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
1051 meaningless.
1052 * i386-tbl.h: Re-generate.
1053
07599e13
JB		 10542018-09-13 Jan Beulich <jbeulich@suse.com>
1055
1056 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
1057 * i386-tbl.h: Re-generate.
1058
1ee3e487
JB		 10592018-09-13 Jan Beulich <jbeulich@suse.com>
1060
1061 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
1062 * i386-tbl.h: Re-generate.
1063
a5f580e5
JB		 10642018-09-13 Jan Beulich <jbeulich@suse.com>
1065
1066 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
1067 * i386-tbl.h: Re-generate.
1068
49d5d12d
JB		 10692018-09-13 Jan Beulich <jbeulich@suse.com>
1070
1071 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
1072 (vpbroadcastw, rdpid): Drop NoRex64.
1073 * i386-tbl.h: Re-generate.
1074
f5eb1d70
JB		 10752018-09-13 Jan Beulich <jbeulich@suse.com>
1076
1077 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
1078 store templates, adding D.
1079 * i386-tbl.h: Re-generate.
1080
dbbc8b7e
JB		 10812018-09-13 Jan Beulich <jbeulich@suse.com>
1082
1083 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
1084 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
1085 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
1086 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
1087 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
1088 Fold load and store templates where possible, adding D. Drop
1089 IgnoreSize where it was pointlessly present. Drop redundant
1090 *word.
1091 * i386-tbl.h: Re-generate.
1092
d276ec69
JB		 10932018-09-13 Jan Beulich <jbeulich@suse.com>
1094
1095 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
1096 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
1097 (intel_operand_size): Handle v_bndmk_mode.
1098 (OP_E_memory): Likewise. Produce (bad) when also riprel.
1099
9da4dfd6
JD		 11002018-09-08 John Darrington <john@darrington.wattle.id.au>
1101
1102 * disassemble.c (ARCH_s12z): Define if ARCH_all.
1103
be192bc2
JW		 11042018-08-31 Kito Cheng <kito@andestech.com>
1105
1106 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
1107 compressed floating point instructions.
1108
43135d3b
JW		 11092018-08-30 Kito Cheng <kito@andestech.com>
1110
1111 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
1112 riscv_opcode.xlen_requirement.
1113 * riscv-opc.c (riscv_opcodes): Update for struct change.
1114
df28970f
MA		 11152018-08-29 Martin Aberg <maberg@gaisler.com>
1116
1117 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
1118 psr (PWRPSR) instruction.
1119
9108bc33
CX		 11202018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1121
1122 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
1123
bd782c07
CX		 11242018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1125
1126 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
1127
ac8cb70f
CX		 11282018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1129
1130 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
1131 loongson3a as an alias of gs464 for compatibility.
1132 * mips-opc.c (mips_opcodes): Change Comments.
1133
a693765e
CX		 11342018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1135
1136 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
1137 option.
1138 (print_mips_disassembler_options): Document -M loongson-ext.
1139 * mips-opc.c (LEXT2): New macro.
1140 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
1141
bdc6c06e
CX		 11422018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1143
1144 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
1145 descriptors.
1146 (parse_mips_ase_option): Handle -M loongson-ext option.
1147 (print_mips_disassembler_options): Document -M loongson-ext.
1148 * mips-opc.c (IL3A): Delete.
1149 * mips-opc.c (LEXT): New macro.
1150 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
1151 instructions.
1152
716c08de
CX		 11532018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
1154
1155 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
1156 descriptors.
1157 (parse_mips_ase_option): Handle -M loongson-cam option.
1158 (print_mips_disassembler_options): Document -M loongson-cam.
1159 * mips-opc.c (LCAM): New macro.
1160 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
1161 instructions.
1162
9cf7e568
AM		 11632018-08-21 Alan Modra <amodra@gmail.com>
1164
1165 * ppc-dis.c (operand_value_powerpc): Init "invalid".
1166 (skip_optional_operands): Count optional operands, and update
1167 ppc_optional_operand_value call.
1168 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
1169 (extract_vlensi): Likewise.
1170 (extract_fxm): Return default value for missing optional operand.
1171 (extract_ls, extract_raq, extract_tbr): Likewise.
1172 (insert_sxl, extract_sxl): New functions.
1173 (insert_esync, extract_esync): Remove Power9 handling and simplify.
1174 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
1175 flag and extra entry.
1176 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
1177 extract_sxl.
1178
d203b41a 11792018-08-20 Alan Modra <amodra@gmail.com>
f4107842 1180
d203b41a 1181 * sh-opc.h (MASK): Simplify.
f4107842 1182
08a8fe2f 11832018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 1184
d203b41a
AM		 1185 * s12z-dis.c (bm_decode): Deal with cases where the mode is
1186 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 1187 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 1188
08a8fe2f 11892018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 1190
1191 * s12z.h: Delete.
7ba3ba91 1192
1bc60e56
L		 11932018-08-14 H.J. Lu <hongjiu.lu@intel.com>
1194
1195 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
1196 address with the addr32 prefix and without base nor index
1197 registers.
1198
d871f3f4
L		 11992018-08-11 H.J. Lu <hongjiu.lu@intel.com>
1200
1201 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
1202 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
1203 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
1204 (cpu_flags): Add CpuCMOV and CpuFXSR.
1205 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
1206 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
1207 * i386-init.h: Regenerated.
1208 * i386-tbl.h: Likewise.
1209
b6523c37 12102018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
1211
1212 * arc-regs.h: Update auxiliary registers.
1213
e968fc9b
JB		 12142018-08-06 Jan Beulich <jbeulich@suse.com>
1215
1216 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1217 (RegIP, RegIZ): Define.
1218 * i386-reg.tbl: Adjust comments.
1219 (rip): Use Qword instead of BaseIndex. Use RegIP.
1220 (eip): Use Dword instead of BaseIndex. Use RegIP.
1221 (riz): Add Qword. Use RegIZ.
1222 (eiz): Add Dword. Use RegIZ.
1223 * i386-tbl.h: Re-generate.
1224
dbf8be89
JB		 12252018-08-03 Jan Beulich <jbeulich@suse.com>
1226
1227 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1228 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1229 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1230 * i386-tbl.h: Re-generate.
1231
c48dadc9
JB		 12322018-08-03 Jan Beulich <jbeulich@suse.com>
1233
1234 * i386-gen.c (operand_types): Remove Mem field.
1235 * i386-opc.h (union i386_operand_type): Remove mem field.
1236 * i386-init.h, i386-tbl.h: Re-generate.
1237
cb86a42a
AM		 12382018-08-01 Alan Modra <amodra@gmail.com>
1239
1240 * po/POTFILES.in: Regenerate.
1241
07cc0450
NC		 12422018-07-31 Nick Clifton <nickc@redhat.com>
1243
1244 * po/sv.po: Updated Swedish translation.
1245
1424ad86
JB		 12462018-07-31 Jan Beulich <jbeulich@suse.com>
1247
1248 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1249 * i386-init.h, i386-tbl.h: Re-generate.
1250
ae2387fe
JB		 12512018-07-31 Jan Beulich <jbeulich@suse.com>
1252
1253 * i386-opc.h (ZEROING_MASKING) Rename to ...
1254 (DYNAMIC_MASKING): ... this. Adjust comment.
1255 * i386-opc.tbl (MaskingMorZ): Define.
1256 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1257 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1258 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1259 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1260 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1261 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1262 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1263 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1264 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1265
6ff00b5e
JB		 12662018-07-31 Jan Beulich <jbeulich@suse.com>
1267
1268 * i386-opc.tbl: Use element rather than vector size for AVX512*
1269 scatter/gather insns.
1270 * i386-tbl.h: Re-generate.
1271
e951d5ca
JB		 12722018-07-31 Jan Beulich <jbeulich@suse.com>
1273
1274 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1275 (cpu_flags): Drop CpuVREX.
1276 * i386-opc.h (CpuVREX): Delete.
1277 (union i386_cpu_flags): Remove cpuvrex.
1278 * i386-init.h, i386-tbl.h: Re-generate.
1279
eb41b248
JW		 12802018-07-30 Jim Wilson <jimw@sifive.com>
1281
1282 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1283 fields.
1284 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1285
b8891f8d
AJ		 12862018-07-30 Andrew Jenner <andrew@codesourcery.com>
1287
1288 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1289 * Makefile.in: Regenerated.
1290 * configure.ac: Add C-SKY.
1291 * configure: Regenerated.
1292 * csky-dis.c: New file.
1293 * csky-opc.h: New file.
1294 * disassemble.c (ARCH_csky): Define.
1295 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1296 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1297
16065af1
AM		 12982018-07-27 Alan Modra <amodra@gmail.com>
1299
1300 * ppc-opc.c (insert_sprbat): Correct function parameter and
1301 return type.
1302 (extract_sprbat): Likewise, variable too.
1303
fa758a70
AC		 13042018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1305 Alan Modra <amodra@gmail.com>
1306
1307 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1308 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1309 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1310 support disjointed BAT.
1311 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1312 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1313 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1314
4a1b91ea
L		 13152018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1316 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1317
1318 * i386-gen.c (adjust_broadcast_modifier): New function.
1319 (process_i386_opcode_modifier): Add an argument for operands.
1320 Adjust the Broadcast value based on operands.
1321 (output_i386_opcode): Pass operand_types to
1322 process_i386_opcode_modifier.
1323 (process_i386_opcodes): Pass NULL as operands to
1324 process_i386_opcode_modifier.
1325 * i386-opc.h (BYTE_BROADCAST): New.
1326 (WORD_BROADCAST): Likewise.
1327 (DWORD_BROADCAST): Likewise.
1328 (QWORD_BROADCAST): Likewise.
1329 (i386_opcode_modifier): Expand broadcast to 3 bits.
1330 * i386-tbl.h: Regenerated.
1331
67ce483b
AM		 13322018-07-24 Alan Modra <amodra@gmail.com>
1333
1334 PR 23430
1335 * or1k-desc.h: Regenerate.
1336
4174bfff
JB		 13372018-07-24 Jan Beulich <jbeulich@suse.com>
1338
1339 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1340 vcvtusi2ss, and vcvtusi2sd.
1341 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1342 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1343 * i386-tbl.h: Re-generate.
1344
04e65276
CZ		 13452018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1346
1347 * arc-opc.c (extract_w6): Fix extending the sign.
1348
47e6f81c
CZ		 13492018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1350
1351 * arc-tbl.h (vewt): Allow it for ARC EM family.
1352
bb71536f
AM		 13532018-07-23 Alan Modra <amodra@gmail.com>
1354
1355 PR 23419
1356 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1357 opcode variants for mtspr/mfspr encodings.
1358
8095d2f7
CX		 13592018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1360 Maciej W. Rozycki <macro@mips.com>
1361
1362 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1363 loongson3a descriptors.
1364 (parse_mips_ase_option): Handle -M loongson-mmi option.
1365 (print_mips_disassembler_options): Document -M loongson-mmi.
1366 * mips-opc.c (LMMI): New macro.
1367 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1368 instructions.
1369
5f32791e
JB		 13702018-07-19 Jan Beulich <jbeulich@suse.com>
1371
1372 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1373 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1374 IgnoreSize and [XYZ]MMword where applicable.
1375 * i386-tbl.h: Re-generate.
1376
625cbd7a
JB		 13772018-07-19 Jan Beulich <jbeulich@suse.com>
1378
1379 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1380 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1381 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1382 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1383 * i386-tbl.h: Re-generate.
1384
86b15c32
JB		 13852018-07-19 Jan Beulich <jbeulich@suse.com>
1386
1387 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1388 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1389 VPCLMULQDQ templates into their respective AVX512VL counterparts
1390 where possible, using Disp8ShiftVL and CheckRegSize instead of
1391 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1392 * i386-tbl.h: Re-generate.
1393
cf769ed5
JB		 13942018-07-19 Jan Beulich <jbeulich@suse.com>
1395
1396 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1397 AVX512VL counterparts where possible, using Disp8ShiftVL and
1398 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1399 IgnoreSize) as appropriate.
1400 * i386-tbl.h: Re-generate.
1401
8282b7ad
JB		 14022018-07-19 Jan Beulich <jbeulich@suse.com>
1403
1404 * i386-opc.tbl: Fold AVX512BW templates into their respective
1405 AVX512VL counterparts where possible, using Disp8ShiftVL and
1406 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1407 IgnoreSize) as appropriate.
1408 * i386-tbl.h: Re-generate.
1409
755908cc
JB		 14102018-07-19 Jan Beulich <jbeulich@suse.com>
1411
1412 * i386-opc.tbl: Fold AVX512CD templates into their respective
1413 AVX512VL counterparts where possible, using Disp8ShiftVL and
1414 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1415 IgnoreSize) as appropriate.
1416 * i386-tbl.h: Re-generate.
1417
7091c612
JB		 14182018-07-19 Jan Beulich <jbeulich@suse.com>
1419
1420 * i386-opc.h (DISP8_SHIFT_VL): New.
1421 * i386-opc.tbl (Disp8ShiftVL): Define.
1422 (various): Fold AVX512VL templates into their respective
1423 AVX512F counterparts where possible, using Disp8ShiftVL and
1424 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1425 IgnoreSize) as appropriate.
1426 * i386-tbl.h: Re-generate.
1427
c30be56e
JB		 14282018-07-19 Jan Beulich <jbeulich@suse.com>
1429
1430 * Makefile.am: Change dependencies and rule for
1431 $(srcdir)/i386-init.h.
1432 * Makefile.in: Re-generate.
1433 * i386-gen.c (process_i386_opcodes): New local variable
1434 "marker". Drop opening of input file. Recognize marker and line
1435 number directives.
1436 * i386-opc.tbl (OPCODE_I386_H): Define.
1437 (i386-opc.h): Include it.
1438 (None): Undefine.
1439
11a322db
L		 14402018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1441
1442 PR gas/23418
1443 * i386-opc.h (Byte): Update comments.
1444 (Word): Likewise.
1445 (Dword): Likewise.
1446 (Fword): Likewise.
1447 (Qword): Likewise.
1448 (Tbyte): Likewise.
1449 (Xmmword): Likewise.
1450 (Ymmword): Likewise.
1451 (Zmmword): Likewise.
1452 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1453 vcvttps2uqq.
1454 * i386-tbl.h: Regenerated.
1455
cde3679e
NC		 14562018-07-12 Sudakshina Das <sudi.das@arm.com>
1457
1458 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1459 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1460 * aarch64-asm-2.c: Regenerate.
1461 * aarch64-dis-2.c: Regenerate.
1462 * aarch64-opc-2.c: Regenerate.
1463
45a28947
TC		 14642018-07-12 Tamar Christina <tamar.christina@arm.com>
1465
1466 PR binutils/23192
1467 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1468 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1469 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1470 sqdmulh, sqrdmulh): Use Em16.
1471
c597cc3d
SD		 14722018-07-11 Sudakshina Das <sudi.das@arm.com>
1473
1474 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1475 csdb together with them.
1476 (thumb32_opcodes): Likewise.
1477
a79eaed6
JB		 14782018-07-11 Jan Beulich <jbeulich@suse.com>
1479
1480 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1481 requiring 32-bit registers as operands 2 and 3. Improve
1482 comments.
1483 (mwait, mwaitx): Fold templates. Improve comments.
1484 OPERAND_TYPE_INOUTPORTREG.
1485 * i386-tbl.h: Re-generate.
1486
2fb5be8d
JB		 14872018-07-11 Jan Beulich <jbeulich@suse.com>
1488
1489 * i386-gen.c (operand_type_init): Remove
1490 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1491 OPERAND_TYPE_INOUTPORTREG.
1492 * i386-init.h: Re-generate.
1493
7f5cad30
JB		 14942018-07-11 Jan Beulich <jbeulich@suse.com>
1495
1496 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1497 (wrssq, wrussq): Add Qword.
1498 * i386-tbl.h: Re-generate.
1499
f0a85b07
JB		 15002018-07-11 Jan Beulich <jbeulich@suse.com>
1501
1502 * i386-opc.h: Rename OTMax to OTNum.
1503 (OTNumOfUints): Adjust calculation.
1504 (OTUnused): Directly alias to OTNum.
1505
9dcb0ba4
MR		 15062018-07-09 Maciej W. Rozycki <macro@mips.com>
1507
1508 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1509 `reg_xys'.
1510 (lea_reg_xys): Likewise.
1511 (print_insn_loop_primitive): Rename `reg' local variable to
1512 `reg_dxy'.
1513
f311ba7e
TC		 15142018-07-06 Tamar Christina <tamar.christina@arm.com>
1515
1516 PR binutils/23242
1517 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1518
cba05feb
TC		 15192018-07-06 Tamar Christina <tamar.christina@arm.com>
1520
1521 PR binutils/23369
1522 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1523 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1524
471b9d15
MR		 15252018-07-02 Maciej W. Rozycki <macro@mips.com>
1526
1527 PR tdep/8282
1528 * mips-dis.c (mips_option_arg_t): New enumeration.
1529 (mips_options): New variable.
1530 (disassembler_options_mips): New function.
1531 (print_mips_disassembler_options): Reimplement in terms of
1532 `disassembler_options_mips'.
1533 * arm-dis.c (disassembler_options_arm): Adapt to using the
1534 `disasm_options_and_args_t' structure.
1535 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1536 * s390-dis.c (disassembler_options_s390): Likewise.
1537
c0c468d5
TP		 15382018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1539
1540 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1541 expected result.
1542 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1543 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1544 * testsuite/ld-arm/tls-longplt.d: Likewise.
1545
369c9167
TC		 15462018-06-29 Tamar Christina <tamar.christina@arm.com>
1547
1548 PR binutils/23192
1549 * aarch64-asm-2.c: Regenerate.
1550 * aarch64-dis-2.c: Likewise.
1551 * aarch64-opc-2.c: Likewise.
1552 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1553 * aarch64-opc.c (operand_general_constraint_met_p,
1554 aarch64_print_operand): Likewise.
1555 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1556 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1557 fmlal2, fmlsl2.
1558 (AARCH64_OPERANDS): Add Em2.
1559
30aa1306
NC		 15602018-06-26 Nick Clifton <nickc@redhat.com>
1561
1562 * po/uk.po: Updated Ukranian translation.
1563 * po/de.po: Updated German translation.
1564 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1565
eca4b721
NC		 15662018-06-26 Nick Clifton <nickc@redhat.com>
1567
1568 * nfp-dis.c: Fix spelling mistake.
1569
71300e2c
NC		 15702018-06-24 Nick Clifton <nickc@redhat.com>
1571
1572 * configure: Regenerate.
1573 * po/opcodes.pot: Regenerate.
1574
719d8288
NC		 15752018-06-24 Nick Clifton <nickc@redhat.com>
1576
1577 2.31 branch created.
1578
514cd3a0
TC		 15792018-06-19 Tamar Christina <tamar.christina@arm.com>
1580
1581 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1582 * aarch64-asm-2.c: Regenerate.
1583 * aarch64-dis-2.c: Likewise.
1584
385e4d0f
MR		 15852018-06-21 Maciej W. Rozycki <macro@mips.com>
1586
1587 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1588 `-M ginv' option description.
1589
160d1b3d
SH		 15902018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1591
1592 PR gas/23305
1593 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1594 la and lla.
1595
d0ac1c44
SM		 15962018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1597
1598 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1599 * configure.ac: Remove AC_PREREQ.
1600 * Makefile.in: Re-generate.
1601 * aclocal.m4: Re-generate.
1602 * configure: Re-generate.
1603
6f20c942
FS		 16042018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1605
1606 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1607 mips64r6 descriptors.
1608 (parse_mips_ase_option): Handle -Mginv option.
1609 (print_mips_disassembler_options): Document -Mginv.
1610 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1611 (GINV): New macro.
1612 (mips_opcodes): Define ginvi and ginvt.
1613
730c3174
SE		 16142018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1615 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1616
1617 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1618 * mips-opc.c (CRC, CRC64): New macros.
1619 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1620 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1621 crc32cd for CRC64.
1622
cb366992
EB		 16232018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1624
1625 PR 20319
1626 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1627 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1628
ce72cd46
AM		 16292018-06-06 Alan Modra <amodra@gmail.com>
1630
1631 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1632 setjmp. Move init for some other vars later too.
1633
4b8e28c7
MF		 16342018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1635
1636 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1637 (dis_private): Add new fields for property section tracking.
1638 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1639 (xtensa_instruction_fits): New functions.
1640 (fetch_data): Bump minimal fetch size to 4.
1641 (print_insn_xtensa): Make struct dis_private static.
1642 Load and prepare property table on section change.
1643 Don't disassemble literals. Don't disassemble instructions that
1644 cross property table boundaries.
1645
55e99962
L		 16462018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1647
1648 * configure: Regenerated.
1649
733bd0ab
JB		 16502018-06-01 Jan Beulich <jbeulich@suse.com>
1651
1652 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1653 * i386-tbl.h: Re-generate.
1654
dfd27d41
JB		 16552018-06-01 Jan Beulich <jbeulich@suse.com>
1656
1657 * i386-opc.tbl (sldt, str): Add NoRex64.
1658 * i386-tbl.h: Re-generate.
1659
64795710
JB		 16602018-06-01 Jan Beulich <jbeulich@suse.com>
1661
1662 * i386-opc.tbl (invpcid): Add Oword.
1663 * i386-tbl.h: Re-generate.
1664
030157d8
AM		 16652018-06-01 Alan Modra <amodra@gmail.com>
1666
1667 * sysdep.h (_bfd_error_handler): Don't declare.
1668 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1669 * rl78-decode.opc: Likewise.
1670 * msp430-decode.c: Regenerate.
1671 * rl78-decode.c: Regenerate.
1672
a9660a6f
AP		 16732018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1674
1675 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1676 * i386-init.h : Regenerated.
1677
277eb7f6
AM		 16782018-05-25 Alan Modra <amodra@gmail.com>
1679
1680 * Makefile.in: Regenerate.
1681 * po/POTFILES.in: Regenerate.
1682
98553ad3
PB		 16832018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1684
1685 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1686 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1687 (insert_bab, extract_bab, insert_btab, extract_btab,
1688 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1689 (BAT, BBA VBA RBS XB6S): Delete macros.
1690 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1691 (BB, BD, RBX, XC6): Update for new macros.
1692 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1693 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1694 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1695 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1696
7b4ae824
JD		 16972018-05-18 John Darrington <john@darrington.wattle.id.au>
1698
1699 * Makefile.am: Add support for s12z architecture.
1700 * configure.ac: Likewise.
1701 * disassemble.c: Likewise.
1702 * disassemble.h: Likewise.
1703 * Makefile.in: Regenerate.
1704 * configure: Regenerate.
1705 * s12z-dis.c: New file.
1706 * s12z.h: New file.
1707
29e0f0a1
AM		 17082018-05-18 Alan Modra <amodra@gmail.com>
1709
1710 * nfp-dis.c: Don't #include libbfd.h.
1711 (init_nfp3200_priv): Use bfd_get_section_contents.
1712 (nit_nfp6000_mecsr_sec): Likewise.
1713
809276d2
NC		 17142018-05-17 Nick Clifton <nickc@redhat.com>
1715
1716 * po/zh_CN.po: Updated simplified Chinese translation.
1717
ff329288
TC		 17182018-05-16 Tamar Christina <tamar.christina@arm.com>
1719
1720 PR binutils/23109
1721 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1722 * aarch64-dis-2.c: Regenerate.
1723
f9830ec1
TC		 17242018-05-15 Tamar Christina <tamar.christina@arm.com>
1725
1726 PR binutils/21446
1727 * aarch64-asm.c (opintl.h): Include.
1728 (aarch64_ins_sysreg): Enforce read/write constraints.
1729 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1730 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1731 (F_REG_READ, F_REG_WRITE): New.
1732 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1733 AARCH64_OPND_SYSREG.
1734 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1735 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1736 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1737 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1738 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1739 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1740 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1741 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1742 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1743 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1744 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1745 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1746 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1747 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1748 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1749 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1750 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1751
7d02540a
TC		 17522018-05-15 Tamar Christina <tamar.christina@arm.com>
1753
1754 PR binutils/21446
1755 * aarch64-dis.c (no_notes: New.
1756 (parse_aarch64_dis_option): Support notes.
1757 (aarch64_decode_insn, print_operands): Likewise.
1758 (print_aarch64_disassembler_options): Document notes.
1759 * aarch64-opc.c (aarch64_print_operand): Support notes.
1760
561a72d4
TC		 17612018-05-15 Tamar Christina <tamar.christina@arm.com>
1762
1763 PR binutils/21446
1764 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1765 and take error struct.
1766 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1767 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1768 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1769 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1770 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1771 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1772 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1773 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1774 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1775 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1776 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1777 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1778 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1779 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1780 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1781 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1782 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1783 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1784 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1785 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1786 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1787 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1788 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1789 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1790 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1791 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1792 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1793 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1794 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1795 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1796 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1797 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1798 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1799 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1800 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1801 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1802 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1803 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1804 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1805 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1806 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1807 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1808 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1809 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1810 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1811 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1812 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1813 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1814 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1815 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1816 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1817 (determine_disassembling_preference, aarch64_decode_insn,
1818 print_insn_aarch64_word, print_insn_data): Take errors struct.
1819 (print_insn_aarch64): Use errors.
1820 * aarch64-asm-2.c: Regenerate.
1821 * aarch64-dis-2.c: Regenerate.
1822 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1823 boolean in aarch64_insert_operan.
1824 (print_operand_extractor): Likewise.
1825 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1826
1678bd35
FT		 18272018-05-15 Francois H. Theron <francois.theron@netronome.com>
1828
1829 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1830
06cfb1c8
L		 18312018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1832
1833 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1834
84f9f8c3
AM		 18352018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1836
1837 * cr16-opc.c (cr16_instruction): Comment typo fix.
1838 * hppa-dis.c (print_insn_hppa): Likewise.
1839
e6f372ba
JW		 18402018-05-08 Jim Wilson <jimw@sifive.com>
1841
1842 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1843 (match_c_slli64, match_srxi_as_c_srxi): New.
1844 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1845 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1846 <c.slli, c.srli, c.srai>: Use match_s_slli.
1847 <c.slli64, c.srli64, c.srai64>: New.
1848
f413a913
AM		 18492018-05-08 Alan Modra <amodra@gmail.com>
1850
1851 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1852 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1853 partition opcode space for index lookup.
1854
a87a6478
PB		 18552018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1856
1857 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1858 <insn_length>: ...with this. Update usage.
1859 Remove duplicate call to *info->memory_error_func.
1860
c0a30a9f
L		 18612018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1862 H.J. Lu <hongjiu.lu@intel.com>
1863
1864 * i386-dis.c (Gva): New.
1865 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1866 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1867 (prefix_table): New instructions (see prefix above).
1868 (mod_table): New instructions (see prefix above).
1869 (OP_G): Handle va_mode.
1870 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1871 CPU_MOVDIR64B_FLAGS.
1872 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1873 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1874 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1875 * i386-opc.tbl: Add movidir{i,64b}.
1876 * i386-init.h: Regenerated.
1877 * i386-tbl.h: Likewise.
1878
75c0a438
L		 18792018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1880
1881 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1882 AddrPrefixOpReg.
1883 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1884 (AddrPrefixOpReg): This.
1885 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1886 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1887
2ceb7719
PB		 18882018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1889
1890 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1891 (vle_num_opcodes): Likewise.
1892 (spe2_num_opcodes): Likewise.
1893 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1894 initialization loop.
1895 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1896 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1897 only once.
1898
b3ac5c6c
TC		 18992018-05-01 Tamar Christina <tamar.christina@arm.com>
1900
1901 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1902
fe944acf
FT		 19032018-04-30 Francois H. Theron <francois.theron@netronome.com>
1904
1905 Makefile.am: Added nfp-dis.c.
1906 configure.ac: Added bfd_nfp_arch.
1907 disassemble.h: Added print_insn_nfp prototype.
1908 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1909 nfp-dis.c: New, for NFP support.
1910 po/POTFILES.in: Added nfp-dis.c to the list.
1911 Makefile.in: Regenerate.
1912 configure: Regenerate.
1913
e2195274
JB		 19142018-04-26 Jan Beulich <jbeulich@suse.com>
1915
1916 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1917 templates into their base ones.
1918 * i386-tlb.h: Re-generate.
1919
59ef5df4
JB		 19202018-04-26 Jan Beulich <jbeulich@suse.com>
1921
1922 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1923 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1924 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1925 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1926 * i386-init.h: Re-generate.
1927
6e041cf4
JB		 19282018-04-26 Jan Beulich <jbeulich@suse.com>
1929
1930 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1931 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1932 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1933 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1934 comment.
1935 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1936 and CpuRegMask.
1937 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1938 CpuRegMask: Delete.
1939 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1940 cpuregzmm, and cpuregmask.
1941 * i386-init.h: Re-generate.
1942 * i386-tbl.h: Re-generate.
1943
0e0eea78
JB		 19442018-04-26 Jan Beulich <jbeulich@suse.com>
1945
1946 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1947 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1948 * i386-init.h: Re-generate.
1949
2f1bada2
JB		 19502018-04-26 Jan Beulich <jbeulich@suse.com>
1951
1952 * i386-gen.c (VexImmExt): Delete.
1953 * i386-opc.h (VexImmExt, veximmext): Delete.
1954 * i386-opc.tbl: Drop all VexImmExt uses.
1955 * i386-tlb.h: Re-generate.
1956
bacd1457
JB		 19572018-04-25 Jan Beulich <jbeulich@suse.com>
1958
1959 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1960 register-only forms.
1961 * i386-tlb.h: Re-generate.
1962
10bba94b
TC		 19632018-04-25 Tamar Christina <tamar.christina@arm.com>
1964
1965 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1966
c48935d7
IT		 19672018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1968
1969 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1970 PREFIX_0F1C.
1971 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1972 (cpu_flags): Add CpuCLDEMOTE.
1973 * i386-init.h: Regenerate.
1974 * i386-opc.h (enum): Add CpuCLDEMOTE,
1975 (i386_cpu_flags): Add cpucldemote.
1976 * i386-opc.tbl: Add cldemote.
1977 * i386-tbl.h: Regenerate.
1978
211dc24b
AM		 19792018-04-16 Alan Modra <amodra@gmail.com>
1980
1981 * Makefile.am: Remove sh5 and sh64 support.
1982 * configure.ac: Likewise.
1983 * disassemble.c: Likewise.
1984 * disassemble.h: Likewise.
1985 * sh-dis.c: Likewise.
1986 * sh64-dis.c: Delete.
1987 * sh64-opc.c: Delete.
1988 * sh64-opc.h: Delete.
1989 * Makefile.in: Regenerate.
1990 * configure: Regenerate.
1991 * po/POTFILES.in: Regenerate.
1992
a9a4b302
AM		 19932018-04-16 Alan Modra <amodra@gmail.com>
1994
1995 * Makefile.am: Remove w65 support.
1996 * configure.ac: Likewise.
1997 * disassemble.c: Likewise.
1998 * disassemble.h: Likewise.
1999 * w65-dis.c: Delete.
2000 * w65-opc.h: Delete.
2001 * Makefile.in: Regenerate.
2002 * configure: Regenerate.
2003 * po/POTFILES.in: Regenerate.
2004
04cb01fd
AM		 20052018-04-16 Alan Modra <amodra@gmail.com>
2006
2007 * configure.ac: Remove we32k support.
2008 * configure: Regenerate.
2009
c2bf1eec
AM		 20102018-04-16 Alan Modra <amodra@gmail.com>
2011
2012 * Makefile.am: Remove m88k support.
2013 * configure.ac: Likewise.
2014 * disassemble.c: Likewise.
2015 * disassemble.h: Likewise.
2016 * m88k-dis.c: Delete.
2017 * Makefile.in: Regenerate.
2018 * configure: Regenerate.
2019 * po/POTFILES.in: Regenerate.
2020
6793974d
AM		 20212018-04-16 Alan Modra <amodra@gmail.com>
2022
2023 * Makefile.am: Remove i370 support.
2024 * configure.ac: Likewise.
2025 * disassemble.c: Likewise.
2026 * disassemble.h: Likewise.
2027 * i370-dis.c: Delete.
2028 * i370-opc.c: Delete.
2029 * Makefile.in: Regenerate.
2030 * configure: Regenerate.
2031 * po/POTFILES.in: Regenerate.
2032
e82aa794
AM		 20332018-04-16 Alan Modra <amodra@gmail.com>
2034
2035 * Makefile.am: Remove h8500 support.
2036 * configure.ac: Likewise.
2037 * disassemble.c: Likewise.
2038 * disassemble.h: Likewise.
2039 * h8500-dis.c: Delete.
2040 * h8500-opc.h: Delete.
2041 * Makefile.in: Regenerate.
2042 * configure: Regenerate.
2043 * po/POTFILES.in: Regenerate.
2044
fceadf09
AM		 20452018-04-16 Alan Modra <amodra@gmail.com>
2046
2047 * configure.ac: Remove tahoe support.
2048 * configure: Regenerate.
2049
ae1d3843
L		 20502018-04-15 H.J. Lu <hongjiu.lu@intel.com>
2051
2052 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
2053 umwait.
2054 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
2055 64-bit mode.
2056 * i386-tbl.h: Regenerated.
2057
de89d0a3
IT		 20582018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2059
2060 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
2061 PREFIX_MOD_1_0FAE_REG_6.
2062 (va_mode): New.
2063 (OP_E_register): Use va_mode.
2064 * i386-dis-evex.h (prefix_table):
2065 New instructions (see prefixes above).
2066 * i386-gen.c (cpu_flag_init): Add WAITPKG.
2067 (cpu_flags): Likewise.
2068 * i386-opc.h (enum): Likewise.
2069 (i386_cpu_flags): Likewise.
2070 * i386-opc.tbl: Add umonitor, umwait, tpause.
2071 * i386-init.h: Regenerate.
2072 * i386-tbl.h: Likewise.
2073
a8eb42a8
AM		 20742018-04-11 Alan Modra <amodra@gmail.com>
2075
2076 * opcodes/i860-dis.c: Delete.
2077 * opcodes/i960-dis.c: Delete.
2078 * Makefile.am: Remove i860 and i960 support.
2079 * configure.ac: Likewise.
2080 * disassemble.c: Likewise.
2081 * disassemble.h: Likewise.
2082 * Makefile.in: Regenerate.
2083 * configure: Regenerate.
2084 * po/POTFILES.in: Regenerate.
2085
caf0678c
L		 20862018-04-04 H.J. Lu <hongjiu.lu@intel.com>
2087
2088 PR binutils/23025
2089 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
2090 to 0.
2091 (print_insn): Clear vex instead of vex.evex.
2092
4fb0d2b9
NC		 20932018-04-04 Nick Clifton <nickc@redhat.com>
2094
2095 * po/es.po: Updated Spanish translation.
2096
c39e5b26
JB		 20972018-03-28 Jan Beulich <jbeulich@suse.com>
2098
2099 * i386-gen.c (opcode_modifiers): Delete VecESize.
2100 * i386-opc.h (VecESize): Delete.
2101 (struct i386_opcode_modifier): Delete vecesize.
2102 * i386-opc.tbl: Drop VecESize.
2103 * i386-tlb.h: Re-generate.
2104
8e6e0792
JB		 21052018-03-28 Jan Beulich <jbeulich@suse.com>
2106
2107 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
2108 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
2109 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
2110 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
2111 * i386-tlb.h: Re-generate.
2112
9f123b91
JB		 21132018-03-28 Jan Beulich <jbeulich@suse.com>
2114
2115 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
2116 Fold AVX512 forms
2117 * i386-tlb.h: Re-generate.
2118
9646c87b
JB		 21192018-03-28 Jan Beulich <jbeulich@suse.com>
2120
2121 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
2122 (vex_len_table): Drop Y for vcvt*2si.
2123 (putop): Replace plain 'Y' handling by abort().
2124
c8d59609
NC		 21252018-03-28 Nick Clifton <nickc@redhat.com>
2126
2127 PR 22988
2128 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
2129 instructions with only a base address register.
2130 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
2131 handle AARHC64_OPND_SVE_ADDR_R.
2132 (aarch64_print_operand): Likewise.
2133 * aarch64-asm-2.c: Regenerate.
2134 * aarch64_dis-2.c: Regenerate.
2135 * aarch64-opc-2.c: Regenerate.
2136
b8c169f3
JB		 21372018-03-22 Jan Beulich <jbeulich@suse.com>
2138
2139 * i386-opc.tbl: Drop VecESize from register only insn forms and
2140 memory forms not allowing broadcast.
2141 * i386-tlb.h: Re-generate.
2142
96bc132a
JB		 21432018-03-22 Jan Beulich <jbeulich@suse.com>
2144
2145 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
2146 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
2147 sha256*): Drop Disp<N>.
2148
9f79e886
JB		 21492018-03-22 Jan Beulich <jbeulich@suse.com>
2150
2151 * i386-dis.c (EbndS, bnd_swap_mode): New.
2152 (prefix_table): Use EbndS.
2153 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
2154 * i386-opc.tbl (bndmov): Move misplaced Load.
2155 * i386-tlb.h: Re-generate.
2156
d6793fa1
JB		 21572018-03-22 Jan Beulich <jbeulich@suse.com>
2158
2159 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
2160 templates allowing memory operands and folded ones for register
2161 only flavors.
2162 * i386-tlb.h: Re-generate.
2163
f7768225
JB		 21642018-03-22 Jan Beulich <jbeulich@suse.com>
2165
2166 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
2167 256-bit templates. Drop redundant leftover Disp<N>.
2168 * i386-tlb.h: Re-generate.
2169
0e35537d
JW		 21702018-03-14 Kito Cheng <kito.cheng@gmail.com>
2171
2172 * riscv-opc.c (riscv_insn_types): New.
2173
b4a3689a
NC		 21742018-03-13 Nick Clifton <nickc@redhat.com>
2175
2176 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2177
d3d50934
L		 21782018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2179
2180 * i386-opc.tbl: Add Optimize to clr.
2181 * i386-tbl.h: Regenerated.
2182
bd5dea88
L		 21832018-03-08 H.J. Lu <hongjiu.lu@intel.com>
2184
2185 * i386-gen.c (opcode_modifiers): Remove OldGcc.
2186 * i386-opc.h (OldGcc): Removed.
2187 (i386_opcode_modifier): Remove oldgcc.
2188 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
2189 instructions for old (<= 2.8.1) versions of gcc.
2190 * i386-tbl.h: Regenerated.
2191
e771e7c9
JB		 21922018-03-08 Jan Beulich <jbeulich@suse.com>
2193
2194 * i386-opc.h (EVEXDYN): New.
2195 * i386-opc.tbl: Fold various AVX512VL templates.
2196 * i386-tlb.h: Re-generate.
2197
ed438a93
JB		 21982018-03-08 Jan Beulich <jbeulich@suse.com>
2199
2200 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2201 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2202 vpexpandd, vpexpandq): Fold AFX512VF templates.
2203 * i386-tlb.h: Re-generate.
2204
454172a9
JB		 22052018-03-08 Jan Beulich <jbeulich@suse.com>
2206
2207 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
2208 Fold 128- and 256-bit VEX-encoded templates.
2209 * i386-tlb.h: Re-generate.
2210
36824150
JB		 22112018-03-08 Jan Beulich <jbeulich@suse.com>
2212
2213 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
2214 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
2215 vpexpandd, vpexpandq): Fold AVX512F templates.
2216 * i386-tlb.h: Re-generate.
2217
e7f5c0a9
JB		 22182018-03-08 Jan Beulich <jbeulich@suse.com>
2219
2220 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2221 64-bit templates. Drop Disp<N>.
2222 * i386-tlb.h: Re-generate.
2223
25a4277f
JB		 22242018-03-08 Jan Beulich <jbeulich@suse.com>
2225
2226 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2227 and 256-bit templates.
2228 * i386-tlb.h: Re-generate.
2229
d2224064
JB		 22302018-03-08 Jan Beulich <jbeulich@suse.com>
2231
2232 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2233 * i386-tlb.h: Re-generate.
2234
1b193f0b
JB		 22352018-03-08 Jan Beulich <jbeulich@suse.com>
2236
2237 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2238 Drop NoAVX.
2239 * i386-tlb.h: Re-generate.
2240
f2f6a710
JB		 22412018-03-08 Jan Beulich <jbeulich@suse.com>
2242
2243 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2244 * i386-tlb.h: Re-generate.
2245
38e314eb
JB		 22462018-03-08 Jan Beulich <jbeulich@suse.com>
2247
2248 * i386-gen.c (opcode_modifiers): Delete FloatD.
2249 * i386-opc.h (FloatD): Delete.
2250 (struct i386_opcode_modifier): Delete floatd.
2251 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2252 FloatD by D.
2253 * i386-tlb.h: Re-generate.
2254
d53e6b98
JB		 22552018-03-08 Jan Beulich <jbeulich@suse.com>
2256
2257 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2258
2907c2f5
JB		 22592018-03-08 Jan Beulich <jbeulich@suse.com>
2260
2261 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2262 * i386-tlb.h: Re-generate.
2263
73053c1f
JB		 22642018-03-08 Jan Beulich <jbeulich@suse.com>
2265
2266 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2267 forms.
2268 * i386-tlb.h: Re-generate.
2269
52fe4420
AM		 22702018-03-07 Alan Modra <amodra@gmail.com>
2271
2272 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2273 bfd_arch_rs6000.
2274 * disassemble.h (print_insn_rs6000): Delete.
2275 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2276 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2277 (print_insn_rs6000): Delete.
2278
a6743a54
AM		 22792018-03-03 Alan Modra <amodra@gmail.com>
2280
2281 * sysdep.h (opcodes_error_handler): Define.
2282 (_bfd_error_handler): Declare.
2283 * Makefile.am: Remove stray #.
2284 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2285 EDIT" comment.
2286 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2287 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2288 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2289 opcodes_error_handler to print errors. Standardize error messages.
2290 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2291 and include opintl.h.
2292 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2293 * i386-gen.c: Standardize error messages.
2294 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2295 * Makefile.in: Regenerate.
2296 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2297 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2298 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2299 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2300 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2301 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2302 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2303 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2304 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2305 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2306 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2307 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2308 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2309
8305403a
L		 23102018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2311
2312 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2313 vpsub[bwdq] instructions.
2314 * i386-tbl.h: Regenerated.
2315
e184813f
AM		 23162018-03-01 Alan Modra <amodra@gmail.com>
2317
2318 * configure.ac (ALL_LINGUAS): Sort.
2319 * configure: Regenerate.
2320
5b616bef
TP		 23212018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2322
2323 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2324 macro by assignements.
2325
b6f8c7c4
L		 23262018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2327
2328 PR gas/22871
2329 * i386-gen.c (opcode_modifiers): Add Optimize.
2330 * i386-opc.h (Optimize): New enum.
2331 (i386_opcode_modifier): Add optimize.
2332 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2333 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2334 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2335 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2336 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2337 vpxord and vpxorq.
2338 * i386-tbl.h: Regenerated.
2339
e95b887f
AM		 23402018-02-26 Alan Modra <amodra@gmail.com>
2341
2342 * crx-dis.c (getregliststring): Allocate a large enough buffer
2343 to silence false positive gcc8 warning.
2344
0bccfb29
JW		 23452018-02-22 Shea Levy <shea@shealevy.com>
2346
2347 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2348
6b6b6807
L		 23492018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2350
2351 * i386-opc.tbl: Add {rex},
2352 * i386-tbl.h: Regenerated.
2353
75f31665
MR		 23542018-02-20 Maciej W. Rozycki <macro@mips.com>
2355
2356 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2357 (mips16_opcodes): Replace `M' with `m' for "restore".
2358
e207bc53
TP		 23592018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2360
2361 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2362
87993319
MR		 23632018-02-13 Maciej W. Rozycki <macro@mips.com>
2364
2365 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2366 variable to `function_index'.
2367
68d20676
NC		 23682018-02-13 Nick Clifton <nickc@redhat.com>
2369
2370 PR 22823
2371 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2372 about truncation of printing.
2373
d2159fdc
HW		 23742018-02-12 Henry Wong <henry@stuffedcow.net>
2375
2376 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2377
f174ef9f
NC		 23782018-02-05 Nick Clifton <nickc@redhat.com>
2379
2380 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2381
be3a8dca
IT		 23822018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2383
2384 * i386-dis.c (enum): Add pconfig.
2385 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2386 (cpu_flags): Add CpuPCONFIG.
2387 * i386-opc.h (enum): Add CpuPCONFIG.
2388 (i386_cpu_flags): Add cpupconfig.
2389 * i386-opc.tbl: Add PCONFIG instruction.
2390 * i386-init.h: Regenerate.
2391 * i386-tbl.h: Likewise.
2392
3233d7d0
IT		 23932018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2394
2395 * i386-dis.c (enum): Add PREFIX_0F09.
2396 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2397 (cpu_flags): Add CpuWBNOINVD.
2398 * i386-opc.h (enum): Add CpuWBNOINVD.
2399 (i386_cpu_flags): Add cpuwbnoinvd.
2400 * i386-opc.tbl: Add WBNOINVD instruction.
2401 * i386-init.h: Regenerate.
2402 * i386-tbl.h: Likewise.
2403
e925c834
JW		 24042018-01-17 Jim Wilson <jimw@sifive.com>
2405
2406 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2407
d777820b
IT		 24082018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2409
2410 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2411 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2412 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2413 (cpu_flags): Add CpuIBT, CpuSHSTK.
2414 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2415 (i386_cpu_flags): Add cpuibt, cpushstk.
2416 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2417 * i386-init.h: Regenerate.
2418 * i386-tbl.h: Likewise.
2419
f6efed01
NC		 24202018-01-16 Nick Clifton <nickc@redhat.com>
2421
2422 * po/pt_BR.po: Updated Brazilian Portugese translation.
2423 * po/de.po: Updated German translation.
2424
2721d702
JW		 24252018-01-15 Jim Wilson <jimw@sifive.com>
2426
2427 * riscv-opc.c (match_c_nop): New.
2428 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2429
616dcb87
NC		 24302018-01-15 Nick Clifton <nickc@redhat.com>
2431
2432 * po/uk.po: Updated Ukranian translation.
2433
3957a496
NC		 24342018-01-13 Nick Clifton <nickc@redhat.com>
2435
2436 * po/opcodes.pot: Regenerated.
2437
769c7ea5
NC		 24382018-01-13 Nick Clifton <nickc@redhat.com>
2439
2440 * configure: Regenerate.
2441
faf766e3
NC		 24422018-01-13 Nick Clifton <nickc@redhat.com>
2443
2444 2.30 branch created.
2445
888a89da
IT		 24462018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2447
2448 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2449 * i386-tbl.h: Regenerate.
2450
cbda583a
JB		 24512018-01-10 Jan Beulich <jbeulich@suse.com>
2452
2453 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2454 * i386-tbl.h: Re-generate.
2455
c9e92278
JB		 24562018-01-10 Jan Beulich <jbeulich@suse.com>
2457
2458 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2459 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2460 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2461 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2462 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2463 Disp8MemShift of AVX512VL forms.
2464 * i386-tbl.h: Re-generate.
2465
35fd2b2b
JW		 24662018-01-09 Jim Wilson <jimw@sifive.com>
2467
2468 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2469 then the hi_addr value is zero.
2470
91d8b670
JG		 24712018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2472
2473 * arm-dis.c (arm_opcodes): Add csdb.
2474 (thumb32_opcodes): Add csdb.
2475
be2e7d95
JG		 24762018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2477
2478 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2479 * aarch64-asm-2.c: Regenerate.
2480 * aarch64-dis-2.c: Regenerate.
2481 * aarch64-opc-2.c: Regenerate.
2482
704a705d
L		 24832018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2484
2485 PR gas/22681
2486 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2487 Remove AVX512 vmovd with 64-bit operands.
2488 * i386-tbl.h: Regenerated.
2489
35eeb78f
JW		 24902018-01-05 Jim Wilson <jimw@sifive.com>
2491
2492 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2493 jalr.
2494
219d1afa
AM		 24952018-01-03 Alan Modra <amodra@gmail.com>
2496
2497 Update year range in copyright notice of all files.
2498
1508bbf5
JB		 24992018-01-02 Jan Beulich <jbeulich@suse.com>
2500
2501 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2502 and OPERAND_TYPE_REGZMM entries.
2503
1e563868 2504For older changes see ChangeLog-2017
3499769a 2505\f
1e563868 2506Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2507
2508Copying and distribution of this file, with or without modification,
2509are permitted in any medium without royalty provided the copyright
2510notice and this notice are preserved.
2511
2512Local Variables:
2513mode: change-log
2514left-margin: 8
2515fill-column: 74
2516version-control: never
2517End:
GDB Binutils - Deliverables
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