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27cee81d
NC		 12019-10-25 Nick Clifton <nickc@redhat.com>
2
3 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
4 access to opcodes.op array element.
5
de6d8dc2
NC		 62019-10-23 Nick Clifton <nickc@redhat.com>
7
8 * rx-dis.c (get_register_name): Fix spelling typo in error
9 message.
10 (get_condition_name, get_flag_name, get_double_register_name)
11 (get_double_register_high_name, get_double_register_low_name)
12 (get_double_control_register_name, get_double_condition_name)
13 (get_opsize_name, get_size_name): Likewise.
14
6207ed28
NC		 152019-10-22 Nick Clifton <nickc@redhat.com>
16
17 * rx-dis.c (get_size_name): New function. Provides safe
18 access to name array.
19 (get_opsize_name): Likewise.
20 (print_insn_rx): Use the accessor functions.
21
12234dfd
NC		 222019-10-16 Nick Clifton <nickc@redhat.com>
23
24 * rx-dis.c (get_register_name): New function. Provides safe
25 access to name array.
26 (get_condition_name, get_flag_name, get_double_register_name)
27 (get_double_register_high_name, get_double_register_low_name)
28 (get_double_control_register_name, get_double_condition_name):
29 Likewise.
30 (print_insn_rx): Use the accessor functions.
31
1d378749
NC		 322019-10-09 Nick Clifton <nickc@redhat.com>
33
34 PR 25041
35 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
36 instructions.
37
d241b910
JB		 382019-10-07 Jan Beulich <jbeulich@suse.com>
39
40 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
41 (cmpsd): Likewise. Move EsSeg to other operand.
42 * opcodes/i386-tbl.h: Re-generate.
43
f5c5b7c1
AM		 442019-09-23 Alan Modra <amodra@gmail.com>
45
46 * m68k-dis.c: Include cpu-m68k.h
47
7beeaeb8
AM		 482019-09-23 Alan Modra <amodra@gmail.com>
49
50 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
51 "elf/mips.h" earlier.
52
3f9aad11
JB		 532018-09-20 Jan Beulich <jbeulich@suse.com>
54
55 PR gas/25012
56 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
57 with SReg operand.
58 * i386-tbl.h: Re-generate.
59
fd361982
AM		 602019-09-18 Alan Modra <amodra@gmail.com>
61
62 * arc-ext.c: Update throughout for bfd section macro changes.
63
e0b2a78c
SM		 642019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
65
66 * Makefile.in: Re-generate.
67 * configure: Re-generate.
68
7e9ad3a3
JW		 692019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
70
71 * riscv-opc.c (riscv_opcodes): Change subset field
72 to insn_class field for all instructions.
73 (riscv_insn_types): Likewise.
74
bb695960
PB		 752019-09-16 Phil Blundell <pb@pbcl.net>
76
77 * configure: Regenerated.
78
8063ab7e
MV		 792019-09-10 Miod Vallat <miod@online.fr>
80
81 PR 24982
82 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
83
60391a25
PB		 842019-09-09 Phil Blundell <pb@pbcl.net>
85
86 binutils 2.33 branch created.
87
f44b758d
NC		 882019-09-03 Nick Clifton <nickc@redhat.com>
89
90 PR 24961
91 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
92 greater than zero before indexing via (bufcnt -1).
93
1e4b5e7d
NC		 942019-09-03 Nick Clifton <nickc@redhat.com>
95
96 PR 24958
97 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
98 (MAX_SPEC_REG_NAME_LEN): Define.
99 (struct mmix_dis_info): Use defined constants for array lengths.
100 (get_reg_name): New function.
101 (get_sprec_reg_name): New function.
102 (print_insn_mmix): Use new functions.
103
c4a23bf8
SP		 1042019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
105
106 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
107 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
108 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
109
a051e2f3
KT		 1102019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
111
112 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
113 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
114 (aarch64_sys_reg_supported_p): Update checks for the above.
115
08132bdd
SP		 1162019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
117
118 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
119 cases MVE_SQRSHRL and MVE_UQRSHLL.
120 (print_insn_mve): Add case for specifier 'k' to check
121 specific bit of the instruction.
122
d88bdcb4
PA		 1232019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
124
125 PR 24854
126 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
127 encountering an unknown machine type.
128 (print_insn_arc): Handle arc_insn_length returning 0. In error
129 cases return -1 rather than calling abort.
130
bc750500
JB		 1312019-08-07 Jan Beulich <jbeulich@suse.com>
132
133 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
134 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
135 IgnoreSize.
136 * i386-tbl.h: Re-generate.
137
23d188c7
BW		 1382019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
139
140 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
141 instructions.
142
c0d6f62f
JW		 1432019-07-30 Mel Chen <mel.chen@sifive.com>
144
145 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
146 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
147
148 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
149 fscsr.
150
0f3f7167
CZ		 1512019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
152
153 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
154 and MPY class instructions.
155 (parse_option): Add nps400 option.
156 (print_arc_disassembler_options): Add nps400 info.
157
7e126ba3
CZ		 1582019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
159
160 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
161 (bspop): Likewise.
162 (modapp): Likewise.
163 * arc-opc.c (RAD_CHK): Add.
164 * arc-tbl.h: Regenerate.
165
a028026d
KT		 1662019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
167
168 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
169 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
170
ac79ff9e
NC		 1712019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
172
173 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
174 instructions as UNPREDICTABLE.
175
231097b0
JM		 1762019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
177
178 * bpf-desc.c: Regenerated.
179
1d942ae9
JB		 1802019-07-17 Jan Beulich <jbeulich@suse.com>
181
182 * i386-gen.c (static_assert): Define.
183 (main): Use it.
184 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
185 (Opcode_Modifier_Num): ... this.
186 (Mem): Delete.
187
dfd69174
JB		 1882019-07-16 Jan Beulich <jbeulich@suse.com>
189
190 * i386-gen.c (operand_types): Move RegMem ...
191 (opcode_modifiers): ... here.
192 * i386-opc.h (RegMem): Move to opcode modifer enum.
193 (union i386_operand_type): Move regmem field ...
194 (struct i386_opcode_modifier): ... here.
195 * i386-opc.tbl (RegMem): Define.
196 (mov, movq): Move RegMem on segment, control, debug, and test
197 register flavors.
198 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
199 to non-SSE2AVX flavor.
200 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
201 Move RegMem on register only flavors. Drop IgnoreSize from
202 legacy encoding flavors.
203 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
204 flavors.
205 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
206 register only flavors.
207 (vmovd): Move RegMem and drop IgnoreSize on register only
208 flavor. Change opcode and operand order to store form.
209 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
210
21df382b
JB		 2112019-07-16 Jan Beulich <jbeulich@suse.com>
212
213 * i386-gen.c (operand_type_init, operand_types): Replace SReg
214 entries.
215 * i386-opc.h (SReg2, SReg3): Replace by ...
216 (SReg): ... this.
217 (union i386_operand_type): Replace sreg fields.
218 * i386-opc.tbl (mov, ): Use SReg.
219 (push, pop): Likewies. Drop i386 and x86-64 specific segment
220 register flavors.
221 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
222 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
223
3719fd55
JM		 2242019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
225
226 * bpf-desc.c: Regenerate.
227 * bpf-opc.c: Likewise.
228 * bpf-opc.h: Likewise.
229
92434a14
JM		 2302019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
231
232 * bpf-desc.c: Regenerate.
233 * bpf-opc.c: Likewise.
234
43dd7626
HPN		 2352019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
236
237 * arm-dis.c (print_insn_coprocessor): Rename index to
238 index_operand.
239
98602811
JW		 2402019-07-05 Kito Cheng <kito.cheng@sifive.com>
241
242 * riscv-opc.c (riscv_insn_types): Add r4 type.
243
244 * riscv-opc.c (riscv_insn_types): Add b and j type.
245
246 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
247 format for sb type and correct s type.
248
01c1ee4a
RS		 2492019-07-02 Richard Sandiford <richard.sandiford@arm.com>
250
251 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
252 SVE FMOV alias of FCPY.
253
83adff69
RS		 2542019-07-02 Richard Sandiford <richard.sandiford@arm.com>
255
256 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
257 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
258
89418844
RS		 2592019-07-02 Richard Sandiford <richard.sandiford@arm.com>
260
261 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
262 registers in an instruction prefixed by MOVPRFX.
263
41be57ca
MM		 2642019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
265
266 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
267 sve_size_13 icode to account for variant behaviour of
268 pmull{t,b}.
269 * aarch64-dis-2.c: Regenerate.
270 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
271 sve_size_13 icode to account for variant behaviour of
272 pmull{t,b}.
273 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
274 (OP_SVE_VVV_Q_D): Add new qualifier.
275 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
276 (struct aarch64_opcode): Split pmull{t,b} into those requiring
277 AES and those not.
278
9d3bf266
JB		 2792019-07-01 Jan Beulich <jbeulich@suse.com>
280
281 * opcodes/i386-gen.c (operand_type_init): Remove
282 OPERAND_TYPE_VEC_IMM4 entry.
283 (operand_types): Remove Vec_Imm4.
284 * opcodes/i386-opc.h (Vec_Imm4): Delete.
285 (union i386_operand_type): Remove vec_imm4.
286 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
287 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
288
c3949f43
JB		 2892019-07-01 Jan Beulich <jbeulich@suse.com>
290
291 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
292 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
293 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
294 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
295 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
296 monitorx, mwaitx): Drop ImmExt from operand-less forms.
297 * i386-tbl.h: Re-generate.
298
5641ec01
JB		 2992019-07-01 Jan Beulich <jbeulich@suse.com>
300
301 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
302 register operands.
303 * i386-tbl.h: Re-generate.
304
79dec6b7
JB		 3052019-07-01 Jan Beulich <jbeulich@suse.com>
306
307 * i386-opc.tbl (C): New.
308 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
309 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
310 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
311 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
312 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
313 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
314 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
315 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
316 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
317 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
318 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
319 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
320 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
321 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
322 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
323 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
324 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
325 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
326 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
327 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
328 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
329 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
330 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
331 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
332 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
333 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
334 flavors.
335 * i386-tbl.h: Re-generate.
336
a0a1771e
JB		 3372019-07-01 Jan Beulich <jbeulich@suse.com>
338
339 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
340 register operands.
341 * i386-tbl.h: Re-generate.
342
cd546e7b
JB		 3432019-07-01 Jan Beulich <jbeulich@suse.com>
344
345 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
346 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
347 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
348 * i386-tbl.h: Re-generate.
349
e3bba3fc
JB		 3502019-07-01 Jan Beulich <jbeulich@suse.com>
351
352 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
353 Disp8MemShift from register only templates.
354 * i386-tbl.h: Re-generate.
355
36cc073e
JB		 3562019-07-01 Jan Beulich <jbeulich@suse.com>
357
358 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
359 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
360 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
361 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
362 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
363 EVEX_W_0F11_P_3_M_1): Delete.
364 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
365 EVEX_W_0F11_P_3): New.
366 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
367 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
368 MOD_EVEX_0F11_PREFIX_3 table entries.
369 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
370 PREFIX_EVEX_0F11 table entries.
371 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
372 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
373 EVEX_W_0F11_P_3_M_{0,1} table entries.
374
219920a7
JB		 3752019-07-01 Jan Beulich <jbeulich@suse.com>
376
377 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
378 Delete.
379
e395f487
L		 3802019-06-27 H.J. Lu <hongjiu.lu@intel.com>
381
382 PR binutils/24719
383 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
384 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
385 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
386 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
387 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
388 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
389 EVEX_LEN_0F38C7_R_6_P_2_W_1.
390 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
391 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
392 PREFIX_EVEX_0F38C6_REG_6 entries.
393 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
394 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
395 EVEX_W_0F38C7_R_6_P_2 entries.
396 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
397 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
398 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
399 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
400 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
401 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
402 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
403
2b7bcc87
JB		 4042019-06-27 Jan Beulich <jbeulich@suse.com>
405
406 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
407 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
408 VEX_LEN_0F2D_P_3): Delete.
409 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
410 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
411 (prefix_table): ... here.
412
c1dc7af5
JB		 4132019-06-27 Jan Beulich <jbeulich@suse.com>
414
415 * i386-dis.c (Iq): Delete.
416 (Id): New.
417 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
418 TBM insns.
419 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
420 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
421 (OP_E_memory): Also honor needindex when deciding whether an
422 address size prefix needs printing.
423 (OP_I): Remove handling of q_mode. Add handling of d_mode.
424
d7560e2d
JW		 4252019-06-26 Jim Wilson <jimw@sifive.com>
426
427 PR binutils/24739
428 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
429 Set info->display_endian to info->endian_code.
430
2c703856
JB		 4312019-06-25 Jan Beulich <jbeulich@suse.com>
432
433 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
434 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
435 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
436 OPERAND_TYPE_ACC64 entries.
437 * i386-init.h: Re-generate.
438
54fbadc0
JB		 4392019-06-25 Jan Beulich <jbeulich@suse.com>
440
441 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
442 Delete.
443 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
444 of dqa_mode.
445 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
446 entries here.
447 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
448 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
449
a280ab8e
JB		 4502019-06-25 Jan Beulich <jbeulich@suse.com>
451
452 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
453 variables.
454
e1a1babd
JB		 4552019-06-25 Jan Beulich <jbeulich@suse.com>
456
457 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
458 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
459 movnti.
d7560e2d 460 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 461 * i386-tbl.h: Re-generate.
462
b8364fa7
JB		 4632019-06-25 Jan Beulich <jbeulich@suse.com>
464
465 * i386-opc.tbl (and): Mark Imm8S form for optimization.
466 * i386-tbl.h: Re-generate.
467
ad692897
L		 4682019-06-21 H.J. Lu <hongjiu.lu@intel.com>
469
470 * i386-dis-evex.h: Break into ...
471 * i386-dis-evex-len.h: New file.
472 * i386-dis-evex-mod.h: Likewise.
473 * i386-dis-evex-prefix.h: Likewise.
474 * i386-dis-evex-reg.h: Likewise.
475 * i386-dis-evex-w.h: Likewise.
476 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
477 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
478 i386-dis-evex-mod.h.
479
f0a6222e
L		 4802019-06-19 H.J. Lu <hongjiu.lu@intel.com>
481
482 PR binutils/24700
483 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
484 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
485 EVEX_W_0F385B_P_2.
486 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
487 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
488 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
489 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
490 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
491 EVEX_LEN_0F385B_P_2_W_1.
492 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
493 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
494 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
495 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
496 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
497 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
498 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
499 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
500 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
501 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
502
6e1c90b7
L		 5032019-06-17 H.J. Lu <hongjiu.lu@intel.com>
504
505 PR binutils/24691
506 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
507 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
508 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
509 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
510 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
511 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
512 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
513 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
514 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
515 EVEX_LEN_0F3A43_P_2_W_1.
516 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
517 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
518 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
519 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
520 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
521 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
522 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
523 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
524 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
525 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
526 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
527 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
528
bcc5a6eb
NC		 5292019-06-14 Nick Clifton <nickc@redhat.com>
530
531 * po/fr.po; Updated French translation.
532
e4c4ac46
SH		 5332019-06-13 Stafford Horne <shorne@gmail.com>
534
535 * or1k-asm.c: Regenerated.
536 * or1k-desc.c: Regenerated.
537 * or1k-desc.h: Regenerated.
538 * or1k-dis.c: Regenerated.
539 * or1k-ibld.c: Regenerated.
540 * or1k-opc.c: Regenerated.
541 * or1k-opc.h: Regenerated.
542 * or1k-opinst.c: Regenerated.
543
a0e44ef5
PB		 5442019-06-12 Peter Bergner <bergner@linux.ibm.com>
545
546 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
547
12efd68d
L		 5482019-06-05 H.J. Lu <hongjiu.lu@intel.com>
549
550 PR binutils/24633
551 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
552 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
553 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
554 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
555 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
556 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
557 EVEX_LEN_0F3A1B_P_2_W_1.
558 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
559 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
560 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
561 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
562 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
563 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
564 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
565 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
566
63c6fc6c
L		 5672019-06-04 H.J. Lu <hongjiu.lu@intel.com>
568
569 PR binutils/24626
570 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
571 EVEX.vvvv when disassembling VEX and EVEX instructions.
572 (OP_VEX): Set vex.register_specifier to 0 after readding
573 vex.register_specifier.
574 (OP_Vex_2src_1): Likewise.
575 (OP_Vex_2src_2): Likewise.
576 (OP_LWP_E): Likewise.
577 (OP_EX_Vex): Don't check vex.register_specifier.
578 (OP_XMM_Vex): Likewise.
579
9186c494
L		 5802019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
581 Lili Cui <lili.cui@intel.com>
582
583 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
584 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
585 instructions.
586 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
587 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
588 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
589 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
590 (i386_cpu_flags): Add cpuavx512_vp2intersect.
591 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
592 * i386-init.h: Regenerated.
593 * i386-tbl.h: Likewise.
594
5d79adc4
L		 5952019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
596 Lili Cui <lili.cui@intel.com>
597
598 * doc/c-i386.texi: Document enqcmd.
599 * testsuite/gas/i386/enqcmd-intel.d: New file.
600 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
601 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
602 * testsuite/gas/i386/enqcmd.d: Likewise.
603 * testsuite/gas/i386/enqcmd.s: Likewise.
604 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
605 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
606 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
607 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
608 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
609 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
610 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
611 and x86-64-enqcmd.
612
a9d96ab9
AH		 6132019-06-04 Alan Hayward <alan.hayward@arm.com>
614
615 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
616
4f6d070a
AM		 6172019-06-03 Alan Modra <amodra@gmail.com>
618
619 * ppc-dis.c (prefix_opcd_indices): Correct size.
620
a2f4b66c
L		 6212019-05-28 H.J. Lu <hongjiu.lu@intel.com>
622
623 PR gas/24625
624 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
625 Disp8ShiftVL.
626 * i386-tbl.h: Regenerated.
627
405b5bd8
AM		 6282019-05-24 Alan Modra <amodra@gmail.com>
629
630 * po/POTFILES.in: Regenerate.
631
8acf1435
PB		 6322019-05-24 Peter Bergner <bergner@linux.ibm.com>
633 Alan Modra <amodra@gmail.com>
634
635 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
636 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
637 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
638 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
639 XTOP>): Define and add entries.
640 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
641 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
642 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
643 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
644
dd7efa79
PB		 6452019-05-24 Peter Bergner <bergner@linux.ibm.com>
646 Alan Modra <amodra@gmail.com>
647
648 * ppc-dis.c (ppc_opts): Add "future" entry.
649 (PREFIX_OPCD_SEGS): Define.
650 (prefix_opcd_indices): New array.
651 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
652 (lookup_prefix): New function.
653 (print_insn_powerpc): Handle 64-bit prefix instructions.
654 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
655 (PMRR, POWERXX): Define.
656 (prefix_opcodes): New instruction table.
657 (prefix_num_opcodes): New constant.
658
79472b45
JM		 6592019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
660
661 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
662 * configure: Regenerated.
663 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
664 and cpu/bpf.opc.
665 (HFILES): Add bpf-desc.h and bpf-opc.h.
666 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
667 bpf-ibld.c and bpf-opc.c.
668 (BPF_DEPS): Define.
669 * Makefile.in: Regenerated.
670 * disassemble.c (ARCH_bpf): Define.
671 (disassembler): Add case for bfd_arch_bpf.
672 (disassemble_init_for_target): Likewise.
673 (enum epbf_isa_attr): Define.
674 * disassemble.h: extern print_insn_bpf.
675 * bpf-asm.c: Generated.
676 * bpf-opc.h: Likewise.
677 * bpf-opc.c: Likewise.
678 * bpf-ibld.c: Likewise.
679 * bpf-dis.c: Likewise.
680 * bpf-desc.h: Likewise.
681 * bpf-desc.c: Likewise.
682
ba6cd17f
SD		 6832019-05-21 Sudakshina Das <sudi.das@arm.com>
684
685 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
686 and VMSR with the new operands.
687
e39c1607
SD		 6882019-05-21 Sudakshina Das <sudi.das@arm.com>
689
690 * arm-dis.c (enum mve_instructions): New enum
691 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
692 and cneg.
693 (mve_opcodes): New instructions as above.
694 (is_mve_encoding_conflict): Add cases for csinc, csinv,
695 csneg and csel.
696 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
697
23d00a41
SD		 6982019-05-21 Sudakshina Das <sudi.das@arm.com>
699
700 * arm-dis.c (emun mve_instructions): Updated for new instructions.
701 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
702 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
703 uqshl, urshrl and urshr.
704 (is_mve_okay_in_it): Add new instructions to TRUE list.
705 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
706 (print_insn_mve): Updated to accept new %j,
707 %<bitfield>m and %<bitfield>n patterns.
708
cd4797ee
FS		 7092019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
710
711 * mips-opc.c (mips_builtin_opcodes): Change source register
712 constraint for DAUI.
713
999b073b
NC		 7142019-05-20 Nick Clifton <nickc@redhat.com>
715
716 * po/fr.po: Updated French translation.
717
14b456f2
AV		 7182019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
719 Michael Collison <michael.collison@arm.com>
720
721 * arm-dis.c (thumb32_opcodes): Add new instructions.
722 (enum mve_instructions): Likewise.
723 (enum mve_undefined): Add new reasons.
724 (is_mve_encoding_conflict): Handle new instructions.
725 (is_mve_undefined): Likewise.
726 (is_mve_unpredictable): Likewise.
727 (print_mve_undefined): Likewise.
728 (print_mve_size): Likewise.
729
f49bb598
AV		 7302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
731 Michael Collison <michael.collison@arm.com>
732
733 * arm-dis.c (thumb32_opcodes): Add new instructions.
734 (enum mve_instructions): Likewise.
735 (is_mve_encoding_conflict): Handle new instructions.
736 (is_mve_undefined): Likewise.
737 (is_mve_unpredictable): Likewise.
738 (print_mve_size): Likewise.
739
56858bea
AV		 7402019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
741 Michael Collison <michael.collison@arm.com>
742
743 * arm-dis.c (thumb32_opcodes): Add new instructions.
744 (enum mve_instructions): Likewise.
745 (is_mve_encoding_conflict): Likewise.
746 (is_mve_unpredictable): Likewise.
747 (print_mve_size): Likewise.
748
e523f101
AV		 7492019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
750 Michael Collison <michael.collison@arm.com>
751
752 * arm-dis.c (thumb32_opcodes): Add new instructions.
753 (enum mve_instructions): Likewise.
754 (is_mve_encoding_conflict): Handle new instructions.
755 (is_mve_undefined): Likewise.
756 (is_mve_unpredictable): Likewise.
757 (print_mve_size): Likewise.
758
66dcaa5d
AV		 7592019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
760 Michael Collison <michael.collison@arm.com>
761
762 * arm-dis.c (thumb32_opcodes): Add new instructions.
763 (enum mve_instructions): Likewise.
764 (is_mve_encoding_conflict): Handle new instructions.
765 (is_mve_undefined): Likewise.
766 (is_mve_unpredictable): Likewise.
767 (print_mve_size): Likewise.
768 (print_insn_mve): Likewise.
769
d052b9b7
AV		 7702019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
771 Michael Collison <michael.collison@arm.com>
772
773 * arm-dis.c (thumb32_opcodes): Add new instructions.
774 (print_insn_thumb32): Handle new instructions.
775
ed63aa17
AV		 7762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
777 Michael Collison <michael.collison@arm.com>
778
779 * arm-dis.c (enum mve_instructions): Add new instructions.
780 (enum mve_undefined): Add new reasons.
781 (is_mve_encoding_conflict): Handle new instructions.
782 (is_mve_undefined): Likewise.
783 (is_mve_unpredictable): Likewise.
784 (print_mve_undefined): Likewise.
785 (print_mve_size): Likewise.
786 (print_mve_shift_n): Likewise.
787 (print_insn_mve): Likewise.
788
897b9bbc
AV		 7892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
790 Michael Collison <michael.collison@arm.com>
791
792 * arm-dis.c (enum mve_instructions): Add new instructions.
793 (is_mve_encoding_conflict): Handle new instructions.
794 (is_mve_unpredictable): Likewise.
795 (print_mve_rotate): Likewise.
796 (print_mve_size): Likewise.
797 (print_insn_mve): Likewise.
798
1c8f2df8
AV		 7992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
800 Michael Collison <michael.collison@arm.com>
801
802 * arm-dis.c (enum mve_instructions): Add new instructions.
803 (is_mve_encoding_conflict): Handle new instructions.
804 (is_mve_unpredictable): Likewise.
805 (print_mve_size): Likewise.
806 (print_insn_mve): Likewise.
807
d3b63143
AV		 8082019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
809 Michael Collison <michael.collison@arm.com>
810
811 * arm-dis.c (enum mve_instructions): Add new instructions.
812 (enum mve_undefined): Add new reasons.
813 (is_mve_encoding_conflict): Handle new instructions.
814 (is_mve_undefined): Likewise.
815 (is_mve_unpredictable): Likewise.
816 (print_mve_undefined): Likewise.
817 (print_mve_size): Likewise.
818 (print_insn_mve): Likewise.
819
14925797
AV		 8202019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
821 Michael Collison <michael.collison@arm.com>
822
823 * arm-dis.c (enum mve_instructions): Add new instructions.
824 (is_mve_encoding_conflict): Handle new instructions.
825 (is_mve_undefined): Likewise.
826 (is_mve_unpredictable): Likewise.
827 (print_mve_size): Likewise.
828 (print_insn_mve): Likewise.
829
c507f10b
AV		 8302019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
831 Michael Collison <michael.collison@arm.com>
832
833 * arm-dis.c (enum mve_instructions): Add new instructions.
834 (enum mve_unpredictable): Add new reasons.
835 (enum mve_undefined): Likewise.
836 (is_mve_okay_in_it): Handle new isntructions.
837 (is_mve_encoding_conflict): Likewise.
838 (is_mve_undefined): Likewise.
839 (is_mve_unpredictable): Likewise.
840 (print_mve_vmov_index): Likewise.
841 (print_simd_imm8): Likewise.
842 (print_mve_undefined): Likewise.
843 (print_mve_unpredictable): Likewise.
844 (print_mve_size): Likewise.
845 (print_insn_mve): Likewise.
846
bf0b396d
AV		 8472019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
848 Michael Collison <michael.collison@arm.com>
849
850 * arm-dis.c (enum mve_instructions): Add new instructions.
851 (enum mve_unpredictable): Add new reasons.
852 (enum mve_undefined): Likewise.
853 (is_mve_encoding_conflict): Handle new instructions.
854 (is_mve_undefined): Likewise.
855 (is_mve_unpredictable): Likewise.
856 (print_mve_undefined): Likewise.
857 (print_mve_unpredictable): Likewise.
858 (print_mve_rounding_mode): Likewise.
859 (print_mve_vcvt_size): Likewise.
860 (print_mve_size): Likewise.
861 (print_insn_mve): Likewise.
862
ef1576a1
AV		 8632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
864 Michael Collison <michael.collison@arm.com>
865
866 * arm-dis.c (enum mve_instructions): Add new instructions.
867 (enum mve_unpredictable): Add new reasons.
868 (enum mve_undefined): Likewise.
869 (is_mve_undefined): Handle new instructions.
870 (is_mve_unpredictable): Likewise.
871 (print_mve_undefined): Likewise.
872 (print_mve_unpredictable): Likewise.
873 (print_mve_size): Likewise.
874 (print_insn_mve): Likewise.
875
aef6d006
AV		 8762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
877 Michael Collison <michael.collison@arm.com>
878
879 * arm-dis.c (enum mve_instructions): Add new instructions.
880 (enum mve_undefined): Add new reasons.
881 (insns): Add new instructions.
882 (is_mve_encoding_conflict):
883 (print_mve_vld_str_addr): New print function.
884 (is_mve_undefined): Handle new instructions.
885 (is_mve_unpredictable): Likewise.
886 (print_mve_undefined): Likewise.
887 (print_mve_size): Likewise.
888 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
889 (print_insn_mve): Handle new operands.
890
04d54ace
AV		 8912019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
892 Michael Collison <michael.collison@arm.com>
893
894 * arm-dis.c (enum mve_instructions): Add new instructions.
895 (enum mve_unpredictable): Add new reasons.
896 (is_mve_encoding_conflict): Handle new instructions.
897 (is_mve_unpredictable): Likewise.
898 (mve_opcodes): Add new instructions.
899 (print_mve_unpredictable): Handle new reasons.
900 (print_mve_register_blocks): New print function.
901 (print_mve_size): Handle new instructions.
902 (print_insn_mve): Likewise.
903
9743db03
AV		 9042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
905 Michael Collison <michael.collison@arm.com>
906
907 * arm-dis.c (enum mve_instructions): Add new instructions.
908 (enum mve_unpredictable): Add new reasons.
909 (enum mve_undefined): Likewise.
910 (is_mve_encoding_conflict): Handle new instructions.
911 (is_mve_undefined): Likewise.
912 (is_mve_unpredictable): Likewise.
913 (coprocessor_opcodes): Move NEON VDUP from here...
914 (neon_opcodes): ... to here.
915 (mve_opcodes): Add new instructions.
916 (print_mve_undefined): Handle new reasons.
917 (print_mve_unpredictable): Likewise.
918 (print_mve_size): Handle new instructions.
919 (print_insn_neon): Handle vdup.
920 (print_insn_mve): Handle new operands.
921
143275ea
AV		 9222019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
923 Michael Collison <michael.collison@arm.com>
924
925 * arm-dis.c (enum mve_instructions): Add new instructions.
926 (enum mve_unpredictable): Add new values.
927 (mve_opcodes): Add new instructions.
928 (vec_condnames): New array with vector conditions.
929 (mve_predicatenames): New array with predicate suffixes.
930 (mve_vec_sizename): New array with vector sizes.
931 (enum vpt_pred_state): New enum with vector predication states.
932 (struct vpt_block): New struct type for vpt blocks.
933 (vpt_block_state): Global struct to keep track of state.
934 (mve_extract_pred_mask): New helper function.
935 (num_instructions_vpt_block): Likewise.
936 (mark_outside_vpt_block): Likewise.
937 (mark_inside_vpt_block): Likewise.
938 (invert_next_predicate_state): Likewise.
939 (update_next_predicate_state): Likewise.
940 (update_vpt_block_state): Likewise.
941 (is_vpt_instruction): Likewise.
942 (is_mve_encoding_conflict): Add entries for new instructions.
943 (is_mve_unpredictable): Likewise.
944 (print_mve_unpredictable): Handle new cases.
945 (print_instruction_predicate): Likewise.
946 (print_mve_size): New function.
947 (print_vec_condition): New function.
948 (print_insn_mve): Handle vpt blocks and new print operands.
949
f08d8ce3
AV		 9502019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
951
952 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
953 8, 14 and 15 for Armv8.1-M Mainline.
954
73cd51e5
AV		 9552019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
956 Michael Collison <michael.collison@arm.com>
957
958 * arm-dis.c (enum mve_instructions): New enum.
959 (enum mve_unpredictable): Likewise.
960 (enum mve_undefined): Likewise.
961 (struct mopcode32): New struct.
962 (is_mve_okay_in_it): New function.
963 (is_mve_architecture): Likewise.
964 (arm_decode_field): Likewise.
965 (arm_decode_field_multiple): Likewise.
966 (is_mve_encoding_conflict): Likewise.
967 (is_mve_undefined): Likewise.
968 (is_mve_unpredictable): Likewise.
969 (print_mve_undefined): Likewise.
970 (print_mve_unpredictable): Likewise.
971 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
972 (print_insn_mve): New function.
973 (print_insn_thumb32): Handle MVE architecture.
974 (select_arm_features): Force thumb for Armv8.1-m Mainline.
975
3076e594
NC		 9762019-05-10 Nick Clifton <nickc@redhat.com>
977
978 PR 24538
979 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
980 end of the table prematurely.
981
387e7624
FS		 9822019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
983
984 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
985 macros for R6.
986
0067be51
AM		 9872019-05-11 Alan Modra <amodra@gmail.com>
988
989 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
990 when -Mraw is in effect.
991
42e6288f
MM		 9922019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
993
994 * aarch64-dis-2.c: Regenerate.
995 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
996 (OP_SVE_BBB): New variant set.
997 (OP_SVE_DDDD): New variant set.
998 (OP_SVE_HHH): New variant set.
999 (OP_SVE_HHHU): New variant set.
1000 (OP_SVE_SSS): New variant set.
1001 (OP_SVE_SSSU): New variant set.
1002 (OP_SVE_SHH): New variant set.
1003 (OP_SVE_SBBU): New variant set.
1004 (OP_SVE_DSS): New variant set.
1005 (OP_SVE_DHHU): New variant set.
1006 (OP_SVE_VMV_HSD_BHS): New variant set.
1007 (OP_SVE_VVU_HSD_BHS): New variant set.
1008 (OP_SVE_VVVU_SD_BH): New variant set.
1009 (OP_SVE_VVVU_BHSD): New variant set.
1010 (OP_SVE_VVV_QHD_DBS): New variant set.
1011 (OP_SVE_VVV_HSD_BHS): New variant set.
1012 (OP_SVE_VVV_HSD_BHS2): New variant set.
1013 (OP_SVE_VVV_BHS_HSD): New variant set.
1014 (OP_SVE_VV_BHS_HSD): New variant set.
1015 (OP_SVE_VVV_SD): New variant set.
1016 (OP_SVE_VVU_BHS_HSD): New variant set.
1017 (OP_SVE_VZVV_SD): New variant set.
1018 (OP_SVE_VZVV_BH): New variant set.
1019 (OP_SVE_VZV_SD): New variant set.
1020 (aarch64_opcode_table): Add sve2 instructions.
1021
28ed815a
MM		 10222019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1023
1024 * aarch64-asm-2.c: Regenerated.
1025 * aarch64-dis-2.c: Regenerated.
1026 * aarch64-opc-2.c: Regenerated.
1027 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1028 for SVE_SHLIMM_UNPRED_22.
1029 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1030 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1031 operand.
1032
fd1dc4a0
MM		 10332019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1034
1035 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1036 sve_size_tsz_bhs iclass encode.
1037 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1038 sve_size_tsz_bhs iclass decode.
1039
31e36ab3
MM		 10402019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1041
1042 * aarch64-asm-2.c: Regenerated.
1043 * aarch64-dis-2.c: Regenerated.
1044 * aarch64-opc-2.c: Regenerated.
1045 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1046 for SVE_Zm4_11_INDEX.
1047 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1048 (fields): Handle SVE_i2h field.
1049 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1050 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1051
1be5f94f
MM		 10522019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1053
1054 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1055 sve_shift_tsz_bhsd iclass encode.
1056 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1057 sve_shift_tsz_bhsd iclass decode.
1058
3c17238b
MM		 10592019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1060
1061 * aarch64-asm-2.c: Regenerated.
1062 * aarch64-dis-2.c: Regenerated.
1063 * aarch64-opc-2.c: Regenerated.
1064 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1065 (aarch64_encode_variant_using_iclass): Handle
1066 sve_shift_tsz_hsd iclass encode.
1067 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1068 sve_shift_tsz_hsd iclass decode.
1069 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1070 for SVE_SHRIMM_UNPRED_22.
1071 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1072 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1073 operand.
1074
cd50a87a
MM		 10752019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1076
1077 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1078 sve_size_013 iclass encode.
1079 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1080 sve_size_013 iclass decode.
1081
3c705960
MM		 10822019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1083
1084 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1085 sve_size_bh iclass encode.
1086 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1087 sve_size_bh iclass decode.
1088
0a57e14f
MM		 10892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1090
1091 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1092 sve_size_sd2 iclass encode.
1093 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1094 sve_size_sd2 iclass decode.
1095 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1096 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1097
c469c864
MM		 10982019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1099
1100 * aarch64-asm-2.c: Regenerated.
1101 * aarch64-dis-2.c: Regenerated.
1102 * aarch64-opc-2.c: Regenerated.
1103 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1104 for SVE_ADDR_ZX.
1105 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1106 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1107
116adc27
MM		 11082019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1109
1110 * aarch64-asm-2.c: Regenerated.
1111 * aarch64-dis-2.c: Regenerated.
1112 * aarch64-opc-2.c: Regenerated.
1113 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1114 for SVE_Zm3_11_INDEX.
1115 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1116 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1117 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1118 fields.
1119 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1120
3bd82c86
MM		 11212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1122
1123 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1124 sve_size_hsd2 iclass encode.
1125 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1126 sve_size_hsd2 iclass decode.
1127 * aarch64-opc.c (fields): Handle SVE_size field.
1128 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1129
adccc507
MM		 11302019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1131
1132 * aarch64-asm-2.c: Regenerated.
1133 * aarch64-dis-2.c: Regenerated.
1134 * aarch64-opc-2.c: Regenerated.
1135 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1136 for SVE_IMM_ROT3.
1137 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1138 (fields): Handle SVE_rot3 field.
1139 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1140 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1141
5cd99750
MM		 11422019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1143
1144 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1145 instructions.
1146
7ce2460a
MM		 11472019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1148
1149 * aarch64-tbl.h
1150 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1151 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1152 aarch64_feature_sve2bitperm): New feature sets.
1153 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1154 for feature set addresses.
1155 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1156 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1157
41cee089
FS		 11582019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1159 Faraz Shahbazker <fshahbazker@wavecomp.com>
1160
1161 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1162 argument and set ASE_EVA_R6 appropriately.
1163 (set_default_mips_dis_options): Pass ISA to above.
1164 (parse_mips_dis_option): Likewise.
1165 * mips-opc.c (EVAR6): New macro.
1166 (mips_builtin_opcodes): Add llwpe, scwpe.
1167
b83b4b13
SD		 11682019-05-01 Sudakshina Das <sudi.das@arm.com>
1169
1170 * aarch64-asm-2.c: Regenerated.
1171 * aarch64-dis-2.c: Regenerated.
1172 * aarch64-opc-2.c: Regenerated.
1173 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1174 AARCH64_OPND_TME_UIMM16.
1175 (aarch64_print_operand): Likewise.
1176 * aarch64-tbl.h (QL_IMM_NIL): New.
1177 (TME): New.
1178 (_TME_INSN): New.
1179 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1180
4a90ce95
JD		 11812019-04-29 John Darrington <john@darrington.wattle.id.au>
1182
1183 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1184
a45328b9
AB		 11852019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1186 Faraz Shahbazker <fshahbazker@wavecomp.com>
1187
1188 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1189
d10be0cb
JD		 11902019-04-24 John Darrington <john@darrington.wattle.id.au>
1191
1192 * s12z-opc.h: Add extern "C" bracketing to help
1193 users who wish to use this interface in c++ code.
1194
a679f24e
JD		 11952019-04-24 John Darrington <john@darrington.wattle.id.au>
1196
1197 * s12z-opc.c (bm_decode): Handle bit map operations with the
1198 "reserved0" mode.
1199
32c36c3c
AV		 12002019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1201
1202 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1203 specifier. Add entries for VLDR and VSTR of system registers.
1204 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1205 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1206 of %J and %K format specifier.
1207
efd6b359
AV		 12082019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1209
1210 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1211 Add new entries for VSCCLRM instruction.
1212 (print_insn_coprocessor): Handle new %C format control code.
1213
6b0dd094
AV		 12142019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1215
1216 * arm-dis.c (enum isa): New enum.
1217 (struct sopcode32): New structure.
1218 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1219 set isa field of all current entries to ANY.
1220 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1221 Only match an entry if its isa field allows the current mode.
1222
4b5a202f
AV		 12232019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1224
1225 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1226 CLRM.
1227 (print_insn_thumb32): Add logic to print %n CLRM register list.
1228
60f993ce
AV		 12292019-04-15 Sudakshina Das <sudi.das@arm.com>
1230
1231 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1232 and %Q patterns.
1233
f6b2b12d
AV		 12342019-04-15 Sudakshina Das <sudi.das@arm.com>
1235
1236 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1237 (print_insn_thumb32): Edit the switch case for %Z.
1238
1889da70
AV		 12392019-04-15 Sudakshina Das <sudi.das@arm.com>
1240
1241 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1242
65d1bc05
AV		 12432019-04-15 Sudakshina Das <sudi.das@arm.com>
1244
1245 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1246
1caf72a5
AV		 12472019-04-15 Sudakshina Das <sudi.das@arm.com>
1248
1249 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1250
f1c7f421
AV		 12512019-04-15 Sudakshina Das <sudi.das@arm.com>
1252
1253 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1254 Arm register with r13 and r15 unpredictable.
1255 (thumb32_opcodes): New instructions for bfx and bflx.
1256
4389b29a
AV		 12572019-04-15 Sudakshina Das <sudi.das@arm.com>
1258
1259 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1260
e5d6e09e
AV		 12612019-04-15 Sudakshina Das <sudi.das@arm.com>
1262
1263 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1264
e12437dc
AV		 12652019-04-15 Sudakshina Das <sudi.das@arm.com>
1266
1267 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1268
031254f2
AV		 12692019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1270
1271 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1272
e5a557ac
JD		 12732019-04-12 John Darrington <john@darrington.wattle.id.au>
1274
1275 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1276 "optr". ("operator" is a reserved word in c++).
1277
bd7ceb8d
SD		 12782019-04-11 Sudakshina Das <sudi.das@arm.com>
1279
1280 * aarch64-opc.c (aarch64_print_operand): Add case for
1281 AARCH64_OPND_Rt_SP.
1282 (verify_constraints): Likewise.
1283 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1284 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1285 to accept Rt|SP as first operand.
1286 (AARCH64_OPERANDS): Add new Rt_SP.
1287 * aarch64-asm-2.c: Regenerated.
1288 * aarch64-dis-2.c: Regenerated.
1289 * aarch64-opc-2.c: Regenerated.
1290
e54010f1
SD		 12912019-04-11 Sudakshina Das <sudi.das@arm.com>
1292
1293 * aarch64-asm-2.c: Regenerated.
1294 * aarch64-dis-2.c: Likewise.
1295 * aarch64-opc-2.c: Likewise.
1296 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1297
7e96e219
RS		 12982019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1299
1300 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1301
6f2791d5
L		 13022019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1303
1304 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1305 * i386-init.h: Regenerated.
1306
e392bad3
AM		 13072019-04-07 Alan Modra <amodra@gmail.com>
1308
1309 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1310 op_separator to control printing of spaces, comma and parens
1311 rather than need_comma, need_paren and spaces vars.
1312
dffaa15c
AM		 13132019-04-07 Alan Modra <amodra@gmail.com>
1314
1315 PR 24421
1316 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1317 (print_insn_neon, print_insn_arm): Likewise.
1318
d6aab7a1
XG		 13192019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1320
1321 * i386-dis-evex.h (evex_table): Updated to support BF16
1322 instructions.
1323 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1324 and EVEX_W_0F3872_P_3.
1325 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1326 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1327 * i386-opc.h (enum): Add CpuAVX512_BF16.
1328 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1329 * i386-opc.tbl: Add AVX512 BF16 instructions.
1330 * i386-init.h: Regenerated.
1331 * i386-tbl.h: Likewise.
1332
66e85460
AM		 13332019-04-05 Alan Modra <amodra@gmail.com>
1334
1335 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1336 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1337 to favour printing of "-" branch hint when using the "y" bit.
1338 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1339
c2b1c275
AM		 13402019-04-05 Alan Modra <amodra@gmail.com>
1341
1342 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1343 opcode until first operand is output.
1344
aae9718e
PB		 13452019-04-04 Peter Bergner <bergner@linux.ibm.com>
1346
1347 PR gas/24349
1348 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1349 (valid_bo_post_v2): Add support for 'at' branch hints.
1350 (insert_bo): Only error on branch on ctr.
1351 (get_bo_hint_mask): New function.
1352 (insert_boe): Add new 'branch_taken' formal argument. Add support
1353 for inserting 'at' branch hints.
1354 (extract_boe): Add new 'branch_taken' formal argument. Add support
1355 for extracting 'at' branch hints.
1356 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1357 (BOE): Delete operand.
1358 (BOM, BOP): New operands.
1359 (RM): Update value.
1360 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1361 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1362 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1363 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1364 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1365 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1366 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1367 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1368 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1369 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1370 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1371 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1372 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1373 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1374 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1375 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1376 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1377 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1378 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1379 bttarl+>: New extended mnemonics.
1380
96a86c01
AM		 13812019-03-28 Alan Modra <amodra@gmail.com>
1382
1383 PR 24390
1384 * ppc-opc.c (BTF): Define.
1385 (powerpc_opcodes): Use for mtfsb*.
1386 * ppc-dis.c (print_insn_powerpc): Print fields with both
1387 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1388
796d6298
TC		 13892019-03-25 Tamar Christina <tamar.christina@arm.com>
1390
1391 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1392 (mapping_symbol_for_insn): Implement new algorithm.
1393 (print_insn): Remove duplicate code.
1394
60df3720
TC		 13952019-03-25 Tamar Christina <tamar.christina@arm.com>
1396
1397 * aarch64-dis.c (print_insn_aarch64):
1398 Implement override.
1399
51457761
TC		 14002019-03-25 Tamar Christina <tamar.christina@arm.com>
1401
1402 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1403 order.
1404
53b2f36b
TC		 14052019-03-25 Tamar Christina <tamar.christina@arm.com>
1406
1407 * aarch64-dis.c (last_stop_offset): New.
1408 (print_insn_aarch64): Use stop_offset.
1409
89199bb5
L		 14102019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1411
1412 PR gas/24359
1413 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1414 CPU_ANY_AVX2_FLAGS.
1415 * i386-init.h: Regenerated.
1416
97ed31ae
L		 14172019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1418
1419 PR gas/24348
1420 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1421 vmovdqu16, vmovdqu32 and vmovdqu64.
1422 * i386-tbl.h: Regenerated.
1423
0919bfe9
AK		 14242019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1425
1426 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1427 from vstrszb, vstrszh, and vstrszf.
1428
14292019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1430
1431 * s390-opc.txt: Add instruction descriptions.
1432
21820ebe
JW		 14332019-02-08 Jim Wilson <jimw@sifive.com>
1434
1435 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1436 <bne>: Likewise.
1437
f7dd2fb2
TC		 14382019-02-07 Tamar Christina <tamar.christina@arm.com>
1439
1440 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1441
6456d318
TC		 14422019-02-07 Tamar Christina <tamar.christina@arm.com>
1443
1444 PR binutils/23212
1445 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1446 * aarch64-opc.c (verify_elem_sd): New.
1447 (fields): Add FLD_sz entr.
1448 * aarch64-tbl.h (_SIMD_INSN): New.
1449 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1450 fmulx scalar and vector by element isns.
1451
4a83b610
NC		 14522019-02-07 Nick Clifton <nickc@redhat.com>
1453
1454 * po/sv.po: Updated Swedish translation.
1455
fc60b8c8
AK		 14562019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1457
1458 * s390-mkopc.c (main): Accept arch13 as cpu string.
1459 * s390-opc.c: Add new instruction formats and instruction opcode
1460 masks.
1461 * s390-opc.txt: Add new arch13 instructions.
1462
e10620d3
TC		 14632019-01-25 Sudakshina Das <sudi.das@arm.com>
1464
1465 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1466 (aarch64_opcode): Change encoding for stg, stzg
1467 st2g and st2zg.
1468 * aarch64-asm-2.c: Regenerated.
1469 * aarch64-dis-2.c: Regenerated.
1470 * aarch64-opc-2.c: Regenerated.
1471
20a4ca55
SD		 14722019-01-25 Sudakshina Das <sudi.das@arm.com>
1473
1474 * aarch64-asm-2.c: Regenerated.
1475 * aarch64-dis-2.c: Likewise.
1476 * aarch64-opc-2.c: Likewise.
1477 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1478
550fd7bf
SD		 14792019-01-25 Sudakshina Das <sudi.das@arm.com>
1480 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1481
1482 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1483 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1484 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1485 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1486 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1487 case for ldstgv_indexed.
1488 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1489 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1490 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1491 * aarch64-asm-2.c: Regenerated.
1492 * aarch64-dis-2.c: Regenerated.
1493 * aarch64-opc-2.c: Regenerated.
1494
d9938630
NC		 14952019-01-23 Nick Clifton <nickc@redhat.com>
1496
1497 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1498
375cd423
NC		 14992019-01-21 Nick Clifton <nickc@redhat.com>
1500
1501 * po/de.po: Updated German translation.
1502 * po/uk.po: Updated Ukranian translation.
1503
57299f48
CX		 15042019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1505 * mips-dis.c (mips_arch_choices): Fix typo in
1506 gs464, gs464e and gs264e descriptors.
1507
f48dfe41
NC		 15082019-01-19 Nick Clifton <nickc@redhat.com>
1509
1510 * configure: Regenerate.
1511 * po/opcodes.pot: Regenerate.
1512
f974f26c
NC		 15132018-06-24 Nick Clifton <nickc@redhat.com>
1514
1515 2.32 branch created.
1516
39f286cd
JD		 15172019-01-09 John Darrington <john@darrington.wattle.id.au>
1518
448b8ca8
JD		 1519 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1520 if it is null.
1521 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1522 zero.
1523
3107326d
AP		 15242019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1525
1526 * configure: Regenerate.
1527
7e9ca91e
AM		 15282019-01-07 Alan Modra <amodra@gmail.com>
1529
1530 * configure: Regenerate.
1531 * po/POTFILES.in: Regenerate.
1532
ef1ad42b
JD		 15332019-01-03 John Darrington <john@darrington.wattle.id.au>
1534
1535 * s12z-opc.c: New file.
1536 * s12z-opc.h: New file.
1537 * s12z-dis.c: Removed all code not directly related to display
1538 of instructions. Used the interface provided by the new files
1539 instead.
1540 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1541 * Makefile.in: Regenerate.
ef1ad42b 1542 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1543 * configure: Regenerate.
ef1ad42b 1544
82704155
AM		 15452019-01-01 Alan Modra <amodra@gmail.com>
1546
1547 Update year range in copyright notice of all files.
1548
d5c04e1b 1549For older changes see ChangeLog-2018
3499769a 1550\f
d5c04e1b 1551Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1552
1553Copying and distribution of this file, with or without modification,
1554are permitted in any medium without royalty provided the copyright
1555notice and this notice are preserved.
1556
1557Local Variables:
1558mode: change-log
1559left-margin: 8
1560fill-column: 74
1561version-control: never
1562End:
GDB Binutils - Deliverables
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