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ussan: d30v: index out of bounds
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
159653d8
AM		 12019-12-11 Alan Modra <amodra@gmail.com>
2
3 * d30v-dis.c (print_insn): Make opind unsigned. Don't access
4 past end of operands array.
5
d93bba9e
AM		 62019-12-11 Alan Modra <amodra@gmail.com>
7
8 * csky-dis.c (csky_chars_to_number): Rewrite. Avoid signed
9 overflow when collecting bytes of a number.
10
c202f69e
AM		 112019-12-11 Alan Modra <amodra@gmail.com>
12
13 * cris-dis.c (print_with_operands): Avoid signed integer
14 overflow when collecting bytes of a 32-bit integer.
15
0ef562a4
AM		 162019-12-11 Alan Modra <amodra@gmail.com>
17
18 * cr16-dis.c (EXTRACT, SBM): Rewrite.
19 (cr16_match_opcode): Delete duplicate bcond test.
20
2fd2b153
AM		 212019-12-11 Alan Modra <amodra@gmail.com>
22
23 * bfin-dis.c (HOST_LONG_WORD_SIZE, XFIELD): Delete.
24 (SIGNBIT): New.
25 (MASKBITS, SIGNEXTEND): Rewrite.
26 (fmtconst): Don't use ? expression now that SIGNEXTEND uses
27 unsigned arithmetic, instead assign result of SIGNEXTEND back
28 to x.
29 (fmtconst_val): Use 1u in shift expression.
30
a11db3e9
AM		 312019-12-11 Alan Modra <amodra@gmail.com>
32
33 * arc-dis.c (find_format_from_table): Use ull constant when
34 shifting by up to 32.
35
9d48687b
AM		 362019-12-11 Alan Modra <amodra@gmail.com>
37
38 PR 25270
39 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Return
40 false when field is zero for sve_size_tsz_bhs.
41
b8e61daa
AM		 422019-12-11 Alan Modra <amodra@gmail.com>
43
44 * epiphany-ibld.c: Regenerate.
45
20135676
AM		 462019-12-10 Alan Modra <amodra@gmail.com>
47
48 PR 24960
49 * disassemble.c (disassemble_free_target): New function.
50
103ebbc3
AM		 512019-12-10 Alan Modra <amodra@gmail.com>
52
53 * cgen-dis.in (print_insn_@arch@): Replace insn_sets with private_data.
54 * disassemble.c (disassemble_init_for_target): Likewise.
55 * bpf-dis.c: Regenerate.
56 * epiphany-dis.c: Regenerate.
57 * fr30-dis.c: Regenerate.
58 * frv-dis.c: Regenerate.
59 * ip2k-dis.c: Regenerate.
60 * iq2000-dis.c: Regenerate.
61 * lm32-dis.c: Regenerate.
62 * m32c-dis.c: Regenerate.
63 * m32r-dis.c: Regenerate.
64 * mep-dis.c: Regenerate.
65 * mt-dis.c: Regenerate.
66 * or1k-dis.c: Regenerate.
67 * xc16x-dis.c: Regenerate.
68 * xstormy16-dis.c: Regenerate.
69
6f0e0752
AM		 702019-12-10 Alan Modra <amodra@gmail.com>
71
72 * ppc-dis.c (private): Delete variable.
73 (get_powerpc_dialect): Don't segfault on NULL info->private_data.
74 (powerpc_init_dialect): Don't use global private.
75
e7c22a69
AM		 762019-12-10 Alan Modra <amodra@gmail.com>
77
78 * s12z-opc.c: Formatting.
79
0a6aef6b
AM		 802019-12-08 Alan Modra <amodra@gmail.com>
81
82 * s12z-opc.c (exg_sex_discrim): Don't leak memory on invalid
83 registers.
84
2dc4b12f
JB		 852019-12-05 Jan Beulich <jbeulich@suse.com>
86
87 * aarch64-tbl.h (aarch64_feature_crypto,
88 aarch64_feature_crypto_v8_2, CRYPTO, CRYPTO_V8_2, CRYP_INSN,
89 CRYPTO_V8_2_INSN): Delete.
90
378fd436
AM		 912019-12-05 Alan Modra <amodra@gmail.com>
92
93 PR 25249
94 * microblaze-dis.c (NUM_STRBUFS, STRBUF_SIZE): Define.
95 (struct string_buf): New.
96 (strbuf): New function.
97 (get_field): Use strbuf rather than strdup of local temp.
98 (get_field_imm, get_field_imm5, get_field_imm5_mbar): Likewise.
99 (get_field_rfsl, get_field_imm15): Likewise.
100 (get_field_rd, get_field_r1, get_field_r2): Update macros.
101 (get_field_special): Likewise. Don't strcpy spr. Formatting.
102 (print_insn_microblaze): Formatting. Init and pass string_buf to
103 get_field functions.
104
0ba59a29
JB		 1052019-12-04 Jan Beulich <jbeulich@suse.com>
106
107 * i386-opc.tbl (lfs, lgs, lss): Drop No_qSuf.
108 * i386-tbl.h: Re-generate.
109
77ad8092
JB		 1102019-12-04 Jan Beulich <jbeulich@suse.com>
111
112 * i386-dis.c (mod_table): Use Ev instead of Em for movdiri.
113
3036c899
JB		 1142019-12-04 Jan Beulich <jbeulich@suse.com>
115
116 * i386-opc.tbl (push, pop): Drop DefaultSize from GPR-only
117 forms.
118 (xbegin): Drop DefaultSize.
119 * i386-tbl.h: Re-generate.
120
8b301fbb
MI		 1212019-11-22 Mihail Ionescu <mihail.ionescu@arm.com>
122
123 * opcodes/arm-dis.c (arm_opcodes, thumb32_opcodes):
124 Change the coproc CRC conditions to use the extension
125 feature set, second word, base on ARM_EXT2_CRC.
126
6aa385b9
JB		 1272019-11-14 Jan Beulich <jbeulich@suse.com>
128
129 * i386-opc.tbl (syscall, sysret): Drop Cpu64 forms.
130 * i386-tbl.h: Re-generate.
131
0cfa3eb3
JB		 1322019-11-14 Jan Beulich <jbeulich@suse.com>
133
134 * i386-gen.c (opcode_modifiers): Remove JumpDword, JumpByte,
135 JumpInterSegment, and JumpAbsolute entries.
136 * i386-opc.h (JUMP, JUMP_DWORD, JUMP_BYTE, JUMP_INTERSEGMENT,
137 JUMP_ABSOLUTE): Define.
138 (struct i386_opcode_modifier): Extend jump field to 3 bits.
139 Remove jumpdword, jumpbyte, jumpintersegment, and jumpabsolute
140 fields.
141 * i386-opc.tbl (JumpByte, JumpDword, JumpAbsolute,
142 JumpInterSegment): Define.
143 * i386-tbl.h: Re-generate.
144
6f2f06be
JB		 1452019-11-14 Jan Beulich <jbeulich@suse.com>
146
147 * i386-gen.c (operand_type_init): Remove
148 OPERAND_TYPE_JUMPABSOLUTE entry.
149 (opcode_modifiers): Add JumpAbsolute entry.
150 (operand_types): Remove JumpAbsolute entry.
151 * i386-opc.h (JumpAbsolute): Move between enums.
152 (struct i386_opcode_modifier): Add jumpabsolute field.
153 (union i386_operand_type): Remove jumpabsolute field.
154 * i386-opc.tbl (call, lcall, jmp, ljmp): Move JumpAbsolute.
155 * i386-init.h, i386-tbl.h: Re-generate.
156
601e8564
JB		 1572019-11-14 Jan Beulich <jbeulich@suse.com>
158
159 * i386-gen.c (opcode_modifiers): Add AnySize entry.
160 (operand_types): Remove AnySize entry.
161 * i386-opc.h (AnySize): Move between enums.
162 (struct i386_opcode_modifier): Add anysize field.
163 (OTUnused): Un-comment.
164 (union i386_operand_type): Remove anysize field.
165 * i386-opc.tbl (lea, invlpg, clflush, prefetchnta, prefetcht0,
166 prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
167 bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote): Move
168 AnySize.
169 * i386-tbl.h: Re-generate.
170
7722d40a
JW		 1712019-11-12 Nelson Chu <nelson.chu@sifive.com>
172
173 * riscv-opc.c (riscv_insn_types): Replace the INSN_CLASS_I with
174 INSN_CLASS_F and the INSN_CLASS_C with INSN_CLASS_F_AND_C if we
175 use the floating point register (FPR).
176
ce760a76
MI		 1772019-11-12 Mihail Ionescu <mihail.ionescu@arm.com>
178
179 * opcodes/arm-dis.c (mve_opcodes): Enable VMOV imm to vec with
180 cmode 1101.
181 (is_mve_encoding_conflict): Update cmode conflict checks for
182 MVE_VMVN_IMM.
183
51c8edf6
JB		 1842019-11-12 Jan Beulich <jbeulich@suse.com>
185
186 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_ESSEG
187 entry.
188 (operand_types): Remove EsSeg entry.
189 (main): Replace stale use of OTMax.
190 * i386-opc.h (IS_STRING_ES_OP0, IS_STRING_ES_OP1): Define.
191 (struct i386_opcode_modifier): Expand isstring field to 2 bits.
192 (EsSeg): Delete.
193 (OTUnused): Comment out.
194 (union i386_operand_type): Remove esseg field.
195 * i386-opc.tbl (IsStringEsOp0, IsStringEsOp1): Define.
196 (cmps, scmp, scas, ssca, cmpsd): Add IsStringEsOp0.
197 (ins, movs, smov, movsd): Add IsStringEsOpOp1.
198 (stos, ssto): Add IsStringEsOp0/IsStringEsOpOp1.
199 * i386-init.h, i386-tbl.h: Re-generate.
200
474da251
JB		 2012019-11-12 Jan Beulich <jbeulich@suse.com>
202
203 * i386-gen.c (operand_instances): Add RegB entry.
204 * i386-opc.h (enum operand_instance): Add RegB.
205 * i386-opc.tbl (RegC, RegD, RegB): Define.
206 (Acc, ShiftCount, InOutPortReg): Adjust definitions.
207 (monitor, mwait, invlpga, skinit, vmload, vmrun, vmsave, clzero,
208 monitorx, mwaitx): Drop ImmExt and convert encodings
209 accordingly.
210 * i386-reg.tbl (ecx, rcx): Add Instance=RegC.
211 (edx, rdx): Add Instance=RegD.
212 (ebx, rbx): Add Instance=RegB.
213 * i386-tbl.h: Re-generate.
214
75e5731b
JB		 2152019-11-12 Jan Beulich <jbeulich@suse.com>
216
217 * i386-gen.c (operand_type_init): Adjust
218 OPERAND_TYPE_INOUTPORTREG, OPERAND_TYPE_SHIFTCOUNT,
219 OPERAND_TYPE_FLOATACC, OPERAND_TYPE_ACC8, OPERAND_TYPE_ACC16,
220 OPERAND_TYPE_ACC32, and OPERAND_TYPE_ACC64 entries.
221 (operand_instances): New.
222 (operand_types): Drop InOutPortReg, ShiftCount, and Acc entries.
223 (output_operand_type): New parameter "instance". Process it.
224 (process_i386_operand_type): New local variable "instance".
225 (main): Adjust static assertions.
226 * i386-opc.h (INSTANCE_WIDTH): Define.
227 (enum operand_instance): New.
228 (Acc, InOutPortReg, ShiftCount): Replace by ClassInstance.
229 (union i386_operand_type): Replace acc, inoutportreg, and
230 shiftcount by instance.
231 * i386-opc.tbl (Acc, InOutPortReg, ShiftCount): Define.
232 * i386-reg.tbl (st, al, cl, ax, dx, eax, rax, xmm0, st(0)):
233 Add Instance=.
234 * i386-init.h, i386-tbl.h: Re-generate.
235
91802f3c
JB		 2362019-11-11 Jan Beulich <jbeulich@suse.com>
237
238 * aarch64-tbl.h (aarch64_opcode_table): Switch SVE2's
239 smaxp/sminp entries' "tied_operand" field to 2.
240
4f5fc85d
JB		 2412019-11-11 Jan Beulich <jbeulich@suse.com>
242
243 * aarch64-opc.c (operand_general_constraint_met_p): Replace
244 "index" local variable by that of the already existing "num".
245
dc2be329
L		 2462019-11-08 H.J. Lu <hongjiu.lu@intel.com>
247
248 PR gas/25167
249 * i386-opc.tbl: Remove IgnoreSize from cmpsd and movsd.
250 * i386-tbl.h: Regenerated.
251
f74a6307
JB		 2522019-11-08 Jan Beulich <jbeulich@suse.com>
253
254 * i386-gen.c (operand_type_init): Add Class= to
255 OPERAND_TYPE_REGMASK and OPERAND_TYPE_REGBND entries. Move up
256 OPERAND_TYPE_REGBND entry.
257 (operand_classes): Add RegMask and RegBND entries.
258 (operand_types): Drop RegMask and RegBND entry.
259 * i386-opc.h (enum operand_class): Add RegMask and RegBND.
260 (RegMask, RegBND): Delete.
261 (union i386_operand_type): Remove regmask and regbnd fields.
262 * i386-opc.tbl (RegMask, RegBND): Define.
263 * i386-reg.tbl: Replace RegMask by Class=RegMask and RegBND by
264 Class=RegBND.
265 * i386-init.h, i386-tbl.h: Re-generate.
266
3528c362
JB		 2672019-11-08 Jan Beulich <jbeulich@suse.com>
268
269 * i386-gen.c (operand_type_init): Add Class= to
270 OPERAND_TYPE_REGMMX, OPERAND_TYPE_REGXMM, OPERAND_TYPE_REGYMM, and
271 OPERAND_TYPE_REGZMM entries.
272 (operand_classes): Add RegMMX and RegSIMD entries.
273 (operand_types): Drop RegMMX and RegSIMD entries.
274 * i386-opc.h (enum operand_class): Add RegMMX and RegSIMD.
275 (RegMMX, RegSIMD): Delete.
276 (union i386_operand_type): Remove regmmx and regsimd fields.
277 * i386-opc.tbl (RegMMX): Define.
278 (RegXMM, RegYMM, RegZMM): Add Class=.
279 * i386-reg.tbl: Replace RegMMX by Class=RegMMX and RegSIMD by
280 Class=RegSIMD.
281 * i386-init.h, i386-tbl.h: Re-generate.
282
4a5c67ed
JB		 2832019-11-08 Jan Beulich <jbeulich@suse.com>
284
285 * i386-gen.c (operand_type_init): Add Class= to
286 OPERAND_TYPE_CONTROL, OPERAND_TYPE_TEST, and OPERAND_TYPE_DEBUG
287 entries.
288 (operand_classes): Add RegCR, RegDR, and RegTR entries.
289 (operand_types): Drop Control, Debug, and Test entries.
290 * i386-opc.h (enum operand_class): Add RegCR, RegDR, and RegTR.
291 (Control, Debug, Test): Delete.
292 (union i386_operand_type): Remove control, debug, and test
293 fields.
294 * i386-opc.tbl (Control, Debug, Test): Define.
295 * i386-reg.tbl: Replace Control by Class=RegCR, Debug by
296 Class=RegDR, and Test by Class=RegTR.
297 * i386-init.h, i386-tbl.h: Re-generate.
298
00cee14f
JB		 2992019-11-08 Jan Beulich <jbeulich@suse.com>
300
301 * i386-gen.c (operand_type_init): Add Class= to
302 OPERAND_TYPE_SREG entry.
303 (operand_classes): Add SReg entry.
304 (operand_types): Drop SReg entry.
305 * i386-opc.h (enum operand_class): Add SReg.
306 (SReg): Delete.
307 (union i386_operand_type): Remove sreg field.
308 * i386-opc.tbl (SReg): Define.
309 * i386-reg.tbl: Replace SReg by Class=SReg.
310 * i386-init.h, i386-tbl.h: Re-generate.
311
bab6aec1
JB		 3122019-11-08 Jan Beulich <jbeulich@suse.com>
313
314 * i386-gen.c (operand_type_init): Add Class=. New
315 OPERAND_TYPE_ANYIMM entry.
316 (operand_classes): New.
317 (operand_types): Drop Reg entry.
318 (output_operand_type): New parameter "class". Process it.
319 (process_i386_operand_type): New local variable "class".
320 (main): Adjust static assertions.
321 * i386-opc.h (CLASS_WIDTH): Define.
322 (enum operand_class): New.
323 (Reg): Replace by Class. Adjust comment.
324 (union i386_operand_type): Replace reg by class.
325 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatReg): Add
326 Class=.
327 * i386-reg.tbl: Replace Reg by Class=Reg.
328 * i386-init.h: Re-generate.
329
1f4cd317
MM		 3302019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
331
332 * opcodes/aarch64-tbl.h (V8_6_INSN): New macro for v8.6 instructions.
333 (aarch64_opcode_table): Add data gathering hint mnemonic.
334 * opcodes/aarch64-dis-2.c: Account for new instruction.
335
616ce08e
MM		 3362019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
337
338 * arm-dis.c (neon_opcodes): Add i8mm SIMD instructions.
339
340
8382113f
MM		 3412019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
342
343 * aarch64-tbl.h (aarch64_feature_i8mm_sve, aarch64_feature_f32mm_sve,
344 aarch64_feature_f64mm_sve, aarch64_feature_i8mm, aarch64_feature_f32mm,
345 aarch64_feature_f64mm): New feature sets.
346 (INT8MATMUL_INSN, F64MATMUL_SVE_INSN, F64MATMUL_INSN,
347 F32MATMUL_SVE_INSN, F32MATMUL_INSN): New macros to define matrix multiply
348 instructions.
349 (I8MM_SVE, F32MM_SVE, F64MM_SVE, I8MM, F32MM, F64MM): New feature set
350 macros.
351 (QL_MMLA64, OP_SVE_SBB): New qualifiers.
352 (OP_SVE_QQQ): New qualifier.
353 (INT8MATMUL_SVE_INSNC, F64MATMUL_SVE_INSNC,
354 F32MATMUL_SVE_INSNC): New feature set for bfloat16 instructions to support
355 the movprfx constraint.
356 (aarch64_opcode_table): Support for SVE_ADDR_RI_S4x32.
357 (aarch64_opcode_table): Define new instructions smmla,
358 ummla, usmmla, usdot, sudot, fmmla, ld1rob, ld1roh, ld1row, ld1rod,
359 uzip{1/2}, trn{1/2}.
360 * aarch64-opc.c (operand_general_constraint_met_p): Handle
361 AARCH64_OPND_SVE_ADDR_RI_S4x32.
362 (aarch64_print_operand): Handle AARCH64_OPND_SVE_ADDR_RI_S4x32.
363 * aarch64-dis-2.c (aarch64_opcode_lookup_1, aarch64_find_next_opcode):
364 Account for new instructions.
365 * opcodes/aarch64-asm-2.c (aarch64_insert_operand): Support the new
366 S4x32 operand.
367 * aarch64-opc-2.c (aarch64_operands): Support the new S4x32 operand.
368
aab2c27d
MM		 3692019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3702019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
371
372 * arm-dis.c (select_arm_features): Update bfd_march_arm_8 with
373 Armv8.6-A.
374 (coprocessor_opcodes): Add bfloat16 vcvt{t,b}.
375 (neon_opcodes): Add bfloat SIMD instructions.
376 (print_insn_coprocessor): Add new control character %b to print
377 condition code without checking cp_num.
378 (print_insn_neon): Account for BFloat16 instructions that have no
379 special top-byte handling.
380
33593eaf
MM		 3812019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3822019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
383
384 * arm-dis.c (print_insn_coprocessor,
385 print_insn_generic_coprocessor): Create wrapper functions around
386 the implementation of the print_insn_coprocessor control codes.
387 (print_insn_coprocessor_1): Original print_insn_coprocessor
388 function that now takes which array to look at as an argument.
389 (print_insn_arm): Use both print_insn_coprocessor and
390 print_insn_generic_coprocessor.
391 (print_insn_thumb32): As above.
392
df678013
MM		 3932019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
3942019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
395
396 * aarch64-asm.c (aarch64_ins_reglane): Use AARCH64_OPND_QLF_S_2H
397 in reglane special case.
398 * aarch64-dis-2.c (aarch64_opcode_lookup_1,
399 aarch64_find_next_opcode): Account for new instructions.
400 * aarch64-dis.c (aarch64_ext_reglane): Use AARCH64_OPND_QLF_S_2H
401 in reglane special case.
402 * aarch64-opc.c (struct operand_qualifier_data): Add data for
403 new AARCH64_OPND_QLF_S_2H qualifier.
404 * aarch64-tbl.h (QL_BFDOT QL_BFDOT64, QL_BFDOT64I, QL_BFMMLA2,
405 QL_BFCVT64, QL_BFCVTN64, QL_BFCVTN2_64): New qualifiers.
406 (aarch64_feature_bfloat16, aarch64_feature_bfloat16_sve): New feature
407 sets.
408 (BFLOAT_SVE, BFLOAT): New feature set macros.
409 (BFLOAT_SVE_INSN, BFLOAT_INSN): New macros to define BFloat16
410 instructions.
411 (aarch64_opcode_table): Define new instructions bfdot,
412 bfmmla, bfcvt, bfcvtnt, bfdot, bfdot, bfcvtn, bfmlal[b/t]
413 bfcvtn2, bfcvt.
414
8ae2d3d9
MM		 4152019-11-07 Mihail Ionescu <mihail.ionescu@arm.com>
4162019-11-07 Matthew Malcomson <matthew.malcomson@arm.com>
417
418 * aarch64-tbl.h (ARMV8_6): New macro.
419
142861df
JB		 4202019-11-07 Jan Beulich <jbeulich@suse.com>
421
422 * i386-dis.c (prefix_table): Add mcommit.
423 (rm_table): Add rdpru.
424 * i386-gen.c (cpu_flag_init): Adjust CPU_ZNVER2_FLAGS entry. Add
425 CPU_RDPRU_FLAGS and CPU_MCOMMIT_FLAGS entries.
426 (cpu_flags): Add CpuRDPRU and CpuMCOMMIT entries.
427 * i386-opc.h (CpuRDPRU, CpuMCOMMIT): New.
428 (union i386_cpu_flags): Add cpurdpru and cpumcommit fields.
429 * i386-opc.tbl (mcommit, rdpru): New.
430 * i386-init.h, i386-tbl.h: Re-generate.
431
081e283f
JB		 4322019-11-07 Jan Beulich <jbeulich@suse.com>
433
434 * i386-dis.c (OP_Mwait): Drop local variable "names", use
435 "names32" instead.
436 (OP_Monitor): Drop local variable "op1_names", re-purpose
437 "names" for it instead, and replace former "names" uses by
438 "names32" ones.
439
c050c89a
JB		 4402019-11-07 Jan Beulich <jbeulich@suse.com>
441
442 PR/gas 25167
443 * opcodes/i386-opc.tbl (movsd, cmpsd): Drop IgnoreSize from
444 operand-less forms.
445 * opcodes/i386-tbl.h: Re-generate.
446
7abb8d81
JB		 4472019-11-05 Jan Beulich <jbeulich@suse.com>
448
449 * i386-dis.c (OP_Mwaitx): Delete.
450 (prefix_table): Use OP_Mwait for mwaitx entry.
451 (OP_Mwait): Also handle mwaitx.
452
267b8516
JB		 4532019-11-05 Jan Beulich <jbeulich@suse.com>
454
455 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_2,
456 PREFIX_0F01_REG_7_MOD_3_RM_3): New.
457 (prefix_table): Add respective entries.
458 (rm_table): Link to those entries.
459
f8687e93
JB		 4602019-11-05 Jan Beulich <jbeulich@suse.com>
461
462 * i386-dis.c (REG_0F1C_MOD_0): Rename to ...
463 (REG_0F1C_P_0_MOD_0): ... this.
464 (REG_0F1E_MOD_3): Rename to ...
465 (REG_0F1E_P_1_MOD_3): ... this.
466 (RM_0F01_REG_5): Rename to ...
467 (RM_0F01_REG_5_MOD_3): ... this.
468 (RM_0F01_REG_7): Rename to ...
469 (RM_0F01_REG_7_MOD_3): ... this.
470 (RM_0F1E_MOD_3_REG_7): Rename to ...
471 (RM_0F1E_P_1_MOD_3_REG_7): ... this.
472 (RM_0FAE_REG_6): Rename to ...
473 (RM_0FAE_REG_6_MOD_3_P_0): ... this.
474 (RM_0FAE_REG_7): Rename to ...
475 (RM_0FAE_REG_7_MOD_3): ... this.
476 (PREFIX_MOD_0_0F01_REG_5): Rename to ...
477 (PREFIX_0F01_REG_5_MOD_0): ... this.
478 (PREFIX_MOD_3_0F01_REG_5_RM_0): Rename to ...
479 (PREFIX_0F01_REG_5_MOD_3_RM_0): ... this.
480 (PREFIX_MOD_3_0F01_REG_5_RM_2): Rename to ...
481 (PREFIX_0F01_REG_5_MOD_3_RM_2): ... this.
482 (PREFIX_0FAE_REG_0): Rename to ...
483 (PREFIX_0FAE_REG_0_MOD_3): ... this.
484 (PREFIX_0FAE_REG_1): Rename to ...
485 (PREFIX_0FAE_REG_1_MOD_3): ... this.
486 (PREFIX_0FAE_REG_2): Rename to ...
487 (PREFIX_0FAE_REG_2_MOD_3): ... this.
488 (PREFIX_0FAE_REG_3): Rename to ...
489 (PREFIX_0FAE_REG_3_MOD_3): ... this.
490 (PREFIX_MOD_0_0FAE_REG_4): Rename to ...
491 (PREFIX_0FAE_REG_4_MOD_0): ... this.
492 (PREFIX_MOD_3_0FAE_REG_4): Rename to ...
493 (PREFIX_0FAE_REG_4_MOD_3): ... this.
494 (PREFIX_MOD_0_0FAE_REG_5): Rename to ...
495 (PREFIX_0FAE_REG_5_MOD_0): ... this.
496 (PREFIX_MOD_3_0FAE_REG_5): Rename to ...
497 (PREFIX_0FAE_REG_5_MOD_3): ... this.
498 (PREFIX_MOD_0_0FAE_REG_6): Rename to ...
499 (PREFIX_0FAE_REG_6_MOD_0): ... this.
500 (PREFIX_MOD_1_0FAE_REG_6): Rename to ...
501 (PREFIX_0FAE_REG_6_MOD_3): ... this.
502 (PREFIX_0FAE_REG_7): Rename to ...
503 (PREFIX_0FAE_REG_7_MOD_0): ... this.
504 (PREFIX_MOD_0_0FC3): Rename to ...
505 (PREFIX_0FC3_MOD_0): ... this.
506 (PREFIX_MOD_0_0FC7_REG_6): Rename to ...
507 (PREFIX_0FC7_REG_6_MOD_0): ... this.
508 (PREFIX_MOD_3_0FC7_REG_6): Rename to ...
509 (PREFIX_0FC7_REG_6_MOD_3): ... this.
510 (PREFIX_MOD_3_0FC7_REG_7): Rename to ...
511 (PREFIX_0FC7_REG_7_MOD_3): ... this.
512 (reg_table, prefix_table, mod_table, rm_table): Adjust
513 accordingly.
514
5103274f
NC		 5152019-11-04 Nick Clifton <nickc@redhat.com>
516
517 * v850-dis.c (get_v850_sreg_name): New function. Returns the name
518 of a v850 system register. Move the v850_sreg_names array into
519 this function.
520 (get_v850_reg_name): Likewise for ordinary register names.
521 (get_v850_vreg_name): Likewise for vector register names.
522 (get_v850_cc_name): Likewise for condition codes.
523 * get_v850_float_cc_name): Likewise for floating point condition
524 codes.
525 (get_v850_cacheop_name): Likewise for cache-ops.
526 (get_v850_prefop_name): Likewise for pref-ops.
527 (disassemble): Use the new accessor functions.
528
1820262b
DB		 5292019-10-30 Delia Burduv <delia.burduv@arm.com>
530
531 * aarch64-opc.c (print_immediate_offset_address): Don't print the
532 immediate for the writeback form of ldraa/ldrab if it is 0.
533 * aarch64-tbl.h: Updated the documentation for ADDR_SIMM10.
534 * aarch64-opc-2.c: Regenerated.
535
3cc17af5
JB		 5362019-10-30 Jan Beulich <jbeulich@suse.com>
537
538 * i386-gen.c (operand_type_shorthands): Delete.
539 (operand_type_init): Expand previous shorthands.
540 (set_bitfield_from_shorthand): Rename back to ...
541 (set_bitfield_from_cpu_flag_init): ... this. Drop processing
542 of operand_type_init[].
543 (set_bitfield): Adjust call to the above function.
544 * i386-opc.tbl (Reg8, Reg16, Reg32, Reg64, FloatAcc, FloatReg,
545 RegXMM, RegYMM, RegZMM): Define.
546 * i386-reg.tbl: Expand prior shorthands.
547
a2cebd03
JB		 5482019-10-30 Jan Beulich <jbeulich@suse.com>
549
550 * i386-gen.c (output_i386_opcode): Change order of fields
551 emitted to output.
552 * i386-opc.h (struct insn_template): Move operands field.
553 Convert extension_opcode field to unsigned short.
554 * i386-tbl.h: Re-generate.
555
507916b8
JB		 5562019-10-30 Jan Beulich <jbeulich@suse.com>
557
558 * i386-gen.c (process_i386_opcode_modifier): Report bogus uses
559 of W.
560 * i386-opc.h (W): Extend comment.
561 * i386-opc.tbl (mov, movabs, movq): Drop W and adjust opcodes of
562 general purpose variants not allowing for byte operands.
563 * i386-tbl.h: Re-generate.
564
efea62b4
NC		 5652019-10-29 Nick Clifton <nickc@redhat.com>
566
567 * tic30-dis.c (print_branch): Correct size of operand array.
568
9adb2591
NC		 5692019-10-29 Nick Clifton <nickc@redhat.com>
570
571 * d30v-dis.c (print_insn): Check that operand index is valid
572 before attempting to access the operands array.
573
993a00a9
NC		 5742019-10-29 Nick Clifton <nickc@redhat.com>
575
576 * ia64-opc.c (locate_opcode_ent): Prevent a negative shift when
577 locating the bit to be tested.
578
66a66a17
NC		 5792019-10-29 Nick Clifton <nickc@redhat.com>
580
581 * s12z-dis.c (opr_emit_disassembly): Check for illegal register
582 values.
583 (shift_size_table): Use a fixed size defined as S12Z_N_SIZES.
584 (print_insn_s12z): Check for illegal size values.
585
1ee3542c
NC		 5862019-10-28 Nick Clifton <nickc@redhat.com>
587
588 * csky-dis.c (csky_chars_to_number): Check for a negative
589 count. Use an unsigned integer to construct the return value.
590
bbf9a0b5
NC		 5912019-10-28 Nick Clifton <nickc@redhat.com>
592
593 * tic30-dis.c (OPERAND_BUFFER_LEN): Define. Use as length of
594 operand buffer. Set value to 15 not 13.
595 (get_register_operand): Use OPERAND_BUFFER_LEN.
596 (get_indirect_operand): Likewise.
597 (print_two_operand): Likewise.
598 (print_three_operand): Likewise.
599 (print_oar_insn): Likewise.
600
d1e304bc
NC		 6012019-10-28 Nick Clifton <nickc@redhat.com>
602
603 * ns32k-dis.c (bit_extract): Add sanitiy check of parameters.
604 (bit_extract_simple): Likewise.
605 (bit_copy): Likewise.
606 (pirnt_insn_ns32k): Ensure that uninitialised elements in the
607 index_offset array are not accessed.
608
dee33451
NC		 6092019-10-28 Nick Clifton <nickc@redhat.com>
610
611 * xgate-dis.c (print_insn): Fix decoding of the XGATE_OP_DYA
612 operand.
613
27cee81d
NC		 6142019-10-25 Nick Clifton <nickc@redhat.com>
615
616 * rx-dis.c (print_insn_rx): Use parenthesis to ensure correct
617 access to opcodes.op array element.
618
de6d8dc2
NC		 6192019-10-23 Nick Clifton <nickc@redhat.com>
620
621 * rx-dis.c (get_register_name): Fix spelling typo in error
622 message.
623 (get_condition_name, get_flag_name, get_double_register_name)
624 (get_double_register_high_name, get_double_register_low_name)
625 (get_double_control_register_name, get_double_condition_name)
626 (get_opsize_name, get_size_name): Likewise.
627
6207ed28
NC		 6282019-10-22 Nick Clifton <nickc@redhat.com>
629
630 * rx-dis.c (get_size_name): New function. Provides safe
631 access to name array.
632 (get_opsize_name): Likewise.
633 (print_insn_rx): Use the accessor functions.
634
12234dfd
NC		 6352019-10-16 Nick Clifton <nickc@redhat.com>
636
637 * rx-dis.c (get_register_name): New function. Provides safe
638 access to name array.
639 (get_condition_name, get_flag_name, get_double_register_name)
640 (get_double_register_high_name, get_double_register_low_name)
641 (get_double_control_register_name, get_double_condition_name):
642 Likewise.
643 (print_insn_rx): Use the accessor functions.
644
1d378749
NC		 6452019-10-09 Nick Clifton <nickc@redhat.com>
646
647 PR 25041
648 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
649 instructions.
650
d241b910
JB		 6512019-10-07 Jan Beulich <jbeulich@suse.com>
652
653 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
654 (cmpsd): Likewise. Move EsSeg to other operand.
655 * opcodes/i386-tbl.h: Re-generate.
656
f5c5b7c1
AM		 6572019-09-23 Alan Modra <amodra@gmail.com>
658
659 * m68k-dis.c: Include cpu-m68k.h
660
7beeaeb8
AM		 6612019-09-23 Alan Modra <amodra@gmail.com>
662
663 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
664 "elf/mips.h" earlier.
665
3f9aad11
JB		 6662018-09-20 Jan Beulich <jbeulich@suse.com>
667
668 PR gas/25012
669 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
670 with SReg operand.
671 * i386-tbl.h: Re-generate.
672
fd361982
AM		 6732019-09-18 Alan Modra <amodra@gmail.com>
674
675 * arc-ext.c: Update throughout for bfd section macro changes.
676
e0b2a78c
SM		 6772019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
678
679 * Makefile.in: Re-generate.
680 * configure: Re-generate.
681
7e9ad3a3
JW		 6822019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
683
684 * riscv-opc.c (riscv_opcodes): Change subset field
685 to insn_class field for all instructions.
686 (riscv_insn_types): Likewise.
687
bb695960
PB		 6882019-09-16 Phil Blundell <pb@pbcl.net>
689
690 * configure: Regenerated.
691
8063ab7e
MV		 6922019-09-10 Miod Vallat <miod@online.fr>
693
694 PR 24982
695 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
696
60391a25
PB		 6972019-09-09 Phil Blundell <pb@pbcl.net>
698
699 binutils 2.33 branch created.
700
f44b758d
NC		 7012019-09-03 Nick Clifton <nickc@redhat.com>
702
703 PR 24961
704 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
705 greater than zero before indexing via (bufcnt -1).
706
1e4b5e7d
NC		 7072019-09-03 Nick Clifton <nickc@redhat.com>
708
709 PR 24958
710 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
711 (MAX_SPEC_REG_NAME_LEN): Define.
712 (struct mmix_dis_info): Use defined constants for array lengths.
713 (get_reg_name): New function.
714 (get_sprec_reg_name): New function.
715 (print_insn_mmix): Use new functions.
716
c4a23bf8
SP		 7172019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
718
719 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
720 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
721 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
722
a051e2f3
KT		 7232019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
724
725 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
726 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
727 (aarch64_sys_reg_supported_p): Update checks for the above.
728
08132bdd
SP		 7292019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
730
731 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
732 cases MVE_SQRSHRL and MVE_UQRSHLL.
733 (print_insn_mve): Add case for specifier 'k' to check
734 specific bit of the instruction.
735
d88bdcb4
PA		 7362019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
737
738 PR 24854
739 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
740 encountering an unknown machine type.
741 (print_insn_arc): Handle arc_insn_length returning 0. In error
742 cases return -1 rather than calling abort.
743
bc750500
JB		 7442019-08-07 Jan Beulich <jbeulich@suse.com>
745
746 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
747 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
748 IgnoreSize.
749 * i386-tbl.h: Re-generate.
750
23d188c7
BW		 7512019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
752
753 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
754 instructions.
755
c0d6f62f
JW		 7562019-07-30 Mel Chen <mel.chen@sifive.com>
757
758 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
759 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
760
761 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
762 fscsr.
763
0f3f7167
CZ		 7642019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
765
766 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
767 and MPY class instructions.
768 (parse_option): Add nps400 option.
769 (print_arc_disassembler_options): Add nps400 info.
770
7e126ba3
CZ		 7712019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
772
773 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
774 (bspop): Likewise.
775 (modapp): Likewise.
776 * arc-opc.c (RAD_CHK): Add.
777 * arc-tbl.h: Regenerate.
778
a028026d
KT		 7792019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
780
781 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
782 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
783
ac79ff9e
NC		 7842019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
785
786 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
787 instructions as UNPREDICTABLE.
788
231097b0
JM		 7892019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
790
791 * bpf-desc.c: Regenerated.
792
1d942ae9
JB		 7932019-07-17 Jan Beulich <jbeulich@suse.com>
794
795 * i386-gen.c (static_assert): Define.
796 (main): Use it.
797 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
798 (Opcode_Modifier_Num): ... this.
799 (Mem): Delete.
800
dfd69174
JB		 8012019-07-16 Jan Beulich <jbeulich@suse.com>
802
803 * i386-gen.c (operand_types): Move RegMem ...
804 (opcode_modifiers): ... here.
805 * i386-opc.h (RegMem): Move to opcode modifer enum.
806 (union i386_operand_type): Move regmem field ...
807 (struct i386_opcode_modifier): ... here.
808 * i386-opc.tbl (RegMem): Define.
809 (mov, movq): Move RegMem on segment, control, debug, and test
810 register flavors.
811 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
812 to non-SSE2AVX flavor.
813 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
814 Move RegMem on register only flavors. Drop IgnoreSize from
815 legacy encoding flavors.
816 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
817 flavors.
818 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
819 register only flavors.
820 (vmovd): Move RegMem and drop IgnoreSize on register only
821 flavor. Change opcode and operand order to store form.
822 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
823
21df382b
JB		 8242019-07-16 Jan Beulich <jbeulich@suse.com>
825
826 * i386-gen.c (operand_type_init, operand_types): Replace SReg
827 entries.
828 * i386-opc.h (SReg2, SReg3): Replace by ...
829 (SReg): ... this.
830 (union i386_operand_type): Replace sreg fields.
831 * i386-opc.tbl (mov, ): Use SReg.
832 (push, pop): Likewies. Drop i386 and x86-64 specific segment
833 register flavors.
834 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
835 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
836
3719fd55
JM		 8372019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
838
839 * bpf-desc.c: Regenerate.
840 * bpf-opc.c: Likewise.
841 * bpf-opc.h: Likewise.
842
92434a14
JM		 8432019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
844
845 * bpf-desc.c: Regenerate.
846 * bpf-opc.c: Likewise.
847
43dd7626
HPN		 8482019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
849
850 * arm-dis.c (print_insn_coprocessor): Rename index to
851 index_operand.
852
98602811
JW		 8532019-07-05 Kito Cheng <kito.cheng@sifive.com>
854
855 * riscv-opc.c (riscv_insn_types): Add r4 type.
856
857 * riscv-opc.c (riscv_insn_types): Add b and j type.
858
859 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
860 format for sb type and correct s type.
861
01c1ee4a
RS		 8622019-07-02 Richard Sandiford <richard.sandiford@arm.com>
863
864 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
865 SVE FMOV alias of FCPY.
866
83adff69
RS		 8672019-07-02 Richard Sandiford <richard.sandiford@arm.com>
868
869 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
870 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
871
89418844
RS		 8722019-07-02 Richard Sandiford <richard.sandiford@arm.com>
873
874 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
875 registers in an instruction prefixed by MOVPRFX.
876
41be57ca
MM		 8772019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
878
879 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
880 sve_size_13 icode to account for variant behaviour of
881 pmull{t,b}.
882 * aarch64-dis-2.c: Regenerate.
883 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
884 sve_size_13 icode to account for variant behaviour of
885 pmull{t,b}.
886 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
887 (OP_SVE_VVV_Q_D): Add new qualifier.
888 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
889 (struct aarch64_opcode): Split pmull{t,b} into those requiring
890 AES and those not.
891
9d3bf266
JB		 8922019-07-01 Jan Beulich <jbeulich@suse.com>
893
894 * opcodes/i386-gen.c (operand_type_init): Remove
895 OPERAND_TYPE_VEC_IMM4 entry.
896 (operand_types): Remove Vec_Imm4.
897 * opcodes/i386-opc.h (Vec_Imm4): Delete.
898 (union i386_operand_type): Remove vec_imm4.
899 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
900 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
901
c3949f43
JB		 9022019-07-01 Jan Beulich <jbeulich@suse.com>
903
904 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
905 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
906 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
907 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
908 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
909 monitorx, mwaitx): Drop ImmExt from operand-less forms.
910 * i386-tbl.h: Re-generate.
911
5641ec01
JB		 9122019-07-01 Jan Beulich <jbeulich@suse.com>
913
914 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
915 register operands.
916 * i386-tbl.h: Re-generate.
917
79dec6b7
JB		 9182019-07-01 Jan Beulich <jbeulich@suse.com>
919
920 * i386-opc.tbl (C): New.
921 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
922 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
923 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
924 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
925 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
926 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
927 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
928 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
929 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
930 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
931 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
932 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
933 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
934 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
935 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
936 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
937 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
938 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
939 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
940 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
941 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
942 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
943 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
944 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
945 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
946 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
947 flavors.
948 * i386-tbl.h: Re-generate.
949
a0a1771e
JB		 9502019-07-01 Jan Beulich <jbeulich@suse.com>
951
952 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
953 register operands.
954 * i386-tbl.h: Re-generate.
955
cd546e7b
JB		 9562019-07-01 Jan Beulich <jbeulich@suse.com>
957
958 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
959 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
960 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
961 * i386-tbl.h: Re-generate.
962
e3bba3fc
JB		 9632019-07-01 Jan Beulich <jbeulich@suse.com>
964
965 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
966 Disp8MemShift from register only templates.
967 * i386-tbl.h: Re-generate.
968
36cc073e
JB		 9692019-07-01 Jan Beulich <jbeulich@suse.com>
970
971 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
972 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
973 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
974 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
975 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
976 EVEX_W_0F11_P_3_M_1): Delete.
977 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
978 EVEX_W_0F11_P_3): New.
979 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
980 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
981 MOD_EVEX_0F11_PREFIX_3 table entries.
982 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
983 PREFIX_EVEX_0F11 table entries.
984 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
985 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
986 EVEX_W_0F11_P_3_M_{0,1} table entries.
987
219920a7
JB		 9882019-07-01 Jan Beulich <jbeulich@suse.com>
989
990 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
991 Delete.
992
e395f487
L		 9932019-06-27 H.J. Lu <hongjiu.lu@intel.com>
994
995 PR binutils/24719
996 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
997 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
998 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
999 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1000 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1001 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1002 EVEX_LEN_0F38C7_R_6_P_2_W_1.
1003 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
1004 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
1005 PREFIX_EVEX_0F38C6_REG_6 entries.
1006 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
1007 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
1008 EVEX_W_0F38C7_R_6_P_2 entries.
1009 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
1010 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
1011 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
1012 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
1013 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
1014 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
1015 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
1016
2b7bcc87
JB		 10172019-06-27 Jan Beulich <jbeulich@suse.com>
1018
1019 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
1020 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
1021 VEX_LEN_0F2D_P_3): Delete.
1022 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
1023 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
1024 (prefix_table): ... here.
1025
c1dc7af5
JB		 10262019-06-27 Jan Beulich <jbeulich@suse.com>
1027
1028 * i386-dis.c (Iq): Delete.
1029 (Id): New.
1030 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
1031 TBM insns.
1032 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
1033 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
1034 (OP_E_memory): Also honor needindex when deciding whether an
1035 address size prefix needs printing.
1036 (OP_I): Remove handling of q_mode. Add handling of d_mode.
1037
d7560e2d
JW		 10382019-06-26 Jim Wilson <jimw@sifive.com>
1039
1040 PR binutils/24739
1041 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
1042 Set info->display_endian to info->endian_code.
1043
2c703856
JB		 10442019-06-25 Jan Beulich <jbeulich@suse.com>
1045
1046 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
1047 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
1048 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
1049 OPERAND_TYPE_ACC64 entries.
1050 * i386-init.h: Re-generate.
1051
54fbadc0
JB		 10522019-06-25 Jan Beulich <jbeulich@suse.com>
1053
1054 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
1055 Delete.
1056 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
1057 of dqa_mode.
1058 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
1059 entries here.
1060 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
1061 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
1062
a280ab8e
JB		 10632019-06-25 Jan Beulich <jbeulich@suse.com>
1064
1065 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
1066 variables.
1067
e1a1babd
JB		 10682019-06-25 Jan Beulich <jbeulich@suse.com>
1069
1070 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
1071 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
1072 movnti.
d7560e2d 1073 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 1074 * i386-tbl.h: Re-generate.
1075
b8364fa7
JB		 10762019-06-25 Jan Beulich <jbeulich@suse.com>
1077
1078 * i386-opc.tbl (and): Mark Imm8S form for optimization.
1079 * i386-tbl.h: Re-generate.
1080
ad692897
L		 10812019-06-21 H.J. Lu <hongjiu.lu@intel.com>
1082
1083 * i386-dis-evex.h: Break into ...
1084 * i386-dis-evex-len.h: New file.
1085 * i386-dis-evex-mod.h: Likewise.
1086 * i386-dis-evex-prefix.h: Likewise.
1087 * i386-dis-evex-reg.h: Likewise.
1088 * i386-dis-evex-w.h: Likewise.
1089 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
1090 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
1091 i386-dis-evex-mod.h.
1092
f0a6222e
L		 10932019-06-19 H.J. Lu <hongjiu.lu@intel.com>
1094
1095 PR binutils/24700
1096 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
1097 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
1098 EVEX_W_0F385B_P_2.
1099 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
1100 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
1101 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
1102 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
1103 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
1104 EVEX_LEN_0F385B_P_2_W_1.
1105 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
1106 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
1107 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
1108 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
1109 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
1110 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
1111 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
1112 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
1113 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
1114 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
1115
6e1c90b7
L		 11162019-06-17 H.J. Lu <hongjiu.lu@intel.com>
1117
1118 PR binutils/24691
1119 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
1120 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
1121 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
1122 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
1123 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
1124 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
1125 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
1126 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
1127 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
1128 EVEX_LEN_0F3A43_P_2_W_1.
1129 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
1130 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
1131 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
1132 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
1133 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
1134 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
1135 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
1136 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
1137 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
1138 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
1139 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
1140 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
1141
bcc5a6eb
NC		 11422019-06-14 Nick Clifton <nickc@redhat.com>
1143
1144 * po/fr.po; Updated French translation.
1145
e4c4ac46
SH		 11462019-06-13 Stafford Horne <shorne@gmail.com>
1147
1148 * or1k-asm.c: Regenerated.
1149 * or1k-desc.c: Regenerated.
1150 * or1k-desc.h: Regenerated.
1151 * or1k-dis.c: Regenerated.
1152 * or1k-ibld.c: Regenerated.
1153 * or1k-opc.c: Regenerated.
1154 * or1k-opc.h: Regenerated.
1155 * or1k-opinst.c: Regenerated.
1156
a0e44ef5
PB		 11572019-06-12 Peter Bergner <bergner@linux.ibm.com>
1158
1159 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
1160
12efd68d
L		 11612019-06-05 H.J. Lu <hongjiu.lu@intel.com>
1162
1163 PR binutils/24633
1164 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
1165 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
1166 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
1167 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
1168 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
1169 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
1170 EVEX_LEN_0F3A1B_P_2_W_1.
1171 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
1172 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
1173 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
1174 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
1175 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
1176 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
1177 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
1178 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
1179
63c6fc6c
L		 11802019-06-04 H.J. Lu <hongjiu.lu@intel.com>
1181
1182 PR binutils/24626
1183 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
1184 EVEX.vvvv when disassembling VEX and EVEX instructions.
1185 (OP_VEX): Set vex.register_specifier to 0 after readding
1186 vex.register_specifier.
1187 (OP_Vex_2src_1): Likewise.
1188 (OP_Vex_2src_2): Likewise.
1189 (OP_LWP_E): Likewise.
1190 (OP_EX_Vex): Don't check vex.register_specifier.
1191 (OP_XMM_Vex): Likewise.
1192
9186c494
L		 11932019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1194 Lili Cui <lili.cui@intel.com>
1195
1196 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
1197 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
1198 instructions.
1199 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
1200 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
1201 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
1202 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
1203 (i386_cpu_flags): Add cpuavx512_vp2intersect.
1204 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
1205 * i386-init.h: Regenerated.
1206 * i386-tbl.h: Likewise.
1207
5d79adc4
L		 12082019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
1209 Lili Cui <lili.cui@intel.com>
1210
1211 * doc/c-i386.texi: Document enqcmd.
1212 * testsuite/gas/i386/enqcmd-intel.d: New file.
1213 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
1214 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
1215 * testsuite/gas/i386/enqcmd.d: Likewise.
1216 * testsuite/gas/i386/enqcmd.s: Likewise.
1217 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
1218 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
1219 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
1220 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
1221 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
1222 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
1223 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
1224 and x86-64-enqcmd.
1225
a9d96ab9
AH		 12262019-06-04 Alan Hayward <alan.hayward@arm.com>
1227
1228 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
1229
4f6d070a
AM		 12302019-06-03 Alan Modra <amodra@gmail.com>
1231
1232 * ppc-dis.c (prefix_opcd_indices): Correct size.
1233
a2f4b66c
L		 12342019-05-28 H.J. Lu <hongjiu.lu@intel.com>
1235
1236 PR gas/24625
1237 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
1238 Disp8ShiftVL.
1239 * i386-tbl.h: Regenerated.
1240
405b5bd8
AM		 12412019-05-24 Alan Modra <amodra@gmail.com>
1242
1243 * po/POTFILES.in: Regenerate.
1244
8acf1435
PB		 12452019-05-24 Peter Bergner <bergner@linux.ibm.com>
1246 Alan Modra <amodra@gmail.com>
1247
1248 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
1249 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
1250 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
1251 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
1252 XTOP>): Define and add entries.
1253 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
1254 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
1255 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
1256 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
1257
dd7efa79
PB		 12582019-05-24 Peter Bergner <bergner@linux.ibm.com>
1259 Alan Modra <amodra@gmail.com>
1260
1261 * ppc-dis.c (ppc_opts): Add "future" entry.
1262 (PREFIX_OPCD_SEGS): Define.
1263 (prefix_opcd_indices): New array.
1264 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
1265 (lookup_prefix): New function.
1266 (print_insn_powerpc): Handle 64-bit prefix instructions.
1267 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
1268 (PMRR, POWERXX): Define.
1269 (prefix_opcodes): New instruction table.
1270 (prefix_num_opcodes): New constant.
1271
79472b45
JM		 12722019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
1273
1274 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
1275 * configure: Regenerated.
1276 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
1277 and cpu/bpf.opc.
1278 (HFILES): Add bpf-desc.h and bpf-opc.h.
1279 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
1280 bpf-ibld.c and bpf-opc.c.
1281 (BPF_DEPS): Define.
1282 * Makefile.in: Regenerated.
1283 * disassemble.c (ARCH_bpf): Define.
1284 (disassembler): Add case for bfd_arch_bpf.
1285 (disassemble_init_for_target): Likewise.
1286 (enum epbf_isa_attr): Define.
1287 * disassemble.h: extern print_insn_bpf.
1288 * bpf-asm.c: Generated.
1289 * bpf-opc.h: Likewise.
1290 * bpf-opc.c: Likewise.
1291 * bpf-ibld.c: Likewise.
1292 * bpf-dis.c: Likewise.
1293 * bpf-desc.h: Likewise.
1294 * bpf-desc.c: Likewise.
1295
ba6cd17f
SD		 12962019-05-21 Sudakshina Das <sudi.das@arm.com>
1297
1298 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
1299 and VMSR with the new operands.
1300
e39c1607
SD		 13012019-05-21 Sudakshina Das <sudi.das@arm.com>
1302
1303 * arm-dis.c (enum mve_instructions): New enum
1304 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
1305 and cneg.
1306 (mve_opcodes): New instructions as above.
1307 (is_mve_encoding_conflict): Add cases for csinc, csinv,
1308 csneg and csel.
1309 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
1310
23d00a41
SD		 13112019-05-21 Sudakshina Das <sudi.das@arm.com>
1312
1313 * arm-dis.c (emun mve_instructions): Updated for new instructions.
1314 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
1315 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
1316 uqshl, urshrl and urshr.
1317 (is_mve_okay_in_it): Add new instructions to TRUE list.
1318 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
1319 (print_insn_mve): Updated to accept new %j,
1320 %<bitfield>m and %<bitfield>n patterns.
1321
cd4797ee
FS		 13222019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
1323
1324 * mips-opc.c (mips_builtin_opcodes): Change source register
1325 constraint for DAUI.
1326
999b073b
NC		 13272019-05-20 Nick Clifton <nickc@redhat.com>
1328
1329 * po/fr.po: Updated French translation.
1330
14b456f2
AV		 13312019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1332 Michael Collison <michael.collison@arm.com>
1333
1334 * arm-dis.c (thumb32_opcodes): Add new instructions.
1335 (enum mve_instructions): Likewise.
1336 (enum mve_undefined): Add new reasons.
1337 (is_mve_encoding_conflict): Handle new instructions.
1338 (is_mve_undefined): Likewise.
1339 (is_mve_unpredictable): Likewise.
1340 (print_mve_undefined): Likewise.
1341 (print_mve_size): Likewise.
1342
f49bb598
AV		 13432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1344 Michael Collison <michael.collison@arm.com>
1345
1346 * arm-dis.c (thumb32_opcodes): Add new instructions.
1347 (enum mve_instructions): Likewise.
1348 (is_mve_encoding_conflict): Handle new instructions.
1349 (is_mve_undefined): Likewise.
1350 (is_mve_unpredictable): Likewise.
1351 (print_mve_size): Likewise.
1352
56858bea
AV		 13532019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1354 Michael Collison <michael.collison@arm.com>
1355
1356 * arm-dis.c (thumb32_opcodes): Add new instructions.
1357 (enum mve_instructions): Likewise.
1358 (is_mve_encoding_conflict): Likewise.
1359 (is_mve_unpredictable): Likewise.
1360 (print_mve_size): Likewise.
1361
e523f101
AV		 13622019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1363 Michael Collison <michael.collison@arm.com>
1364
1365 * arm-dis.c (thumb32_opcodes): Add new instructions.
1366 (enum mve_instructions): Likewise.
1367 (is_mve_encoding_conflict): Handle new instructions.
1368 (is_mve_undefined): Likewise.
1369 (is_mve_unpredictable): Likewise.
1370 (print_mve_size): Likewise.
1371
66dcaa5d
AV		 13722019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1373 Michael Collison <michael.collison@arm.com>
1374
1375 * arm-dis.c (thumb32_opcodes): Add new instructions.
1376 (enum mve_instructions): Likewise.
1377 (is_mve_encoding_conflict): Handle new instructions.
1378 (is_mve_undefined): Likewise.
1379 (is_mve_unpredictable): Likewise.
1380 (print_mve_size): Likewise.
1381 (print_insn_mve): Likewise.
1382
d052b9b7
AV		 13832019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1384 Michael Collison <michael.collison@arm.com>
1385
1386 * arm-dis.c (thumb32_opcodes): Add new instructions.
1387 (print_insn_thumb32): Handle new instructions.
1388
ed63aa17
AV		 13892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1390 Michael Collison <michael.collison@arm.com>
1391
1392 * arm-dis.c (enum mve_instructions): Add new instructions.
1393 (enum mve_undefined): Add new reasons.
1394 (is_mve_encoding_conflict): Handle new instructions.
1395 (is_mve_undefined): Likewise.
1396 (is_mve_unpredictable): Likewise.
1397 (print_mve_undefined): Likewise.
1398 (print_mve_size): Likewise.
1399 (print_mve_shift_n): Likewise.
1400 (print_insn_mve): Likewise.
1401
897b9bbc
AV		 14022019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1403 Michael Collison <michael.collison@arm.com>
1404
1405 * arm-dis.c (enum mve_instructions): Add new instructions.
1406 (is_mve_encoding_conflict): Handle new instructions.
1407 (is_mve_unpredictable): Likewise.
1408 (print_mve_rotate): Likewise.
1409 (print_mve_size): Likewise.
1410 (print_insn_mve): Likewise.
1411
1c8f2df8
AV		 14122019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1413 Michael Collison <michael.collison@arm.com>
1414
1415 * arm-dis.c (enum mve_instructions): Add new instructions.
1416 (is_mve_encoding_conflict): Handle new instructions.
1417 (is_mve_unpredictable): Likewise.
1418 (print_mve_size): Likewise.
1419 (print_insn_mve): Likewise.
1420
d3b63143
AV		 14212019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1422 Michael Collison <michael.collison@arm.com>
1423
1424 * arm-dis.c (enum mve_instructions): Add new instructions.
1425 (enum mve_undefined): Add new reasons.
1426 (is_mve_encoding_conflict): Handle new instructions.
1427 (is_mve_undefined): Likewise.
1428 (is_mve_unpredictable): Likewise.
1429 (print_mve_undefined): Likewise.
1430 (print_mve_size): Likewise.
1431 (print_insn_mve): Likewise.
1432
14925797
AV		 14332019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1434 Michael Collison <michael.collison@arm.com>
1435
1436 * arm-dis.c (enum mve_instructions): Add new instructions.
1437 (is_mve_encoding_conflict): Handle new instructions.
1438 (is_mve_undefined): Likewise.
1439 (is_mve_unpredictable): Likewise.
1440 (print_mve_size): Likewise.
1441 (print_insn_mve): Likewise.
1442
c507f10b
AV		 14432019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1444 Michael Collison <michael.collison@arm.com>
1445
1446 * arm-dis.c (enum mve_instructions): Add new instructions.
1447 (enum mve_unpredictable): Add new reasons.
1448 (enum mve_undefined): Likewise.
1449 (is_mve_okay_in_it): Handle new isntructions.
1450 (is_mve_encoding_conflict): Likewise.
1451 (is_mve_undefined): Likewise.
1452 (is_mve_unpredictable): Likewise.
1453 (print_mve_vmov_index): Likewise.
1454 (print_simd_imm8): Likewise.
1455 (print_mve_undefined): Likewise.
1456 (print_mve_unpredictable): Likewise.
1457 (print_mve_size): Likewise.
1458 (print_insn_mve): Likewise.
1459
bf0b396d
AV		 14602019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1461 Michael Collison <michael.collison@arm.com>
1462
1463 * arm-dis.c (enum mve_instructions): Add new instructions.
1464 (enum mve_unpredictable): Add new reasons.
1465 (enum mve_undefined): Likewise.
1466 (is_mve_encoding_conflict): Handle new instructions.
1467 (is_mve_undefined): Likewise.
1468 (is_mve_unpredictable): Likewise.
1469 (print_mve_undefined): Likewise.
1470 (print_mve_unpredictable): Likewise.
1471 (print_mve_rounding_mode): Likewise.
1472 (print_mve_vcvt_size): Likewise.
1473 (print_mve_size): Likewise.
1474 (print_insn_mve): Likewise.
1475
ef1576a1
AV		 14762019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1477 Michael Collison <michael.collison@arm.com>
1478
1479 * arm-dis.c (enum mve_instructions): Add new instructions.
1480 (enum mve_unpredictable): Add new reasons.
1481 (enum mve_undefined): Likewise.
1482 (is_mve_undefined): Handle new instructions.
1483 (is_mve_unpredictable): Likewise.
1484 (print_mve_undefined): Likewise.
1485 (print_mve_unpredictable): Likewise.
1486 (print_mve_size): Likewise.
1487 (print_insn_mve): Likewise.
1488
aef6d006
AV		 14892019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1490 Michael Collison <michael.collison@arm.com>
1491
1492 * arm-dis.c (enum mve_instructions): Add new instructions.
1493 (enum mve_undefined): Add new reasons.
1494 (insns): Add new instructions.
1495 (is_mve_encoding_conflict):
1496 (print_mve_vld_str_addr): New print function.
1497 (is_mve_undefined): Handle new instructions.
1498 (is_mve_unpredictable): Likewise.
1499 (print_mve_undefined): Likewise.
1500 (print_mve_size): Likewise.
1501 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
1502 (print_insn_mve): Handle new operands.
1503
04d54ace
AV		 15042019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1505 Michael Collison <michael.collison@arm.com>
1506
1507 * arm-dis.c (enum mve_instructions): Add new instructions.
1508 (enum mve_unpredictable): Add new reasons.
1509 (is_mve_encoding_conflict): Handle new instructions.
1510 (is_mve_unpredictable): Likewise.
1511 (mve_opcodes): Add new instructions.
1512 (print_mve_unpredictable): Handle new reasons.
1513 (print_mve_register_blocks): New print function.
1514 (print_mve_size): Handle new instructions.
1515 (print_insn_mve): Likewise.
1516
9743db03
AV		 15172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1518 Michael Collison <michael.collison@arm.com>
1519
1520 * arm-dis.c (enum mve_instructions): Add new instructions.
1521 (enum mve_unpredictable): Add new reasons.
1522 (enum mve_undefined): Likewise.
1523 (is_mve_encoding_conflict): Handle new instructions.
1524 (is_mve_undefined): Likewise.
1525 (is_mve_unpredictable): Likewise.
1526 (coprocessor_opcodes): Move NEON VDUP from here...
1527 (neon_opcodes): ... to here.
1528 (mve_opcodes): Add new instructions.
1529 (print_mve_undefined): Handle new reasons.
1530 (print_mve_unpredictable): Likewise.
1531 (print_mve_size): Handle new instructions.
1532 (print_insn_neon): Handle vdup.
1533 (print_insn_mve): Handle new operands.
1534
143275ea
AV		 15352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1536 Michael Collison <michael.collison@arm.com>
1537
1538 * arm-dis.c (enum mve_instructions): Add new instructions.
1539 (enum mve_unpredictable): Add new values.
1540 (mve_opcodes): Add new instructions.
1541 (vec_condnames): New array with vector conditions.
1542 (mve_predicatenames): New array with predicate suffixes.
1543 (mve_vec_sizename): New array with vector sizes.
1544 (enum vpt_pred_state): New enum with vector predication states.
1545 (struct vpt_block): New struct type for vpt blocks.
1546 (vpt_block_state): Global struct to keep track of state.
1547 (mve_extract_pred_mask): New helper function.
1548 (num_instructions_vpt_block): Likewise.
1549 (mark_outside_vpt_block): Likewise.
1550 (mark_inside_vpt_block): Likewise.
1551 (invert_next_predicate_state): Likewise.
1552 (update_next_predicate_state): Likewise.
1553 (update_vpt_block_state): Likewise.
1554 (is_vpt_instruction): Likewise.
1555 (is_mve_encoding_conflict): Add entries for new instructions.
1556 (is_mve_unpredictable): Likewise.
1557 (print_mve_unpredictable): Handle new cases.
1558 (print_instruction_predicate): Likewise.
1559 (print_mve_size): New function.
1560 (print_vec_condition): New function.
1561 (print_insn_mve): Handle vpt blocks and new print operands.
1562
f08d8ce3
AV		 15632019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1564
1565 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
1566 8, 14 and 15 for Armv8.1-M Mainline.
1567
73cd51e5
AV		 15682019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1569 Michael Collison <michael.collison@arm.com>
1570
1571 * arm-dis.c (enum mve_instructions): New enum.
1572 (enum mve_unpredictable): Likewise.
1573 (enum mve_undefined): Likewise.
1574 (struct mopcode32): New struct.
1575 (is_mve_okay_in_it): New function.
1576 (is_mve_architecture): Likewise.
1577 (arm_decode_field): Likewise.
1578 (arm_decode_field_multiple): Likewise.
1579 (is_mve_encoding_conflict): Likewise.
1580 (is_mve_undefined): Likewise.
1581 (is_mve_unpredictable): Likewise.
1582 (print_mve_undefined): Likewise.
1583 (print_mve_unpredictable): Likewise.
1584 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
1585 (print_insn_mve): New function.
1586 (print_insn_thumb32): Handle MVE architecture.
1587 (select_arm_features): Force thumb for Armv8.1-m Mainline.
1588
3076e594
NC		 15892019-05-10 Nick Clifton <nickc@redhat.com>
1590
1591 PR 24538
1592 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
1593 end of the table prematurely.
1594
387e7624
FS		 15952019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
1596
1597 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
1598 macros for R6.
1599
0067be51
AM		 16002019-05-11 Alan Modra <amodra@gmail.com>
1601
1602 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
1603 when -Mraw is in effect.
1604
42e6288f
MM		 16052019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1606
1607 * aarch64-dis-2.c: Regenerate.
1608 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
1609 (OP_SVE_BBB): New variant set.
1610 (OP_SVE_DDDD): New variant set.
1611 (OP_SVE_HHH): New variant set.
1612 (OP_SVE_HHHU): New variant set.
1613 (OP_SVE_SSS): New variant set.
1614 (OP_SVE_SSSU): New variant set.
1615 (OP_SVE_SHH): New variant set.
1616 (OP_SVE_SBBU): New variant set.
1617 (OP_SVE_DSS): New variant set.
1618 (OP_SVE_DHHU): New variant set.
1619 (OP_SVE_VMV_HSD_BHS): New variant set.
1620 (OP_SVE_VVU_HSD_BHS): New variant set.
1621 (OP_SVE_VVVU_SD_BH): New variant set.
1622 (OP_SVE_VVVU_BHSD): New variant set.
1623 (OP_SVE_VVV_QHD_DBS): New variant set.
1624 (OP_SVE_VVV_HSD_BHS): New variant set.
1625 (OP_SVE_VVV_HSD_BHS2): New variant set.
1626 (OP_SVE_VVV_BHS_HSD): New variant set.
1627 (OP_SVE_VV_BHS_HSD): New variant set.
1628 (OP_SVE_VVV_SD): New variant set.
1629 (OP_SVE_VVU_BHS_HSD): New variant set.
1630 (OP_SVE_VZVV_SD): New variant set.
1631 (OP_SVE_VZVV_BH): New variant set.
1632 (OP_SVE_VZV_SD): New variant set.
1633 (aarch64_opcode_table): Add sve2 instructions.
1634
28ed815a
MM		 16352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1636
1637 * aarch64-asm-2.c: Regenerated.
1638 * aarch64-dis-2.c: Regenerated.
1639 * aarch64-opc-2.c: Regenerated.
1640 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1641 for SVE_SHLIMM_UNPRED_22.
1642 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1643 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1644 operand.
1645
fd1dc4a0
MM		 16462019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1647
1648 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1649 sve_size_tsz_bhs iclass encode.
1650 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1651 sve_size_tsz_bhs iclass decode.
1652
31e36ab3
MM		 16532019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1654
1655 * aarch64-asm-2.c: Regenerated.
1656 * aarch64-dis-2.c: Regenerated.
1657 * aarch64-opc-2.c: Regenerated.
1658 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1659 for SVE_Zm4_11_INDEX.
1660 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1661 (fields): Handle SVE_i2h field.
1662 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1663 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1664
1be5f94f
MM		 16652019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1666
1667 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1668 sve_shift_tsz_bhsd iclass encode.
1669 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1670 sve_shift_tsz_bhsd iclass decode.
1671
3c17238b
MM		 16722019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1673
1674 * aarch64-asm-2.c: Regenerated.
1675 * aarch64-dis-2.c: Regenerated.
1676 * aarch64-opc-2.c: Regenerated.
1677 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1678 (aarch64_encode_variant_using_iclass): Handle
1679 sve_shift_tsz_hsd iclass encode.
1680 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1681 sve_shift_tsz_hsd iclass decode.
1682 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1683 for SVE_SHRIMM_UNPRED_22.
1684 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1685 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1686 operand.
1687
cd50a87a
MM		 16882019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1689
1690 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1691 sve_size_013 iclass encode.
1692 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1693 sve_size_013 iclass decode.
1694
3c705960
MM		 16952019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1696
1697 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1698 sve_size_bh iclass encode.
1699 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1700 sve_size_bh iclass decode.
1701
0a57e14f
MM		 17022019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1703
1704 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1705 sve_size_sd2 iclass encode.
1706 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1707 sve_size_sd2 iclass decode.
1708 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1709 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1710
c469c864
MM		 17112019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1712
1713 * aarch64-asm-2.c: Regenerated.
1714 * aarch64-dis-2.c: Regenerated.
1715 * aarch64-opc-2.c: Regenerated.
1716 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1717 for SVE_ADDR_ZX.
1718 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1719 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1720
116adc27
MM		 17212019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1722
1723 * aarch64-asm-2.c: Regenerated.
1724 * aarch64-dis-2.c: Regenerated.
1725 * aarch64-opc-2.c: Regenerated.
1726 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1727 for SVE_Zm3_11_INDEX.
1728 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1729 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1730 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1731 fields.
1732 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1733
3bd82c86
MM		 17342019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1735
1736 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1737 sve_size_hsd2 iclass encode.
1738 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1739 sve_size_hsd2 iclass decode.
1740 * aarch64-opc.c (fields): Handle SVE_size field.
1741 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1742
adccc507
MM		 17432019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1744
1745 * aarch64-asm-2.c: Regenerated.
1746 * aarch64-dis-2.c: Regenerated.
1747 * aarch64-opc-2.c: Regenerated.
1748 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1749 for SVE_IMM_ROT3.
1750 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1751 (fields): Handle SVE_rot3 field.
1752 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1753 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1754
5cd99750
MM		 17552019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1756
1757 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1758 instructions.
1759
7ce2460a
MM		 17602019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1761
1762 * aarch64-tbl.h
1763 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1764 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1765 aarch64_feature_sve2bitperm): New feature sets.
1766 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1767 for feature set addresses.
1768 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1769 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1770
41cee089
FS		 17712019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1772 Faraz Shahbazker <fshahbazker@wavecomp.com>
1773
1774 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1775 argument and set ASE_EVA_R6 appropriately.
1776 (set_default_mips_dis_options): Pass ISA to above.
1777 (parse_mips_dis_option): Likewise.
1778 * mips-opc.c (EVAR6): New macro.
1779 (mips_builtin_opcodes): Add llwpe, scwpe.
1780
b83b4b13
SD		 17812019-05-01 Sudakshina Das <sudi.das@arm.com>
1782
1783 * aarch64-asm-2.c: Regenerated.
1784 * aarch64-dis-2.c: Regenerated.
1785 * aarch64-opc-2.c: Regenerated.
1786 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1787 AARCH64_OPND_TME_UIMM16.
1788 (aarch64_print_operand): Likewise.
1789 * aarch64-tbl.h (QL_IMM_NIL): New.
1790 (TME): New.
1791 (_TME_INSN): New.
1792 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1793
4a90ce95
JD		 17942019-04-29 John Darrington <john@darrington.wattle.id.au>
1795
1796 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1797
a45328b9
AB		 17982019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1799 Faraz Shahbazker <fshahbazker@wavecomp.com>
1800
1801 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1802
d10be0cb
JD		 18032019-04-24 John Darrington <john@darrington.wattle.id.au>
1804
1805 * s12z-opc.h: Add extern "C" bracketing to help
1806 users who wish to use this interface in c++ code.
1807
a679f24e
JD		 18082019-04-24 John Darrington <john@darrington.wattle.id.au>
1809
1810 * s12z-opc.c (bm_decode): Handle bit map operations with the
1811 "reserved0" mode.
1812
32c36c3c
AV		 18132019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1814
1815 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1816 specifier. Add entries for VLDR and VSTR of system registers.
1817 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1818 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1819 of %J and %K format specifier.
1820
efd6b359
AV		 18212019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1822
1823 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1824 Add new entries for VSCCLRM instruction.
1825 (print_insn_coprocessor): Handle new %C format control code.
1826
6b0dd094
AV		 18272019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1828
1829 * arm-dis.c (enum isa): New enum.
1830 (struct sopcode32): New structure.
1831 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1832 set isa field of all current entries to ANY.
1833 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1834 Only match an entry if its isa field allows the current mode.
1835
4b5a202f
AV		 18362019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1837
1838 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1839 CLRM.
1840 (print_insn_thumb32): Add logic to print %n CLRM register list.
1841
60f993ce
AV		 18422019-04-15 Sudakshina Das <sudi.das@arm.com>
1843
1844 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1845 and %Q patterns.
1846
f6b2b12d
AV		 18472019-04-15 Sudakshina Das <sudi.das@arm.com>
1848
1849 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1850 (print_insn_thumb32): Edit the switch case for %Z.
1851
1889da70
AV		 18522019-04-15 Sudakshina Das <sudi.das@arm.com>
1853
1854 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1855
65d1bc05
AV		 18562019-04-15 Sudakshina Das <sudi.das@arm.com>
1857
1858 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1859
1caf72a5
AV		 18602019-04-15 Sudakshina Das <sudi.das@arm.com>
1861
1862 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1863
f1c7f421
AV		 18642019-04-15 Sudakshina Das <sudi.das@arm.com>
1865
1866 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1867 Arm register with r13 and r15 unpredictable.
1868 (thumb32_opcodes): New instructions for bfx and bflx.
1869
4389b29a
AV		 18702019-04-15 Sudakshina Das <sudi.das@arm.com>
1871
1872 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1873
e5d6e09e
AV		 18742019-04-15 Sudakshina Das <sudi.das@arm.com>
1875
1876 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1877
e12437dc
AV		 18782019-04-15 Sudakshina Das <sudi.das@arm.com>
1879
1880 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1881
031254f2
AV		 18822019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1883
1884 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1885
e5a557ac
JD		 18862019-04-12 John Darrington <john@darrington.wattle.id.au>
1887
1888 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1889 "optr". ("operator" is a reserved word in c++).
1890
bd7ceb8d
SD		 18912019-04-11 Sudakshina Das <sudi.das@arm.com>
1892
1893 * aarch64-opc.c (aarch64_print_operand): Add case for
1894 AARCH64_OPND_Rt_SP.
1895 (verify_constraints): Likewise.
1896 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1897 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1898 to accept Rt|SP as first operand.
1899 (AARCH64_OPERANDS): Add new Rt_SP.
1900 * aarch64-asm-2.c: Regenerated.
1901 * aarch64-dis-2.c: Regenerated.
1902 * aarch64-opc-2.c: Regenerated.
1903
e54010f1
SD		 19042019-04-11 Sudakshina Das <sudi.das@arm.com>
1905
1906 * aarch64-asm-2.c: Regenerated.
1907 * aarch64-dis-2.c: Likewise.
1908 * aarch64-opc-2.c: Likewise.
1909 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1910
7e96e219
RS		 19112019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1912
1913 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1914
6f2791d5
L		 19152019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1916
1917 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1918 * i386-init.h: Regenerated.
1919
e392bad3
AM		 19202019-04-07 Alan Modra <amodra@gmail.com>
1921
1922 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1923 op_separator to control printing of spaces, comma and parens
1924 rather than need_comma, need_paren and spaces vars.
1925
dffaa15c
AM		 19262019-04-07 Alan Modra <amodra@gmail.com>
1927
1928 PR 24421
1929 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1930 (print_insn_neon, print_insn_arm): Likewise.
1931
d6aab7a1
XG		 19322019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1933
1934 * i386-dis-evex.h (evex_table): Updated to support BF16
1935 instructions.
1936 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1937 and EVEX_W_0F3872_P_3.
1938 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1939 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1940 * i386-opc.h (enum): Add CpuAVX512_BF16.
1941 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1942 * i386-opc.tbl: Add AVX512 BF16 instructions.
1943 * i386-init.h: Regenerated.
1944 * i386-tbl.h: Likewise.
1945
66e85460
AM		 19462019-04-05 Alan Modra <amodra@gmail.com>
1947
1948 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1949 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1950 to favour printing of "-" branch hint when using the "y" bit.
1951 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1952
c2b1c275
AM		 19532019-04-05 Alan Modra <amodra@gmail.com>
1954
1955 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1956 opcode until first operand is output.
1957
aae9718e
PB		 19582019-04-04 Peter Bergner <bergner@linux.ibm.com>
1959
1960 PR gas/24349
1961 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1962 (valid_bo_post_v2): Add support for 'at' branch hints.
1963 (insert_bo): Only error on branch on ctr.
1964 (get_bo_hint_mask): New function.
1965 (insert_boe): Add new 'branch_taken' formal argument. Add support
1966 for inserting 'at' branch hints.
1967 (extract_boe): Add new 'branch_taken' formal argument. Add support
1968 for extracting 'at' branch hints.
1969 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1970 (BOE): Delete operand.
1971 (BOM, BOP): New operands.
1972 (RM): Update value.
1973 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1974 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1975 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1976 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1977 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1978 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1979 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1980 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1981 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1982 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1983 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1984 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1985 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1986 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1987 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1988 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1989 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1990 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1991 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1992 bttarl+>: New extended mnemonics.
1993
96a86c01
AM		 19942019-03-28 Alan Modra <amodra@gmail.com>
1995
1996 PR 24390
1997 * ppc-opc.c (BTF): Define.
1998 (powerpc_opcodes): Use for mtfsb*.
1999 * ppc-dis.c (print_insn_powerpc): Print fields with both
2000 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
2001
796d6298
TC		 20022019-03-25 Tamar Christina <tamar.christina@arm.com>
2003
2004 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
2005 (mapping_symbol_for_insn): Implement new algorithm.
2006 (print_insn): Remove duplicate code.
2007
60df3720
TC		 20082019-03-25 Tamar Christina <tamar.christina@arm.com>
2009
2010 * aarch64-dis.c (print_insn_aarch64):
2011 Implement override.
2012
51457761
TC		 20132019-03-25 Tamar Christina <tamar.christina@arm.com>
2014
2015 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
2016 order.
2017
53b2f36b
TC		 20182019-03-25 Tamar Christina <tamar.christina@arm.com>
2019
2020 * aarch64-dis.c (last_stop_offset): New.
2021 (print_insn_aarch64): Use stop_offset.
2022
89199bb5
L		 20232019-03-19 H.J. Lu <hongjiu.lu@intel.com>
2024
2025 PR gas/24359
2026 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
2027 CPU_ANY_AVX2_FLAGS.
2028 * i386-init.h: Regenerated.
2029
97ed31ae
L		 20302019-03-18 H.J. Lu <hongjiu.lu@intel.com>
2031
2032 PR gas/24348
2033 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
2034 vmovdqu16, vmovdqu32 and vmovdqu64.
2035 * i386-tbl.h: Regenerated.
2036
0919bfe9
AK		 20372019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2038
2039 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
2040 from vstrszb, vstrszh, and vstrszf.
2041
20422019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
2043
2044 * s390-opc.txt: Add instruction descriptions.
2045
21820ebe
JW		 20462019-02-08 Jim Wilson <jimw@sifive.com>
2047
2048 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
2049 <bne>: Likewise.
2050
f7dd2fb2
TC		 20512019-02-07 Tamar Christina <tamar.christina@arm.com>
2052
2053 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
2054
6456d318
TC		 20552019-02-07 Tamar Christina <tamar.christina@arm.com>
2056
2057 PR binutils/23212
2058 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
2059 * aarch64-opc.c (verify_elem_sd): New.
2060 (fields): Add FLD_sz entr.
2061 * aarch64-tbl.h (_SIMD_INSN): New.
2062 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
2063 fmulx scalar and vector by element isns.
2064
4a83b610
NC		 20652019-02-07 Nick Clifton <nickc@redhat.com>
2066
2067 * po/sv.po: Updated Swedish translation.
2068
fc60b8c8
AK		 20692019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
2070
2071 * s390-mkopc.c (main): Accept arch13 as cpu string.
2072 * s390-opc.c: Add new instruction formats and instruction opcode
2073 masks.
2074 * s390-opc.txt: Add new arch13 instructions.
2075
e10620d3
TC		 20762019-01-25 Sudakshina Das <sudi.das@arm.com>
2077
2078 * aarch64-tbl.h (QL_LDST_AT): Update macro.
2079 (aarch64_opcode): Change encoding for stg, stzg
2080 st2g and st2zg.
2081 * aarch64-asm-2.c: Regenerated.
2082 * aarch64-dis-2.c: Regenerated.
2083 * aarch64-opc-2.c: Regenerated.
2084
20a4ca55
SD		 20852019-01-25 Sudakshina Das <sudi.das@arm.com>
2086
2087 * aarch64-asm-2.c: Regenerated.
2088 * aarch64-dis-2.c: Likewise.
2089 * aarch64-opc-2.c: Likewise.
2090 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
2091
550fd7bf
SD		 20922019-01-25 Sudakshina Das <sudi.das@arm.com>
2093 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
2094
2095 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
2096 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
2097 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
2098 * aarch64-dis.h (ext_addr_simple_2): Likewise.
2099 * aarch64-opc.c (operand_general_constraint_met_p): Remove
2100 case for ldstgv_indexed.
2101 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
2102 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
2103 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
2104 * aarch64-asm-2.c: Regenerated.
2105 * aarch64-dis-2.c: Regenerated.
2106 * aarch64-opc-2.c: Regenerated.
2107
d9938630
NC		 21082019-01-23 Nick Clifton <nickc@redhat.com>
2109
2110 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2111
375cd423
NC		 21122019-01-21 Nick Clifton <nickc@redhat.com>
2113
2114 * po/de.po: Updated German translation.
2115 * po/uk.po: Updated Ukranian translation.
2116
57299f48
CX		 21172019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
2118 * mips-dis.c (mips_arch_choices): Fix typo in
2119 gs464, gs464e and gs264e descriptors.
2120
f48dfe41
NC		 21212019-01-19 Nick Clifton <nickc@redhat.com>
2122
2123 * configure: Regenerate.
2124 * po/opcodes.pot: Regenerate.
2125
f974f26c
NC		 21262018-06-24 Nick Clifton <nickc@redhat.com>
2127
2128 2.32 branch created.
2129
39f286cd
JD		 21302019-01-09 John Darrington <john@darrington.wattle.id.au>
2131
448b8ca8
JD		 2132 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
2133 if it is null.
2134 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 2135 zero.
2136
3107326d
AP		 21372019-01-09 Andrew Paprocki <andrew@ishiboo.com>
2138
2139 * configure: Regenerate.
2140
7e9ca91e
AM		 21412019-01-07 Alan Modra <amodra@gmail.com>
2142
2143 * configure: Regenerate.
2144 * po/POTFILES.in: Regenerate.
2145
ef1ad42b
JD		 21462019-01-03 John Darrington <john@darrington.wattle.id.au>
2147
2148 * s12z-opc.c: New file.
2149 * s12z-opc.h: New file.
2150 * s12z-dis.c: Removed all code not directly related to display
2151 of instructions. Used the interface provided by the new files
2152 instead.
2153 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 2154 * Makefile.in: Regenerate.
ef1ad42b 2155 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 2156 * configure: Regenerate.
ef1ad42b 2157
82704155
AM		 21582019-01-01 Alan Modra <amodra@gmail.com>
2159
2160 Update year range in copyright notice of all files.
2161
d5c04e1b 2162For older changes see ChangeLog-2018
3499769a 2163\f
d5c04e1b 2164Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 2165
2166Copying and distribution of this file, with or without modification,
2167are permitted in any medium without royalty provided the copyright
2168notice and this notice are preserved.
2169
2170Local Variables:
2171mode: change-log
2172left-margin: 8
2173fill-column: 74
2174version-control: never
2175End:
GDB Binutils - Deliverables
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