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gdb: Remove support for obsolete OSABIs and a.out
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
39f66f3a
MR		 12016-12-08 Maciej W. Rozycki <macro@imgtec.com>
2
3 * mips-dis.c (print_mips16_insn_arg): Remove extraneous
4 indentation space across.
5
860b03a8
MR		 62016-12-08 Maciej W. Rozycki <macro@imgtec.com>
7
8 * mips-dis.c (print_mips16_insn_arg): Avoid delay-slot
9 adjustment for PC-relative operations following MIPS16e compact
10 jumps or undefined RR/J(AL)R(C) encodings.
11
329d01f7
MR		 122016-12-08 Maciej W. Rozycki <macro@imgtec.com>
13
14 * aarch64-asm.c (aarch64_ins_reglane): Rename `index' local
15 variable to `reglane_index'.
16
3a2488dd
LM		 172016-12-08 Luis Machado <lgustavo@codesourcery.com>
18
19 * ppc-dis.c (get_powerpc_dialect): Check NULL info->section.
20
5f5c6e03
MR		 212016-12-07 Maciej W. Rozycki <macro@imgtec.com>
22
23 * mips-dis.c (print_mips16_insn_arg): Fix comment typo.
24
343fa690
MR		 252016-12-07 Maciej W. Rozycki <macro@imgtec.com>
26
27 * mips16-opc.c (mips16_opcodes): Update comment naming structure
28 members.
29
6725647c
MR		 302016-12-07 Maciej W. Rozycki <macro@imgtec.com>
31
32 * mips-dis.c (print_mips_disassembler_options): Reformat output.
33
c28eeff2
SN		 342016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
35
36 * arm-dis.c (coprocessor_opcodes): Add vcmla and vcadd.
37 (print_insn_coprocessor): Add 'V' format for neon D or Q regs.
38
49e8a725
SN		 392016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com>
40
41 * arm-dis.c (coprocessor_opcodes): Add vjcvt.
42
a37a2806
NC		 432016-12-01 Nick Clifton <nickc@redhat.com>
44
45 PR binutils/20893
46 * i386-dis.c (OP_VEX): Replace call to abort with a append of bad
47 opcode designator.
48
abe7c33b
CZ		 492016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
50
51 * arc-opc.c (insert_ra_chk): New function.
52 (insert_rb_chk): Likewise.
53 (insert_rad): Update text error message.
54 (insert_rcd): Likewise.
55 (insert_rhv2): Likewise.
56 (insert_r0): Likewise.
57 (insert_r1): Likewise.
58 (insert_r2): Likewise.
59 (insert_r3): Likewise.
60 (insert_sp): Likewise.
61 (insert_gp): Likewise.
62 (insert_pcl): Likewise.
63 (insert_blink): Likewise.
64 (insert_ilink1): Likewise.
65 (insert_ilink2): Likewise.
66 (insert_ras): Likewise.
67 (insert_rbs): Likewise.
68 (insert_rcs): Likewise.
69 (insert_simm3s): Likewise.
70 (insert_rrange): Likewise.
71 (insert_fpel): Likewise.
72 (insert_blinkel): Likewise.
73 (insert_pcel): Likewise.
74 (insert_nps_3bit_dst): Likewise.
75 (insert_nps_3bit_dst_short): Likewise.
76 (insert_nps_3bit_src2_short): Likewise.
77 (insert_nps_bitop_size_2b): Likewise.
78 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
79 (RA_CHK): Define.
80 (RB): Adjust.
81 (RB_CHK): Define.
82 (RC): Adjust.
83 * arc-dis.c (print_insn_arc): Add LOAD and STORE class.
84 * arc-tbl.h (div, divu): All instructions are DIVREM class.
85 Change first insn argument to check for LP_COUNT usage.
86 (rem): Likewise.
87 (ld, ldd): All instructions are LOAD class. Change first insn
88 argument to check for LP_COUNT usage.
89 (st, std): All instructions are STORE class.
90 (mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
91 Change first insn argument to check for LP_COUNT usage.
92 (mov): All instructions are MOVE class. Change first insn
93 argument to check for LP_COUNT usage.
94
ee881e5d
CZ		 952016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
96
97 * arc-dis.c (is_compatible_p): Remove function.
98 (skip_this_opcode): Don't add any decoding class to decode list.
99 Remove warning.
100 (find_format_from_table): Go through all opcodes, and warn if we
101 use a guessed mnemonic.
102
abfcb414
AP		 1032016-11-28 Ramiro Polla <ramiro@hex-rays.com>
104 Amit Pawar <amit.pawar@amd.com>
105
106 PR binutils/20637
107 * i386-dis.c (get_valid_dis386): Ignore REX_B for 32-bit XOP
108 instructions.
109
96fe4562
AM		 1102016-11-22 Ambrogino Modigliani <ambrogino.modigliani@gmail.com>
111
112 * configure: Regenerate.
113
6884417a
JM		 1142016-11-22 Jose E. Marchesi <jose.marchesi@oracle.com>
115
116 * sparc-opc.c (HWS_V8): Definition moved from
117 gas/config/tc-sparc.c.
118 (HWS_V9): Likewise.
119 (HWS_VA): Likewise.
120 (HWS_VB): Likewise.
121 (HWS_VC): Likewise.
122 (HWS_VD): Likewise.
123 (HWS_VE): Likewise.
124 (HWS_VV): Likewise.
125 (HWS_VM): Likewise.
126 (HWS2_VM): Likewise.
127 (sparc_opcode_archs): Initialize hwcaps and hwcaps2 fields of
128 existing entries.
129
c4b943d7
CZ		 1302016-11-22 Claudiu Zissulescu <claziss@synopsys.com>
131
132 * arc-tbl.h: Reorder conditional flags with delay flags for 'b'
133 instructions.
134
c2c4ff8d
SN		 1352016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
136
137 * aarch64-tbl.h (QL_V3SAMEHSD_ROT, QL_ELEMENT_ROT): Define.
138 (aarch64_feature_simd_v8_3, SIMD_V8_3): Define.
139 (aarch64_opcode_table): Add fcmla and fcadd.
140 (AARCH64_OPERANDS): Add IMM_ROT{1,2,3}.
141 * aarch64-asm.h (aarch64_ins_imm_rotate): Declare.
142 * aarch64-asm.c (aarch64_ins_imm_rotate): Define.
143 * aarch64-dis.h (aarch64_ext_imm_rotate): Declare.
144 * aarch64-dis.c (aarch64_ext_imm_rotate): Define.
145 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_rotate{1,2,3}.
146 * aarch64-opc.c (fields): Add FLD_rotate{1,2,3}.
147 (operand_general_constraint_met_p): Rotate and index range check.
148 (aarch64_print_operand): Handle rotate operand.
149 * aarch64-asm-2.c: Regenerate.
150 * aarch64-dis-2.c: Likewise.
151 * aarch64-opc-2.c: Likewise.
152
28617675
SN		 1532016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
154
155 * aarch64-tbl.h (arch64_opcode_table): Add ldaprb, ldaprh, ldapr.
156 * aarch64-asm-2.c: Regenerate.
157 * aarch64-dis-2.c: Regenerate.
158 * aarch64-opc-2.c: Regenerate.
159
ccfc90a3
SN		 1602016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
161
162 * aarch64-tbl.h (arch64_opcode_table): Add fjcvtzs.
163 (QL_FP2INT_W_D, aarch64_feature_fp_v8_3, FP_V8_3): Define.
164 * aarch64-asm-2.c: Regenerate.
165 * aarch64-dis-2.c: Regenerate.
166 * aarch64-opc-2.c: Regenerate.
167
3f06e550
SN		 1682016-11-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
169
170 * aarch64-tbl.h (QL_X1NIL): New.
171 (arch64_opcode_table): Add ldraa, ldrab.
172 (AARCH64_OPERANDS): Add "ADDR_SIMM10".
173 * aarch64-asm.h (aarch64_ins_addr_simm10): Declare.
174 * aarch64-asm.c (aarch64_ins_addr_simm10): Define.
175 * aarch64-dis.h (aarch64_ext_addr_simm10): Declare.
176 * aarch64-dis.c (aarch64_ext_addr_simm10): Define.
177 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_S_simm10.
178 * aarch64-opc.c (fields): Add data for FLD_S_simm10.
179 (operand_general_constraint_met_p): Handle AARCH64_OPND_ADDR_SIMM10.
180 (aarch64_print_operand): Likewise.
181 * aarch64-asm-2.c: Regenerate.
182 * aarch64-dis-2.c: Regenerate.
183 * aarch64-opc-2.c: Regenerate.
184
74f5402d
SN		 1852016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
186
187 * aarch64-tbl.h (arch64_opcode_table): Add braa, brab, blraa, blrab, braaz,
188 brabz, blraaz, blrabz, retaa, retab, eretaa, eretab.
189 * aarch64-asm-2.c: Regenerate.
190 * aarch64-dis-2.c: Regenerate.
191 * aarch64-opc-2.c: Regenerate.
192
c84364ec
SN		 1932016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
194
195 * aarch64-tbl.h (arch64_opcode_table): Add pacga.
196 (AARCH64_OPERANDS): Add Rm_SP.
197 * aarch64-opc.c (aarch64_print_operand): Handle AARCH64_OPND_Rm_SP.
198 * aarch64-asm-2.c: Regenerate.
199 * aarch64-dis-2.c: Regenerate.
200 * aarch64-opc-2.c: Regenerate.
201
a2cfc830
SN		 2022016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
203
204 * aarch64-tbl.h (arch64_opcode_table): Add pacia, pacib, pacda, pacdb, autia,
205 autib, autda, autdb, paciza, pacizb, pacdza, pacdzb, autiza, autizb, autdza,
206 autdzb, xpaci, xpacd.
207 * aarch64-asm-2.c: Regenerate.
208 * aarch64-dis-2.c: Regenerate.
209 * aarch64-opc-2.c: Regenerate.
210
b0bfa7b5
SN		 2112016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
212
213 * aarch64-opc.c (aarch64_sys_regs): Add apiakeylo_el1, apiakeyhi_el1,
214 apibkeylo_el1, apibkeyhi_el1, apdakeylo_el1, apdakeyhi_el1,
215 apdbkeylo_el1, apdbkeyhi_el1, apgakeylo_el1 and apgakeyhi_el1.
216 (aarch64_sys_reg_supported_p): Add feature test for new registers.
217
8787d804
SN		 2182016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
219
220 * aarch64-tbl.h (aarch64_feature_v8_3, ARMV8_3, V8_3_INSN): New.
221 (arch64_opcode_table): Add xpaclri, pacia1716, pacib1716, autia1716,
222 autib1716, paciaz, paciasp, pacibz, pacibsp, autiaz, autiasp, autibz,
223 autibsp.
224 * aarch64-asm-2.c: Regenerate.
225 * aarch64-dis-2.c: Regenerate.
226
3d731f69
SN		 2272016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
228
229 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
230
60227d64
L		 2312016-11-09 H.J. Lu <hongjiu.lu@intel.com>
232
233 PR binutils/20799
234 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
235 * i386-dis.c (EdqwS): Removed.
236 (dqw_swap_mode): Likewise.
237 (intel_operand_size): Don't check dqw_swap_mode.
238 (OP_E_register): Likewise.
239 (OP_E_memory): Likewise.
240 (OP_G): Likewise.
241 (OP_EX): Likewise.
242 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
243 * i386-tbl.h: Regerated.
244
7efeed17
L		 2452016-11-09 H.J. Lu <hongjiu.lu@intel.com>
246
247 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 248 * i386-tbl.h: Regerated.
7efeed17 249
1f334aeb
L		 2502016-11-08 H.J. Lu <hongjiu.lu@intel.com>
251
252 PR binutils/20701
253 * i386-dis.c (THREE_BYTE_0F7A): Removed.
254 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
255 (three_byte_table): Remove THREE_BYTE_0F7A.
256
48c97fa1
L		 2572016-11-07 H.J. Lu <hongjiu.lu@intel.com>
258
259 PR binutils/20775
260 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
261 (FGRPd9_4): Replace 1 with 2.
262 (FGRPd9_5): Replace 2 with 3.
263 (FGRPd9_6): Replace 3 with 4.
264 (FGRPd9_7): Replace 4 with 5.
265 (FGRPda_5): Replace 5 with 6.
266 (FGRPdb_4): Replace 6 with 7.
267 (FGRPde_3): Replace 7 with 8.
268 (FGRPdf_4): Replace 8 with 9.
269 (fgrps): Add an entry for Bad_Opcode.
270
b437d035
AB		 2712016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
272
273 * arc-opc.c (arc_flag_operands): Add F_DI14.
274 (arc_flag_classes): Add C_DI14.
275 * arc-nps400-tbl.h: Add new exc instructions.
276
5a736821
GM		 2772016-11-03 Graham Markall <graham.markall@embecosm.com>
278
279 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
280 major opcode 0xa.
281 * arc-nps-400-tbl.h: Add dcmac instruction.
282 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
283 (insert_nps_rbdouble_64): Added.
284 (extract_nps_rbdouble_64): Added.
285 (insert_nps_proto_size): Added.
286 (extract_nps_proto_size): Added.
287
bdfe53e3
AB		 2882016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
289
290 * arc-dis.c (struct arc_operand_iterator): Remove all fields
291 relating to long instruction processing, add new limm field.
292 (OPCODE): Rename to...
293 (OPCODE_32BIT_INSN): ...this.
294 (OPCODE_AC): Delete.
295 (skip_this_opcode): Handle different instruction lengths, update
296 macro name.
297 (special_flag_p): Update parameter type.
298 (find_format_from_table): Update for more instruction lengths.
299 (find_format_long_instructions): Delete.
300 (find_format): Update for more instruction lengths.
301 (arc_insn_length): Likewise.
302 (extract_operand_value): Update for more instruction lengths.
303 (operand_iterator_next): Remove code relating to long
304 instructions.
305 (arc_opcode_to_insn_type): New function.
306 (print_insn_arc):Update for more instructions lengths.
307 * arc-ext.c (extInstruction_t): Change argument type.
308 * arc-ext.h (extInstruction_t): Change argument type.
309 * arc-fxi.h: Change type unsigned to unsigned long long
310 extensively throughout.
311 * arc-nps400-tbl.h: Add long instructions taken from
312 arc_long_opcodes table in arc-opc.c.
313 * arc-opc.c: Update parameter types on insert/extract handlers.
314 (arc_long_opcodes): Delete.
315 (arc_num_long_opcodes): Delete.
316 (arc_opcode_len): Update for more instruction lengths.
317
90f61cce
GM		 3182016-11-03 Graham Markall <graham.markall@embecosm.com>
319
320 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
321
06fe285f
GM		 3222016-11-03 Graham Markall <graham.markall@embecosm.com>
323
324 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
325 with arc_opcode_len.
326 (find_format_long_instructions): Likewise.
327 * arc-opc.c (arc_opcode_len): New function.
328
ecf64ec6
AB		 3292016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
330
331 * arc-nps400-tbl.h: Fix some instruction masks.
332
d039fef3
L		 3332016-11-03 H.J. Lu <hongjiu.lu@intel.com>
334
335 * i386-dis.c (REG_82): Removed.
336 (X86_64_82_REG_0): Likewise.
337 (X86_64_82_REG_1): Likewise.
338 (X86_64_82_REG_2): Likewise.
339 (X86_64_82_REG_3): Likewise.
340 (X86_64_82_REG_4): Likewise.
341 (X86_64_82_REG_5): Likewise.
342 (X86_64_82_REG_6): Likewise.
343 (X86_64_82_REG_7): Likewise.
344 (X86_64_82): New.
345 (dis386): Use X86_64_82 instead of REG_82.
346 (reg_table): Remove REG_82.
347 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
348 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
349 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
350 X86_64_82_REG_7.
351
8b89fe14
L		 3522016-11-03 H.J. Lu <hongjiu.lu@intel.com>
353
354 PR binutils/20754
355 * i386-dis.c (REG_82): New.
356 (X86_64_82_REG_0): Likewise.
357 (X86_64_82_REG_1): Likewise.
358 (X86_64_82_REG_2): Likewise.
359 (X86_64_82_REG_3): Likewise.
360 (X86_64_82_REG_4): Likewise.
361 (X86_64_82_REG_5): Likewise.
362 (X86_64_82_REG_6): Likewise.
363 (X86_64_82_REG_7): Likewise.
364 (dis386): Use REG_82.
365 (reg_table): Add REG_82.
366 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
367 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
368 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
369
7148c369
L		 3702016-11-03 H.J. Lu <hongjiu.lu@intel.com>
371
372 * i386-dis.c (REG_82): Renamed to ...
373 (REG_83): This.
374 (dis386): Updated.
375 (reg_table): Likewise.
376
47acf0bd
IT		 3772016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
378
379 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
380 * i386-dis-evex.h (evex_table): Updated.
381 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
382 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
383 (cpu_flags): Add CpuAVX512_4VNNIW.
384 * i386-opc.h (enum): (AVX512_4VNNIW): New.
385 (i386_cpu_flags): Add cpuavx512_4vnniw.
386 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
387 * i386-init.h: Regenerate.
388 * i386-tbl.h: Ditto.
389
920d2ddc
IT		 3902016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
391
392 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
393 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
394 * i386-dis-evex.h (evex_table): Updated.
395 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
396 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
397 (cpu_flags): Add CpuAVX512_4FMAPS.
398 (opcode_modifiers): Add ImplicitQuadGroup modifier.
399 * i386-opc.h (AVX512_4FMAP): New.
400 (i386_cpu_flags): Add cpuavx512_4fmaps.
401 (ImplicitQuadGroup): New.
402 (i386_opcode_modifier): Add implicitquadgroup.
403 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
404 * i386-init.h: Regenerate.
405 * i386-tbl.h: Ditto.
406
e23eba97
NC		 4072016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
408 Andrew Waterman <andrew@sifive.com>
409
410 Add support for RISC-V architecture.
411 * configure.ac: Add entry for bfd_riscv_arch.
412 * configure: Regenerate.
413 * disassemble.c (disassembler): Add support for riscv.
414 (disassembler_usage): Likewise.
415 * riscv-dis.c: New file.
416 * riscv-opc.c: New file.
417
b5cefcca
L		 4182016-10-21 H.J. Lu <hongjiu.lu@intel.com>
419
420 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
421 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
422 (rm_table): Update the RM_0FAE_REG_7 entry.
423 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
424 (cpu_flags): Remove CpuPCOMMIT.
425 * i386-opc.h (CpuPCOMMIT): Removed.
426 (i386_cpu_flags): Remove cpupcommit.
427 * i386-opc.tbl: Remove pcommit.
428 * i386-init.h: Regenerated.
429 * i386-tbl.h: Likewise.
430
9889cbb1
L		 4312016-10-20 H.J. Lu <hongjiu.lu@intel.com>
432
433 PR binutis/20705
434 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
435 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
436 32-bit mode. Don't check vex.register_specifier in 32-bit
437 mode.
438 (OP_VEX): Check for invalid mask registers.
439
28596323
L		 4402016-10-18 H.J. Lu <hongjiu.lu@intel.com>
441
442 PR binutis/20699
443 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
444 sizeflag.
445
da8d7d66
L		 4462016-10-18 H.J. Lu <hongjiu.lu@intel.com>
447
448 PR binutis/20704
449 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
450
eaf02703
MR		 4512016-10-18 Maciej W. Rozycki <macro@imgtec.com>
452
453 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
454 local variable to `index_regno'.
455
decf5bd1
CM		 4562016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
457
458 * arc-tbl.h: Removed any "inv.+" instructions from the table.
459
e5b06ef0
CZ		 4602016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
461
462 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
463 usage on ISA basis.
464
93562a34
JW		 4652016-10-11 Jiong Wang <jiong.wang@arm.com>
466
467 PR target/20666
468 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
469
362c0c4d
JW		 4702016-10-07 Jiong Wang <jiong.wang@arm.com>
471
472 PR target/20667
473 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
474 available.
475
1047201f
AM		 4762016-10-07 Alan Modra <amodra@gmail.com>
477
478 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
479
1a0670f3
AM		 4802016-10-06 Alan Modra <amodra@gmail.com>
481
482 * aarch64-opc.c: Spell fall through comments consistently.
483 * i386-dis.c: Likewise.
484 * aarch64-dis.c: Add missing fall through comments.
485 * aarch64-opc.c: Likewise.
486 * arc-dis.c: Likewise.
487 * arm-dis.c: Likewise.
488 * i386-dis.c: Likewise.
489 * m68k-dis.c: Likewise.
490 * mep-asm.c: Likewise.
491 * ns32k-dis.c: Likewise.
492 * sh-dis.c: Likewise.
493 * tic4x-dis.c: Likewise.
494 * tic6x-dis.c: Likewise.
495 * vax-dis.c: Likewise.
496
2b804145
AM		 4972016-10-06 Alan Modra <amodra@gmail.com>
498
499 * arc-ext.c (create_map): Add missing break.
500 * msp430-decode.opc (encode_as): Likewise.
501 * msp430-decode.c: Regenerate.
502
616ec358
AM		 5032016-10-06 Alan Modra <amodra@gmail.com>
504
505 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
506 * crx-dis.c (print_insn_crx): Likewise.
507
72da393d
L		 5082016-09-30 H.J. Lu <hongjiu.lu@intel.com>
509
510 PR binutils/20657
511 * i386-dis.c (putop): Don't assign alt twice.
512
744ce302
JW		 5132016-09-29 Jiong Wang <jiong.wang@arm.com>
514
515 PR target/20553
516 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
517
a5721ba2
AM		 5182016-09-29 Alan Modra <amodra@gmail.com>
519
520 * ppc-opc.c (L): Make compulsory.
521 (LOPT): New, optional form of L.
522 (HTM_R): Define as LOPT.
523 (L0, L1): Delete.
524 (L32OPT): New, optional for 32-bit L.
525 (L2OPT): New, 2-bit L for dcbf.
526 (SVC_LEC): Update.
527 (L2): Define.
528 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
529 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
530 <dcbf>: Use L2OPT.
531 <tlbiel, tlbie>: Use LOPT.
532 <wclr, wclrall>: Use L2.
533
c5da1932
VZ		 5342016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
535
536 * Makefile.in: Regenerate.
537 * configure: Likewise.
538
2b848ebd
CZ		 5392016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
540
541 * arc-ext-tbl.h (EXTINSN2OPF): Define.
542 (EXTINSN2OP): Use EXTINSN2OPF.
543 (bspeekm, bspop, modapp): New extension instructions.
544 * arc-opc.c (F_DNZ_ND): Define.
545 (F_DNZ_D): Likewise.
546 (F_SIZEB1): Changed.
547 (C_DNZ_D): Define.
548 (C_HARD): Changed.
549 * arc-tbl.h (dbnz): New instruction.
550 (prealloc): Allow it for ARC EM.
551 (xbfu): Likewise.
552
ad43e107
RS		 5532016-09-21 Richard Sandiford <richard.sandiford@arm.com>
554
555 * aarch64-opc.c (print_immediate_offset_address): Print spaces
556 after commas in addresses.
557 (aarch64_print_operand): Likewise.
558
ab3b8fcf
RS		 5592016-09-21 Richard Sandiford <richard.sandiford@arm.com>
560
561 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
562 rather than "should be" or "expected to be" in error messages.
563
bb7eff52
RS		 5642016-09-21 Richard Sandiford <richard.sandiford@arm.com>
565
566 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
567 (print_mnemonic_name): ...here.
568 (print_comment): New function.
569 (print_aarch64_insn): Call it.
570 * aarch64-opc.c (aarch64_conds): Add SVE names.
571 (aarch64_print_operand): Print alternative condition names in
572 a comment.
573
c0890d26
RS		 5742016-09-21 Richard Sandiford <richard.sandiford@arm.com>
575
576 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
577 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
578 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
579 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
580 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
581 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
582 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
583 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
584 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
585 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
586 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
587 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
588 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
589 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
590 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
591 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
592 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
593 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
594 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
595 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
596 (OP_SVE_XWU, OP_SVE_XXU): New macros.
597 (aarch64_feature_sve): New variable.
598 (SVE): New macro.
599 (_SVE_INSN): Likewise.
600 (aarch64_opcode_table): Add SVE instructions.
601 * aarch64-opc.h (extract_fields): Declare.
602 * aarch64-opc-2.c: Regenerate.
603 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
604 * aarch64-asm-2.c: Regenerate.
605 * aarch64-dis.c (extract_fields): Make global.
606 (do_misc_decoding): Handle the new SVE aarch64_ops.
607 * aarch64-dis-2.c: Regenerate.
608
116b6019
RS		 6092016-09-21 Richard Sandiford <richard.sandiford@arm.com>
610
611 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
612 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
613 aarch64_field_kinds.
614 * aarch64-opc.c (fields): Add corresponding entries.
615 * aarch64-asm.c (aarch64_get_variant): New function.
616 (aarch64_encode_variant_using_iclass): Likewise.
617 (aarch64_opcode_encode): Call it.
618 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
619 (aarch64_opcode_decode): Call it.
620
047cd301
RS		 6212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
622
623 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
624 and FP register operands.
625 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
626 (FLD_SVE_Vn): New aarch64_field_kinds.
627 * aarch64-opc.c (fields): Add corresponding entries.
628 (aarch64_print_operand): Handle the new SVE core and FP register
629 operands.
630 * aarch64-opc-2.c: Regenerate.
631 * aarch64-asm-2.c: Likewise.
632 * aarch64-dis-2.c: Likewise.
633
165d4950
RS		 6342016-09-21 Richard Sandiford <richard.sandiford@arm.com>
635
636 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
637 immediate operands.
638 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
639 * aarch64-opc.c (fields): Add corresponding entry.
640 (operand_general_constraint_met_p): Handle the new SVE FP immediate
641 operands.
642 (aarch64_print_operand): Likewise.
643 * aarch64-opc-2.c: Regenerate.
644 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
645 (ins_sve_float_zero_one): New inserters.
646 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
647 (aarch64_ins_sve_float_half_two): Likewise.
648 (aarch64_ins_sve_float_zero_one): Likewise.
649 * aarch64-asm-2.c: Regenerate.
650 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
651 (ext_sve_float_zero_one): New extractors.
652 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
653 (aarch64_ext_sve_float_half_two): Likewise.
654 (aarch64_ext_sve_float_zero_one): Likewise.
655 * aarch64-dis-2.c: Regenerate.
656
e950b345
RS		 6572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
658
659 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
660 integer immediate operands.
661 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
662 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
663 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
664 * aarch64-opc.c (fields): Add corresponding entries.
665 (operand_general_constraint_met_p): Handle the new SVE integer
666 immediate operands.
667 (aarch64_print_operand): Likewise.
668 (aarch64_sve_dupm_mov_immediate_p): New function.
669 * aarch64-opc-2.c: Regenerate.
670 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
671 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
672 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
673 (aarch64_ins_limm): ...here.
674 (aarch64_ins_inv_limm): New function.
675 (aarch64_ins_sve_aimm): Likewise.
676 (aarch64_ins_sve_asimm): Likewise.
677 (aarch64_ins_sve_limm_mov): Likewise.
678 (aarch64_ins_sve_shlimm): Likewise.
679 (aarch64_ins_sve_shrimm): Likewise.
680 * aarch64-asm-2.c: Regenerate.
681 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
682 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
683 * aarch64-dis.c (decode_limm): New function, split out from...
684 (aarch64_ext_limm): ...here.
685 (aarch64_ext_inv_limm): New function.
686 (decode_sve_aimm): Likewise.
687 (aarch64_ext_sve_aimm): Likewise.
688 (aarch64_ext_sve_asimm): Likewise.
689 (aarch64_ext_sve_limm_mov): Likewise.
690 (aarch64_top_bit): Likewise.
691 (aarch64_ext_sve_shlimm): Likewise.
692 (aarch64_ext_sve_shrimm): Likewise.
693 * aarch64-dis-2.c: Regenerate.
694
98907a70
RS		 6952016-09-21 Richard Sandiford <richard.sandiford@arm.com>
696
697 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
698 operands.
699 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
700 the AARCH64_MOD_MUL_VL entry.
701 (value_aligned_p): Cope with non-power-of-two alignments.
702 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
703 (print_immediate_offset_address): Likewise.
704 (aarch64_print_operand): Likewise.
705 * aarch64-opc-2.c: Regenerate.
706 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
707 (ins_sve_addr_ri_s9xvl): New inserters.
708 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
709 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
710 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
711 * aarch64-asm-2.c: Regenerate.
712 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
713 (ext_sve_addr_ri_s9xvl): New extractors.
714 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
715 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
716 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
717 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
718 * aarch64-dis-2.c: Regenerate.
719
4df068de
RS		 7202016-09-21 Richard Sandiford <richard.sandiford@arm.com>
721
722 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
723 address operands.
724 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
725 (FLD_SVE_xs_22): New aarch64_field_kinds.
726 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
727 (get_operand_specific_data): New function.
728 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
729 FLD_SVE_xs_14 and FLD_SVE_xs_22.
730 (operand_general_constraint_met_p): Handle the new SVE address
731 operands.
732 (sve_reg): New array.
733 (get_addr_sve_reg_name): New function.
734 (aarch64_print_operand): Handle the new SVE address operands.
735 * aarch64-opc-2.c: Regenerate.
736 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
737 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
738 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
739 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
740 (aarch64_ins_sve_addr_rr_lsl): Likewise.
741 (aarch64_ins_sve_addr_rz_xtw): Likewise.
742 (aarch64_ins_sve_addr_zi_u5): Likewise.
743 (aarch64_ins_sve_addr_zz): Likewise.
744 (aarch64_ins_sve_addr_zz_lsl): Likewise.
745 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
746 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
747 * aarch64-asm-2.c: Regenerate.
748 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
749 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
750 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
751 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
752 (aarch64_ext_sve_addr_ri_u6): Likewise.
753 (aarch64_ext_sve_addr_rr_lsl): Likewise.
754 (aarch64_ext_sve_addr_rz_xtw): Likewise.
755 (aarch64_ext_sve_addr_zi_u5): Likewise.
756 (aarch64_ext_sve_addr_zz): Likewise.
757 (aarch64_ext_sve_addr_zz_lsl): Likewise.
758 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
759 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
760 * aarch64-dis-2.c: Regenerate.
761
2442d846
RS		 7622016-09-21 Richard Sandiford <richard.sandiford@arm.com>
763
764 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
765 AARCH64_OPND_SVE_PATTERN_SCALED.
766 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
767 * aarch64-opc.c (fields): Add a corresponding entry.
768 (set_multiplier_out_of_range_error): New function.
769 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
770 (operand_general_constraint_met_p): Handle
771 AARCH64_OPND_SVE_PATTERN_SCALED.
772 (print_register_offset_address): Use PRIi64 to print the
773 shift amount.
774 (aarch64_print_operand): Likewise. Handle
775 AARCH64_OPND_SVE_PATTERN_SCALED.
776 * aarch64-opc-2.c: Regenerate.
777 * aarch64-asm.h (ins_sve_scale): New inserter.
778 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
779 * aarch64-asm-2.c: Regenerate.
780 * aarch64-dis.h (ext_sve_scale): New inserter.
781 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
782 * aarch64-dis-2.c: Regenerate.
783
245d2e3f
RS		 7842016-09-21 Richard Sandiford <richard.sandiford@arm.com>
785
786 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
787 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
788 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
789 (FLD_SVE_prfop): Likewise.
790 * aarch64-opc.c: Include libiberty.h.
791 (aarch64_sve_pattern_array): New variable.
792 (aarch64_sve_prfop_array): Likewise.
793 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
794 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
795 AARCH64_OPND_SVE_PRFOP.
796 * aarch64-asm-2.c: Regenerate.
797 * aarch64-dis-2.c: Likewise.
798 * aarch64-opc-2.c: Likewise.
799
d50c751e
RS		 8002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
801
802 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
803 AARCH64_OPND_QLF_P_[ZM].
804 (aarch64_print_operand): Print /z and /m where appropriate.
805
f11ad6bc
RS		 8062016-09-21 Richard Sandiford <richard.sandiford@arm.com>
807
808 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
809 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
810 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
811 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
812 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
813 * aarch64-opc.c (fields): Add corresponding entries here.
814 (operand_general_constraint_met_p): Check that SVE register lists
815 have the correct length. Check the ranges of SVE index registers.
816 Check for cases where p8-p15 are used in 3-bit predicate fields.
817 (aarch64_print_operand): Handle the new SVE operands.
818 * aarch64-opc-2.c: Regenerate.
819 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
820 * aarch64-asm.c (aarch64_ins_sve_index): New function.
821 (aarch64_ins_sve_reglist): Likewise.
822 * aarch64-asm-2.c: Regenerate.
823 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
824 * aarch64-dis.c (aarch64_ext_sve_index): New function.
825 (aarch64_ext_sve_reglist): Likewise.
826 * aarch64-dis-2.c: Regenerate.
827
0c608d6b
RS		 8282016-09-21 Richard Sandiford <richard.sandiford@arm.com>
829
830 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
831 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
832 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
833 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
834 tied operands.
835
01dbfe4c
RS		 8362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
837
838 * aarch64-opc.c (get_offset_int_reg_name): New function.
839 (print_immediate_offset_address): Likewise.
840 (print_register_offset_address): Take the base and offset
841 registers as parameters.
842 (aarch64_print_operand): Update caller accordingly. Use
843 print_immediate_offset_address.
844
72e9f319
RS		 8452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
846
847 * aarch64-opc.c (BANK): New macro.
848 (R32, R64): Take a register number as argument
849 (int_reg): Use BANK.
850
8a7f0c1b
RS		 8512016-09-21 Richard Sandiford <richard.sandiford@arm.com>
852
853 * aarch64-opc.c (print_register_list): Add a prefix parameter.
854 (aarch64_print_operand): Update accordingly.
855
aa2aa4c6
RS		 8562016-09-21 Richard Sandiford <richard.sandiford@arm.com>
857
858 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
859 for FPIMM.
860 * aarch64-asm.h (ins_fpimm): New inserter.
861 * aarch64-asm.c (aarch64_ins_fpimm): New function.
862 * aarch64-asm-2.c: Regenerate.
863 * aarch64-dis.h (ext_fpimm): New extractor.
864 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
865 (aarch64_ext_fpimm): New function.
866 * aarch64-dis-2.c: Regenerate.
867
b5464a68
RS		 8682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
869
870 * aarch64-asm.c: Include libiberty.h.
871 (insert_fields): New function.
872 (aarch64_ins_imm): Use it.
873 * aarch64-dis.c (extract_fields): New function.
874 (aarch64_ext_imm): Use it.
875
42408347
RS		 8762016-09-21 Richard Sandiford <richard.sandiford@arm.com>
877
878 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
879 with an esize parameter.
880 (operand_general_constraint_met_p): Update accordingly.
881 Fix misindented code.
882 * aarch64-asm.c (aarch64_ins_limm): Update call to
883 aarch64_logical_immediate_p.
884
4989adac
RS		 8852016-09-21 Richard Sandiford <richard.sandiford@arm.com>
886
887 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
888
bd11d5d8
RS		 8892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
890
891 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
892
f807f43d
CZ		 8932016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
894
895 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
896
fd486b63
PB		 8972016-09-14 Peter Bergner <bergner@vnet.ibm.com>
898
899 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
900 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
901 xor3>: Delete mnemonics.
902 <cp_abort>: Rename mnemonic from ...
903 <cpabort>: ...to this.
904 <setb>: Change to a X form instruction.
905 <sync>: Change to 1 operand form.
906 <copy>: Delete mnemonic.
907 <copy_first>: Rename mnemonic from ...
908 <copy>: ...to this.
909 <paste, paste.>: Delete mnemonics.
910 <paste_last>: Rename mnemonic from ...
911 <paste.>: ...to this.
912
dce08442
AK		 9132016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
914
915 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
916
952c3f51
AK		 9172016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
918
919 * s390-mkopc.c (main): Support alternate arch strings.
920
8b71537b
PS		 9212016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
922
923 * s390-opc.txt: Fix kmctr instruction type.
924
5b64d091
L		 9252016-09-07 H.J. Lu <hongjiu.lu@intel.com>
926
927 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
928 * i386-init.h: Regenerated.
929
7763838e
CM		 9302016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
931
932 * opcodes/arc-dis.c (print_insn_arc): Changed.
933
1b8b6532
JM		 9342016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
935
936 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
937 camellia_fl.
938
1a336194
TP		 9392016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
940
941 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
942 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
943 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
944
6b40c462
L		 9452016-08-24 H.J. Lu <hongjiu.lu@intel.com>
946
947 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
948 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
949 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
950 PREFIX_MOD_3_0FAE_REG_4.
951 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
952 PREFIX_MOD_3_0FAE_REG_4.
953 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
954 (cpu_flags): Add CpuPTWRITE.
955 * i386-opc.h (CpuPTWRITE): New.
956 (i386_cpu_flags): Add cpuptwrite.
957 * i386-opc.tbl: Add ptwrite instruction.
958 * i386-init.h: Regenerated.
959 * i386-tbl.h: Likewise.
960
ab548d2d
AK		 9612016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
962
963 * arc-dis.h: Wrap around in extern "C".
964
344bde0a
RS		 9652016-08-23 Richard Sandiford <richard.sandiford@arm.com>
966
967 * aarch64-tbl.h (V8_2_INSN): New macro.
968 (aarch64_opcode_table): Use it.
969
5ce912d8
RS		 9702016-08-23 Richard Sandiford <richard.sandiford@arm.com>
971
972 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
973 CORE_INSN, __FP_INSN and SIMD_INSN.
974
9d30b0bd
RS		 9752016-08-23 Richard Sandiford <richard.sandiford@arm.com>
976
977 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
978 (aarch64_opcode_table): Update uses accordingly.
979
dfdaec14
AJ		 9802016-07-25 Andrew Jenner <andrew@codesourcery.com>
981 Kwok Cheung Yeung <kcy@codesourcery.com>
982
983 opcodes/
984 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
985 'e_cmplwi' to 'e_cmpli' instead.
986 (OPVUPRT, OPVUPRT_MASK): Define.
987 (powerpc_opcodes): Add E200Z4 insns.
988 (vle_opcodes): Add context save/restore insns.
989
7bd374a4
MR		 9902016-07-27 Maciej W. Rozycki <macro@imgtec.com>
991
992 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
993 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
994 "j".
995
db18dbab
GM		 9962016-07-27 Graham Markall <graham.markall@embecosm.com>
997
998 * arc-nps400-tbl.h: Change block comments to GNU format.
999 * arc-dis.c: Add new globals addrtypenames,
1000 addrtypenames_max, and addtypeunknown.
1001 (get_addrtype): New function.
1002 (print_insn_arc): Print colons and address types when
1003 required.
1004 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
1005 define insert and extract functions for all address types.
1006 (arc_operands): Add operands for colon and all address
1007 types.
1008 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
1009 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
1010 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
1011 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
1012 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
1013 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
1014
fecd57f9
L		 10152016-07-21 H.J. Lu <hongjiu.lu@intel.com>
1016
1017 * configure: Regenerated.
1018
37fd5ef3
CZ		 10192016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
1020
1021 * arc-dis.c (skipclass): New structure.
1022 (decodelist): New variable.
1023 (is_compatible_p): New function.
1024 (new_element): Likewise.
1025 (skip_class_p): Likewise.
1026 (find_format_from_table): Use skip_class_p function.
1027 (find_format): Decode first the extension instructions.
1028 (print_insn_arc): Select either ARCEM or ARCHS based on elf
1029 e_flags.
1030 (parse_option): New function.
1031 (parse_disassembler_options): Likewise.
1032 (print_arc_disassembler_options): Likewise.
1033 (print_insn_arc): Use parse_disassembler_options function. Proper
1034 select ARCv2 cpu variant.
1035 * disassemble.c (disassembler_usage): Add ARC disassembler
1036 options.
1037
92281a5b
MR		 10382016-07-13 Maciej W. Rozycki <macro@imgtec.com>
1039
1040 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
1041 annotation from the "nal" entry and reorder it beyond "bltzal".
1042
6e7ced37
JM		 10432016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
1044
1045 * sparc-opc.c (ldtxa): New macro.
1046 (sparc_opcodes): Use the macro defined above to add entries for
1047 the LDTXA instructions.
1048 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
1049 instruction.
1050
2f831b9a 10512016-07-07 James Bowman <james.bowman@ftdichip.com>
1052
1053 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
1054 and "jmpc".
1055
c07315e0
JB		 10562016-07-01 Jan Beulich <jbeulich@suse.com>
1057
1058 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
1059 (movzb): Adjust to cover all permitted suffixes.
1060 (movzw): New.
1061 * i386-tbl.h: Re-generate.
1062
9243100a
JB		 10632016-07-01 Jan Beulich <jbeulich@suse.com>
1064
1065 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
1066 (lgdt): Remove Tbyte from non-64-bit variant.
1067 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
1068 xsaves64, xsavec64): Remove Disp16.
1069 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
1070 Remove Disp32S from non-64-bit variants. Remove Disp16 from
1071 64-bit variants.
1072 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
1073 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
1074 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
1075 64-bit variants.
1076 * i386-tbl.h: Re-generate.
1077
8325cc63
JB		 10782016-07-01 Jan Beulich <jbeulich@suse.com>
1079
1080 * i386-opc.tbl (xlat): Remove RepPrefixOk.
1081 * i386-tbl.h: Re-generate.
1082
838441e4
YQ		 10832016-06-30 Yao Qi <yao.qi@linaro.org>
1084
1085 * arm-dis.c (print_insn): Fix typo in comment.
1086
dab26bf4
RS		 10872016-06-28 Richard Sandiford <richard.sandiford@arm.com>
1088
1089 * aarch64-opc.c (operand_general_constraint_met_p): Check the
1090 range of ldst_elemlist operands.
1091 (print_register_list): Use PRIi64 to print the index.
1092 (aarch64_print_operand): Likewise.
1093
5703197e
TS		 10942016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1095
1096 * mcore-opc.h: Remove sentinal.
1097 * mcore-dis.c (print_insn_mcore): Adjust.
1098
ce440d63
GM		 10992016-06-23 Graham Markall <graham.markall@embecosm.com>
1100
1101 * arc-opc.c: Correct description of availability of NPS400
1102 features.
1103
6fd3a02d
PB		 11042016-06-22 Peter Bergner <bergner@vnet.ibm.com>
1105
1106 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
1107 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
1108 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
1109 xor3>: New mnemonics.
1110 <setb>: Change to a VX form instruction.
1111 (insert_sh6): Add support for rldixor.
1112 (extract_sh6): Likewise.
1113
6b477896
TS		 11142016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1115
1116 * arc-ext.h: Wrap in extern C.
1117
bdd582db
GM		 11182016-06-21 Graham Markall <graham.markall@embecosm.com>
1119
1120 * arc-dis.c (arc_insn_length): Add comment on instruction length.
1121 Use same method for determining instruction length on ARC700 and
1122 NPS-400.
1123 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
1124 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
1125 with the NPS400 subclass.
1126 * arc-opc.c: Likewise.
1127
96074adc
JM		 11282016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1129
1130 * sparc-opc.c (rdasr): New macro.
1131 (wrasr): Likewise.
1132 (rdpr): Likewise.
1133 (wrpr): Likewise.
1134 (rdhpr): Likewise.
1135 (wrhpr): Likewise.
1136 (sparc_opcodes): Use the macros above to fix and expand the
1137 definition of read/write instructions from/to
1138 asr/privileged/hyperprivileged instructions.
1139 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
1140 %hva_mask_nz. Prefer softint_set and softint_clear over
1141 set_softint and clear_softint.
1142 (print_insn_sparc): Support %ver in Rd.
1143
7a10c22f
JM		 11442016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1145
1146 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
1147 architecture according to the hardware capabilities they require.
1148
4f26fb3a
JM		 11492016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
1150
1151 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
1152 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
1153 bfd_mach_sparc_v9{c,d,e,v,m}.
1154 * sparc-opc.c (MASK_V9C): Define.
1155 (MASK_V9D): Likewise.
1156 (MASK_V9E): Likewise.
1157 (MASK_V9V): Likewise.
1158 (MASK_V9M): Likewise.
1159 (v6): Add MASK_V9{C,D,E,V,M}.
1160 (v6notlet): Likewise.
1161 (v7): Likewise.
1162 (v8): Likewise.
1163 (v9): Likewise.
1164 (v9andleon): Likewise.
1165 (v9a): Likewise.
1166 (v9b): Likewise.
1167 (v9c): Define.
1168 (v9d): Likewise.
1169 (v9e): Likewise.
1170 (v9v): Likewise.
1171 (v9m): Likewise.
1172 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
1173
3ee6e4fb
NC		 11742016-06-15 Nick Clifton <nickc@redhat.com>
1175
1176 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
1177 constants to match expected behaviour.
1178 (nds32_parse_opcode): Likewise. Also for whitespace.
1179
02f3be19
AB		 11802016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
1181
1182 * arc-opc.c (extract_rhv1): Extract value from insn.
1183
6f9f37ed 11842016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 1185
1186 * arc-nps400-tbl.h: Add ldbit instruction.
1187 * arc-opc.c: Add flag classes required for ldbit.
1188
6f9f37ed 11892016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 1190
1191 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
1192 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1193 support the above instructions.
1194
6f9f37ed 11952016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 1196
1197 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
1198 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
1199 csma, cbba, zncv, and hofs.
1200 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
1201 support the above instructions.
1202
12032016-06-06 Graham Markall <graham.markall@embecosm.com>
1204
1205 * arc-nps400-tbl.h: Add andab and orab instructions.
1206
12072016-06-06 Graham Markall <graham.markall@embecosm.com>
1208
1209 * arc-nps400-tbl.h: Add addl-like instructions.
1210
12112016-06-06 Graham Markall <graham.markall@embecosm.com>
1212
1213 * arc-nps400-tbl.h: Add mxb and imxb instructions.
1214
12152016-06-06 Graham Markall <graham.markall@embecosm.com>
1216
1217 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
1218 instructions.
1219
b2cc3f6f
AK		 12202016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1221
1222 * s390-dis.c (option_use_insn_len_bits_p): New file scope
1223 variable.
1224 (init_disasm): Handle new command line option "insnlength".
1225 (print_s390_disassembler_options): Mention new option in help
1226 output.
1227 (print_insn_s390): Use the encoded insn length when dumping
1228 unknown instructions.
1229
1857fe72
DC		 12302016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1231
1232 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1233 to the address and set as symbol address for LDS/ STS immediate operands.
1234
14b57c7c
AM		 12352016-06-07 Alan Modra <amodra@gmail.com>
1236
1237 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1238 cpu for "vle" to e500.
1239 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1240 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1241 (PPCNONE): Delete, substitute throughout.
1242 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1243 except for major opcode 4 and 31.
1244 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1245
4d1464f2
MW		 12462016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1247
1248 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1249 ARM_EXT_RAS in relevant entries.
1250
026122a6
PB		 12512016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1252
1253 PR binutils/20196
1254 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1255 opcodes for E6500.
1256
07f5af7d
L		 12572016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1258
1259 PR binutis/18386
1260 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1261 (indir_v_mode): New.
1262 Add comments for '&'.
1263 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1264 (putop): Handle '&'.
1265 (intel_operand_size): Handle indir_v_mode.
1266 (OP_E_register): Likewise.
1267 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1268 64-bit indirect call/jmp for AMD64.
1269 * i386-tbl.h: Regenerated
1270
4eb6f892
AB		 12712016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1272
1273 * arc-dis.c (struct arc_operand_iterator): New structure.
1274 (find_format_from_table): All the old content from find_format,
1275 with some minor adjustments, and parameter renaming.
1276 (find_format_long_instructions): New function.
1277 (find_format): Rewritten.
1278 (arc_insn_length): Add LSB parameter.
1279 (extract_operand_value): New function.
1280 (operand_iterator_next): New function.
1281 (print_insn_arc): Use new functions to find opcode, and iterator
1282 over operands.
1283 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1284 (extract_nps_3bit_dst_short): New function.
1285 (insert_nps_3bit_src2_short): New function.
1286 (extract_nps_3bit_src2_short): New function.
1287 (insert_nps_bitop1_size): New function.
1288 (extract_nps_bitop1_size): New function.
1289 (insert_nps_bitop2_size): New function.
1290 (extract_nps_bitop2_size): New function.
1291 (insert_nps_bitop_mod4_msb): New function.
1292 (extract_nps_bitop_mod4_msb): New function.
1293 (insert_nps_bitop_mod4_lsb): New function.
1294 (extract_nps_bitop_mod4_lsb): New function.
1295 (insert_nps_bitop_dst_pos3_pos4): New function.
1296 (extract_nps_bitop_dst_pos3_pos4): New function.
1297 (insert_nps_bitop_ins_ext): New function.
1298 (extract_nps_bitop_ins_ext): New function.
1299 (arc_operands): Add new operands.
1300 (arc_long_opcodes): New global array.
1301 (arc_num_long_opcodes): New global.
1302 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1303
1fe0971e
TS		 13042016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1305
1306 * nds32-asm.h: Add extern "C".
1307 * sh-opc.h: Likewise.
1308
315f180f
GM		 13092016-06-01 Graham Markall <graham.markall@embecosm.com>
1310
1311 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1312 0,b,limm to the rflt instruction.
1313
a2b5fccc
TS		 13142016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1315
1316 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1317 constant.
1318
0cbd0046
L		 13192016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1320
1321 PR gas/20145
1322 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1323 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1324 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1325 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1326 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1327 * i386-init.h: Regenerated.
1328
1848e567
L		 13292016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1330
1331 PR gas/20145
1332 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1333 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1334 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1335 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1336 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1337 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1338 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1339 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1340 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1341 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1342 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1343 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1344 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1345 CpuRegMask for AVX512.
1346 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1347 and CpuRegMask.
1348 (set_bitfield_from_cpu_flag_init): New function.
1349 (set_bitfield): Remove const on f. Call
1350 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1351 * i386-opc.h (CpuRegMMX): New.
1352 (CpuRegXMM): Likewise.
1353 (CpuRegYMM): Likewise.
1354 (CpuRegZMM): Likewise.
1355 (CpuRegMask): Likewise.
1356 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1357 and cpuregmask.
1358 * i386-init.h: Regenerated.
1359 * i386-tbl.h: Likewise.
1360
e92bae62
L		 13612016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1362
1363 PR gas/20154
1364 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1365 (opcode_modifiers): Add AMD64 and Intel64.
1366 (main): Properly verify CpuMax.
1367 * i386-opc.h (CpuAMD64): Removed.
1368 (CpuIntel64): Likewise.
1369 (CpuMax): Set to CpuNo64.
1370 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1371 (AMD64): New.
1372 (Intel64): Likewise.
1373 (i386_opcode_modifier): Add amd64 and intel64.
1374 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1375 on call and jmp.
1376 * i386-init.h: Regenerated.
1377 * i386-tbl.h: Likewise.
1378
e89c5eaa
L		 13792016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1380
1381 PR gas/20154
1382 * i386-gen.c (main): Fail if CpuMax is incorrect.
1383 * i386-opc.h (CpuMax): Set to CpuIntel64.
1384 * i386-tbl.h: Regenerated.
1385
77d66e7b
NC		 13862016-05-27 Nick Clifton <nickc@redhat.com>
1387
1388 PR target/20150
1389 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1390 (msp430dis_opcode_unsigned): New function.
1391 (msp430dis_opcode_signed): New function.
1392 (msp430_singleoperand): Use the new opcode reading functions.
1393 Only disassenmble bytes if they were successfully read.
1394 (msp430_doubleoperand): Likewise.
1395 (msp430_branchinstr): Likewise.
1396 (msp430x_callx_instr): Likewise.
1397 (print_insn_msp430): Check that it is safe to read bytes before
1398 attempting disassembly. Use the new opcode reading functions.
1399
19dfcc89
PB		 14002016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1401
1402 * ppc-opc.c (CY): New define. Document it.
1403 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1404
f3ad7637
L		 14052016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1406
1407 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1408 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1409 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1410 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1411 CPU_ANY_AVX_FLAGS.
1412 * i386-init.h: Regenerated.
1413
f1360d58
L		 14142016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1415
1416 PR gas/20141
1417 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1418 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1419 * i386-init.h: Regenerated.
1420
293f5f65
L		 14212016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1422
1423 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1424 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1425 * i386-init.h: Regenerated.
1426
d9eca1df
CZ		 14272016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1428
1429 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1430 information.
1431 (print_insn_arc): Set insn_type information.
1432 * arc-opc.c (C_CC): Add F_CLASS_COND.
1433 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1434 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1435 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1436 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1437 (brne, brne_s, jeq_s, jne_s): Likewise.
1438
87789e08
CZ		 14392016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1440
1441 * arc-tbl.h (neg): New instruction variant.
1442
c810e0b8
CZ		 14432016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1444
1445 * arc-dis.c (find_format, find_format, get_auxreg)
1446 (print_insn_arc): Changed.
1447 * arc-ext.h (INSERT_XOP): Likewise.
1448
3d207518
TS		 14492016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1450
1451 * tic54x-dis.c (sprint_mmr): Adjust.
1452 * tic54x-opc.c: Likewise.
1453
514e58b7
AM		 14542016-05-19 Alan Modra <amodra@gmail.com>
1455
1456 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1457
e43de63c
AM		 14582016-05-19 Alan Modra <amodra@gmail.com>
1459
1460 * ppc-opc.c: Formatting.
1461 (NSISIGNOPT): Define.
1462 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1463
1401d2fe
MR		 14642016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1465
1466 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1467 replacing references to `micromips_ase' throughout.
1468 (_print_insn_mips): Don't use file-level microMIPS annotation to
1469 determine the disassembly mode with the symbol table.
1470
1178da44
PB		 14712016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1472
1473 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1474
8f4f9071
MF		 14752016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1476
1477 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1478 mips64r6.
1479 * mips-opc.c (D34): New macro.
1480 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1481
8bc52696
AF		 14822016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1483
1484 * i386-dis.c (prefix_table): Add RDPID instruction.
1485 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1486 (cpu_flags): Add RDPID bitfield.
1487 * i386-opc.h (enum): Add RDPID element.
1488 (i386_cpu_flags): Add RDPID field.
1489 * i386-opc.tbl: Add RDPID instruction.
1490 * i386-init.h: Regenerate.
1491 * i386-tbl.h: Regenerate.
1492
39d911fc
TP		 14932016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1494
1495 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1496 branch type of a symbol.
1497 (print_insn): Likewise.
1498
16a1fa25
TP		 14992016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1500
1501 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1502 Mainline Security Extensions instructions.
1503 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1504 Extensions instructions.
1505 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1506 instructions.
1507 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1508 special registers.
1509
d751b79e
JM		 15102016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1511
1512 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1513
945e0f82
CZ		 15142016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1515
1516 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1517 (arcExtMap_genOpcode): Likewise.
1518 * arc-opc.c (arg_32bit_rc): Define new variable.
1519 (arg_32bit_u6): Likewise.
1520 (arg_32bit_limm): Likewise.
1521
20f55f38
SN		 15222016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1523
1524 * aarch64-gen.c (VERIFIER): Define.
1525 * aarch64-opc.c (VERIFIER): Define.
1526 (verify_ldpsw): Use static linkage.
1527 * aarch64-opc.h (verify_ldpsw): Remove.
1528 * aarch64-tbl.h: Use VERIFIER for verifiers.
1529
4bd13cde
NC		 15302016-04-28 Nick Clifton <nickc@redhat.com>
1531
1532 PR target/19722
1533 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1534 * aarch64-opc.c (verify_ldpsw): New function.
1535 * aarch64-opc.h (verify_ldpsw): New prototype.
1536 * aarch64-tbl.h: Add initialiser for verifier field.
1537 (LDPSW): Set verifier to verify_ldpsw.
1538
c0f92bf9
L		 15392016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1540
1541 PR binutils/19983
1542 PR binutils/19984
1543 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1544 smaller than address size.
1545
e6c7cdec
TS		 15462016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1547
1548 * alpha-dis.c: Regenerate.
1549 * crx-dis.c: Likewise.
1550 * disassemble.c: Likewise.
1551 * epiphany-opc.c: Likewise.
1552 * fr30-opc.c: Likewise.
1553 * frv-opc.c: Likewise.
1554 * ip2k-opc.c: Likewise.
1555 * iq2000-opc.c: Likewise.
1556 * lm32-opc.c: Likewise.
1557 * lm32-opinst.c: Likewise.
1558 * m32c-opc.c: Likewise.
1559 * m32r-opc.c: Likewise.
1560 * m32r-opinst.c: Likewise.
1561 * mep-opc.c: Likewise.
1562 * mt-opc.c: Likewise.
1563 * or1k-opc.c: Likewise.
1564 * or1k-opinst.c: Likewise.
1565 * tic80-opc.c: Likewise.
1566 * xc16x-opc.c: Likewise.
1567 * xstormy16-opc.c: Likewise.
1568
537aefaf
AB		 15692016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1570
1571 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1572 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1573 calcsd, and calcxd instructions.
1574 * arc-opc.c (insert_nps_bitop_size): Delete.
1575 (extract_nps_bitop_size): Delete.
1576 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1577 (extract_nps_qcmp_m3): Define.
1578 (extract_nps_qcmp_m2): Define.
1579 (extract_nps_qcmp_m1): Define.
1580 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1581 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1582 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1583 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1584 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1585 NPS_QCMP_M3.
1586
c8f785f2
AB		 15872016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1588
1589 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1590
6fd8e7c2
L		 15912016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1592
1593 * Makefile.in: Regenerated with automake 1.11.6.
1594 * aclocal.m4: Likewise.
1595
4b0c052e
AB		 15962016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1597
1598 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1599 instructions.
1600 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1601 (extract_nps_cmem_uimm16): New function.
1602 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1603
cb040366
AB		 16042016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1605
1606 * arc-dis.c (arc_insn_length): New function.
1607 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1608 (find_format): Change insnLen parameter to unsigned.
1609
accc0180
NC		 16102016-04-13 Nick Clifton <nickc@redhat.com>
1611
1612 PR target/19937
1613 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1614 the LD.B and LD.BU instructions.
1615
f36e33da
CZ		 16162016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1617
1618 * arc-dis.c (find_format): Check for extension flags.
1619 (print_flags): New function.
1620 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1621 .extAuxRegister.
1622 * arc-ext.c (arcExtMap_coreRegName): Use
1623 LAST_EXTENSION_CORE_REGISTER.
1624 (arcExtMap_coreReadWrite): Likewise.
1625 (dump_ARC_extmap): Update printing.
1626 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1627 (arc_aux_regs): Add cpu field.
1628 * arc-regs.h: Add cpu field, lower case name aux registers.
1629
1c2e355e
CZ		 16302016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1631
1632 * arc-tbl.h: Add rtsc, sleep with no arguments.
1633
b99747ae
CZ		 16342016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1635
1636 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1637 Initialize.
1638 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1639 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1640 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1641 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1642 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1643 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1644 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1645 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1646 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1647 (arc_opcode arc_opcodes): Null terminate the array.
1648 (arc_num_opcodes): Remove.
1649 * arc-ext.h (INSERT_XOP): Define.
1650 (extInstruction_t): Likewise.
1651 (arcExtMap_instName): Delete.
1652 (arcExtMap_insn): New function.
1653 (arcExtMap_genOpcode): Likewise.
1654 * arc-ext.c (ExtInstruction): Remove.
1655 (create_map): Zero initialize instruction fields.
1656 (arcExtMap_instName): Remove.
1657 (arcExtMap_insn): New function.
1658 (dump_ARC_extmap): More info while debuging.
1659 (arcExtMap_genOpcode): New function.
1660 * arc-dis.c (find_format): New function.
1661 (print_insn_arc): Use find_format.
1662 (arc_get_disassembler): Enable dump_ARC_extmap only when
1663 debugging.
1664
92708cec
MR		 16652016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1666
1667 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1668 instruction bits out.
1669
a42a4f84
AB		 16702016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1671
1672 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1673 * arc-opc.c (arc_flag_operands): Add new flags.
1674 (arc_flag_classes): Add new classes.
1675
1328504b
AB		 16762016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1677
1678 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1679
820f03ff
AB		 16802016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1681
1682 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1683 encode1, rflt, crc16, and crc32 instructions.
1684 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1685 (arc_flag_classes): Add C_NPS_R.
1686 (insert_nps_bitop_size_2b): New function.
1687 (extract_nps_bitop_size_2b): Likewise.
1688 (insert_nps_bitop_uimm8): Likewise.
1689 (extract_nps_bitop_uimm8): Likewise.
1690 (arc_operands): Add new operand entries.
1691
8ddf6b2a
CZ		 16922016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1693
b99747ae
CZ		 1694 * arc-regs.h: Add a new subclass field. Add double assist
1695 accumulator register values.
1696 * arc-tbl.h: Use DPA subclass to mark the double assist
1697 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1698 * arc-opc.c (RSP): Define instead of SP.
1699 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1700
589a7d88
JW		 17012016-04-05 Jiong Wang <jiong.wang@arm.com>
1702
1703 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1704
0a191de9 17052016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1706
1707 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1708 NPS_R_SRC1.
1709
0a106562
AB		 17102016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1711
1712 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1713 issues. No functional changes.
1714
bd05ac5f
CZ		 17152016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1716
b99747ae
CZ		 1717 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1718 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1719 (RTT): Remove duplicate.
1720 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1721 (PCT_CONFIG*): Remove.
1722 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1723
9885948f
CZ		 17242016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1725
b99747ae 1726 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1727
f2dd8838
CZ		 17282016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1729
b99747ae
CZ		 1730 * arc-tbl.h (invld07): Remove.
1731 * arc-ext-tbl.h: New file.
1732 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1733 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1734
0d2f91fe
JK		 17352016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1736
1737 Fix -Wstack-usage warnings.
1738 * aarch64-dis.c (print_operands): Substitute size.
1739 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1740
a6b71f42
JM		 17412016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1742
1743 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1744 to get a proper diagnostic when an invalid ASR register is used.
1745
9780e045
NC		 17462016-03-22 Nick Clifton <nickc@redhat.com>
1747
1748 * configure: Regenerate.
1749
e23e8ebe
AB		 17502016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1751
1752 * arc-nps400-tbl.h: New file.
1753 * arc-opc.c: Add top level comment.
1754 (insert_nps_3bit_dst): New function.
1755 (extract_nps_3bit_dst): New function.
1756 (insert_nps_3bit_src2): New function.
1757 (extract_nps_3bit_src2): New function.
1758 (insert_nps_bitop_size): New function.
1759 (extract_nps_bitop_size): New function.
1760 (arc_flag_operands): Add nps400 entries.
1761 (arc_flag_classes): Add nps400 entries.
1762 (arc_operands): Add nps400 entries.
1763 (arc_opcodes): Add nps400 include.
1764
1ae8ab47
AB		 17652016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1766
1767 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1768 the new class enum values.
1769
8699fc3e
AB		 17702016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1771
1772 * arc-dis.c (print_insn_arc): Handle nps400.
1773
24740d83
AB		 17742016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1775
1776 * arc-opc.c (BASE): Delete.
1777
8678914f
NC		 17782016-03-18 Nick Clifton <nickc@redhat.com>
1779
1780 PR target/19721
1781 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1782 of MOV insn that aliases an ORR insn.
1783
cc933301
JW		 17842016-03-16 Jiong Wang <jiong.wang@arm.com>
1785
1786 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1787
f86f5863
TS		 17882016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1789
1790 * mcore-opc.h: Add const qualifiers.
1791 * microblaze-opc.h (struct op_code_struct): Likewise.
1792 * sh-opc.h: Likewise.
1793 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1794 (tic4x_print_op): Likewise.
1795
62de1c63
AM		 17962016-03-02 Alan Modra <amodra@gmail.com>
1797
d11698cd 1798 * or1k-desc.h: Regenerate.
62de1c63 1799 * fr30-ibld.c: Regenerate.
c697cf0b 1800 * rl78-decode.c: Regenerate.
62de1c63 1801
020efce5
NC		 18022016-03-01 Nick Clifton <nickc@redhat.com>
1803
1804 PR target/19747
1805 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1806
b0c11777
RL		 18072016-02-24 Renlin Li <renlin.li@arm.com>
1808
1809 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1810 (print_insn_coprocessor): Support fp16 instructions.
1811
3e309328
RL		 18122016-02-24 Renlin Li <renlin.li@arm.com>
1813
1814 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1815 vminnm, vrint(mpna).
1816
8afc7bea
RL		 18172016-02-24 Renlin Li <renlin.li@arm.com>
1818
1819 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1820 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1821
4fd7268a
L		 18222016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1823
1824 * i386-dis.c (print_insn): Parenthesize expression to prevent
1825 truncated addresses.
1826 (OP_J): Likewise.
1827
4670103e
CZ		 18282016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1829 Janek van Oirschot <jvanoirs@synopsys.com>
1830
b99747ae
CZ		 1831 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1832 variable.
4670103e 1833
c1d9289f
NC		 18342016-02-04 Nick Clifton <nickc@redhat.com>
1835
1836 PR target/19561
1837 * msp430-dis.c (print_insn_msp430): Add a special case for
1838 decoding an RRC instruction with the ZC bit set in the extension
1839 word.
1840
a143b004
AB		 18412016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1842
1843 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1844 * epiphany-ibld.c: Regenerate.
1845 * fr30-ibld.c: Regenerate.
1846 * frv-ibld.c: Regenerate.
1847 * ip2k-ibld.c: Regenerate.
1848 * iq2000-ibld.c: Regenerate.
1849 * lm32-ibld.c: Regenerate.
1850 * m32c-ibld.c: Regenerate.
1851 * m32r-ibld.c: Regenerate.
1852 * mep-ibld.c: Regenerate.
1853 * mt-ibld.c: Regenerate.
1854 * or1k-ibld.c: Regenerate.
1855 * xc16x-ibld.c: Regenerate.
1856 * xstormy16-ibld.c: Regenerate.
1857
b89807c6
AB		 18582016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1859
1860 * epiphany-dis.c: Regenerated from latest cpu files.
1861
d8c823c8
MM		 18622016-02-01 Michael McConville <mmcco@mykolab.com>
1863
1864 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1865 test bit.
1866
5bc5ae88
RL		 18672016-01-25 Renlin Li <renlin.li@arm.com>
1868
1869 * arm-dis.c (mapping_symbol_for_insn): New function.
1870 (find_ifthen_state): Call mapping_symbol_for_insn().
1871
0bff6e2d
MW		 18722016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1873
1874 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1875 of MSR UAO immediate operand.
1876
100b4f2e
MR		 18772016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1878
1879 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1880 instruction support.
1881
5c14705f
AM		 18822016-01-17 Alan Modra <amodra@gmail.com>
1883
1884 * configure: Regenerate.
1885
4d82fe66
NC		 18862016-01-14 Nick Clifton <nickc@redhat.com>
1887
1888 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1889 instructions that can support stack pointer operations.
1890 * rl78-decode.c: Regenerate.
1891 * rl78-dis.c: Fix display of stack pointer in MOVW based
1892 instructions.
1893
651657fa
MW		 18942016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1895
1896 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1897 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1898 erxtatus_el1 and erxaddr_el1.
1899
105bde57
MW		 19002016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1901
1902 * arm-dis.c (arm_opcodes): Add "esb".
1903 (thumb_opcodes): Likewise.
1904
afa8d405
PB		 19052016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1906
1907 * ppc-opc.c <xscmpnedp>: Delete.
1908 <xvcmpnedp>: Likewise.
1909 <xvcmpnedp.>: Likewise.
1910 <xvcmpnesp>: Likewise.
1911 <xvcmpnesp.>: Likewise.
1912
83c3256e
AS		 19132016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1914
1915 PR gas/13050
1916 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1917 addition to ISA_A.
1918
6f2750fe
AM		 19192016-01-01 Alan Modra <amodra@gmail.com>
1920
1921 Update year range in copyright notice of all files.
1922
3499769a
AM		 1923For older changes see ChangeLog-2015
1924\f
1925Copyright (C) 2016 Free Software Foundation, Inc.
1926
1927Copying and distribution of this file, with or without modification,
1928are permitted in any medium without royalty provided the copyright
1929notice and this notice are preserved.
1930
1931Local Variables:
1932mode: change-log
1933left-margin: 8
1934fill-column: 74
1935version-control: never
1936End:
GDB Binutils - Deliverables
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