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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9e8c70f9
DM		 12011-09-21 David S. Miller <davem@davemloft.net>
2
3 * sparc-opc.c (sparc_opcodes): Annotate table with HWCAP flag
4 bits. Fix "fchksm16" mnemonic.
5
9bf29d72
DM		 62011-09-08 Mark Fortescue <mark@mtfhpc.demon.co.uk>
7
8 The changes below bring 'mov' and 'ticc' instructions into line
9 with the V8 SPARC Architecture Manual.
10 * sparc-opc.c (sparc_opcodes): Add entry for 'ticc imm + regrs1'.
11 * sparc-opc.c (sparc_opcodes): Add alias entries for
12 'mov regrs2,%asrX'; 'mov regrs2,%y'; 'mov regrs2,%prs';
13 'mov regrs2,%wim' and 'mov regrs2,%tbr'.
14 * sparc-opc.c (sparc_opcodes): Move/Change entries for
15 'mov imm,%asrX'; 'mov imm,%y'; 'mov imm,%prs'; 'mov imm,%wim'
16 and 'mov imm,%tbr'.
17 * sparc-opc.c (sparc_opcodes): Add wr alias entries to match above
18 mov aliases.
19
8dbb9eb3
DM		 20 * sparc-opc.c (sparc_opcodes): Add entry for 'save simm13,regrs1,regrd'
21 This has been reported as being accepted by the Sun assmebler.
22
cdf49201
DM		 232011-09-08 David S. Miller <davem@davemloft.net>
24
25 * sparc-opc.c (pdistn): Destination is integer not float register.
26
96e67898
AS		 272011-09-07 Andreas Schwab <schwab@linux-m68k.org>
28
b2ea1829 29 PR gas/13145
96e67898
AS		 30 * m68k-opc.c: Use "y" in moveml pattern for mcfisa_a.
31
7cf80422
NC		 322011-08-26 Nick Clifton <nickc@redhat.com>
33
34 * po/es.po: Updated Spanish translation.
35
dc15e575
NC		 362011-08-22 Nick Clifton <nickc@redhat.com>
37
38 * Makefile.am (CPUDIR): Redfine to point to top level cpu
39 directory.
40 (stamp-frv): Use CPUDIR.
41 (stamp-iq2000): Likewise.
42 (stamp-lm32): Likewise.
43 (stamp-m32c): Likewise.
44 (stamp-mt): Likewise.
45 (stamp-xc16x): Likewise.
46 * Makefile.in: Regenerate.
47
dec0624d
MR		 482011-08-09 Chao-ying Fu <fu@mips.com>
49 Maciej W. Rozycki <macro@codesourcery.com>
50
51 * mips-dis.c (mips_arch_choices): Enable MCU for "mips32r2"
52 and "mips64r2".
53 (print_insn_args, print_insn_micromips): Handle MCU.
54 * micromips-opc.c (MC): New macro.
55 (micromips_opcodes): Add "aclr", "aset" and "iret".
56 * mips-opc.c (MC): New macro.
57 (mips_builtin_opcodes): Add "aclr", "aset" and "iret".
58
2b0c8b40
MR		 592011-08-09 Maciej W. Rozycki <macro@codesourcery.com>
60
61 * micromips-opc.c (MOD_mb, MOD_mc, MOD_md): Remove macros.
62 (MOD_me, MOD_mf, MOD_mg, MOD_mhi, MOD_mj, MOD_ml): Likewise.
63 (MOD_mm, MOD_mn, MOD_mp, MOD_mq, MOD_sp): Likewise.
64 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf): New macros.
65 (RD_mg, WR_mhi, RD_mj, WR_mj, RD_ml, RD_mmn): Likewise.
66 (RD_mp, WR_mp, RD_mq, RD_sp, WR_sp): Likewise.
67 (WR_s): Update macro.
68 (micromips_opcodes): Update register use flags of: "addiu",
69 "addiupc", "addiur1sp", "addiur2", "addius5", "addiusp", "addu",
70 "and", "andi", "beq", "beqz", "bne", "bnez", "di", "ei", "j",
71 "jalr", "jalrs", "jr", "jraddiusp", "jrc", "lbu", "lhu", "li",
72 "lui", "lw", "lwm", "mfhi", "mflo", "move", "movep", "not",
73 "nor", "or", "ori", "sb", "sh", "sll", "srl", "subu", "sw",
74 "swm" and "xor" instructions.
75
ea783ef3
DM		 762011-08-05 David S. Miller <davem@davemloft.net>
77
78 * sparc-dis.c (v9a_ast_reg_names): Add "cps".
79 (X_RS3): New macro.
80 (print_insn_sparc): Handle '4', '5', and '(' format codes.
81 Accept %asr numbers below 28.
82 * sparc-opc.c (sparc_opcodes): Add entries for HPC and VIS3
83 instructions.
84
3929df09
QN		 852011-08-02 Quentin Neill <quentin.neill@amd.com>
86
87 * i386-dis.c (xop_table): Remove spurious bextr insn.
88
d7921315
L		 892011-08-01 H.J. Lu <hongjiu.lu@intel.com>
90
91 PR ld/13048
92 * i386-dis.c (print_insn): Optimize info->mach check.
93
00f51a41
L		 942011-08-01 H.J. Lu <hongjiu.lu@intel.com>
95
96 PR gas/13046
97 * i386-opc.tbl: Add Disp32S to 64bit call.
98 * i386-tbl.h: Regenerated.
99
df58fc94
RS		 1002011-07-24 Chao-ying Fu <fu@mips.com>
101 Maciej W. Rozycki <macro@codesourcery.com>
102
103 * micromips-opc.c: New file.
104 * mips-dis.c (micromips_to_32_reg_b_map): New array.
105 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
106 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
107 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
108 (micromips_to_32_reg_q_map): Likewise.
109 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
110 (micromips_ase): New variable.
111 (is_micromips): New function.
112 (set_default_mips_dis_options): Handle microMIPS ASE.
113 (print_insn_micromips): New function.
114 (is_compressed_mode_p): Likewise.
115 (_print_insn_mips): Handle microMIPS instructions.
116 * Makefile.am (CFILES): Add micromips-opc.c.
117 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
118 * Makefile.in: Regenerate.
119 * configure: Regenerate.
120
121 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
122 (micromips_to_32_reg_i_map): Likewise.
123 (micromips_to_32_reg_m_map): Likewise.
124 (micromips_to_32_reg_n_map): New macro.
125
bcd530a7
RS		 1262011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
127
128 * mips-opc.c (NODS): New macro.
129 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
130 (DSP_VOLA): Likewise.
131 (mips_builtin_opcodes): Add NODS annotation to "deret" and
132 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
133 place of TRAP for "wait", "waiti" and "yield".
134 * mips16-opc.c (NODS): New macro.
135 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
136 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
137 "restore" and "save".
138
7a9068fe
L		 1392011-07-22 H.J. Lu <hongjiu.lu@intel.com>
140
141 * configure.in: Handle bfd_k1om_arch.
142 * configure: Regenerated.
143
144 * disassemble.c (disassembler): Handle bfd_k1om_arch.
145
146 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
147 bfd_mach_k1om_intel_syntax.
148
149 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
150 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
151 (cpu_flags): Add CpuK1OM.
152
153 * i386-opc.h (CpuK1OM): New.
154 (i386_cpu_flags): Add cpuk1om.
155
156 * i386-init.h: Regenerated.
157 * i386-tbl.h: Likewise.
158
1b93226d
NC		 1592011-07-12 Nick Clifton <nickc@redhat.com>
160
161 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
162 accidental change.
163
5d73b1f1
NC		 1642011-07-01 Nick Clifton <nickc@redhat.com>
165
166 PR binutils/12329
167 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
168 insns using post-increment addressing.
169
182ae480
L		 1702011-06-30 H.J. Lu <hongjiu.lu@intel.com>
171
172 * i386-dis.c (vex_len_table): Update rorxS.
173
4cb0953d
L		 1742011-06-30 H.J. Lu <hongjiu.lu@intel.com>
175
176 AVX Programming Reference (June, 2011)
177 * i386-dis.c (vex_len_table): Correct rorxS.
178
179 * i386-opc.tbl: Correct rorx.
180 * i386-tbl.h: Regenerated.
181
906efcbc
L		 1822011-06-29 H.J. Lu <hongjiu.lu@intel.com>
183
184 * tilegx-opc.c (find_opcode): Replace "index" with "i".
185 * tilepro-opc.c (find_opcode): Likewise.
186
ceb94aa5
RS		 1872011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
188
189 * mips16-opc.c (jalrc, jrc): Move earlier in file.
190
f7002f42
L		 1912011-06-21 H.J. Lu <hongjiu.lu@intel.com>
192
193 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
194 PREFIX_VEX_0F388E.
195
56300268
AS		 1962011-06-17 Andreas Schwab <schwab@redhat.com>
197
198 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
199 (MOSTLYCLEANFILES): ... here.
200 * Makefile.in: Regenerate.
201
bcf2cf9f
AM		 2022011-06-14 Alan Modra <amodra@gmail.com>
203
204 * Makefile.in: Regenerate.
205
aa137e4d
NC		 2062011-06-13 Walter Lee <walt@tilera.com>
207
208 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
209 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
210 * Makefile.in: Regenerate.
211 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
212 * configure: Regenerate.
213 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
214 * po/POTFILES.in: Regenerate.
215 * tilegx-dis.c: New file.
216 * tilegx-opc.c: New file.
217 * tilepro-dis.c: New file.
218 * tilepro-opc.c: New file.
219
6c30d220
L		 2202011-06-10 H.J. Lu <hongjiu.lu@intel.com>
221
222 AVX Programming Reference (June, 2011)
223 * i386-dis.c (XMGatherQ): New.
224 * i386-dis.c (EXxmm_mb): New.
225 (EXxmm_mb): Likewise.
226 (EXxmm_mw): Likewise.
227 (EXxmm_md): Likewise.
228 (EXxmm_mq): Likewise.
229 (EXxmmdw): Likewise.
230 (EXxmmqd): Likewise.
231 (VexGatherQ): Likewise.
232 (MVexVSIBDWpX): Likewise.
233 (MVexVSIBQWpX): Likewise.
234 (xmm_mb_mode): Likewise.
235 (xmm_mw_mode): Likewise.
236 (xmm_md_mode): Likewise.
237 (xmm_mq_mode): Likewise.
238 (xmmdw_mode): Likewise.
239 (xmmqd_mode): Likewise.
240 (ymmxmm_mode): Likewise.
241 (vex_vsib_d_w_dq_mode): Likewise.
242 (vex_vsib_q_w_dq_mode): Likewise.
243 (MOD_VEX_0F385A_PREFIX_2): Likewise.
244 (MOD_VEX_0F388C_PREFIX_2): Likewise.
245 (MOD_VEX_0F388E_PREFIX_2): Likewise.
246 (PREFIX_0F3882): Likewise.
247 (PREFIX_VEX_0F3816): Likewise.
248 (PREFIX_VEX_0F3836): Likewise.
249 (PREFIX_VEX_0F3845): Likewise.
250 (PREFIX_VEX_0F3846): Likewise.
251 (PREFIX_VEX_0F3847): Likewise.
252 (PREFIX_VEX_0F3858): Likewise.
253 (PREFIX_VEX_0F3859): Likewise.
254 (PREFIX_VEX_0F385A): Likewise.
255 (PREFIX_VEX_0F3878): Likewise.
256 (PREFIX_VEX_0F3879): Likewise.
257 (PREFIX_VEX_0F388C): Likewise.
258 (PREFIX_VEX_0F388E): Likewise.
259 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
260 (PREFIX_VEX_0F38F5): Likewise.
261 (PREFIX_VEX_0F38F6): Likewise.
262 (PREFIX_VEX_0F3A00): Likewise.
263 (PREFIX_VEX_0F3A01): Likewise.
264 (PREFIX_VEX_0F3A02): Likewise.
265 (PREFIX_VEX_0F3A38): Likewise.
266 (PREFIX_VEX_0F3A39): Likewise.
267 (PREFIX_VEX_0F3A46): Likewise.
268 (PREFIX_VEX_0F3AF0): Likewise.
269 (VEX_LEN_0F3816_P_2): Likewise.
270 (VEX_LEN_0F3819_P_2): Likewise.
271 (VEX_LEN_0F3836_P_2): Likewise.
272 (VEX_LEN_0F385A_P_2_M_0): Likewise.
273 (VEX_LEN_0F38F5_P_0): Likewise.
274 (VEX_LEN_0F38F5_P_1): Likewise.
275 (VEX_LEN_0F38F5_P_3): Likewise.
276 (VEX_LEN_0F38F6_P_3): Likewise.
277 (VEX_LEN_0F38F7_P_1): Likewise.
278 (VEX_LEN_0F38F7_P_2): Likewise.
279 (VEX_LEN_0F38F7_P_3): Likewise.
280 (VEX_LEN_0F3A00_P_2): Likewise.
281 (VEX_LEN_0F3A01_P_2): Likewise.
282 (VEX_LEN_0F3A38_P_2): Likewise.
283 (VEX_LEN_0F3A39_P_2): Likewise.
284 (VEX_LEN_0F3A46_P_2): Likewise.
285 (VEX_LEN_0F3AF0_P_3): Likewise.
286 (VEX_W_0F3816_P_2): Likewise.
287 (VEX_W_0F3818_P_2): Likewise.
288 (VEX_W_0F3819_P_2): Likewise.
289 (VEX_W_0F3836_P_2): Likewise.
290 (VEX_W_0F3846_P_2): Likewise.
291 (VEX_W_0F3858_P_2): Likewise.
292 (VEX_W_0F3859_P_2): Likewise.
293 (VEX_W_0F385A_P_2_M_0): Likewise.
294 (VEX_W_0F3878_P_2): Likewise.
295 (VEX_W_0F3879_P_2): Likewise.
296 (VEX_W_0F3A00_P_2): Likewise.
297 (VEX_W_0F3A01_P_2): Likewise.
298 (VEX_W_0F3A02_P_2): Likewise.
299 (VEX_W_0F3A38_P_2): Likewise.
300 (VEX_W_0F3A39_P_2): Likewise.
301 (VEX_W_0F3A46_P_2): Likewise.
302 (MOD_VEX_0F3818_PREFIX_2): Removed.
303 (MOD_VEX_0F3819_PREFIX_2): Likewise.
304 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
305 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
306 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
307 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
308 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
309 (VEX_LEN_0F3A0E_P_2): Likewise.
310 (VEX_LEN_0F3A0F_P_2): Likewise.
311 (VEX_LEN_0F3A42_P_2): Likewise.
312 (VEX_LEN_0F3A4C_P_2): Likewise.
313 (VEX_W_0F3818_P_2_M_0): Likewise.
314 (VEX_W_0F3819_P_2_M_0): Likewise.
315 (prefix_table): Updated.
316 (three_byte_table): Likewise.
317 (vex_table): Likewise.
318 (vex_len_table): Likewise.
319 (vex_w_table): Likewise.
320 (mod_table): Likewise.
321 (putop): Handle "LW".
322 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
323 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
324 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
325 (OP_EX): Likewise.
326 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
327 vex_vsib_q_w_dq_mode.
328 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
329 (OP_VEX): Likewise.
330
331 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
332 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
333 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
334 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
335 (opcode_modifiers): Add VecSIB.
336
337 * i386-opc.h (CpuAVX2): New.
338 (CpuBMI2): Likewise.
339 (CpuLZCNT): Likewise.
340 (CpuINVPCID): Likewise.
341 (VecSIB128): Likewise.
342 (VecSIB256): Likewise.
343 (VecSIB): Likewise.
344 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
345 (i386_opcode_modifier): Add vecsib.
346
347 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
348 * i386-init.h: Regenerated.
349 * i386-tbl.h: Likewise.
350
d535accd
QN		 3512011-06-03 Quentin Neill <quentin.neill@amd.com>
352
353 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
354 * i386-init.h: Regenerated.
355
f8b960bc
NC		 3562011-06-03 Nick Clifton <nickc@redhat.com>
357
358 PR binutils/12752
359 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
360 computing address offsets.
361 (print_arm_address): Likewise.
362 (print_insn_arm): Likewise.
363 (print_insn_thumb16): Likewise.
364 (print_insn_thumb32): Likewise.
365
26d97720
NS		 3662011-06-02 Jie Zhang <jie@codesourcery.com>
367 Nathan Sidwell <nathan@codesourcery.com>
368 Maciej Rozycki <macro@codesourcery.com>
369
370 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
371 as address offset.
372 (print_arm_address): Likewise. Elide positive #0 appropriately.
373 (print_insn_arm): Likewise.
374
f8b960bc
NC		 3752011-06-02 Nick Clifton <nickc@redhat.com>
376
377 PR gas/12752
378 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
379 passed to print_address_func.
380
cc643b88
NC		 3812011-06-02 Nick Clifton <nickc@redhat.com>
382
383 * arm-dis.c: Fix spelling mistakes.
384 * op/opcodes.pot: Regenerate.
385
c8fa16ed
AK		 3862011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
387
388 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
389 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
390 * s390-opc.txt: Fix cxr instruction type.
391
5e4b319c
AK		 3922011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
393
394 * s390-opc.c: Add new instruction types marking register pair
395 operands.
396 * s390-opc.txt: Match instructions having register pair operands
397 to the new instruction types.
398
fda544a2
NC		 3992011-05-19 Nick Clifton <nickc@redhat.com>
400
401 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
402 operands.
403
4cab4add
QN		 4042011-05-10 Quentin Neill <quentin.neill@amd.com>
405
406 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
407 * i386-init.h: Regenerated.
408
b4e7b885
NC		 4092011-04-27 Nick Clifton <nickc@redhat.com>
410
411 * po/da.po: Updated Danish translation.
412
2f7f7710
AM		 4132011-04-26 Anton Blanchard <anton@samba.org>
414
415 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
416
9887672f
DD		 4172011-04-21 DJ Delorie <dj@redhat.com>
418
419 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
420 * rx-decode.c: Regenerate.
421
3251b375
L		 4222011-04-20 H.J. Lu <hongjiu.lu@intel.com>
423
424 * i386-init.h: Regenerated.
425
b13a3ca6
QN		 4262011-04-19 Quentin Neill <quentin.neill@amd.com>
427
428 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
429 from bdver1 flags.
430
7d063384
NC		 4312011-04-13 Nick Clifton <nickc@redhat.com>
432
433 * v850-dis.c (disassemble): Always print a closing square brace if
434 an opening square brace was printed.
435
32a94698
NC		 4362011-04-12 Nick Clifton <nickc@redhat.com>
437
438 PR binutils/12534
439 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
440 patterns.
441 (print_insn_thumb32): Handle %L.
442
d2cd1205
JB		 4432011-04-11 Julian Brown <julian@codesourcery.com>
444
445 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
446 (print_insn_thumb32): Add APSR bitmask support.
447
1fbaefec
PB		 4482011-04-07 Paul Carroll<pcarroll@codesourcery.com>
449
450 * arm-dis.c (print_insn): init vars moved into private_data structure.
451
67171547
MF		 4522011-03-24 Mike Frysinger <vapier@gentoo.org>
453
454 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
455
8cc66334
EW		 4562011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
457
458 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
459 post-increment to support LPM Z+ instruction. Add support for 'E'
460 constraint for DES instruction.
461 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
462
34e77a92
RS		 4632011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
464
465 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
466
35fc36a8
RS		 4672011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
468
469 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
470 Use branch types instead.
471 (print_insn): Likewise.
472
0067d8fc
MR		 4732011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
474
475 * mips-opc.c (mips_builtin_opcodes): Correct register use
476 annotation of "alnv.ps".
477
3eebd5eb
MR		 4782011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
479
480 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
481
500cccad
MF		 4822011-02-22 Mike Frysinger <vapier@gentoo.org>
483
484 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
485
f5caf9f4
MF		 4862011-02-22 Mike Frysinger <vapier@gentoo.org>
487
488 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
489
e5bc4265
MF		 4902011-02-19 Mike Frysinger <vapier@gentoo.org>
491
492 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
493 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
494 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
495 exception, end_of_registers, msize, memory, bfd_mach.
496 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
497 LB0REG, LC1REG, LT1REG, LB1REG): Delete
498 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
499 (get_allreg): Change to new defines. Fallback to abort().
500
602427c4
MF		 5012011-02-14 Mike Frysinger <vapier@gentoo.org>
502
503 * bfin-dis.c: Add whitespace/parenthesis where needed.
504
298c1ec2
MF		 5052011-02-14 Mike Frysinger <vapier@gentoo.org>
506
507 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
508 than 7.
509
822ce8ee
RW		 5102011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
511
512 * configure: Regenerate.
513
13c02f06
MF		 5142011-02-13 Mike Frysinger <vapier@gentoo.org>
515
516 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
517
4db66394
MF		 5182011-02-13 Mike Frysinger <vapier@gentoo.org>
519
520 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
521 dregs only when P is set, and dregs_lo otherwise.
522
36f44611
MF		 5232011-02-13 Mike Frysinger <vapier@gentoo.org>
524
525 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
526
9805c0a5
MF		 5272011-02-12 Mike Frysinger <vapier@gentoo.org>
528
529 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
530
43a6aa65
MF		 5312011-02-12 Mike Frysinger <vapier@gentoo.org>
532
533 * bfin-dis.c (machine_registers): Delete REG_GP.
534 (reg_names): Delete "GP".
535 (decode_allregs): Change REG_GP to REG_LASTREG.
536
26bb3ddd
MF		 5372011-02-12 Mike Frysinger <vapier@gentoo.org>
538
89c0d58c
MR		 539 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
540 M_IH, M_IU): Delete.
26bb3ddd 541
69b8ea4a
MF		 5422011-02-11 Mike Frysinger <vapier@gentoo.org>
543
544 * bfin-dis.c (reg_names): Add const.
545 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
546 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
547 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
548 decode_counters, decode_allregs): Likewise.
549
42d5f9c6
MS		 5502011-02-09 Michael Snyder <msnyder@vmware.com>
551
56300268 552 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 553 truncated addresses.
554 (print_insn): Fix indentation off-by-one.
555
4be0c941
NC		 5562011-02-01 Nick Clifton <nickc@redhat.com>
557
558 * po/da.po: Updated Danish translation.
559
6b069ee7
AM		 5602011-01-21 Dave Murphy <davem@devkitpro.org>
561
562 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
563
e3949f17
L		 5642011-01-18 H.J. Lu <hongjiu.lu@intel.com>
565
566 * i386-dis.c (sIbT): New.
567 (b_T_mode): Likewise.
568 (dis386): Replace sIb with sIbT on "pushT".
569 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
570 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
571
752573b2
JK		 5722011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
573
574 * i386-init.h: Regenerated.
575 * i386-tbl.h: Regenerated
576
2a2a0f38
QN		 5772011-01-17 Quentin Neill <quentin.neill@amd.com>
578
579 * i386-dis.c (REG_XOP_TBM_01): New.
580 (REG_XOP_TBM_02): New.
581 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
582 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
583 entries, and add bextr instruction.
584
585 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
586 (cpu_flags): Add CpuTBM.
587
588 * i386-opc.h (CpuTBM) New.
589 (i386_cpu_flags): Add bit cputbm.
590
591 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
592 blcs, blsfill, blsic, t1mskc, and tzmsk.
593
90d6ff62
DD		 5942011-01-12 DJ Delorie <dj@redhat.com>
595
596 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
597
c95354ed
MX		 5982011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
599
600 * mips-dis.c (print_insn_args): Adjust the value to print the real
601 offset for "+c" argument.
602
f7465604
NC		 6032011-01-10 Nick Clifton <nickc@redhat.com>
604
605 * po/da.po: Updated Danish translation.
606
639e30d2
NS		 6072011-01-05 Nathan Sidwell <nathan@codesourcery.com>
608
609 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
610
f12dc422
L		 6112011-01-04 H.J. Lu <hongjiu.lu@intel.com>
612
613 * i386-dis.c (REG_VEX_38F3): New.
614 (PREFIX_0FBC): Likewise.
615 (PREFIX_VEX_38F2): Likewise.
616 (PREFIX_VEX_38F3_REG_1): Likewise.
617 (PREFIX_VEX_38F3_REG_2): Likewise.
618 (PREFIX_VEX_38F3_REG_3): Likewise.
619 (PREFIX_VEX_38F7): Likewise.
620 (VEX_LEN_38F2_P_0): Likewise.
621 (VEX_LEN_38F3_R_1_P_0): Likewise.
622 (VEX_LEN_38F3_R_2_P_0): Likewise.
623 (VEX_LEN_38F3_R_3_P_0): Likewise.
624 (VEX_LEN_38F7_P_0): Likewise.
625 (dis386_twobyte): Use PREFIX_0FBC.
626 (reg_table): Add REG_VEX_38F3.
627 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
628 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
629 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
630 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
631 PREFIX_VEX_38F7.
632 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
633 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
634 VEX_LEN_38F7_P_0.
635
636 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
637 (cpu_flags): Add CpuBMI.
638
639 * i386-opc.h (CpuBMI): New.
640 (i386_cpu_flags): Add cpubmi.
641
642 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
643 * i386-init.h: Regenerated.
644 * i386-tbl.h: Likewise.
645
cb21baef
L		 6462011-01-04 H.J. Lu <hongjiu.lu@intel.com>
647
648 * i386-dis.c (VexGdq): New.
649 (OP_VEX): Handle dq_mode.
650
0db46eb4
L		 6512011-01-01 H.J. Lu <hongjiu.lu@intel.com>
652
653 * i386-gen.c (process_copyright): Update copyright to 2011.
654
9e9e0820 655For older changes see ChangeLog-2010
252b5132
RH		 656\f
657Local Variables:
2f6d2f85
NC		 658mode: change-log
659left-margin: 8
660fill-column: 74
252b5132
RH		 661version-control: never
662End:
GDB Binutils - Deliverables
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