Add new port: crx-elf
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
2
3 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
4 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
5 (crx-dis.lo): New target.
6 (crx-opc.lo): Likewise.
7 * Makefile.in: Regenerate.
8 * configure.in: Handle bfd_crx_arch.
9 * configure: Regenerate.
10 * crx-dis.c: New file.
11 * crx-opc.c: New file.
12 * disassemble.c (ARCH_crx): Define.
13 (disassembler): Handle ARCH_crx.
14
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152004-06-29 James E Wilson <wilson@specifixinc.com>
16
17 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
18 * ia64-asmtab.c: Regnerate.
19
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202004-06-28 Alan Modra <amodra@bigpond.net.au>
21
22 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
23 (extract_fxm): Don't test dialect.
24 (XFXFXM_MASK): Include the power4 bit.
25 (XFXM): Add p4 param.
26 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
27
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282004-06-27 Alexandre Oliva <aoliva@redhat.com>
29
30 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
31 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
32
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332004-06-26 Alan Modra <amodra@bigpond.net.au>
34
35 * ppc-opc.c (BH, XLBH_MASK): Define.
36 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
37
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382004-06-24 Alan Modra <amodra@bigpond.net.au>
39
40 * i386-dis.c (x_mode): Comment.
41 (two_source_ops): File scope.
42 (float_mem): Correct fisttpll and fistpll.
43 (float_mem_mode): New table.
44 (dofloat): Use it.
45 (OP_E): Correct intel mode PTR output.
46 (ptr_reg): Use open_char and close_char.
47 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
48 operands. Set two_source_ops.
49
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502004-06-15 Alan Modra <amodra@bigpond.net.au>
51
52 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
53 instead of _raw_size.
54
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552004-06-08 Jakub Jelinek <jakub@redhat.com>
56
57 * ia64-gen.c (in_iclass): Handle more postinc st
58 and ld variants.
59 * ia64-asmtab.c: Rebuilt.
60
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612004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
62
63 * s390-opc.txt: Correct architecture mask for some opcodes.
64 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
65 in the esa mode as well.
66
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672004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
68
69 * sh-dis.c (target_arch): Make unsigned.
70 (print_insn_sh): Replace (most of) switch with a call to
71 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
72 * sh-opc.h: Redefine architecture flags values.
73 Add sh3-nommu architecture.
74 Reorganise <arch>_up macros so they make more visual sense.
75 (SH_MERGE_ARCH_SET): Define new macro.
76 (SH_VALID_BASE_ARCH_SET): Likewise.
77 (SH_VALID_MMU_ARCH_SET): Likewise.
78 (SH_VALID_CO_ARCH_SET): Likewise.
79 (SH_VALID_ARCH_SET): Likewise.
80 (SH_MERGE_ARCH_SET_VALID): Likewise.
81 (SH_ARCH_SET_HAS_FPU): Likewise.
82 (SH_ARCH_SET_HAS_DSP): Likewise.
83 (SH_ARCH_UNKNOWN_ARCH): Likewise.
84 (sh_get_arch_from_bfd_mach): Add prototype.
85 (sh_get_arch_up_from_bfd_mach): Likewise.
86 (sh_get_bfd_mach_from_arch_set): Likewise.
87 (sh_merge_bfd_arc): Likewise.
88
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892004-05-24 Peter Barada <peter@the-baradas.com>
90
91 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
92 into new match_insn_m68k function. Loop over canidate
93 matches and select first that completely matches.
94 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
95 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
96 to verify addressing for MAC/EMAC.
97 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
98 reigster halves since 'fpu' and 'spl' look misleading.
99 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
100 * m68k-opc.c: Rearragne mac/emac cases to use longest for
101 first, tighten up match masks.
102 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
103 'size' from special case code in print_insn_m68k to
104 determine decode size of insns.
105
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1062004-05-19 Alan Modra <amodra@bigpond.net.au>
107
108 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
109 well as when -mpower4.
110
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1112004-05-13 Nick Clifton <nickc@redhat.com>
112
113 * po/fr.po: Updated French translation.
114
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1152004-05-05 Peter Barada <peter@the-baradas.com>
116
117 * m68k-dis.c(print_insn_m68k): Add new chips, use core
118 variants in arch_mask. Only set m68881/68851 for 68k chips.
119 * m68k-op.c: Switch from ColdFire chips to core variants.
120
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1212004-05-05 Alan Modra <amodra@bigpond.net.au>
122
a30e9cc4 123 PR 147.
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124 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
125
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1262004-04-29 Ben Elliston <bje@au.ibm.com>
127
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128 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
129 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 130
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1312004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
132
133 * sh-dis.c (print_insn_sh): Print the value in constant pool
134 as a symbol if it looks like a symbol.
135
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1362004-04-22 Peter Barada <peter@the-baradas.com>
137
138 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
139 appropriate ColdFire architectures.
140 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
141 mask addressing.
142 Add EMAC instructions, fix MAC instructions. Remove
143 macmw/macml/msacmw/msacml instructions since mask addressing now
144 supported.
145
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1462004-04-20 Jakub Jelinek <jakub@redhat.com>
147
148 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
149 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
150 suffix. Use fmov*x macros, create all 3 fpsize variants in one
151 macro. Adjust all users.
152
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1532004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
154
155 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
156 separately.
157
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1582004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
159
160 * m32r-asm.c: Regenerate.
161
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1622004-03-29 Stan Shebs <shebs@apple.com>
163
164 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
165 used.
166
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1672004-03-19 Alan Modra <amodra@bigpond.net.au>
168
169 * aclocal.m4: Regenerate.
170 * config.in: Regenerate.
171 * configure: Regenerate.
172 * po/POTFILES.in: Regenerate.
173 * po/opcodes.pot: Regenerate.
174
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1752004-03-16 Alan Modra <amodra@bigpond.net.au>
176
177 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
178 PPC_OPERANDS_GPR_0.
179 * ppc-opc.c (RA0): Define.
180 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
181 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 182 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 183
2dc111b3 1842004-03-15 Aldy Hernandez <aldyh@redhat.com>
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185
186 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 187
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1882004-03-15 Alan Modra <amodra@bigpond.net.au>
189
190 * sparc-dis.c (print_insn_sparc): Update getword prototype.
191
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1922004-03-12 Michal Ludvig <mludvig@suse.cz>
193
194 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 195 (grps): Delete GRPPLOCK entry.
7ffdda93 196
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1972004-03-12 Alan Modra <amodra@bigpond.net.au>
198
199 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
200 (M, Mp): Use OP_M.
201 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
202 (GRPPADLCK): Define.
203 (dis386): Use NOP_Fixup on "nop".
204 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
205 (twobyte_has_modrm): Set for 0xa7.
206 (padlock_table): Delete. Move to..
207 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
208 and clflush.
209 (print_insn): Revert PADLOCK_SPECIAL code.
210 (OP_E): Delete sfence, lfence, mfence checks.
211
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2122004-03-12 Jakub Jelinek <jakub@redhat.com>
213
214 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
215 (INVLPG_Fixup): New function.
216 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
217
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2182004-03-12 Michal Ludvig <mludvig@suse.cz>
219
220 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
221 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
222 (padlock_table): New struct with PadLock instructions.
223 (print_insn): Handle PADLOCK_SPECIAL.
224
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2252004-03-12 Alan Modra <amodra@bigpond.net.au>
226
227 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
228 (OP_E): Twiddle clflush to sfence here.
229
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2302004-03-08 Nick Clifton <nickc@redhat.com>
231
232 * po/de.po: Updated German translation.
233
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2342003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
235
236 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
237 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
238 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
239 accordingly.
240
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2412004-03-01 Richard Sandiford <rsandifo@redhat.com>
242
243 * frv-asm.c: Regenerate.
244 * frv-desc.c: Regenerate.
245 * frv-desc.h: Regenerate.
246 * frv-dis.c: Regenerate.
247 * frv-ibld.c: Regenerate.
248 * frv-opc.c: Regenerate.
249 * frv-opc.h: Regenerate.
250
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2512004-03-01 Richard Sandiford <rsandifo@redhat.com>
252
253 * frv-desc.c, frv-opc.c: Regenerate.
254
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2552004-03-01 Richard Sandiford <rsandifo@redhat.com>
256
257 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
258
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2592004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
260
261 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
262 Also correct mistake in the comment.
263
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2642004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
265
266 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
267 ensure that double registers have even numbers.
268 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
269 that reserved instruction 0xfffd does not decode the same
270 as 0xfdfd (ftrv).
271 * sh-opc.h: Add REG_N_D nibble type and use it whereever
272 REG_N refers to a double register.
273 Add REG_N_B01 nibble type and use it instead of REG_NM
274 in ftrv.
275 Adjust the bit patterns in a few comments.
276
e5d2b64f 2772004-02-25 Aldy Hernandez <aldyh@redhat.com>
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278
279 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 280
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2812004-02-20 Aldy Hernandez <aldyh@redhat.com>
282
283 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
284
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2852004-02-20 Aldy Hernandez <aldyh@redhat.com>
286
287 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
288
f0b26da6 2892004-02-20 Aldy Hernandez <aldyh@redhat.com>
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290
291 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
292 mtivor32, mtivor33, mtivor34.
f0b26da6 293
23d59c56 2942004-02-19 Aldy Hernandez <aldyh@redhat.com>
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295
296 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 297
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2982004-02-10 Petko Manolov <petkan@nucleusys.com>
299
300 * arm-opc.h Maverick accumulator register opcode fixes.
301
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3022004-02-13 Ben Elliston <bje@wasabisystems.com>
303
304 * m32r-dis.c: Regenerate.
305
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3062004-01-27 Michael Snyder <msnyder@redhat.com>
307
308 * sh-opc.h (sh_table): "fsrra", not "fssra".
309
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3102004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
311
312 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
313 contraints.
314
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3152004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
316
317 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
318
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3192004-01-19 Alan Modra <amodra@bigpond.net.au>
320
321 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
322 1. Don't print scale factor on AT&T mode when index missing.
323
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3242004-01-16 Alexandre Oliva <aoliva@redhat.com>
325
326 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
327 when loaded into XR registers.
328
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3292004-01-14 Richard Sandiford <rsandifo@redhat.com>
330
331 * frv-desc.h: Regenerate.
332 * frv-desc.c: Regenerate.
333 * frv-opc.c: Regenerate.
334
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3352004-01-13 Michael Snyder <msnyder@redhat.com>
336
337 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
338
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3392004-01-09 Paul Brook <paul@codesourcery.com>
340
341 * arm-opc.h (arm_opcodes): Move generic mcrr after known
342 specific opcodes.
343
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3442004-01-07 Daniel Jacobowitz <drow@mvista.com>
345
346 * Makefile.am (libopcodes_la_DEPENDENCIES)
347 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
348 comment about the problem.
349 * Makefile.in: Regenerate.
350
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3512004-01-06 Alexandre Oliva <aoliva@redhat.com>
352
353 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
354 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
355 cut&paste errors in shifting/truncating numerical operands.
356 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
357 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
358 (parse_uslo16): Likewise.
359 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
360 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
361 (parse_s12): Likewise.
362 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
363 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
364 (parse_uslo16): Likewise.
365 (parse_uhi16): Parse gothi and gotfuncdeschi.
366 (parse_d12): Parse got12 and gotfuncdesc12.
367 (parse_s12): Likewise.
368
3ab48931
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3692004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
370
371 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
372 instruction which looks similar to an 'rla' instruction.
a0bd404e 373
c9e214e5 374For older changes see ChangeLog-0203
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375\f
376Local Variables:
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377mode: change-log
378left-margin: 8
379fill-column: 74
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380version-control: never
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