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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2033b4b9
L		 12005-01-12 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
4
0bcb06d2
AS		 52005-01-10 Andreas Schwab <schwab@suse.de>
6
7 * disassemble.c (disassemble_init_for_target) <case
8 bfd_arch_ia64>: Set skip_zeroes to 16.
9 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
10
47add74d
TL		 112004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
12
13 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
14
246f4c05
SS		 152004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
16
17 * avr-dis.c: Prettyprint. Added printing of symbol names in all
18 memory references. Convert avr_operand() to C90 formatting.
19
0e1200e5
TL		 202004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
21
22 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
23
89a649f7
TL		 242004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
25
26 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
27 (no_op_insn): Initialize array with instructions that have no
28 operands.
29 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
30
6255809c
RE		 312004-11-29 Richard Earnshaw <rearnsha@arm.com>
32
33 * arm-dis.c: Correct top-level comment.
34
2fbad815
RE		 352004-11-27 Richard Earnshaw <rearnsha@arm.com>
36
37 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
38 architecuture defining the insn.
39 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 40 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
41 field.
2fbad815
RE		 42 Also include opcode/arm.h.
43 * Makefile.am (arm-dis.lo): Update dependency list.
44 * Makefile.in: Regenerate.
45
d81acc42
NC		 462004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
47
48 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
49 reflect the change to the short immediate syntax.
50
ca4f2377
AM		 512004-11-19 Alan Modra <amodra@bigpond.net.au>
52
5da8bf1b
AM		 53 * or32-opc.c (debug): Warning fix.
54 * po/POTFILES.in: Regenerate.
55
ca4f2377
AM		 56 * maxq-dis.c: Formatting.
57 (print_insn): Warning fix.
58
b7693d02
DJ		 592004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
60
61 * arm-dis.c (WORD_ADDRESS): Define.
62 (print_insn): Use it. Correct big-endian end-of-section handling.
63
300dac7e
NC		 642004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
65 Vineet Sharma <vineets@noida.hcltech.com>
66
67 * maxq-dis.c: New file.
68 * disassemble.c (ARCH_maxq): Define.
69 (disassembler): Add 'print_insn_maxq_little' for handling maxq
70 instructions..
71 * configure.in: Add case for bfd_maxq_arch.
72 * configure: Regenerate.
73 * Makefile.am: Add support for maxq-dis.c
74 * Makefile.in: Regenerate.
75 * aclocal.m4: Regenerate.
76
42048ee7
TL		 772004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
78
79 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
80 mode.
81 * crx-dis.c: Likewise.
82
bd21e58e
HPN		 832004-11-04 Hans-Peter Nilsson <hp@axis.com>
84
85 Generally, handle CRISv32.
86 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
87 (struct cris_disasm_data): New type.
88 (format_reg, format_hex, cris_constraint, print_flags)
89 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
90 callers changed.
91 (format_sup_reg, print_insn_crisv32_with_register_prefix)
92 (print_insn_crisv32_without_register_prefix)
93 (print_insn_crisv10_v32_with_register_prefix)
94 (print_insn_crisv10_v32_without_register_prefix)
95 (cris_parse_disassembler_options): New functions.
96 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
97 parameter. All callers changed.
98 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
99 failure.
100 (cris_constraint) <case 'Y', 'U'>: New cases.
101 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
102 for constraint 'n'.
103 (print_with_operands) <case 'Y'>: New case.
104 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
105 <case 'N', 'Y', 'Q'>: New cases.
106 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
107 (print_insn_cris_with_register_prefix)
108 (print_insn_cris_without_register_prefix): Call
109 cris_parse_disassembler_options.
110 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
111 for CRISv32 and the size of immediate operands. New v32-only
112 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
113 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
114 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
115 Change brp to be v3..v10.
116 (cris_support_regs): New vector.
117 (cris_opcodes): Update head comment. New format characters '[',
118 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
119 Add new opcodes for v32 and adjust existing opcodes to accommodate
120 differences to earlier variants.
121 (cris_cond15s): New vector.
122
9306ca4a
JB		 1232004-11-04 Jan Beulich <jbeulich@novell.com>
124
125 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
126 (indirEb): Remove.
127 (Mp): Use f_mode rather than none at all.
128 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
129 replaces what previously was x_mode; x_mode now means 128-bit SSE
130 operands.
131 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
132 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
133 pinsrw's second operand is Edqw.
134 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
135 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
136 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
137 mode when an operand size override is present or always suffixing.
138 More instructions will need to be added to this group.
139 (putop): Handle new macro chars 'C' (short/long suffix selector),
140 'I' (Intel mode override for following macro char), and 'J' (for
141 adding the 'l' prefix to far branches in AT&T mode). When an
142 alternative was specified in the template, honor macro character when
143 specified for Intel mode.
144 (OP_E): Handle new *_mode values. Correct pointer specifications for
145 memory operands. Consolidate output of index register.
146 (OP_G): Handle new *_mode values.
147 (OP_I): Handle const_1_mode.
148 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
149 respective opcode prefix bits have been consumed.
150 (OP_EM, OP_EX): Provide some default handling for generating pointer
151 specifications.
152
f39c96a9
TL		 1532004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
154
155 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
156 COP_INST macro.
157
812337be
TL		 1582004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
159
160 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
161 (getregliststring): Support HI/LO and user registers.
162 * crx-opc.c (crx_instruction): Update data structure according to the
163 rearrangement done in CRX opcode header file.
164 (crx_regtab): Likewise.
165 (crx_optab): Likewise.
166 (crx_instruction): Reorder load/stor instructions, remove unsupported
167 formats.
168 support new Co-Processor instruction 'cpi'.
169
4030fa5a
NC		 1702004-10-27 Nick Clifton <nickc@redhat.com>
171
172 * opcodes/iq2000-asm.c: Regenerate.
173 * opcodes/iq2000-desc.c: Regenerate.
174 * opcodes/iq2000-desc.h: Regenerate.
175 * opcodes/iq2000-dis.c: Regenerate.
176 * opcodes/iq2000-ibld.c: Regenerate.
177 * opcodes/iq2000-opc.c: Regenerate.
178 * opcodes/iq2000-opc.h: Regenerate.
179
fc3d45e8
TL		 1802004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
181
182 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
183 us4, us5 (respectively).
184 Remove unsupported 'popa' instruction.
185 Reverse operands order in store co-processor instructions.
186
3c55da70
AM		 1872004-10-15 Alan Modra <amodra@bigpond.net.au>
188
189 * Makefile.am: Run "make dep-am"
190 * Makefile.in: Regenerate.
191
7fa3d080
BW		 1922004-10-12 Bob Wilson <bob.wilson@acm.org>
193
194 * xtensa-dis.c: Use ISO C90 formatting.
195
e612bb4d
AM		 1962004-10-09 Alan Modra <amodra@bigpond.net.au>
197
198 * ppc-opc.c: Revert 2004-09-09 change.
199
43cd72b9
BW		 2002004-10-07 Bob Wilson <bob.wilson@acm.org>
201
202 * xtensa-dis.c (state_names): Delete.
203 (fetch_data): Use xtensa_isa_maxlength.
204 (print_xtensa_operand): Replace operand parameter with opcode/operand
205 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
206 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
207 instruction bundles. Use xmalloc instead of malloc.
208
bbac1f2a
NC		 2092004-10-07 David Gibson <david@gibson.dropbear.id.au>
210
211 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
212 initializers.
213
48c9f030
NC		 2142004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
215
216 * crx-opc.c (crx_instruction): Support Co-processor insns.
217 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
218 (getregliststring): Change function to use the above enum.
219 (print_arg): Handle CO-Processor insns.
220 (crx_cinvs): Add 'b' option to invalidate the branch-target
221 cache.
222
12c64a4e
AH		 2232004-10-06 Aldy Hernandez <aldyh@redhat.com>
224
225 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
226 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
227 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
228 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
229 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
230
14127cc4
NC		 2312004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
232
233 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
234 rather than add it.
235
0dd132b6
NC		 2362004-09-30 Paul Brook <paul@codesourcery.com>
237
238 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
239 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
240
3f85e526
L		 2412004-09-17 H.J. Lu <hongjiu.lu@intel.com>
242
243 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
244 (CONFIG_STATUS_DEPENDENCIES): New.
245 (Makefile): Removed.
246 (config.status): Likewise.
247 * Makefile.in: Regenerated.
248
8ae85421
AM		 2492004-09-17 Alan Modra <amodra@bigpond.net.au>
250
251 * Makefile.am: Run "make dep-am".
252 * Makefile.in: Regenerate.
253 * aclocal.m4: Regenerate.
254 * configure: Regenerate.
255 * po/POTFILES.in: Regenerate.
256 * po/opcodes.pot: Regenerate.
257
24443139
AS		 2582004-09-11 Andreas Schwab <schwab@suse.de>
259
260 * configure: Rebuild.
261
2a309db0
AM		 2622004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
263
264 * ppc-opc.c (L): Make this field not optional.
265
42851540
NC		 2662004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
267
268 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
269 Fix parameter to 'm[t|f]csr' insns.
270
979273e3
NN		 2712004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
272
273 * configure.in: Autoupdate to autoconf 2.59.
274 * aclocal.m4: Rebuild with aclocal 1.4p6.
275 * configure: Rebuild with autoconf 2.59.
276 * Makefile.in: Rebuild with automake 1.4p6 (picking up
277 bfd changes for autoconf 2.59 on the way).
278 * config.in: Rebuild with autoheader 2.59.
279
ac28a1cb
RS		 2802004-08-27 Richard Sandiford <rsandifo@redhat.com>
281
282 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
283
30d1c836
ML		 2842004-07-30 Michal Ludvig <mludvig@suse.cz>
285
286 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
287 (GRPPADLCK2): New define.
288 (twobyte_has_modrm): True for 0xA6.
289 (grps): GRPPADLCK2 for opcode 0xA6.
290
0b0ac059
AO		 2912004-07-29 Alexandre Oliva <aoliva@redhat.com>
292
293 Introduce SH2a support.
294 * sh-opc.h (arch_sh2a_base): Renumber.
295 (arch_sh2a_nofpu_base): Remove.
296 (arch_sh_base_mask): Adjust.
297 (arch_opann_mask): New.
298 (arch_sh2a, arch_sh2a_nofpu): Adjust.
299 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
300 (sh_table): Adjust whitespace.
301 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
302 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
303 instruction list throughout.
304 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
305 of arch_sh2a in instruction list throughout.
306 (arch_sh2e_up): Accomodate above changes.
307 (arch_sh2_up): Ditto.
308 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
309 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
310 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
311 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
312 * sh-opc.h (arch_sh2a_nofpu): New.
313 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
314 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
315 instruction.
316 2004-01-20 DJ Delorie <dj@redhat.com>
317 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
318 2003-12-29 DJ Delorie <dj@redhat.com>
319 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
320 sh_opcode_info, sh_table): Add sh2a support.
321 (arch_op32): New, to tag 32-bit opcodes.
322 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
323 2003-12-02 Michael Snyder <msnyder@redhat.com>
324 * sh-opc.h (arch_sh2a): Add.
325 * sh-dis.c (arch_sh2a): Handle.
326 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
327
670ec21d
NC		 3282004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
329
330 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
331
ed049af3
NC		 3322004-07-22 Nick Clifton <nickc@redhat.com>
333
334 PR/280
335 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
336 insns - this is done by objdump itself.
337 * h8500-dis.c (print_insn_h8500): Likewise.
338
20f0a1fc
NC		 3392004-07-21 Jan Beulich <jbeulich@novell.com>
340
341 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
342 regardless of address size prefix in effect.
343 (ptr_reg): Size or address registers does not depend on rex64, but
344 on the presence of an address size override.
345 (OP_MMX): Use rex.x only for xmm registers.
346 (OP_EM): Use rex.z only for xmm registers.
347
6f14957b
MR		 3482004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
349
350 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
351 move/branch operations to the bottom so that VR5400 multimedia
352 instructions take precedence in disassembly.
353
1586d91e
MR		 3542004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
355
356 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
357 ISA-specific "break" encoding.
358
982de27a
NC		 3592004-07-13 Elvis Chiang <elvisfb@gmail.com>
360
361 * arm-opc.h: Fix typo in comment.
362
4300ab10
AS		 3632004-07-11 Andreas Schwab <schwab@suse.de>
364
365 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
366
8577e690
AS		 3672004-07-09 Andreas Schwab <schwab@suse.de>
368
369 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
370
1fe1f39c
NC		 3712004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
372
373 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
374 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
375 (crx-dis.lo): New target.
376 (crx-opc.lo): Likewise.
377 * Makefile.in: Regenerate.
378 * configure.in: Handle bfd_crx_arch.
379 * configure: Regenerate.
380 * crx-dis.c: New file.
381 * crx-opc.c: New file.
382 * disassemble.c (ARCH_crx): Define.
383 (disassembler): Handle ARCH_crx.
384
7a33b495
JW		 3852004-06-29 James E Wilson <wilson@specifixinc.com>
386
387 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
388 * ia64-asmtab.c: Regnerate.
389
98e69875
AM		 3902004-06-28 Alan Modra <amodra@bigpond.net.au>
391
392 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
393 (extract_fxm): Don't test dialect.
394 (XFXFXM_MASK): Include the power4 bit.
395 (XFXM): Add p4 param.
396 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
397
a53b85e2
AO		 3982004-06-27 Alexandre Oliva <aoliva@redhat.com>
399
400 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
401 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
402
d0618d1c
AM		 4032004-06-26 Alan Modra <amodra@bigpond.net.au>
404
405 * ppc-opc.c (BH, XLBH_MASK): Define.
406 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
407
1d9f512f
AM		 4082004-06-24 Alan Modra <amodra@bigpond.net.au>
409
410 * i386-dis.c (x_mode): Comment.
411 (two_source_ops): File scope.
412 (float_mem): Correct fisttpll and fistpll.
413 (float_mem_mode): New table.
414 (dofloat): Use it.
415 (OP_E): Correct intel mode PTR output.
416 (ptr_reg): Use open_char and close_char.
417 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
418 operands. Set two_source_ops.
419
52886d70
AM		 4202004-06-15 Alan Modra <amodra@bigpond.net.au>
421
422 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
423 instead of _raw_size.
424
bad9ceea
JJ		 4252004-06-08 Jakub Jelinek <jakub@redhat.com>
426
427 * ia64-gen.c (in_iclass): Handle more postinc st
428 and ld variants.
429 * ia64-asmtab.c: Rebuilt.
430
0451f5df
MS		 4312004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
432
433 * s390-opc.txt: Correct architecture mask for some opcodes.
434 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
435 in the esa mode as well.
436
f6f9408f
JR		 4372004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
438
439 * sh-dis.c (target_arch): Make unsigned.
440 (print_insn_sh): Replace (most of) switch with a call to
441 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
442 * sh-opc.h: Redefine architecture flags values.
443 Add sh3-nommu architecture.
444 Reorganise <arch>_up macros so they make more visual sense.
445 (SH_MERGE_ARCH_SET): Define new macro.
446 (SH_VALID_BASE_ARCH_SET): Likewise.
447 (SH_VALID_MMU_ARCH_SET): Likewise.
448 (SH_VALID_CO_ARCH_SET): Likewise.
449 (SH_VALID_ARCH_SET): Likewise.
450 (SH_MERGE_ARCH_SET_VALID): Likewise.
451 (SH_ARCH_SET_HAS_FPU): Likewise.
452 (SH_ARCH_SET_HAS_DSP): Likewise.
453 (SH_ARCH_UNKNOWN_ARCH): Likewise.
454 (sh_get_arch_from_bfd_mach): Add prototype.
455 (sh_get_arch_up_from_bfd_mach): Likewise.
456 (sh_get_bfd_mach_from_arch_set): Likewise.
457 (sh_merge_bfd_arc): Likewise.
458
be8c092b
NC		 4592004-05-24 Peter Barada <peter@the-baradas.com>
460
461 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
462 into new match_insn_m68k function. Loop over canidate
463 matches and select first that completely matches.
464 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
465 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
466 to verify addressing for MAC/EMAC.
467 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
468 reigster halves since 'fpu' and 'spl' look misleading.
469 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
470 * m68k-opc.c: Rearragne mac/emac cases to use longest for
471 first, tighten up match masks.
472 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
473 'size' from special case code in print_insn_m68k to
474 determine decode size of insns.
475
a30e9cc4
AM		 4762004-05-19 Alan Modra <amodra@bigpond.net.au>
477
478 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
479 well as when -mpower4.
480
9598fbe5
NC		 4812004-05-13 Nick Clifton <nickc@redhat.com>
482
483 * po/fr.po: Updated French translation.
484
6b6e92f4
NC		 4852004-05-05 Peter Barada <peter@the-baradas.com>
486
487 * m68k-dis.c(print_insn_m68k): Add new chips, use core
488 variants in arch_mask. Only set m68881/68851 for 68k chips.
489 * m68k-op.c: Switch from ColdFire chips to core variants.
490
a404d431
AM		 4912004-05-05 Alan Modra <amodra@bigpond.net.au>
492
a30e9cc4 493 PR 147.
a404d431
AM		 494 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
495
f3806e43
BE		 4962004-04-29 Ben Elliston <bje@au.ibm.com>
497
520ceea4
BE		 498 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
499 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 500
1f1799d5
KK		 5012004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
502
503 * sh-dis.c (print_insn_sh): Print the value in constant pool
504 as a symbol if it looks like a symbol.
505
fd99574b
NC		 5062004-04-22 Peter Barada <peter@the-baradas.com>
507
508 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
509 appropriate ColdFire architectures.
510 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
511 mask addressing.
512 Add EMAC instructions, fix MAC instructions. Remove
513 macmw/macml/msacmw/msacml instructions since mask addressing now
514 supported.
515
b4781d44
JJ		 5162004-04-20 Jakub Jelinek <jakub@redhat.com>
517
518 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
519 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
520 suffix. Use fmov*x macros, create all 3 fpsize variants in one
521 macro. Adjust all users.
522
91809fda
NC		 5232004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
524
525 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
526 separately.
527
f4453dfa
NC		 5282004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
529
530 * m32r-asm.c: Regenerate.
531
9b0de91a
SS		 5322004-03-29 Stan Shebs <shebs@apple.com>
533
534 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
535 used.
536
e20c0b3d
AM		 5372004-03-19 Alan Modra <amodra@bigpond.net.au>
538
539 * aclocal.m4: Regenerate.
540 * config.in: Regenerate.
541 * configure: Regenerate.
542 * po/POTFILES.in: Regenerate.
543 * po/opcodes.pot: Regenerate.
544
fdd12ef3
AM		 5452004-03-16 Alan Modra <amodra@bigpond.net.au>
546
547 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
548 PPC_OPERANDS_GPR_0.
549 * ppc-opc.c (RA0): Define.
550 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
551 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 552 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 553
2dc111b3 5542004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 555
556 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 557
7bfeee7b
AM		 5582004-03-15 Alan Modra <amodra@bigpond.net.au>
559
560 * sparc-dis.c (print_insn_sparc): Update getword prototype.
561
7ffdda93
ML		 5622004-03-12 Michal Ludvig <mludvig@suse.cz>
563
564 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 565 (grps): Delete GRPPLOCK entry.
7ffdda93 566
cc0ec051
AM		 5672004-03-12 Alan Modra <amodra@bigpond.net.au>
568
569 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
570 (M, Mp): Use OP_M.
571 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
572 (GRPPADLCK): Define.
573 (dis386): Use NOP_Fixup on "nop".
574 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
575 (twobyte_has_modrm): Set for 0xa7.
576 (padlock_table): Delete. Move to..
577 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
578 and clflush.
579 (print_insn): Revert PADLOCK_SPECIAL code.
580 (OP_E): Delete sfence, lfence, mfence checks.
581
4fd61dcb
JJ		 5822004-03-12 Jakub Jelinek <jakub@redhat.com>
583
584 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
585 (INVLPG_Fixup): New function.
586 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
587
0f10071e
ML		 5882004-03-12 Michal Ludvig <mludvig@suse.cz>
589
590 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
591 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
592 (padlock_table): New struct with PadLock instructions.
593 (print_insn): Handle PADLOCK_SPECIAL.
594
c02908d2
AM		 5952004-03-12 Alan Modra <amodra@bigpond.net.au>
596
597 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
598 (OP_E): Twiddle clflush to sfence here.
599
d5bb7600
NC		 6002004-03-08 Nick Clifton <nickc@redhat.com>
601
602 * po/de.po: Updated German translation.
603
ae51a426
JR		 6042003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
605
606 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
607 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
608 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
609 accordingly.
610
676a64f4
RS		 6112004-03-01 Richard Sandiford <rsandifo@redhat.com>
612
613 * frv-asm.c: Regenerate.
614 * frv-desc.c: Regenerate.
615 * frv-desc.h: Regenerate.
616 * frv-dis.c: Regenerate.
617 * frv-ibld.c: Regenerate.
618 * frv-opc.c: Regenerate.
619 * frv-opc.h: Regenerate.
620
c7a48b9a
RS		 6212004-03-01 Richard Sandiford <rsandifo@redhat.com>
622
623 * frv-desc.c, frv-opc.c: Regenerate.
624
8ae0baa2
RS		 6252004-03-01 Richard Sandiford <rsandifo@redhat.com>
626
627 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
628
ce11586c
JR		 6292004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
630
631 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
632 Also correct mistake in the comment.
633
6a5709a5
JR		 6342004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
635
636 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
637 ensure that double registers have even numbers.
638 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
639 that reserved instruction 0xfffd does not decode the same
640 as 0xfdfd (ftrv).
641 * sh-opc.h: Add REG_N_D nibble type and use it whereever
642 REG_N refers to a double register.
643 Add REG_N_B01 nibble type and use it instead of REG_NM
644 in ftrv.
645 Adjust the bit patterns in a few comments.
646
e5d2b64f 6472004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 648
649 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 650
1f04b05f
AH		 6512004-02-20 Aldy Hernandez <aldyh@redhat.com>
652
653 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
654
2f3b8700
AH		 6552004-02-20 Aldy Hernandez <aldyh@redhat.com>
656
657 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
658
f0b26da6 6592004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 660
661 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
662 mtivor32, mtivor33, mtivor34.
f0b26da6 663
23d59c56 6642004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 665
666 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 667
34920d91
NC		 6682004-02-10 Petko Manolov <petkan@nucleusys.com>
669
670 * arm-opc.h Maverick accumulator register opcode fixes.
671
44d86481
BE		 6722004-02-13 Ben Elliston <bje@wasabisystems.com>
673
674 * m32r-dis.c: Regenerate.
675
17707c23
MS		 6762004-01-27 Michael Snyder <msnyder@redhat.com>
677
678 * sh-opc.h (sh_table): "fsrra", not "fssra".
679
fe3a9bc4
NC		 6802004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
681
682 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
683 contraints.
684
ff24f124
JJ		 6852004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
686
687 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
688
a02a862a
AM		 6892004-01-19 Alan Modra <amodra@bigpond.net.au>
690
691 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
692 1. Don't print scale factor on AT&T mode when index missing.
693
d164ea7f
AO		 6942004-01-16 Alexandre Oliva <aoliva@redhat.com>
695
696 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
697 when loaded into XR registers.
698
cb10e79a
RS		 6992004-01-14 Richard Sandiford <rsandifo@redhat.com>
700
701 * frv-desc.h: Regenerate.
702 * frv-desc.c: Regenerate.
703 * frv-opc.c: Regenerate.
704
f532f3fa
MS		 7052004-01-13 Michael Snyder <msnyder@redhat.com>
706
707 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
708
e45d0630
PB		 7092004-01-09 Paul Brook <paul@codesourcery.com>
710
711 * arm-opc.h (arm_opcodes): Move generic mcrr after known
712 specific opcodes.
713
3ba7a1aa
DJ		 7142004-01-07 Daniel Jacobowitz <drow@mvista.com>
715
716 * Makefile.am (libopcodes_la_DEPENDENCIES)
717 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
718 comment about the problem.
719 * Makefile.in: Regenerate.
720
ba2d3f07
AO		 7212004-01-06 Alexandre Oliva <aoliva@redhat.com>
722
723 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
724 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
725 cut&paste errors in shifting/truncating numerical operands.
726 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
727 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
728 (parse_uslo16): Likewise.
729 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
730 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
731 (parse_s12): Likewise.
732 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
733 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
734 (parse_uslo16): Likewise.
735 (parse_uhi16): Parse gothi and gotfuncdeschi.
736 (parse_d12): Parse got12 and gotfuncdesc12.
737 (parse_s12): Likewise.
738
3ab48931
NC		 7392004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
740
741 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
742 instruction which looks similar to an 'rla' instruction.
a0bd404e 743
c9e214e5 744For older changes see ChangeLog-0203
252b5132
RH		 745\f
746Local Variables:
2f6d2f85
NC		 747mode: change-log
748left-margin: 8
749fill-column: 74
252b5132
RH		 750version-control: never
751End:
GDB Binutils - Deliverables
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