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2007-05-18 Paul Brook <paul@codesourcery.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
ea192fa3
PB		 12007-05-16 Peter Bergner <bergner@vnet.ibm.com>
2
3 * ppc-dis.c (operand_value_powerpc, skip_optional_operands): New.
4 (print_insn_powerpc): Use the new operand_value_powerpc and
5 skip_optional_operands functions to omit or print all optional
6 operands as a group.
7 * ppc-opc.c (BFF, W, XFL_L, XWRA_MASK): New.
8 (XFL_MASK): Delete L and W bits from the mask.
9 (mtfsfi, mtfsfi.): Replace use of BF with BFF. Relpace use of XRA_MASK
10 with XWRA_MASK. Use W.
11 (mtfsf, mtfsf.): Use XFL_L and W.
12
9beff690
L		 132007-05-14 H.J. Lu <hongjiu.lu@intel.com>
14
15 PR binutils/4502
16 * i386-dis.c (Suffix3DNow): Replace "pfmulhrw" with "pmulhrw".
17
4d67a4d3
L		 182007-05-10 H.J. Lu <hongjiu.lu@intel.com>
19
20 * i386-opc.h (ShortForm): Redefined.
21 (Jump): Likewise.
22 (JumpDword): Likewise.
23 (JumpByte): Likewise.
24 (JumpInterSegment): Likewise.
25 (FloatMF): Likewise.
26 (FloatR): Likewise.
27 (FloatD): Likewise.
28 (Size16): Likewise.
29 (Size32): Likewise.
30 (Size64): Likewise.
31 (IgnoreSize): Likewise.
32 (DefaultSize): Likewise.
33 (No_bSuf): Likewise.
34 (No_wSuf): Likewise.
35 (No_lSuf): Likewise.
36 (No_sSuf): Likewise.
37 (No_qSuf): Likewise.
38 (No_xSuf): Likewise.
39 (FWait): Likewise.
40 (IsString): Likewise.
41 (regKludge): Likewise.
42 (IsPrefix): Likewise.
43 (ImmExt): Likewise.
44 (NoRex64): Likewise.
45 (Rex64): Likewise.
46 (Ugh): Likewise.
47
8de28984
L		 482007-05-07 H.J. Lu <hongjiu.lu@intel.com>
49
50 * i386-dis.c (threebyte_0x38_uses_DATA_prefix): Correct entries
51 for some SSE4 instructions.
52 (threebyte_0x3a_uses_DATA_prefix): Likewise.
53
20592a94
L		 542007-05-03 H.J. Lu <hongjiu.lu@intel.com>
55
56 * i386-dis.c (CRC32_Fixup): Don't print suffix in Intel mode.
57
58 * i386-opc.c (i386_optab): Remove IgnoreSize and correct operand
59 type for crc32.
60
9344ff29
L		 612007-05-01 H.J. Lu <hongjiu.lu@intel.com>
62
63 * i386-dis.c (CRC32_Fixup): Properly handle Intel mode and
64 check data size prefix in 16bit mode.
65
66 * i386-opc.c (i386_optab): Default crc32 to non-8bit and
67 support Intel mode.
68
53289dcd
MS		 692007-04-30 Mark Salter <msalter@redhat.com>
70
71 * frv-desc.c: Regenerate.
72 * frv-desc.h: Regenerate.
73
eb42fac1
AM		 742007-04-30 Alan Modra <amodra@bigpond.net.au>
75
76 PR 4436
77 * ppc-opc.c (powerpc_operands): Correct bitm for second entry of MBE.
78
484c222e
L		 792007-04-27 H.J. Lu <hongjiu.lu@intel.com>
80
81 * i386-dis.c (modrm): Put reg before rm.
82
5d669648
L		 832007-04-26 H.J. Lu <hongjiu.lu@intel.com>
84
85 PR binutils/4430
86 * i386-dis.c (print_displacement): New.
87 (OP_E): Call print_displacement instead of print_operand_value
88 to output displacement when either base or index exist. Print
89 the explicit zero displacement in 16bit mode.
90
185b1163
L		 912007-04-26 H.J. Lu <hongjiu.lu@intel.com>
92
93 PR binutils/4429
94 * i386-dis.c (print_insn): Also swap the order of op_riprel
95 when swapping op_index. Break when the RIP relative address
96 is printed.
97 (OP_E): Properly handle RIP relative addressing and print the
98 explicit zero displacement for Intel mode.
99
eddc20ad
AM		 1002007-04-27 Alan Modra <amodra@bigpond.net.au>
101
102 * Makefile.am: Run "make dep-am".
103 * Makefile.in: Regenerate.
104 * ns32k-dis.c: Include sysdep.h first.
105
dacc8b01
MS		 1062007-04-24 Andreas Krebbel <krebbel1@de.ibm.com>
107
108 * opcodes/s390-opc.c (MASK_SSF_RRDRD): Fourth nybble belongs to the
109 opcode.
eddc20ad
AM		 110 * opcodes/s390-opc.txt (pfpo, ectg, csst): Add new z9-ec instructions.
111
fbb92301
NC		 1122007-04-24 Nick Clifton <nickc@redhat.com>
113
114 * arm-dis.c (print_insn): Initialise type.
115
4c273957
AM		 1162007-04-24 Alan Modra <amodra@bigpond.net.au>
117
118 * cgen-types.h: Include bfd_stdint.h, not stdint.h.
119 * Makefile.am: Run "make dep-am".
120 * Makefile.in: Regenerate.
121
9a2e615a
NS		 1222007-04-23 Nathan Sidwell <nathan@codesourcery.com>
123
124 * m68k-opc.c: Mark mcfisa_c instructions.
125
37b37b2d
RE		 1262007-04-21 Richard Earnshaw <rearnsha@arm.com>
127
128 * arm-dis.c (arm_opcodes): Disassemble to unified syntax.
129 (thumb_opcodes): Add missing white space in adr.
130 (arm_decode_shift): New parameter, print_shift. Only decode the
131 shift parameter if set. Adjust callers.
132 (print_insn_arm): Support for operand type q with no shift decode.
133
717bbdf1
AM		 1342007-04-21 Alan Modra <amodra@bigpond.net.au>
135
db557034
AM		 136 * i386-opc.c (i386_float_regtab, i386_float_regtab_size): Delete.
137 Move contents to..
138 (i386_regtab): ..here.
139 * i386-opc.h (i386_float_regtab, i386_float_regtab_size): Delete.
140
717bbdf1
AM		 141 * ppc-opc.c (powerpc_operands): Delete duplicate entries.
142 (BA_MASK, FXM_MASK, STRM_MASK, VA_MASK, VB_MASK, VC_MASK): Delete.
143 (VD_MASK, WS_MASK, MTMSRD_L, XRT_L): Delete.
144 (powerpc_opcodes): Replace uses of MTMSRD_L and XRT_L.
145
78336706
NS		 1462007-04-20 Nathan Sidwell <nathan@codesourcery.com>
147
148 * m68k-dis.c (print_insn_arg): Show c04 as rambar0 and c05 as
149 rambar1.
150
b84bf58a
AM		 1512007-04-20 Alan Modra <amodra@bigpond.net.au>
152
153 * ppc-dis.c (print_insn_powerpc): Adjust for struct powerpc_operand
154 change.
155 * ppc-opc.c (powerpc_operands): Replace bit count with bit mask
156 in all entries. Add PPC_OPERAND_SIGNED to DE entry. Remove
157 references to following deleted functions.
158 (insert_bd, extract_bd, insert_dq, extract_dq): Delete.
159 (insert_ds, extract_ds, insert_de, extract_de): Delete.
160 (insert_des, extract_des, insert_li, extract_li): Delete.
161 (insert_nb, insert_rsq, insert_rtq, insert_ev2, extract_ev2): Delete.
162 (insert_ev4, extract_ev4, insert_ev8, extract_ev8): Delete.
163 (num_powerpc_operands): New constant.
164 (XSPRG_MASK): Remove entire SPRG field.
165 (powerpc_opcodes <bcctre, bcctrel>): Use XLBB_MASK not XLYBB_MASK.
166
0bbdef92
AM		 1672007-04-20 Alan Modra <amodra@bigpond.net.au>
168
169 * ppc-opc.c (DCM, DGM, TE, RMC, R, SP, S): Correct shift.
170 (Z2_MASK): Define.
171 (powerpc_opcodes): Use Z2_MASK in all insns taking RMC operand.
172
86ad2a13
RE		 1732007-04-20 Richard Earnshaw <rearnsha@arm.com>
174
175 * arm-dis.c (print_insn): Only look for a mapping symbol in the section
176 being disassembled.
177
a33e055d
AM		 1782007-04-19 Alan Modra <amodra@bigpond.net.au>
179
180 * Makefile.am: Run "make dep-am".
181 * Makefile.in: Regenerate.
182 * po/POTFILES.in: Regenerate.
183
360b1600
AM		 1842007-04-19 Alan Modra <amodra@bigpond.net.au>
185
186 * ppc-opc.c (powerpc_opcodes): Add cctpl, cctpm, cctph, db8cyc,
187 db10cyc, db12cyc, db16cyc.
188
b20ae55e
AM		 1892007-04-19 Nathan Froyd <froydnj@codesourcery.com>
190
191 * ppc-opc.c (powerpc_opcodes): Recognize three-operand tlbsxe.
192
381d071f
L		 1932007-04-18 H.J. Lu <hongjiu.lu@intel.com>
194
195 * i386-dis.c (CRC32_Fixup): New.
196 (PREGRP85, PREGRP86, PREGRP87, PREGRP88, PREGRP89, PREGRP90,
197 PREGRP91): New.
198 (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.2.
199 (threebyte_0x3a_uses_DATA_prefix): Likewise.
200 (prefix_user_table): Add PREGRP85, PREGRP86, PREGRP87,
201 PREGRP88, PREGRP89, PREGRP90 and PREGRP91.
202 (three_byte_table): Likewise.
203
204 * i386-opc.c (i386_optab): Add SSE4.2 opcodes.
205
f6fdceb7 206 * i386-opc.h (CpuSSE4_2): New.
381d071f
L		 207 (CpuSSE4): Likewise.
208 (CpuUnknownFlags): Add CpuSSE4_2.
209
42903f7f
L		 2102007-04-18 H.J. Lu <hongjiu.lu@intel.com>
211
212 * i386-dis.c (XMM_Fixup): New.
213 (Edqb): New.
214 (Edqd): New.
215 (XMM0): New.
216 (dqb_mode): New.
217 (dqd_mode): New.
218 (PREGRP39 ... PREGRP85): New.
219 (threebyte_0x38_uses_DATA_prefix): Updated for SSE4.
220 (threebyte_0x3a_uses_DATA_prefix): Likewise.
221 (prefix_user_table): Add PREGRP39 ... PREGRP85.
222 (three_byte_table): Likewise.
223 (putop): Handle 'K'.
224 (intel_operand_size): Handle dqb_mode, dqd_mode):
225 (OP_E): Likewise.
226 (OP_G): Likewise.
227
228 * i386-opc.c (i386_optab): Add SSE4.1 opcodes.
229
230 * i386-opc.h (CpuSSE4_1): New.
231 (CpuUnknownFlags): Add CpuSSE4_1.
232 (regKludge): Update comment.
233
ee5c21a0
DJ		 2342007-04-18 Matthias Klose <doko@ubuntu.com>
235
236 * Makefile.am (libopcodes_la_LDFLAGS): Use bfd soversion.
237 * Makefile.in: Regenerate.
238
b7d19ba6
SE		 2392007-04-14 Steve Ellcey <sje@cup.hp.com>
240
241 * Makefile.am: Add ACLOCAL_AMFLAGS.
242 * Makefile.in: Regenerate.
243
246c51aa
L		 2442007-04-13 H.J. Lu <hongjiu.lu@intel.com>
245
246 * i386-dis.c: Remove trailing white spaces.
6e26e51a
L		 247 * i386-opc.c: Likewise.
248 * i386-opc.h: Likewise.
246c51aa 249
7967e09e
L		 2502007-04-11 H.J. Lu <hongjiu.lu@intel.com>
251
252 PR binutils/4333
253 * i386-dis.c (GRP1a): New.
254 (GRP1b ... GRPPADLCK2): Update index.
255 (dis386): Use GRP1a for entry 0x8f.
256 (mod, rm, reg): Removed. Replaced by ...
257 (modrm): This.
258 (grps): Add GRP1a.
259
56dc1f8a
KH		 2602007-04-09 Kazu Hirata <kazu@codesourcery.com>
261
262 * m68k-dis.c (print_insn_m68k): Restore info->fprintf_func and
263 info->print_address_func if longjmp is called.
264
144f4bc6
DD		 2652007-03-29 DJ Delorie <dj@redhat.com>
266
267 * m32c-desc.c: Regenerate.
268 * m32c-dis.c: Regenerate.
269 * m32c-opc.c: Regenerate.
270
e72cf3ec
L		 2712007-03-28 H.J. Lu <hongjiu.lu@intel.com>
272
273 * i386-opc.c (i386_optab): Change InvMem to RegMem for mov and
274 movq. Remove InvMem from sldt, smsw and str.
275
276 * i386-opc.h (InvMem): Renamed to ...
277 (RegMem): Update comments.
278 (AnyMem): Remove InvMem.
279
831480e9 2802007-03-27 Paul Brook <paul@codesourcery.com>
b74ed8f5 281
b74ed8f5
PB		 282 * arm-dis.c (thumb_opcodes): Add entry for undefined insns (0xbe??).
283
4146fd53
PB		 2842007-03-24 Paul Brook <paul@codesourcery.com>
285
286 * arm-dis.c (coprocessor_opcodes): Remove superfluous 0x.
287 (print_insn_coprocessor): Handle %<bitfield>x.
288
b6702015 2892007-03-24 Paul Brook <paul@codesourcery.com>
e72cf3ec 290 Mark Shinwell <shinwell@codesourcery.com>
b6702015
PB		 291
292 * arm-dis.c (arm_opcodes): Print SRS base register.
293
831480e9 2942007-03-23 H.J. Lu <hongjiu.lu@intel.com>
0003779b
L		 295
296 * i386-dis.c (prefix_name): Replace rex64XYZ with rex.WRXB.
297
298 * i386-opc.c (i386_optab): Add rex.wrxb.
299
831480e9 3002007-03-21 H.J. Lu <hongjiu.lu@intel.com>
161a04f6
L		 301
302 * i386-dis.c (REX_MODE64): Remove definition.
303 (REX_EXTX): Likewise.
304 (REX_EXTY): Likewise.
305 (REX_EXTZ): Likewise.
306 (USED_REX): Use REX_OPCODE instead of 0x40.
307 Replace REX_MODE64, REX_EXTX, REX_EXTY and REX_EXTZ with REX_W,
308 REX_R, REX_X and REX_B respectively.
309
831480e9 3102007-03-21 H.J. Lu <hongjiu.lu@intel.com>
8b38ad71
L		 311
312 PR binutils/4218
313 * i386-dis.c (PREGRP38): New.
314 (dis386): Use PREGRP38 for 0x90.
315 (prefix_user_table): Add PREGRP38.
316 (print_insn): Set uses_REPZ_prefix to 1 for pause.
317 (NOP_Fixup1): Properly handle REX bits.
318 (NOP_Fixup2): Likewise.
319
320 * i386-opc.c (i386_optab): Allow %eax with xchg in 64bit.
321 Allow register with nop.
322
75b06e7b
DD		 3232007-03-20 DJ Delorie <dj@redhat.com>
324
325 * m32c-asm.c: Regenerate.
326 * m32c-desc.c: Regenerate.
327 * m32c-desc.h: Regenerate.
328 * m32c-dis.h: Regenerate.
329 * m32c-ibld.c: Regenerate.
330 * m32c-opc.c: Regenerate.
331 * m32c-opc.h: Regenerate.
332
c3fe08fa
L		 3332007-03-15 H.J. Lu <hongjiu.lu@intel.com>
334
335 * i386-opc.c: Include "libiberty.h".
336 (i386_regtab): Remove the last entry.
337 (i386_regtab_size): New.
338 (i386_float_regtab_size): Likewise.
339
340 * i386-opc.h (i386_regtab_size): New.
341 (i386_float_regtab_size): Likewise.
342
0b1cf022
L		 3432007-03-15 H.J. Lu <hongjiu.lu@intel.com>
344
345 * Makefile.am (CFILES): Add i386-opc.c.
346 (ALL_MACHINES): Add i386-opc.lo.
347 Run "make dep-am".
348 * Makefile.in: Regenerated.
349
350 * configure.in: Add i386-opc.lo for bfd_i386_arch.
351 * configure: Regenerated.
352
353 * i386-dis.c: Include "opcode/i386.h".
354 (MAXLEN): Renamed to MAX_MNEM_SIZE. Remove definition.
355 (FWAIT_OPCODE): Remove definition.
356 (UNIXWARE_COMPAT): Renamed to SYSV386_COMPAT. Remove definition.
357 (MAX_OPERANDS): Remove definition.
358
359 * i386-opc.c: New file.
360 * i386-opc.h: Likewise.
361
56eced12
L		 3622007-03-15 H.J. Lu <hongjiu.lu@intel.com>
363
364 * Makefile.in: Regenerated.
365
6f74c397
L		 3662007-03-09 H.J. Lu <hongjiu.lu@intel.com>
367
368 * i386-dis.c (OP_Rd): Renamed to ...
369 (OP_R): This.
370 (Rd): Updated.
371 (Rm): Likewise.
372
a6d04ec4
AM		 3732007-03-08 Alan Modra <amodra@bigpond.net.au>
374
1620f33d
AM		 375 * fr30-asm.c: Regenerate.
376 * frv-asm.c: Regenerate.
377 * ip2k-asm.c: Regenerate.
378 * iq2000-asm.c: Regenerate.
379 * m32c-asm.c: Regenerate.
380 * m32r-asm.c: Regenerate.
381 * m32r-dis.c: Regenerate.
382 * mt-asm.c: Regenerate.
383 * mt-ibld.c: Regenerate.
384 * mt-opc.c: Regenerate.
385 * openrisc-asm.c: Regenerate.
386 * xc16x-asm.c: Regenerate.
387 * xstormy16-asm.c: Regenerate.
388
a6d04ec4
AM		 389 * Makefile.am: Run "make dep-am".
390 * Makefile.in: Regenerate.
391 * po/POTFILES.in: Regenerate.
392
b5639b37
MS		 3932007-03-06 Andreas Krebbel <krebbel1@de.ibm.com>
394
395 * opcodes/s390-opc.c (INSTR_RRE_FR, INSTR_RRF_F0FF2, INSTR_RRF_F0FR,
396 INSTR_RRF_UUFF, INSTR_RRF_0UFF, INSTR_RRF_FFFU, INSTR_RRR_F0FF): New
397 instruction formats added.
398 (MASK_RRE_FR, MASK_RRF_F0FF2, MASK_RRF_F0FR, MASK_RRF_UUFF,
399 MASK_RRF_0UFF, MASK_RRF_FFFU, MASK_RRR_F0FF): New instruction format
400 masks added.
401 * opcodes/s390-opc.txt (lpdfr - tgxt): Decimal floating point
402 instructions added.
403 * opcodes/s390-mkopc.c (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
404 (main): z9-ec cpu type option added.
405 * include/opcode/s390.h (s390_opcode_cpu_val): S390_OPCODE_Z9_EC added.
406
b2e818b7
DD		 4072007-02-22 DJ Delorie <dj@redhat.com>
408
409 * s390-opc.c (INSTR_SS_L2RDRD): New.
410 (MASK_SS_L2RDRD): New.
411 * s390-opc.txt (pka): Use it.
412
8b082fb1
TS		 4132007-02-20 Thiemo Seufer <ths@mips.com>
414 Chao-Ying Fu <fu@mips.com>
415
416 * mips-dis.c (mips_arch_choices): Add DSP R2 support.
417 (print_insn_args): Add support for balign instruction.
418 * mips-opc.c (D33): New shortcut for DSP R2 instructions.
419 (mips_builtin_opcodes): Add DSP R2 instructions.
420
929e4d1a
MS		 4212007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
422
423 * s390-opc.c (INSTR_RRF_U0FR, MASK_RRF_U0FR): Removed.
424 (INSTR_RRF_U0RF, MASK_RRF_U0RF): Added.
425 * s390-opc.txt (cfxbr, cfdbr, cfebr, cgebr, cgdbr, cgxbr, cger, cgdr,
426 cgxr, cfxr, cfdr, cfer): Instruction type set to INSTR_RRF_U0RF.
427
b8e55848
MS		 4282007-02-19 Andreas Krebbel <krebbel1@de.ibm.com>
429
430 * s390-opc.txt ("efpc", "sfpc"): Set to RRE_RR_OPT instruction type.
431 * s390-opc.c (s390_operands): Add RO_28 as optional gpr.
432 (INSTR_RRE_RR_OPT, MASK_RRE_RR_OPT): New instruction type for efpc
433 and sfpc.
434
af692060
NC		 4352007-02-16 Nick Clifton <nickc@redhat.com>
436
437 PR binutils/4045
438 * avr-dis.c (comment_start): New variable, contains the prefix to
439 use when printing addresses in comments.
440 (print_insn_avr): Set comment_start to an empty space if there is
441 no symbol table available as the generic address printing code
442 will prefix the numeric value of the address with 0x.
443
ce518a5f
L		 4442007-02-13 H.J. Lu <hongjiu.lu@intel.com>
445
446 * i386-dis.c: Updated to use an array of MAX_OPERANDS operands
447 in struct dis386.
448
bd2f2e55 4492007-02-05 Dave Brolley <brolley@redhat.com>
8c9c183d
DB		 450 Richard Sandiford <rsandifo@redhat.com>
451 DJ Delorie <dj@redhat.com>
452 Graydon Hoare <graydon@redhat.com>
453 Frank Ch. Eigler <fche@redhat.com>
454 Ben Elliston <bje@redhat.com>
455
456 * Makefile.am (HFILES): Add mep-desc.h mep-opc.h.
457 (CFILES): Add mep-*.c
458 (ALL_MACHINES): Add mep-*.lo.
459 (CLEANFILES): Add stamp-mep.
460 (CGEN_CPUS): Add mep.
461 (MEP_DEPS): New variable.
462 (mep-*): New targets.
463 * configure.in: Handle bfd_mep_arch.
464 * disassemble.c (ARCH_mep): New macro.
465 (disassembler): Handle bfd_arch_mep.
466 (disassemble_init_for_target): Likewise.
467 * mep-*: New files for Toshiba Media Processor (MeP).
bd2f2e55
DB		 468 * Makefile.in: Regenerated.
469 * configure: Regenerated.
470
eb7834a6 4712007-02-05 H.J. Lu <hongjiu.lu@intel.com>
65ca155d
L		 472
473 * i386-dis.c (OP_J): Undo the last change. Properly handle 64K
474 wrap around within the same segment in 16bit mode.
475
eb7834a6 4762007-02-02 H.J. Lu <hongjiu.lu@intel.com>
206717e8
L		 477
478 * i386-dis.c (OP_J): Mask to 16bit only if there is a data16
479 prefix.
480
c4f5c3d7
L		 4812007-02-02 H.J. Lu <hongjiu.lu@intel.com>
482
483 * avr-dis.c (avr_operand): Correct PR number in comment.
484
fc523535 4852007-02-02 H.J. Lu <hongjiu.lu@intel.com>
f59a29b9
L		 486
487 * disassemble.c (disassembler_usage): Call
488 print_i386_disassembler_options for i386 disassembler.
489
490 * i386-dis.c (print_i386_disassembler_options): New.
491 (print_insn): Support the new addr64 option.
492
64a3a6fc
NC		 4932007-02-02 Hiroki Kaminaga <kaminaga@sm.sony.co.jp>
494
495 * ppc-dis.c (powerpc_dialect): Handle ppc440.
496 * ppc-dis.c (print_ppc_disassembler_options): Note the -M440 can
497 be used.
498
ba4e851b
AM		 4992007-02-02 Alan Modra <amodra@bigpond.net.au>
500
501 * ppc-opc.c (insert_bdm): -Many comment.
502 (valid_bo): Add "extract" param. Accept both powerpc and power4
503 BO fields when disassembling with -Many.
504 (insert_bo, extract_bo, insert_boe, extract_boe): Adjust valid_bo call.
505
3bdcfdf4
KH		 5062007-01-08 Kazu Hirata <kazu@codesourcery.com>
507
508 * m68k-opc.c (m68k_opcodes): Replace cpu32 with
509 cpu32 | fido_a except on tbl instructions.
510
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PB		 5112007-01-04 Paul Brook <paul@codesourcery.com>
512
513 * arm-dis.c (arm_opcodes): Fix cpsie and cpsid entries.
514
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AS		 5152007-01-04 Andreas Schwab <schwab@suse.de>
516
517 * m68k-opc.c: Fix encoding of signed bit in the cpu32 tbls insns.
518
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JB		 5192007-01-04 Julian Brown <julian@codesourcery.com>
520
521 * arm-dis.c (neon_opcode): Fix disassembly for vshl, vqshl, vrshl,
522 vqrshl instructions.
523
10a2343e 524For older changes see ChangeLog-2006
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RH		 525\f
526Local Variables:
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NC		 527mode: change-log
528left-margin: 8
529fill-column: 74
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RH		 530version-control: never
531End:
GDB Binutils - Deliverables
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