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x86: avoid attaching suffix to register-only CRC32
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
2875b28a
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (CRC32_Fixup): Delete.
4 (prefix_table): Use Eb/Ev for crc32 entries.
5
e184e611
JB		 62020-07-14 Jan Beulich <jbeulich@suse.com>
7
8 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
9 Conditionalize invocations of "USED_REX (0)".
10
e8b5d5f9
JB		 112020-07-14 Jan Beulich <jbeulich@suse.com>
12
13 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
14 CH, DH, BH, AX, DX): Delete.
15 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
16 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
17 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
18
260cd341
LC		 192020-07-10 Lili Cui <lili.cui@intel.com>
20
21 * i386-dis.c (TMM): New.
22 (EXtmm): Likewise.
23 (VexTmm): Likewise.
24 (MVexSIBMEM): Likewise.
25 (tmm_mode): Likewise.
26 (vex_sibmem_mode): Likewise.
27 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
28 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
29 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
30 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
31 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
32 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
33 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
34 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
35 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
36 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
37 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
38 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
39 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
40 (PREFIX_VEX_0F3849_X86_64): Likewise.
41 (PREFIX_VEX_0F384B_X86_64): Likewise.
42 (PREFIX_VEX_0F385C_X86_64): Likewise.
43 (PREFIX_VEX_0F385E_X86_64): Likewise.
44 (X86_64_VEX_0F3849): Likewise.
45 (X86_64_VEX_0F384B): Likewise.
46 (X86_64_VEX_0F385C): Likewise.
47 (X86_64_VEX_0F385E): Likewise.
48 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
49 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
50 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
51 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
52 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
53 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
54 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
55 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
56 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
57 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
58 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
59 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
60 (VEX_W_0F3849_X86_64_P_0): Likewise.
61 (VEX_W_0F3849_X86_64_P_2): Likewise.
62 (VEX_W_0F3849_X86_64_P_3): Likewise.
63 (VEX_W_0F384B_X86_64_P_1): Likewise.
64 (VEX_W_0F384B_X86_64_P_2): Likewise.
65 (VEX_W_0F384B_X86_64_P_3): Likewise.
66 (VEX_W_0F385C_X86_64_P_1): Likewise.
67 (VEX_W_0F385E_X86_64_P_0): Likewise.
68 (VEX_W_0F385E_X86_64_P_1): Likewise.
69 (VEX_W_0F385E_X86_64_P_2): Likewise.
70 (VEX_W_0F385E_X86_64_P_3): Likewise.
71 (names_tmm): Likewise.
72 (att_names_tmm): Likewise.
73 (intel_operand_size): Handle void_mode.
74 (OP_XMM): Handle tmm_mode.
75 (OP_EX): Likewise.
76 (OP_VEX): Likewise.
77 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
78 CpuAMX_BF16 and CpuAMX_TILE.
79 (operand_type_shorthands): Add RegTMM.
80 (operand_type_init): Likewise.
81 (operand_types): Add Tmmword.
82 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
83 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
84 * i386-opc.h (CpuAMX_INT8): New.
85 (CpuAMX_BF16): Likewise.
86 (CpuAMX_TILE): Likewise.
87 (SIBMEM): Likewise.
88 (Tmmword): Likewise.
89 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
90 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
91 (i386_operand_type): Add tmmword.
92 * i386-opc.tbl: Add AMX instructions.
93 * i386-reg.tbl: Add AMX registers.
94 * i386-init.h: Regenerated.
95 * i386-tbl.h: Likewise.
96
467bbef0
JB		 972020-07-08 Jan Beulich <jbeulich@suse.com>
98
99 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
100 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
101 Rename to ...
102 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
103 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
104 respectively.
105 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
106 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
107 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
108 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
109 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
110 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
111 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
112 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
113 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
114 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
115 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
116 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
117 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
118 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
119 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
120 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
121 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
122 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
123 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
124 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
125 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
126 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
127 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
128 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
129 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
130 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
131 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
132 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
133 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
134 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
135 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
136 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
137 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
138 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
139 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
140 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
141 (reg_table): Re-order XOP entries. Adjust their operands.
142 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
143 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
144 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
145 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
146 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
147 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
148 entries by references ...
149 (vex_len_table): ... to resepctive new entries here. For several
150 new and existing entries reference ...
151 (vex_w_table): ... new entries here.
152 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
153
6384fd9e
JB		 1542020-07-08 Jan Beulich <jbeulich@suse.com>
155
156 * i386-dis.c (XMVexScalarI4): Define.
157 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
158 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
159 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
160 (vex_len_table): Move scalar FMA4 entries ...
161 (prefix_table): ... here.
162 (OP_REG_VexI4): Handle scalar_mode.
163 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
164 * i386-tbl.h: Re-generate.
165
e6123d0c
JB		 1662020-07-08 Jan Beulich <jbeulich@suse.com>
167
168 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
169 Vex_2src_2): Delete.
170 (OP_VexW, VexW): New.
171 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
172 for shifts and rotates by register.
173
93abb146
JB		 1742020-07-08 Jan Beulich <jbeulich@suse.com>
175
176 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
177 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
178 OP_EX_VexReg): Delete.
179 (OP_VexI4, VexI4): New.
180 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
181 (prefix_table): ... here.
182 (print_insn): Drop setting of vex_w_done.
183
b13b1bc0
JB		 1842020-07-08 Jan Beulich <jbeulich@suse.com>
185
186 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
187 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
188 (xop_table): Replace operands of 4-operand insns.
189 (OP_REG_VexI4): Move VEX.W based operand swaping here.
190
f337259f
CZ		 1912020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
192
193 * arc-opc.c (insert_rbd): New function.
194 (RBD): Define.
195 (RBDdup): Likewise.
196 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
197 instructions.
198
931452b6
JB		 1992020-07-07 Jan Beulich <jbeulich@suse.com>
200
201 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
202 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
203 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
204 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
205 Delete.
206 (putop): Handle "BW".
207 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
208 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
209 and 0F3A3F ...
210 * i386-dis-evex-prefix.h: ... here.
211
b5b098c2
JB		 2122020-07-06 Jan Beulich <jbeulich@suse.com>
213
214 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
215 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
216 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
217 VEX_W_0FXOP_09_83): New enumerators.
218 (xop_table): Reference the above.
219 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
220 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
221 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
222 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
223
21a3faeb
JB		 2242020-07-06 Jan Beulich <jbeulich@suse.com>
225
226 * i386-dis.c (EVEX_W_0F3838_P_1,
227 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
228 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
229 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
230 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
231 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
232 (putop): Centralize management of last[]. Delete SAVE_LAST.
233 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
234 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
235 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
236 * i386-dis-evex-prefix.h: here.
237
bc152a17
JB		 2382020-07-06 Jan Beulich <jbeulich@suse.com>
239
240 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
241 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
242 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
243 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
244 enumerators.
245 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
246 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
247 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
248 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
249 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
250 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
251 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
252 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
253 these, respectively.
254 * i386-dis-evex-len.h: Adjust comments.
255 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
256 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
257 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
258 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
259 MOD_EVEX_0F385B_P_2_W_1 table entries.
260 * i386-dis-evex-w.h: Reference mod_table[] for
261 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
262 EVEX_W_0F385B_P_2.
263
c82a99a0
JB		 2642020-07-06 Jan Beulich <jbeulich@suse.com>
265
266 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
267 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
268 EXymm.
269 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
270 Likewise. Mark 256-bit entries invalid.
271
fedfb81e
JB		 2722020-07-06 Jan Beulich <jbeulich@suse.com>
273
274 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
275 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
276 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
277 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
278 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
279 PREFIX_EVEX_0F382B): Delete.
280 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
281 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
282 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
283 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
284 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
285 to ...
286 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
287 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
288 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
289 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
290 respectively.
291 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
292 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
293 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
294 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
295 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
296 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
297 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
298 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
299 PREFIX_EVEX_0F382B): Remove table entries.
300 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
301 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
302 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
303
3a57774c
JB		 3042020-07-06 Jan Beulich <jbeulich@suse.com>
305
306 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
307 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
308 enumerators.
309 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
310 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
311 EVEX_LEN_0F3A01_P_2_W_1 table entries.
312 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
313 entries.
314
e74d9fa9
JB		 3152020-07-06 Jan Beulich <jbeulich@suse.com>
316
317 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
318 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
319 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
320 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
321 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
322 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
323 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
324 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
325 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
326 entries.
327
6431c801
JB		 3282020-07-06 Jan Beulich <jbeulich@suse.com>
329
330 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
331 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
332 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
333 respectively.
334 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
335 entries.
336 * i386-dis-evex.h (evex_table): Reference VEX table entry for
337 opcode 0F3A1D.
338 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
339 entry.
340 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
341
6df22cf6
JB		 3422020-07-06 Jan Beulich <jbeulich@suse.com>
343
344 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
345 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
346 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
347 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
348 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
349 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
350 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
351 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
352 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
353 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
354 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
355 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
356 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
357 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
358 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
359 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
360 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
361 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
362 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
363 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
364 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
365 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
366 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
367 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
368 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
369 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
370 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
371 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
372 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
373 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
374 (prefix_table): Add EXxEVexR to FMA table entries.
375 (OP_Rounding): Move abort() invocation.
376 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
377 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
378 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
379 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
380 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
381 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
382 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
383 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
384 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
385 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
386 0F3ACE, 0F3ACF.
387 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
388 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
389 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
390 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
391 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
392 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
393 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
394 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
395 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
396 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
397 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
398 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
399 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
400 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
401 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
402 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
403 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
404 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
405 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
406 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
407 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
408 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
409 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
410 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
411 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
412 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
413 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
414 Delete table entries.
415 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
416 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
417 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
418 Likewise.
419
39e0f456
JB		 4202020-07-06 Jan Beulich <jbeulich@suse.com>
421
422 * i386-dis.c (EXqScalarS): Delete.
423 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
424 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
425
5b872f7d
JB		 4262020-07-06 Jan Beulich <jbeulich@suse.com>
427
428 * i386-dis.c (safe-ctype.h): Include.
429 (EXdScalar, EXqScalar): Delete.
430 (d_scalar_mode, q_scalar_mode): Delete.
431 (prefix_table, vex_len_table): Use EXxmm_md in place of
432 EXdScalar and EXxmm_mq in place of EXqScalar.
433 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
434 d_scalar_mode and q_scalar_mode.
435 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
436 (vmovsd): Use EXxmm_mq.
437
ddc73fa9
NC		 4382020-07-06 Yuri Chornoivan <yurchor@ukr.net>
439
440 PR 26204
441 * arc-dis.c: Fix spelling mistake.
442 * po/opcodes.pot: Regenerate.
443
17550be7
NC		 4442020-07-06 Nick Clifton <nickc@redhat.com>
445
446 * po/pt_BR.po: Updated Brazilian Portugugese translation.
447 * po/uk.po: Updated Ukranian translation.
448
b19d852d
NC		 4492020-07-04 Nick Clifton <nickc@redhat.com>
450
451 * configure: Regenerate.
452 * po/opcodes.pot: Regenerate.
453
b115b9fd
NC		 4542020-07-04 Nick Clifton <nickc@redhat.com>
455
456 Binutils 2.35 branch created.
457
c2ecccb3
L		 4582020-07-02 H.J. Lu <hongjiu.lu@intel.com>
459
460 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
461 * i386-opc.h (VexSwapSources): New.
462 (i386_opcode_modifier): Add vexswapsources.
463 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
464 with two source operands swapped.
465 * i386-tbl.h: Regenerated.
466
08ccfccf
NC		 4672020-06-30 Nelson Chu <nelson.chu@sifive.com>
468
469 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
470 unprivileged CSR can also be initialized.
471
279edac5
AM		 4722020-06-29 Alan Modra <amodra@gmail.com>
473
474 * arm-dis.c: Use C style comments.
475 * cr16-opc.c: Likewise.
476 * ft32-dis.c: Likewise.
477 * moxie-opc.c: Likewise.
478 * tic54x-dis.c: Likewise.
479 * s12z-opc.c: Remove useless comment.
480 * xgate-dis.c: Likewise.
481
e978ad62
L		 4822020-06-26 H.J. Lu <hongjiu.lu@intel.com>
483
484 * i386-opc.tbl: Add a blank line.
485
63112cd6
L		 4862020-06-26 H.J. Lu <hongjiu.lu@intel.com>
487
488 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
489 (VecSIB128): Renamed to ...
490 (VECSIB128): This.
491 (VecSIB256): Renamed to ...
492 (VECSIB256): This.
493 (VecSIB512): Renamed to ...
494 (VECSIB512): This.
495 (VecSIB): Renamed to ...
496 (SIB): This.
497 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 498 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 499 (VecSIB256): Likewise.
500 (VecSIB512): Likewise.
79b32e73 501 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 502 and VecSIB512, respectively.
503
d1c36125
JB		 5042020-06-26 Jan Beulich <jbeulich@suse.com>
505
506 * i386-dis.c: Adjust description of I macro.
507 (x86_64_table): Drop use of I.
508 (float_mem): Replace use of I.
509 (putop): Remove handling of I. Adjust setting/clearing of "alt".
510
2a1bb84c
JB		 5112020-06-26 Jan Beulich <jbeulich@suse.com>
512
513 * i386-dis.c: (print_insn): Avoid straight assignment to
514 priv.orig_sizeflag when processing -M sub-options.
515
8f570d62
JB		 5162020-06-25 Jan Beulich <jbeulich@suse.com>
517
518 * i386-dis.c: Adjust description of J macro.
519 (dis386, x86_64_table, mod_table): Replace J.
520 (putop): Remove handling of J.
521
464dc4af
JB		 5222020-06-25 Jan Beulich <jbeulich@suse.com>
523
524 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
525
589958d6
JB		 5262020-06-25 Jan Beulich <jbeulich@suse.com>
527
528 * i386-dis.c: Adjust description of "LQ" macro.
529 (dis386_twobyte): Use LQ for sysret.
530 (putop): Adjust handling of LQ.
531
39ff0b81
NC		 5322020-06-22 Nelson Chu <nelson.chu@sifive.com>
533
534 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
535 * riscv-dis.c: Include elfxx-riscv.h.
536
d27c357a
JB		 5372020-06-18 H.J. Lu <hongjiu.lu@intel.com>
538
539 * i386-dis.c (prefix_table): Revert the last vmgexit change.
540
6fde587f
CL		 5412020-06-17 Lili Cui <lili.cui@intel.com>
542
543 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
544
efe30057
L		 5452020-06-14 H.J. Lu <hongjiu.lu@intel.com>
546
547 PR gas/26115
548 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
549 * i386-opc.tbl: Likewise.
550 * i386-tbl.h: Regenerated.
551
d8af286f
NC		 5522020-06-12 Nelson Chu <nelson.chu@sifive.com>
553
554 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
555
14962256
AC		 5562020-06-11 Alex Coplan <alex.coplan@arm.com>
557
558 * aarch64-opc.c (SYSREG): New macro for describing system registers.
559 (SR_CORE): Likewise.
560 (SR_FEAT): Likewise.
561 (SR_RNG): Likewise.
562 (SR_V8_1): Likewise.
563 (SR_V8_2): Likewise.
564 (SR_V8_3): Likewise.
565 (SR_V8_4): Likewise.
566 (SR_PAN): Likewise.
567 (SR_RAS): Likewise.
568 (SR_SSBS): Likewise.
569 (SR_SVE): Likewise.
570 (SR_ID_PFR2): Likewise.
571 (SR_PROFILE): Likewise.
572 (SR_MEMTAG): Likewise.
573 (SR_SCXTNUM): Likewise.
574 (aarch64_sys_regs): Refactor to store feature information in the table.
575 (aarch64_sys_reg_supported_p): Collapse logic for system registers
576 that now describe their own features.
577 (aarch64_pstatefield_supported_p): Likewise.
578
f9630fa6
L		 5792020-06-09 H.J. Lu <hongjiu.lu@intel.com>
580
581 * i386-dis.c (prefix_table): Fix a typo in comments.
582
73239888
JB		 5832020-06-09 Jan Beulich <jbeulich@suse.com>
584
585 * i386-dis.c (rex_ignored): Delete.
586 (ckprefix): Drop rex_ignored initialization.
587 (get_valid_dis386): Drop setting of rex_ignored.
588 (print_insn): Drop checking of rex_ignored. Don't record data
589 size prefix as used with VEX-and-alike encodings.
590
18897deb
JB		 5912020-06-09 Jan Beulich <jbeulich@suse.com>
592
593 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
594 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
595 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
596 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
597 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
598 VEX_0F12, and VEX_0F16.
599 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
600 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
601 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
602 from movlps and movhlps. New MOD_0F12_PREFIX_2,
603 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
604 MOD_VEX_0F16_PREFIX_2 entries.
605
97e6786a
JB		 6062020-06-09 Jan Beulich <jbeulich@suse.com>
607
608 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
609 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
610 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
611 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
612 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
613 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
614 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
615 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
616 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
617 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
618 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
619 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
620 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
621 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
622 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
623 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
624 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
625 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
626 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
627 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
628 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
629 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
630 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
631 EVEX_W_0FC6_P_2): Delete.
632 (print_insn): Add EVEX.W vs embedded prefix consistency check
633 to prefix validation.
634 * i386-dis-evex.h (evex_table): Don't further descend for
635 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
636 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
637 and 0F2B.
638 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
639 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
640 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
641 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
642 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
643 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
644 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
645 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
646 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
647 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
648 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
649 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
650 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
651 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
652 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
653 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
654 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
655 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
656 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
657 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
658 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
659 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
660 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
661 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
662 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
663 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
664 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
665
bf926894
JB		 6662020-06-09 Jan Beulich <jbeulich@suse.com>
667
668 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
669 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
670 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
671 vmovmskpX.
672 (print_insn): Drop pointless check against bad_opcode. Split
673 prefix validation into legacy and VEX-and-alike parts.
674 (putop): Re-work 'X' macro handling.
675
a5aaedb9
JB		 6762020-06-09 Jan Beulich <jbeulich@suse.com>
677
678 * i386-dis.c (MOD_0F51): Rename to ...
679 (MOD_0F50): ... this.
680
26417f19
AC		 6812020-06-08 Alex Coplan <alex.coplan@arm.com>
682
683 * arm-dis.c (arm_opcodes): Add dfb.
684 (thumb32_opcodes): Add dfb.
685
8a6fb3f9
JB		 6862020-06-08 Jan Beulich <jbeulich@suse.com>
687
688 * i386-opc.h (reg_entry): Const-qualify reg_name field.
689
1424c35d
AM		 6902020-06-06 Alan Modra <amodra@gmail.com>
691
692 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
693
d3d1cc7b
AM		 6942020-06-05 Alan Modra <amodra@gmail.com>
695
696 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
697 size is large enough.
698
d8740be1
JM		 6992020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
700
701 * disassemble.c (disassemble_init_for_target): Set endian_code for
702 bpf targets.
703 * bpf-desc.c: Regenerate.
704 * bpf-opc.c: Likewise.
705 * bpf-dis.c: Likewise.
706
e9bffec9
JM		 7072020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
708
709 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
710 (cgen_put_insn_value): Likewise.
711 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
712 * cgen-dis.in (print_insn): Likewise.
713 * cgen-ibld.in (insert_1): Likewise.
714 (insert_1): Likewise.
715 (insert_insn_normal): Likewise.
716 (extract_1): Likewise.
717 * bpf-dis.c: Regenerate.
718 * bpf-ibld.c: Likewise.
719 * bpf-ibld.c: Likewise.
720 * cgen-dis.in: Likewise.
721 * cgen-ibld.in: Likewise.
722 * cgen-opc.c: Likewise.
723 * epiphany-dis.c: Likewise.
724 * epiphany-ibld.c: Likewise.
725 * fr30-dis.c: Likewise.
726 * fr30-ibld.c: Likewise.
727 * frv-dis.c: Likewise.
728 * frv-ibld.c: Likewise.
729 * ip2k-dis.c: Likewise.
730 * ip2k-ibld.c: Likewise.
731 * iq2000-dis.c: Likewise.
732 * iq2000-ibld.c: Likewise.
733 * lm32-dis.c: Likewise.
734 * lm32-ibld.c: Likewise.
735 * m32c-dis.c: Likewise.
736 * m32c-ibld.c: Likewise.
737 * m32r-dis.c: Likewise.
738 * m32r-ibld.c: Likewise.
739 * mep-dis.c: Likewise.
740 * mep-ibld.c: Likewise.
741 * mt-dis.c: Likewise.
742 * mt-ibld.c: Likewise.
743 * or1k-dis.c: Likewise.
744 * or1k-ibld.c: Likewise.
745 * xc16x-dis.c: Likewise.
746 * xc16x-ibld.c: Likewise.
747 * xstormy16-dis.c: Likewise.
748 * xstormy16-ibld.c: Likewise.
749
b3db6d07
JM		 7502020-06-04 Jose E. Marchesi <jemarch@gnu.org>
751
752 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
753 (print_insn_): Handle instruction endian.
754 * bpf-dis.c: Regenerate.
755 * bpf-desc.c: Regenerate.
756 * epiphany-dis.c: Likewise.
757 * epiphany-desc.c: Likewise.
758 * fr30-dis.c: Likewise.
759 * fr30-desc.c: Likewise.
760 * frv-dis.c: Likewise.
761 * frv-desc.c: Likewise.
762 * ip2k-dis.c: Likewise.
763 * ip2k-desc.c: Likewise.
764 * iq2000-dis.c: Likewise.
765 * iq2000-desc.c: Likewise.
766 * lm32-dis.c: Likewise.
767 * lm32-desc.c: Likewise.
768 * m32c-dis.c: Likewise.
769 * m32c-desc.c: Likewise.
770 * m32r-dis.c: Likewise.
771 * m32r-desc.c: Likewise.
772 * mep-dis.c: Likewise.
773 * mep-desc.c: Likewise.
774 * mt-dis.c: Likewise.
775 * mt-desc.c: Likewise.
776 * or1k-dis.c: Likewise.
777 * or1k-desc.c: Likewise.
778 * xc16x-dis.c: Likewise.
779 * xc16x-desc.c: Likewise.
780 * xstormy16-dis.c: Likewise.
781 * xstormy16-desc.c: Likewise.
782
4ee4189f
NC		 7832020-06-03 Nick Clifton <nickc@redhat.com>
784
785 * po/sr.po: Updated Serbian translation.
786
44730156
NC		 7872020-06-03 Nelson Chu <nelson.chu@sifive.com>
788
789 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
790 (riscv_get_priv_spec_class): Likewise.
791
3c3d0376
AM		 7922020-06-01 Alan Modra <amodra@gmail.com>
793
794 * bpf-desc.c: Regenerate.
795
78c1c354
JM		 7962020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
797 David Faust <david.faust@oracle.com>
798
799 * bpf-desc.c: Regenerate.
800 * bpf-opc.h: Likewise.
801 * bpf-opc.c: Likewise.
802 * bpf-dis.c: Likewise.
803
efcf5fb5
AM		 8042020-05-28 Alan Modra <amodra@gmail.com>
805
806 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
807 values.
808
ab382d64
AM		 8092020-05-28 Alan Modra <amodra@gmail.com>
810
811 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
812 immediates.
813 (print_insn_ns32k): Revert last change.
814
151f5de4
NC		 8152020-05-28 Nick Clifton <nickc@redhat.com>
816
817 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
818 static.
819
25e1eca8
SL		 8202020-05-26 Sandra Loosemore <sandra@codesourcery.com>
821
822 Fix extraction of signed constants in nios2 disassembler (again).
823
824 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
825 extractions of signed fields.
826
57b17940
SSF		 8272020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
828
829 * s390-opc.txt: Relocate vector load/store instructions with
830 additional alignment parameter and change architecture level
831 constraint from z14 to z13.
832
d96bf37b
AM		 8332020-05-21 Alan Modra <amodra@gmail.com>
834
835 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
836 * sparc-dis.c: Likewise.
837 * tic4x-dis.c: Likewise.
838 * xtensa-dis.c: Likewise.
839 * bpf-desc.c: Regenerate.
840 * epiphany-desc.c: Regenerate.
841 * fr30-desc.c: Regenerate.
842 * frv-desc.c: Regenerate.
843 * ip2k-desc.c: Regenerate.
844 * iq2000-desc.c: Regenerate.
845 * lm32-desc.c: Regenerate.
846 * m32c-desc.c: Regenerate.
847 * m32r-desc.c: Regenerate.
848 * mep-asm.c: Regenerate.
849 * mep-desc.c: Regenerate.
850 * mt-desc.c: Regenerate.
851 * or1k-desc.c: Regenerate.
852 * xc16x-desc.c: Regenerate.
853 * xstormy16-desc.c: Regenerate.
854
8f595e9b
NC		 8552020-05-20 Nelson Chu <nelson.chu@sifive.com>
856
857 * riscv-opc.c (riscv_ext_version_table): The table used to store
858 all information about the supported spec and the corresponding ISA
859 versions. Currently, only Zicsr is supported to verify the
860 correctness of Z sub extension settings. Others will be supported
861 in the future patches.
862 (struct isa_spec_t, isa_specs): List for all supported ISA spec
863 classes and the corresponding strings.
864 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
865 spec class by giving a ISA spec string.
866 * riscv-opc.c (struct priv_spec_t): New structure.
867 (struct priv_spec_t priv_specs): List for all supported privilege spec
868 classes and the corresponding strings.
869 (riscv_get_priv_spec_class): New function. Get the corresponding
870 privilege spec class by giving a spec string.
871 (riscv_get_priv_spec_name): New function. Get the corresponding
872 privilege spec string by giving a CSR version class.
873 * riscv-dis.c: Updated since DECLARE_CSR is changed.
874 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
875 according to the chosen version. Build a hash table riscv_csr_hash to
876 store the valid CSR for the chosen pirv verison. Dump the direct
877 CSR address rather than it's name if it is invalid.
878 (parse_riscv_dis_option_without_args): New function. Parse the options
879 without arguments.
880 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
881 parse the options without arguments first, and then handle the options
882 with arguments. Add the new option -Mpriv-spec, which has argument.
883 * riscv-dis.c (print_riscv_disassembler_options): Add description
884 about the new OBJDUMP option.
885
3d205eb4
PB		 8862020-05-19 Peter Bergner <bergner@linux.ibm.com>
887
888 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
889 WC values on POWER10 sync, dcbf and wait instructions.
890 (insert_pl, extract_pl): New functions.
891 (L2OPT, LS, WC): Use insert_ls and extract_ls.
892 (LS3): New , 3-bit L for sync.
893 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
894 (SC2, PL): New, 2-bit SC and PL for sync and wait.
895 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
896 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
897 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
898 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
899 <wait>: Enable PL operand on POWER10.
900 <dcbf>: Enable L3OPT operand on POWER10.
901 <sync>: Enable SC2 operand on POWER10.
902
a501eb44
SH		 9032020-05-19 Stafford Horne <shorne@gmail.com>
904
905 PR 25184
906 * or1k-asm.c: Regenerate.
907 * or1k-desc.c: Regenerate.
908 * or1k-desc.h: Regenerate.
909 * or1k-dis.c: Regenerate.
910 * or1k-ibld.c: Regenerate.
911 * or1k-opc.c: Regenerate.
912 * or1k-opc.h: Regenerate.
913 * or1k-opinst.c: Regenerate.
914
3b646889
AM		 9152020-05-11 Alan Modra <amodra@gmail.com>
916
917 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
918 xsmaxcqp, xsmincqp.
919
9cc4ce88
AM		 9202020-05-11 Alan Modra <amodra@gmail.com>
921
922 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
923 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
924
5d57bc3f
AM		 9252020-05-11 Alan Modra <amodra@gmail.com>
926
927 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
928
66ef5847
AM		 9292020-05-11 Alan Modra <amodra@gmail.com>
930
931 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
932 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
933
4f3e9537
PB		 9342020-05-11 Peter Bergner <bergner@linux.ibm.com>
935
936 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
937 mnemonics.
938
ec40e91c
AM		 9392020-05-11 Alan Modra <amodra@gmail.com>
940
941 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
942 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
943 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
944 (prefix_opcodes): Add xxeval.
945
d7e97a76
AM		 9462020-05-11 Alan Modra <amodra@gmail.com>
947
948 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
949 xxgenpcvwm, xxgenpcvdm.
950
fdefed7c
AM		 9512020-05-11 Alan Modra <amodra@gmail.com>
952
953 * ppc-opc.c (MP, VXVAM_MASK): Define.
954 (VXVAPS_MASK): Use VXVA_MASK.
955 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
956 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
957 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
958 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
959
aa3c112f
AM		 9602020-05-11 Alan Modra <amodra@gmail.com>
961 Peter Bergner <bergner@linux.ibm.com>
962
963 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
964 New functions.
965 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
966 YMSK2, XA6a, XA6ap, XB6a entries.
967 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
968 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
969 (PPCVSX4): Define.
970 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
971 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
972 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
973 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
974 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
975 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
976 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
977 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
978 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
979 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
980 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
981 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
982 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
983 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
984
6edbfd3b
AM		 9852020-05-11 Alan Modra <amodra@gmail.com>
986
987 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
988 (insert_xts, extract_xts): New functions.
989 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
990 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
991 (VXRC_MASK, VXSH_MASK): Define.
992 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
993 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
994 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
995 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
996 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
997 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
998 xxblendvh, xxblendvw, xxblendvd, xxpermx.
999
c7d7aea2
AM		 10002020-05-11 Alan Modra <amodra@gmail.com>
1001
1002 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1003 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1004 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1005 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1006 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1007
94ba9882
AM		 10082020-05-11 Alan Modra <amodra@gmail.com>
1009
1010 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1011 (XTP, DQXP, DQXP_MASK): Define.
1012 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1013 (prefix_opcodes): Add plxvp and pstxvp.
1014
f4791f1a
AM		 10152020-05-11 Alan Modra <amodra@gmail.com>
1016
1017 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1018 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1019 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1020
3ff0a5ba
PB		 10212020-05-11 Peter Bergner <bergner@linux.ibm.com>
1022
1023 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1024
afef4fe9
PB		 10252020-05-11 Peter Bergner <bergner@linux.ibm.com>
1026
1027 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1028 (L1OPT): Define.
1029 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1030
1224c05d
PB		 10312020-05-11 Peter Bergner <bergner@linux.ibm.com>
1032
1033 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1034
6bbb0c05
AM		 10352020-05-11 Alan Modra <amodra@gmail.com>
1036
1037 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1038
7c1f4227
AM		 10392020-05-11 Alan Modra <amodra@gmail.com>
1040
1041 * ppc-dis.c (ppc_opts): Add "power10" entry.
1042 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1043 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1044
73199c2b
NC		 10452020-05-11 Nick Clifton <nickc@redhat.com>
1046
1047 * po/fr.po: Updated French translation.
1048
09c1e68a
AC		 10492020-04-30 Alex Coplan <alex.coplan@arm.com>
1050
1051 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1052 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1053 (operand_general_constraint_met_p): validate
1054 AARCH64_OPND_UNDEFINED.
1055 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1056 for FLD_imm16_2.
1057 * aarch64-asm-2.c: Regenerated.
1058 * aarch64-dis-2.c: Regenerated.
1059 * aarch64-opc-2.c: Regenerated.
1060
9654d51a
NC		 10612020-04-29 Nick Clifton <nickc@redhat.com>
1062
1063 PR 22699
1064 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1065 and SETRC insns.
1066
c2e71e57
NC		 10672020-04-29 Nick Clifton <nickc@redhat.com>
1068
1069 * po/sv.po: Updated Swedish translation.
1070
5c936ef5
NC		 10712020-04-29 Nick Clifton <nickc@redhat.com>
1072
1073 PR 22699
1074 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1075 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1076 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1077 IMM0_8U case.
1078
bb2a1453
AS		 10792020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1080
1081 PR 25848
1082 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1083 cmpi only on m68020up and cpu32.
1084
c2e5c986
SD		 10852020-04-20 Sudakshina Das <sudi.das@arm.com>
1086
1087 * aarch64-asm.c (aarch64_ins_none): New.
1088 * aarch64-asm.h (ins_none): New declaration.
1089 * aarch64-dis.c (aarch64_ext_none): New.
1090 * aarch64-dis.h (ext_none): New declaration.
1091 * aarch64-opc.c (aarch64_print_operand): Update case for
1092 AARCH64_OPND_BARRIER_PSB.
1093 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1094 (AARCH64_OPERANDS): Update inserter/extracter for
1095 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1096 * aarch64-asm-2.c: Regenerated.
1097 * aarch64-dis-2.c: Regenerated.
1098 * aarch64-opc-2.c: Regenerated.
1099
8a6e1d1d
SD		 11002020-04-20 Sudakshina Das <sudi.das@arm.com>
1101
1102 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1103 (aarch64_feature_ras, RAS): Likewise.
1104 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1105 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1106 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1107 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1108 * aarch64-asm-2.c: Regenerated.
1109 * aarch64-dis-2.c: Regenerated.
1110 * aarch64-opc-2.c: Regenerated.
1111
e409955d
FS		 11122020-04-17 Fredrik Strupe <fredrik@strupe.net>
1113
1114 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1115 (print_insn_neon): Support disassembly of conditional
1116 instructions.
1117
c54a9b56
DF		 11182020-02-16 David Faust <david.faust@oracle.com>
1119
1120 * bpf-desc.c: Regenerate.
1121 * bpf-desc.h: Likewise.
1122 * bpf-opc.c: Regenerate.
1123 * bpf-opc.h: Likewise.
1124
bb651e8b
CL		 11252020-04-07 Lili Cui <lili.cui@intel.com>
1126
1127 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1128 (prefix_table): New instructions (see prefixes above).
1129 (rm_table): Likewise
1130 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1131 CPU_ANY_TSXLDTRK_FLAGS.
1132 (cpu_flags): Add CpuTSXLDTRK.
1133 * i386-opc.h (enum): Add CpuTSXLDTRK.
1134 (i386_cpu_flags): Add cputsxldtrk.
1135 * i386-opc.tbl: Add XSUSPLDTRK insns.
1136 * i386-init.h: Regenerate.
1137 * i386-tbl.h: Likewise.
1138
4b27d27c
L		 11392020-04-02 Lili Cui <lili.cui@intel.com>
1140
1141 * i386-dis.c (prefix_table): New instructions serialize.
1142 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1143 CPU_ANY_SERIALIZE_FLAGS.
1144 (cpu_flags): Add CpuSERIALIZE.
1145 * i386-opc.h (enum): Add CpuSERIALIZE.
1146 (i386_cpu_flags): Add cpuserialize.
1147 * i386-opc.tbl: Add SERIALIZE insns.
1148 * i386-init.h: Regenerate.
1149 * i386-tbl.h: Likewise.
1150
832a5807
AM		 11512020-03-26 Alan Modra <amodra@gmail.com>
1152
1153 * disassemble.h (opcodes_assert): Declare.
1154 (OPCODES_ASSERT): Define.
1155 * disassemble.c: Don't include assert.h. Include opintl.h.
1156 (opcodes_assert): New function.
1157 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1158 (bfd_h8_disassemble): Reduce size of data array. Correctly
1159 calculate maxlen. Omit insn decoding when insn length exceeds
1160 maxlen. Exit from nibble loop when looking for E, before
1161 accessing next data byte. Move processing of E outside loop.
1162 Replace tests of maxlen in loop with assertions.
1163
4c4addbe
AM		 11642020-03-26 Alan Modra <amodra@gmail.com>
1165
1166 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1167
a18cd0ca
AM		 11682020-03-25 Alan Modra <amodra@gmail.com>
1169
1170 * z80-dis.c (suffix): Init mybuf.
1171
57cb32b3
AM		 11722020-03-22 Alan Modra <amodra@gmail.com>
1173
1174 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1175 successflly read from section.
1176
beea5cc1
AM		 11772020-03-22 Alan Modra <amodra@gmail.com>
1178
1179 * arc-dis.c (find_format): Use ISO C string concatenation rather
1180 than line continuation within a string. Don't access needs_limm
1181 before testing opcode != NULL.
1182
03704c77
AM		 11832020-03-22 Alan Modra <amodra@gmail.com>
1184
1185 * ns32k-dis.c (print_insn_arg): Update comment.
1186 (print_insn_ns32k): Reduce size of index_offset array, and
1187 initialize, passing -1 to print_insn_arg for args that are not
1188 an index. Don't exit arg loop early. Abort on bad arg number.
1189
d1023b5d
AM		 11902020-03-22 Alan Modra <amodra@gmail.com>
1191
1192 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1193 * s12z-opc.c: Formatting.
1194 (operands_f): Return an int.
1195 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1196 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1197 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1198 (exg_sex_discrim): Likewise.
1199 (create_immediate_operand, create_bitfield_operand),
1200 (create_register_operand_with_size, create_register_all_operand),
1201 (create_register_all16_operand, create_simple_memory_operand),
1202 (create_memory_operand, create_memory_auto_operand): Don't
1203 segfault on malloc failure.
1204 (z_ext24_decode): Return an int status, negative on fail, zero
1205 on success.
1206 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1207 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1208 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1209 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1210 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1211 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1212 (loop_primitive_decode, shift_decode, psh_pul_decode),
1213 (bit_field_decode): Similarly.
1214 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1215 to return value, update callers.
1216 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1217 Don't segfault on NULL operand.
1218 (decode_operation): Return OP_INVALID on first fail.
1219 (decode_s12z): Check all reads, returning -1 on fail.
1220
340f3ac8
AM		 12212020-03-20 Alan Modra <amodra@gmail.com>
1222
1223 * metag-dis.c (print_insn_metag): Don't ignore status from
1224 read_memory_func.
1225
fe90ae8a
AM		 12262020-03-20 Alan Modra <amodra@gmail.com>
1227
1228 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1229 Initialize parts of buffer not written when handling a possible
1230 2-byte insn at end of section. Don't attempt decoding of such
1231 an insn by the 4-byte machinery.
1232
833d919c
AM		 12332020-03-20 Alan Modra <amodra@gmail.com>
1234
1235 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1236 partially filled buffer. Prevent lookup of 4-byte insns when
1237 only VLE 2-byte insns are possible due to section size. Print
1238 ".word" rather than ".long" for 2-byte leftovers.
1239
327ef784
NC		 12402020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1241
1242 PR 25641
1243 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1244
1673df32
JB		 12452020-03-13 Jan Beulich <jbeulich@suse.com>
1246
1247 * i386-dis.c (X86_64_0D): Rename to ...
1248 (X86_64_0E): ... this.
1249
384f3689
L		 12502020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1251
1252 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1253 * Makefile.in: Regenerated.
1254
865e2027
JB		 12552020-03-09 Jan Beulich <jbeulich@suse.com>
1256
1257 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1258 3-operand pseudos.
1259 * i386-tbl.h: Re-generate.
1260
2f13234b
JB		 12612020-03-09 Jan Beulich <jbeulich@suse.com>
1262
1263 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1264 vprot*, vpsha*, and vpshl*.
1265 * i386-tbl.h: Re-generate.
1266
3fabc179
JB		 12672020-03-09 Jan Beulich <jbeulich@suse.com>
1268
1269 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1270 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1271 * i386-tbl.h: Re-generate.
1272
3677e4c1
JB		 12732020-03-09 Jan Beulich <jbeulich@suse.com>
1274
1275 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1276 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1277 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1278 * i386-tbl.h: Re-generate.
1279
4c4898e8
JB		 12802020-03-09 Jan Beulich <jbeulich@suse.com>
1281
1282 * i386-gen.c (struct template_arg, struct template_instance,
1283 struct template_param, struct template, templates,
1284 parse_template, expand_templates): New.
1285 (process_i386_opcodes): Various local variables moved to
1286 expand_templates. Call parse_template and expand_templates.
1287 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1288 * i386-tbl.h: Re-generate.
1289
bc49bfd8
JB		 12902020-03-06 Jan Beulich <jbeulich@suse.com>
1291
1292 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1293 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1294 register and memory source templates. Replace VexW= by VexW*
1295 where applicable.
1296 * i386-tbl.h: Re-generate.
1297
4873e243
JB		 12982020-03-06 Jan Beulich <jbeulich@suse.com>
1299
1300 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1301 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1302 * i386-tbl.h: Re-generate.
1303
672a349b
JB		 13042020-03-06 Jan Beulich <jbeulich@suse.com>
1305
1306 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1307 * i386-tbl.h: Re-generate.
1308
4ed21b58
JB		 13092020-03-06 Jan Beulich <jbeulich@suse.com>
1310
1311 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1312 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1313 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1314 VexW0 on SSE2AVX variants.
1315 (vmovq): Drop NoRex64 from XMM/XMM variants.
1316 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1317 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1318 applicable use VexW0.
1319 * i386-tbl.h: Re-generate.
1320
643bb870
JB		 13212020-03-06 Jan Beulich <jbeulich@suse.com>
1322
1323 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1324 * i386-opc.h (Rex64): Delete.
1325 (struct i386_opcode_modifier): Remove rex64 field.
1326 * i386-opc.tbl (crc32): Drop Rex64.
1327 Replace Rex64 with Size64 everywhere else.
1328 * i386-tbl.h: Re-generate.
1329
a23b33b3
JB		 13302020-03-06 Jan Beulich <jbeulich@suse.com>
1331
1332 * i386-dis.c (OP_E_memory): Exclude recording of used address
1333 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1334 addressed memory operands for MPX insns.
1335
a0497384
JB		 13362020-03-06 Jan Beulich <jbeulich@suse.com>
1337
1338 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1339 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1340 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1341 (ptwrite): Split into non-64-bit and 64-bit forms.
1342 * i386-tbl.h: Re-generate.
1343
b630c145
JB		 13442020-03-06 Jan Beulich <jbeulich@suse.com>
1345
1346 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1347 template.
1348 * i386-tbl.h: Re-generate.
1349
a847e322
JB		 13502020-03-04 Jan Beulich <jbeulich@suse.com>
1351
1352 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1353 (prefix_table): Move vmmcall here. Add vmgexit.
1354 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1355 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1356 (cpu_flags): Add CpuSEV_ES entry.
1357 * i386-opc.h (CpuSEV_ES): New.
1358 (union i386_cpu_flags): Add cpusev_es field.
1359 * i386-opc.tbl (vmgexit): New.
1360 * i386-init.h, i386-tbl.h: Re-generate.
1361
3cd7f3e3
L		 13622020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1363
1364 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1365 with MnemonicSize.
1366 * i386-opc.h (IGNORESIZE): New.
1367 (DEFAULTSIZE): Likewise.
1368 (IgnoreSize): Removed.
1369 (DefaultSize): Likewise.
1370 (MnemonicSize): New.
1371 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1372 mnemonicsize.
1373 * i386-opc.tbl (IgnoreSize): New.
1374 (DefaultSize): Likewise.
1375 * i386-tbl.h: Regenerated.
1376
b8ba1385
SB		 13772020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1378
1379 PR 25627
1380 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1381 instructions.
1382
10d97a0f
L		 13832020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1384
1385 PR gas/25622
1386 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1387 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1388 * i386-tbl.h: Regenerated.
1389
dc1e8a47
AM		 13902020-02-26 Alan Modra <amodra@gmail.com>
1391
1392 * aarch64-asm.c: Indent labels correctly.
1393 * aarch64-dis.c: Likewise.
1394 * aarch64-gen.c: Likewise.
1395 * aarch64-opc.c: Likewise.
1396 * alpha-dis.c: Likewise.
1397 * i386-dis.c: Likewise.
1398 * nds32-asm.c: Likewise.
1399 * nfp-dis.c: Likewise.
1400 * visium-dis.c: Likewise.
1401
265b4673
CZ		 14022020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1403
1404 * arc-regs.h (int_vector_base): Make it available for all ARC
1405 CPUs.
1406
bd0cf5a6
NC		 14072020-02-20 Nelson Chu <nelson.chu@sifive.com>
1408
1409 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1410 changed.
1411
fa164239
JW		 14122020-02-19 Nelson Chu <nelson.chu@sifive.com>
1413
1414 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1415 c.mv/c.li if rs1 is zero.
1416
272a84b1
L		 14172020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1418
1419 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1420 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1421 CPU_POPCNT_FLAGS.
1422 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1423 * i386-opc.h (CpuABM): Removed.
1424 (CpuPOPCNT): New.
1425 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1426 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1427 popcnt. Remove CpuABM from lzcnt.
1428 * i386-init.h: Regenerated.
1429 * i386-tbl.h: Likewise.
1430
1f730c46
JB		 14312020-02-17 Jan Beulich <jbeulich@suse.com>
1432
1433 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1434 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1435 VexW1 instead of open-coding them.
1436 * i386-tbl.h: Re-generate.
1437
c8f8eebc
JB		 14382020-02-17 Jan Beulich <jbeulich@suse.com>
1439
1440 * i386-opc.tbl (AddrPrefixOpReg): Define.
1441 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1442 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1443 templates. Drop NoRex64.
1444 * i386-tbl.h: Re-generate.
1445
b9915cbc
JB		 14462020-02-17 Jan Beulich <jbeulich@suse.com>
1447
1448 PR gas/6518
1449 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1450 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1451 into Intel syntax instance (with Unpsecified) and AT&T one
1452 (without).
1453 (vcvtneps2bf16): Likewise, along with folding the two so far
1454 separate ones.
1455 * i386-tbl.h: Re-generate.
1456
ce504911
L		 14572020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1458
1459 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1460 CPU_ANY_SSE4A_FLAGS.
1461
dabec65d
AM		 14622020-02-17 Alan Modra <amodra@gmail.com>
1463
1464 * i386-gen.c (cpu_flag_init): Correct last change.
1465
af5c13b0
L		 14662020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1467
1468 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1469 CPU_ANY_SSE4_FLAGS.
1470
6867aac0
L		 14712020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1472
1473 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1474 (movzx): Likewise.
1475
65fca059
JB		 14762020-02-14 Jan Beulich <jbeulich@suse.com>
1477
1478 PR gas/25438
1479 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1480 destination for Cpu64-only variant.
1481 (movzx): Fold patterns.
1482 * i386-tbl.h: Re-generate.
1483
7deea9aa
JB		 14842020-02-13 Jan Beulich <jbeulich@suse.com>
1485
1486 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1487 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1488 CPU_ANY_SSE4_FLAGS entry.
1489 * i386-init.h: Re-generate.
1490
6c0946d0
JB		 14912020-02-12 Jan Beulich <jbeulich@suse.com>
1492
1493 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1494 with Unspecified, making the present one AT&T syntax only.
1495 * i386-tbl.h: Re-generate.
1496
ddb56fe6
JB		 14972020-02-12 Jan Beulich <jbeulich@suse.com>
1498
1499 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1500 * i386-tbl.h: Re-generate.
1501
5990e377
JB		 15022020-02-12 Jan Beulich <jbeulich@suse.com>
1503
1504 PR gas/24546
1505 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1506 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1507 Amd64 and Intel64 templates.
1508 (call, jmp): Likewise for far indirect variants. Dro
1509 Unspecified.
1510 * i386-tbl.h: Re-generate.
1511
50128d0c
JB		 15122020-02-11 Jan Beulich <jbeulich@suse.com>
1513
1514 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1515 * i386-opc.h (ShortForm): Delete.
1516 (struct i386_opcode_modifier): Remove shortform field.
1517 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1518 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1519 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1520 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1521 Drop ShortForm.
1522 * i386-tbl.h: Re-generate.
1523
1e05b5c4
JB		 15242020-02-11 Jan Beulich <jbeulich@suse.com>
1525
1526 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1527 fucompi): Drop ShortForm from operand-less templates.
1528 * i386-tbl.h: Re-generate.
1529
2f5dd314
AM		 15302020-02-11 Alan Modra <amodra@gmail.com>
1531
1532 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1533 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1534 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1535 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1536 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1537
5aae9ae9
MM		 15382020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1539
1540 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1541 (cde_opcodes): Add VCX* instructions.
1542
4934a27c
MM		 15432020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1544 Matthew Malcomson <matthew.malcomson@arm.com>
1545
1546 * arm-dis.c (struct cdeopcode32): New.
1547 (CDE_OPCODE): New macro.
1548 (cde_opcodes): New disassembly table.
1549 (regnames): New option to table.
1550 (cde_coprocs): New global variable.
1551 (print_insn_cde): New
1552 (print_insn_thumb32): Use print_insn_cde.
1553 (parse_arm_disassembler_options): Parse coprocN args.
1554
4b5aaf5f
L		 15552020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1556
1557 PR gas/25516
1558 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1559 with ISA64.
1560 * i386-opc.h (AMD64): Removed.
1561 (Intel64): Likewose.
1562 (AMD64): New.
1563 (INTEL64): Likewise.
1564 (INTEL64ONLY): Likewise.
1565 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1566 * i386-opc.tbl (Amd64): New.
1567 (Intel64): Likewise.
1568 (Intel64Only): Likewise.
1569 Replace AMD64 with Amd64. Update sysenter/sysenter with
1570 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1571 * i386-tbl.h: Regenerated.
1572
9fc0b501
SB		 15732020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1574
1575 PR 25469
1576 * z80-dis.c: Add support for GBZ80 opcodes.
1577
c5d7be0c
AM		 15782020-02-04 Alan Modra <amodra@gmail.com>
1579
1580 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1581
44e4546f
AM		 15822020-02-03 Alan Modra <amodra@gmail.com>
1583
1584 * m32c-ibld.c: Regenerate.
1585
b2b1453a
AM		 15862020-02-01 Alan Modra <amodra@gmail.com>
1587
1588 * frv-ibld.c: Regenerate.
1589
4102be5c
JB		 15902020-01-31 Jan Beulich <jbeulich@suse.com>
1591
1592 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1593 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1594 (OP_E_memory): Replace xmm_mdq_mode case label by
1595 vex_scalar_w_dq_mode one.
1596 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1597
825bd36c
JB		 15982020-01-31 Jan Beulich <jbeulich@suse.com>
1599
1600 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1601 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1602 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1603 (intel_operand_size): Drop vex_w_dq_mode case label.
1604
c3036ed0
RS		 16052020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1606
1607 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1608 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1609
0c115f84
AM		 16102020-01-30 Alan Modra <amodra@gmail.com>
1611
1612 * m32c-ibld.c: Regenerate.
1613
bd434cc4
JM		 16142020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1615
1616 * bpf-opc.c: Regenerate.
1617
aeab2b26
JB		 16182020-01-30 Jan Beulich <jbeulich@suse.com>
1619
1620 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1621 (dis386): Use them to replace C2/C3 table entries.
1622 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1623 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1624 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1625 * i386-tbl.h: Re-generate.
1626
62b3f548
JB		 16272020-01-30 Jan Beulich <jbeulich@suse.com>
1628
1629 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1630 forms.
1631 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1632 DefaultSize.
1633 * i386-tbl.h: Re-generate.
1634
1bd8ae10
AM		 16352020-01-30 Alan Modra <amodra@gmail.com>
1636
1637 * tic4x-dis.c (tic4x_dp): Make unsigned.
1638
bc31405e
L		 16392020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1640 Jan Beulich <jbeulich@suse.com>
1641
1642 PR binutils/25445
1643 * i386-dis.c (MOVSXD_Fixup): New function.
1644 (movsxd_mode): New enum.
1645 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1646 (intel_operand_size): Handle movsxd_mode.
1647 (OP_E_register): Likewise.
1648 (OP_G): Likewise.
1649 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1650 register on movsxd. Add movsxd with 16-bit destination register
1651 for AMD64 and Intel64 ISAs.
1652 * i386-tbl.h: Regenerated.
1653
7568c93b
TC		 16542020-01-27 Tamar Christina <tamar.christina@arm.com>
1655
1656 PR 25403
1657 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1658 * aarch64-asm-2.c: Regenerate
1659 * aarch64-dis-2.c: Likewise.
1660 * aarch64-opc-2.c: Likewise.
1661
c006a730
JB		 16622020-01-21 Jan Beulich <jbeulich@suse.com>
1663
1664 * i386-opc.tbl (sysret): Drop DefaultSize.
1665 * i386-tbl.h: Re-generate.
1666
c906a69a
JB		 16672020-01-21 Jan Beulich <jbeulich@suse.com>
1668
1669 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1670 Dword.
1671 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1672 * i386-tbl.h: Re-generate.
1673
26916852
NC		 16742020-01-20 Nick Clifton <nickc@redhat.com>
1675
1676 * po/de.po: Updated German translation.
1677 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1678 * po/uk.po: Updated Ukranian translation.
1679
4d6cbb64
AM		 16802020-01-20 Alan Modra <amodra@gmail.com>
1681
1682 * hppa-dis.c (fput_const): Remove useless cast.
1683
2bddb71a
AM		 16842020-01-20 Alan Modra <amodra@gmail.com>
1685
1686 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1687
1b1bb2c6
NC		 16882020-01-18 Nick Clifton <nickc@redhat.com>
1689
1690 * configure: Regenerate.
1691 * po/opcodes.pot: Regenerate.
1692
ae774686
NC		 16932020-01-18 Nick Clifton <nickc@redhat.com>
1694
1695 Binutils 2.34 branch created.
1696
07f1f3aa
CB		 16972020-01-17 Christian Biesinger <cbiesinger@google.com>
1698
1699 * opintl.h: Fix spelling error (seperate).
1700
42e04b36
L		 17012020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1702
1703 * i386-opc.tbl: Add {vex} pseudo prefix.
1704 * i386-tbl.h: Regenerated.
1705
2da2eaf4
AV		 17062020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1707
1708 PR 25376
1709 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1710 (neon_opcodes): Likewise.
1711 (select_arm_features): Make sure we enable MVE bits when selecting
1712 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1713 any architecture.
1714
d0849eed
JB		 17152020-01-16 Jan Beulich <jbeulich@suse.com>
1716
1717 * i386-opc.tbl: Drop stale comment from XOP section.
1718
9cf70a44
JB		 17192020-01-16 Jan Beulich <jbeulich@suse.com>
1720
1721 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1722 (extractps): Add VexWIG to SSE2AVX forms.
1723 * i386-tbl.h: Re-generate.
1724
4814632e
JB		 17252020-01-16 Jan Beulich <jbeulich@suse.com>
1726
1727 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1728 Size64 from and use VexW1 on SSE2AVX forms.
1729 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1730 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1731 * i386-tbl.h: Re-generate.
1732
aad09917
AM		 17332020-01-15 Alan Modra <amodra@gmail.com>
1734
1735 * tic4x-dis.c (tic4x_version): Make unsigned long.
1736 (optab, optab_special, registernames): New file scope vars.
1737 (tic4x_print_register): Set up registernames rather than
1738 malloc'd registertable.
1739 (tic4x_disassemble): Delete optable and optable_special. Use
1740 optab and optab_special instead. Throw away old optab,
1741 optab_special and registernames when info->mach changes.
1742
7a6bf3be
SB		 17432020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1744
1745 PR 25377
1746 * z80-dis.c (suffix): Use .db instruction to generate double
1747 prefix.
1748
ca1eaac0
AM		 17492020-01-14 Alan Modra <amodra@gmail.com>
1750
1751 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1752 values to unsigned before shifting.
1753
1d67fe3b
TT		 17542020-01-13 Thomas Troeger <tstroege@gmx.de>
1755
1756 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1757 flow instructions.
1758 (print_insn_thumb16, print_insn_thumb32): Likewise.
1759 (print_insn): Initialize the insn info.
1760 * i386-dis.c (print_insn): Initialize the insn info fields, and
1761 detect jumps.
1762
5e4f7e05
CZ		 17632012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1764
1765 * arc-opc.c (C_NE): Make it required.
1766
b9fe6b8a
CZ		 17672012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1768
1769 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1770 reserved register name.
1771
90dee485
AM		 17722020-01-13 Alan Modra <amodra@gmail.com>
1773
1774 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1775 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1776
febda64f
AM		 17772020-01-13 Alan Modra <amodra@gmail.com>
1778
1779 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1780 result of wasm_read_leb128 in a uint64_t and check that bits
1781 are not lost when copying to other locals. Use uint32_t for
1782 most locals. Use PRId64 when printing int64_t.
1783
df08b588
AM		 17842020-01-13 Alan Modra <amodra@gmail.com>
1785
1786 * score-dis.c: Formatting.
1787 * score7-dis.c: Formatting.
1788
b2c759ce
AM		 17892020-01-13 Alan Modra <amodra@gmail.com>
1790
1791 * score-dis.c (print_insn_score48): Use unsigned variables for
1792 unsigned values. Don't left shift negative values.
1793 (print_insn_score32): Likewise.
1794 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1795
5496abe1
AM		 17962020-01-13 Alan Modra <amodra@gmail.com>
1797
1798 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1799
202e762b
AM		 18002020-01-13 Alan Modra <amodra@gmail.com>
1801
1802 * fr30-ibld.c: Regenerate.
1803
7ef412cf
AM		 18042020-01-13 Alan Modra <amodra@gmail.com>
1805
1806 * xgate-dis.c (print_insn): Don't left shift signed value.
1807 (ripBits): Formatting, use 1u.
1808
7f578b95
AM		 18092020-01-10 Alan Modra <amodra@gmail.com>
1810
1811 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1812 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1813
441af85b
AM		 18142020-01-10 Alan Modra <amodra@gmail.com>
1815
1816 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1817 and XRREG value earlier to avoid a shift with negative exponent.
1818 * m10200-dis.c (disassemble): Similarly.
1819
bce58db4
NC		 18202020-01-09 Nick Clifton <nickc@redhat.com>
1821
1822 PR 25224
1823 * z80-dis.c (ld_ii_ii): Use correct cast.
1824
40c75bc8
SB		 18252020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1826
1827 PR 25224
1828 * z80-dis.c (ld_ii_ii): Use character constant when checking
1829 opcode byte value.
1830
d835a58b
JB		 18312020-01-09 Jan Beulich <jbeulich@suse.com>
1832
1833 * i386-dis.c (SEP_Fixup): New.
1834 (SEP): Define.
1835 (dis386_twobyte): Use it for sysenter/sysexit.
1836 (enum x86_64_isa): Change amd64 enumerator to value 1.
1837 (OP_J): Compare isa64 against intel64 instead of amd64.
1838 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1839 forms.
1840 * i386-tbl.h: Re-generate.
1841
030a2e78
AM		 18422020-01-08 Alan Modra <amodra@gmail.com>
1843
1844 * z8k-dis.c: Include libiberty.h
1845 (instr_data_s): Make max_fetched unsigned.
1846 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1847 Don't exceed byte_info bounds.
1848 (output_instr): Make num_bytes unsigned.
1849 (unpack_instr): Likewise for nibl_count and loop.
1850 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1851 idx unsigned.
1852 * z8k-opc.h: Regenerate.
1853
bb82aefe
SV		 18542020-01-07 Shahab Vahedi <shahab@synopsys.com>
1855
1856 * arc-tbl.h (llock): Use 'LLOCK' as class.
1857 (llockd): Likewise.
1858 (scond): Use 'SCOND' as class.
1859 (scondd): Likewise.
1860 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1861 (scondd): Likewise.
1862
cc6aa1a6
AM		 18632020-01-06 Alan Modra <amodra@gmail.com>
1864
1865 * m32c-ibld.c: Regenerate.
1866
660e62b1
AM		 18672020-01-06 Alan Modra <amodra@gmail.com>
1868
1869 PR 25344
1870 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1871 Peek at next byte to prevent recursion on repeated prefix bytes.
1872 Ensure uninitialised "mybuf" is not accessed.
1873 (print_insn_z80): Don't zero n_fetch and n_used here,..
1874 (print_insn_z80_buf): ..do it here instead.
1875
c9ae58fe
AM		 18762020-01-04 Alan Modra <amodra@gmail.com>
1877
1878 * m32r-ibld.c: Regenerate.
1879
5f57d4ec
AM		 18802020-01-04 Alan Modra <amodra@gmail.com>
1881
1882 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1883
2c5c1196
AM		 18842020-01-04 Alan Modra <amodra@gmail.com>
1885
1886 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1887
2e98c6c5
AM		 18882020-01-04 Alan Modra <amodra@gmail.com>
1889
1890 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1891
567dfba2
JB		 18922020-01-03 Jan Beulich <jbeulich@suse.com>
1893
5437a02a
JB		 1894 * aarch64-tbl.h (aarch64_opcode_table): Use
1895 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1896
18972020-01-03 Jan Beulich <jbeulich@suse.com>
1898
1899 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1900 forms of SUDOT and USDOT.
1901
8c45011a
JB		 19022020-01-03 Jan Beulich <jbeulich@suse.com>
1903
5437a02a 1904 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1905 uzip{1,2}.
1906 * opcodes/aarch64-dis-2.c: Re-generate.
1907
f4950f76
JB		 19082020-01-03 Jan Beulich <jbeulich@suse.com>
1909
5437a02a 1910 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1911 FMMLA encoding.
1912 * opcodes/aarch64-dis-2.c: Re-generate.
1913
6655dba2
SB		 19142020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1915
1916 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1917
b14ce8bf
AM		 19182020-01-01 Alan Modra <amodra@gmail.com>
1919
1920 Update year range in copyright notice of all files.
1921
0b114740 1922For older changes see ChangeLog-2019
3499769a 1923\f
0b114740 1924Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1925
1926Copying and distribution of this file, with or without modification,
1927are permitted in any medium without royalty provided the copyright
1928notice and this notice are preserved.
1929
1930Local Variables:
1931mode: change-log
1932left-margin: 8
1933fill-column: 74
1934version-control: never
1935End:
GDB Binutils - Deliverables
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