projects / deliverable / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
New option falkor for Qualcomm server part
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d039fef3
L		 12016-11-03 H.J. Lu <hongjiu.lu@intel.com>
2
3 * i386-dis.c (REG_82): Removed.
4 (X86_64_82_REG_0): Likewise.
5 (X86_64_82_REG_1): Likewise.
6 (X86_64_82_REG_2): Likewise.
7 (X86_64_82_REG_3): Likewise.
8 (X86_64_82_REG_4): Likewise.
9 (X86_64_82_REG_5): Likewise.
10 (X86_64_82_REG_6): Likewise.
11 (X86_64_82_REG_7): Likewise.
12 (X86_64_82): New.
13 (dis386): Use X86_64_82 instead of REG_82.
14 (reg_table): Remove REG_82.
15 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
16 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
17 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
18 X86_64_82_REG_7.
19
8b89fe14
L		 202016-11-03 H.J. Lu <hongjiu.lu@intel.com>
21
22 PR binutils/20754
23 * i386-dis.c (REG_82): New.
24 (X86_64_82_REG_0): Likewise.
25 (X86_64_82_REG_1): Likewise.
26 (X86_64_82_REG_2): Likewise.
27 (X86_64_82_REG_3): Likewise.
28 (X86_64_82_REG_4): Likewise.
29 (X86_64_82_REG_5): Likewise.
30 (X86_64_82_REG_6): Likewise.
31 (X86_64_82_REG_7): Likewise.
32 (dis386): Use REG_82.
33 (reg_table): Add REG_82.
34 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
35 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
36 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
37
7148c369
L		 382016-11-03 H.J. Lu <hongjiu.lu@intel.com>
39
40 * i386-dis.c (REG_82): Renamed to ...
41 (REG_83): This.
42 (dis386): Updated.
43 (reg_table): Likewise.
44
47acf0bd
IT		 452016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
46
47 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
48 * i386-dis-evex.h (evex_table): Updated.
49 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
50 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
51 (cpu_flags): Add CpuAVX512_4VNNIW.
52 * i386-opc.h (enum): (AVX512_4VNNIW): New.
53 (i386_cpu_flags): Add cpuavx512_4vnniw.
54 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
55 * i386-init.h: Regenerate.
56 * i386-tbl.h: Ditto.
57
920d2ddc
IT		 582016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
59
60 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
61 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
62 * i386-dis-evex.h (evex_table): Updated.
63 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
64 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
65 (cpu_flags): Add CpuAVX512_4FMAPS.
66 (opcode_modifiers): Add ImplicitQuadGroup modifier.
67 * i386-opc.h (AVX512_4FMAP): New.
68 (i386_cpu_flags): Add cpuavx512_4fmaps.
69 (ImplicitQuadGroup): New.
70 (i386_opcode_modifier): Add implicitquadgroup.
71 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
72 * i386-init.h: Regenerate.
73 * i386-tbl.h: Ditto.
74
e23eba97
NC		 752016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
76 Andrew Waterman <andrew@sifive.com>
77
78 Add support for RISC-V architecture.
79 * configure.ac: Add entry for bfd_riscv_arch.
80 * configure: Regenerate.
81 * disassemble.c (disassembler): Add support for riscv.
82 (disassembler_usage): Likewise.
83 * riscv-dis.c: New file.
84 * riscv-opc.c: New file.
85
b5cefcca
L		 862016-10-21 H.J. Lu <hongjiu.lu@intel.com>
87
88 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
89 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
90 (rm_table): Update the RM_0FAE_REG_7 entry.
91 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
92 (cpu_flags): Remove CpuPCOMMIT.
93 * i386-opc.h (CpuPCOMMIT): Removed.
94 (i386_cpu_flags): Remove cpupcommit.
95 * i386-opc.tbl: Remove pcommit.
96 * i386-init.h: Regenerated.
97 * i386-tbl.h: Likewise.
98
9889cbb1
L		 992016-10-20 H.J. Lu <hongjiu.lu@intel.com>
100
101 PR binutis/20705
102 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
103 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
104 32-bit mode. Don't check vex.register_specifier in 32-bit
105 mode.
106 (OP_VEX): Check for invalid mask registers.
107
28596323
L		 1082016-10-18 H.J. Lu <hongjiu.lu@intel.com>
109
110 PR binutis/20699
111 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
112 sizeflag.
113
da8d7d66
L		 1142016-10-18 H.J. Lu <hongjiu.lu@intel.com>
115
116 PR binutis/20704
117 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
118
eaf02703
MR		 1192016-10-18 Maciej W. Rozycki <macro@imgtec.com>
120
121 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
122 local variable to `index_regno'.
123
decf5bd1
CM		 1242016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
125
126 * arc-tbl.h: Removed any "inv.+" instructions from the table.
127
e5b06ef0
CZ		 1282016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
129
130 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
131 usage on ISA basis.
132
93562a34
JW		 1332016-10-11 Jiong Wang <jiong.wang@arm.com>
134
135 PR target/20666
136 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
137
362c0c4d
JW		 1382016-10-07 Jiong Wang <jiong.wang@arm.com>
139
140 PR target/20667
141 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
142 available.
143
1047201f
AM		 1442016-10-07 Alan Modra <amodra@gmail.com>
145
146 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
147
1a0670f3
AM		 1482016-10-06 Alan Modra <amodra@gmail.com>
149
150 * aarch64-opc.c: Spell fall through comments consistently.
151 * i386-dis.c: Likewise.
152 * aarch64-dis.c: Add missing fall through comments.
153 * aarch64-opc.c: Likewise.
154 * arc-dis.c: Likewise.
155 * arm-dis.c: Likewise.
156 * i386-dis.c: Likewise.
157 * m68k-dis.c: Likewise.
158 * mep-asm.c: Likewise.
159 * ns32k-dis.c: Likewise.
160 * sh-dis.c: Likewise.
161 * tic4x-dis.c: Likewise.
162 * tic6x-dis.c: Likewise.
163 * vax-dis.c: Likewise.
164
2b804145
AM		 1652016-10-06 Alan Modra <amodra@gmail.com>
166
167 * arc-ext.c (create_map): Add missing break.
168 * msp430-decode.opc (encode_as): Likewise.
169 * msp430-decode.c: Regenerate.
170
616ec358
AM		 1712016-10-06 Alan Modra <amodra@gmail.com>
172
173 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
174 * crx-dis.c (print_insn_crx): Likewise.
175
72da393d
L		 1762016-09-30 H.J. Lu <hongjiu.lu@intel.com>
177
178 PR binutils/20657
179 * i386-dis.c (putop): Don't assign alt twice.
180
744ce302
JW		 1812016-09-29 Jiong Wang <jiong.wang@arm.com>
182
183 PR target/20553
184 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
185
a5721ba2
AM		 1862016-09-29 Alan Modra <amodra@gmail.com>
187
188 * ppc-opc.c (L): Make compulsory.
189 (LOPT): New, optional form of L.
190 (HTM_R): Define as LOPT.
191 (L0, L1): Delete.
192 (L32OPT): New, optional for 32-bit L.
193 (L2OPT): New, 2-bit L for dcbf.
194 (SVC_LEC): Update.
195 (L2): Define.
196 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
197 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
198 <dcbf>: Use L2OPT.
199 <tlbiel, tlbie>: Use LOPT.
200 <wclr, wclrall>: Use L2.
201
c5da1932
VZ		 2022016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
203
204 * Makefile.in: Regenerate.
205 * configure: Likewise.
206
2b848ebd
CZ		 2072016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
208
209 * arc-ext-tbl.h (EXTINSN2OPF): Define.
210 (EXTINSN2OP): Use EXTINSN2OPF.
211 (bspeekm, bspop, modapp): New extension instructions.
212 * arc-opc.c (F_DNZ_ND): Define.
213 (F_DNZ_D): Likewise.
214 (F_SIZEB1): Changed.
215 (C_DNZ_D): Define.
216 (C_HARD): Changed.
217 * arc-tbl.h (dbnz): New instruction.
218 (prealloc): Allow it for ARC EM.
219 (xbfu): Likewise.
220
ad43e107
RS		 2212016-09-21 Richard Sandiford <richard.sandiford@arm.com>
222
223 * aarch64-opc.c (print_immediate_offset_address): Print spaces
224 after commas in addresses.
225 (aarch64_print_operand): Likewise.
226
ab3b8fcf
RS		 2272016-09-21 Richard Sandiford <richard.sandiford@arm.com>
228
229 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
230 rather than "should be" or "expected to be" in error messages.
231
bb7eff52
RS		 2322016-09-21 Richard Sandiford <richard.sandiford@arm.com>
233
234 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
235 (print_mnemonic_name): ...here.
236 (print_comment): New function.
237 (print_aarch64_insn): Call it.
238 * aarch64-opc.c (aarch64_conds): Add SVE names.
239 (aarch64_print_operand): Print alternative condition names in
240 a comment.
241
c0890d26
RS		 2422016-09-21 Richard Sandiford <richard.sandiford@arm.com>
243
244 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
245 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
246 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
247 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
248 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
249 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
250 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
251 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
252 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
253 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
254 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
255 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
256 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
257 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
258 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
259 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
260 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
261 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
262 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
263 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
264 (OP_SVE_XWU, OP_SVE_XXU): New macros.
265 (aarch64_feature_sve): New variable.
266 (SVE): New macro.
267 (_SVE_INSN): Likewise.
268 (aarch64_opcode_table): Add SVE instructions.
269 * aarch64-opc.h (extract_fields): Declare.
270 * aarch64-opc-2.c: Regenerate.
271 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
272 * aarch64-asm-2.c: Regenerate.
273 * aarch64-dis.c (extract_fields): Make global.
274 (do_misc_decoding): Handle the new SVE aarch64_ops.
275 * aarch64-dis-2.c: Regenerate.
276
116b6019
RS		 2772016-09-21 Richard Sandiford <richard.sandiford@arm.com>
278
279 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
280 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
281 aarch64_field_kinds.
282 * aarch64-opc.c (fields): Add corresponding entries.
283 * aarch64-asm.c (aarch64_get_variant): New function.
284 (aarch64_encode_variant_using_iclass): Likewise.
285 (aarch64_opcode_encode): Call it.
286 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
287 (aarch64_opcode_decode): Call it.
288
047cd301
RS		 2892016-09-21 Richard Sandiford <richard.sandiford@arm.com>
290
291 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
292 and FP register operands.
293 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
294 (FLD_SVE_Vn): New aarch64_field_kinds.
295 * aarch64-opc.c (fields): Add corresponding entries.
296 (aarch64_print_operand): Handle the new SVE core and FP register
297 operands.
298 * aarch64-opc-2.c: Regenerate.
299 * aarch64-asm-2.c: Likewise.
300 * aarch64-dis-2.c: Likewise.
301
165d4950
RS		 3022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
303
304 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
305 immediate operands.
306 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
307 * aarch64-opc.c (fields): Add corresponding entry.
308 (operand_general_constraint_met_p): Handle the new SVE FP immediate
309 operands.
310 (aarch64_print_operand): Likewise.
311 * aarch64-opc-2.c: Regenerate.
312 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
313 (ins_sve_float_zero_one): New inserters.
314 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
315 (aarch64_ins_sve_float_half_two): Likewise.
316 (aarch64_ins_sve_float_zero_one): Likewise.
317 * aarch64-asm-2.c: Regenerate.
318 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
319 (ext_sve_float_zero_one): New extractors.
320 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
321 (aarch64_ext_sve_float_half_two): Likewise.
322 (aarch64_ext_sve_float_zero_one): Likewise.
323 * aarch64-dis-2.c: Regenerate.
324
e950b345
RS		 3252016-09-21 Richard Sandiford <richard.sandiford@arm.com>
326
327 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
328 integer immediate operands.
329 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
330 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
331 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
332 * aarch64-opc.c (fields): Add corresponding entries.
333 (operand_general_constraint_met_p): Handle the new SVE integer
334 immediate operands.
335 (aarch64_print_operand): Likewise.
336 (aarch64_sve_dupm_mov_immediate_p): New function.
337 * aarch64-opc-2.c: Regenerate.
338 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
339 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
340 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
341 (aarch64_ins_limm): ...here.
342 (aarch64_ins_inv_limm): New function.
343 (aarch64_ins_sve_aimm): Likewise.
344 (aarch64_ins_sve_asimm): Likewise.
345 (aarch64_ins_sve_limm_mov): Likewise.
346 (aarch64_ins_sve_shlimm): Likewise.
347 (aarch64_ins_sve_shrimm): Likewise.
348 * aarch64-asm-2.c: Regenerate.
349 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
350 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
351 * aarch64-dis.c (decode_limm): New function, split out from...
352 (aarch64_ext_limm): ...here.
353 (aarch64_ext_inv_limm): New function.
354 (decode_sve_aimm): Likewise.
355 (aarch64_ext_sve_aimm): Likewise.
356 (aarch64_ext_sve_asimm): Likewise.
357 (aarch64_ext_sve_limm_mov): Likewise.
358 (aarch64_top_bit): Likewise.
359 (aarch64_ext_sve_shlimm): Likewise.
360 (aarch64_ext_sve_shrimm): Likewise.
361 * aarch64-dis-2.c: Regenerate.
362
98907a70
RS		 3632016-09-21 Richard Sandiford <richard.sandiford@arm.com>
364
365 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
366 operands.
367 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
368 the AARCH64_MOD_MUL_VL entry.
369 (value_aligned_p): Cope with non-power-of-two alignments.
370 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
371 (print_immediate_offset_address): Likewise.
372 (aarch64_print_operand): Likewise.
373 * aarch64-opc-2.c: Regenerate.
374 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
375 (ins_sve_addr_ri_s9xvl): New inserters.
376 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
377 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
378 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
379 * aarch64-asm-2.c: Regenerate.
380 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
381 (ext_sve_addr_ri_s9xvl): New extractors.
382 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
383 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
384 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
385 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
386 * aarch64-dis-2.c: Regenerate.
387
4df068de
RS		 3882016-09-21 Richard Sandiford <richard.sandiford@arm.com>
389
390 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
391 address operands.
392 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
393 (FLD_SVE_xs_22): New aarch64_field_kinds.
394 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
395 (get_operand_specific_data): New function.
396 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
397 FLD_SVE_xs_14 and FLD_SVE_xs_22.
398 (operand_general_constraint_met_p): Handle the new SVE address
399 operands.
400 (sve_reg): New array.
401 (get_addr_sve_reg_name): New function.
402 (aarch64_print_operand): Handle the new SVE address operands.
403 * aarch64-opc-2.c: Regenerate.
404 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
405 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
406 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
407 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
408 (aarch64_ins_sve_addr_rr_lsl): Likewise.
409 (aarch64_ins_sve_addr_rz_xtw): Likewise.
410 (aarch64_ins_sve_addr_zi_u5): Likewise.
411 (aarch64_ins_sve_addr_zz): Likewise.
412 (aarch64_ins_sve_addr_zz_lsl): Likewise.
413 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
414 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
415 * aarch64-asm-2.c: Regenerate.
416 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
417 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
418 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
419 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
420 (aarch64_ext_sve_addr_ri_u6): Likewise.
421 (aarch64_ext_sve_addr_rr_lsl): Likewise.
422 (aarch64_ext_sve_addr_rz_xtw): Likewise.
423 (aarch64_ext_sve_addr_zi_u5): Likewise.
424 (aarch64_ext_sve_addr_zz): Likewise.
425 (aarch64_ext_sve_addr_zz_lsl): Likewise.
426 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
427 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
428 * aarch64-dis-2.c: Regenerate.
429
2442d846
RS		 4302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
431
432 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
433 AARCH64_OPND_SVE_PATTERN_SCALED.
434 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
435 * aarch64-opc.c (fields): Add a corresponding entry.
436 (set_multiplier_out_of_range_error): New function.
437 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
438 (operand_general_constraint_met_p): Handle
439 AARCH64_OPND_SVE_PATTERN_SCALED.
440 (print_register_offset_address): Use PRIi64 to print the
441 shift amount.
442 (aarch64_print_operand): Likewise. Handle
443 AARCH64_OPND_SVE_PATTERN_SCALED.
444 * aarch64-opc-2.c: Regenerate.
445 * aarch64-asm.h (ins_sve_scale): New inserter.
446 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
447 * aarch64-asm-2.c: Regenerate.
448 * aarch64-dis.h (ext_sve_scale): New inserter.
449 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
450 * aarch64-dis-2.c: Regenerate.
451
245d2e3f
RS		 4522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
453
454 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
455 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
456 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
457 (FLD_SVE_prfop): Likewise.
458 * aarch64-opc.c: Include libiberty.h.
459 (aarch64_sve_pattern_array): New variable.
460 (aarch64_sve_prfop_array): Likewise.
461 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
462 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
463 AARCH64_OPND_SVE_PRFOP.
464 * aarch64-asm-2.c: Regenerate.
465 * aarch64-dis-2.c: Likewise.
466 * aarch64-opc-2.c: Likewise.
467
d50c751e
RS		 4682016-09-21 Richard Sandiford <richard.sandiford@arm.com>
469
470 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
471 AARCH64_OPND_QLF_P_[ZM].
472 (aarch64_print_operand): Print /z and /m where appropriate.
473
f11ad6bc
RS		 4742016-09-21 Richard Sandiford <richard.sandiford@arm.com>
475
476 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
477 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
478 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
479 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
480 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
481 * aarch64-opc.c (fields): Add corresponding entries here.
482 (operand_general_constraint_met_p): Check that SVE register lists
483 have the correct length. Check the ranges of SVE index registers.
484 Check for cases where p8-p15 are used in 3-bit predicate fields.
485 (aarch64_print_operand): Handle the new SVE operands.
486 * aarch64-opc-2.c: Regenerate.
487 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
488 * aarch64-asm.c (aarch64_ins_sve_index): New function.
489 (aarch64_ins_sve_reglist): Likewise.
490 * aarch64-asm-2.c: Regenerate.
491 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
492 * aarch64-dis.c (aarch64_ext_sve_index): New function.
493 (aarch64_ext_sve_reglist): Likewise.
494 * aarch64-dis-2.c: Regenerate.
495
0c608d6b
RS		 4962016-09-21 Richard Sandiford <richard.sandiford@arm.com>
497
498 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
499 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
500 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
501 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
502 tied operands.
503
01dbfe4c
RS		 5042016-09-21 Richard Sandiford <richard.sandiford@arm.com>
505
506 * aarch64-opc.c (get_offset_int_reg_name): New function.
507 (print_immediate_offset_address): Likewise.
508 (print_register_offset_address): Take the base and offset
509 registers as parameters.
510 (aarch64_print_operand): Update caller accordingly. Use
511 print_immediate_offset_address.
512
72e9f319
RS		 5132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
514
515 * aarch64-opc.c (BANK): New macro.
516 (R32, R64): Take a register number as argument
517 (int_reg): Use BANK.
518
8a7f0c1b
RS		 5192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
520
521 * aarch64-opc.c (print_register_list): Add a prefix parameter.
522 (aarch64_print_operand): Update accordingly.
523
aa2aa4c6
RS		 5242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
525
526 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
527 for FPIMM.
528 * aarch64-asm.h (ins_fpimm): New inserter.
529 * aarch64-asm.c (aarch64_ins_fpimm): New function.
530 * aarch64-asm-2.c: Regenerate.
531 * aarch64-dis.h (ext_fpimm): New extractor.
532 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
533 (aarch64_ext_fpimm): New function.
534 * aarch64-dis-2.c: Regenerate.
535
b5464a68
RS		 5362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
537
538 * aarch64-asm.c: Include libiberty.h.
539 (insert_fields): New function.
540 (aarch64_ins_imm): Use it.
541 * aarch64-dis.c (extract_fields): New function.
542 (aarch64_ext_imm): Use it.
543
42408347
RS		 5442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
545
546 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
547 with an esize parameter.
548 (operand_general_constraint_met_p): Update accordingly.
549 Fix misindented code.
550 * aarch64-asm.c (aarch64_ins_limm): Update call to
551 aarch64_logical_immediate_p.
552
4989adac
RS		 5532016-09-21 Richard Sandiford <richard.sandiford@arm.com>
554
555 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
556
bd11d5d8
RS		 5572016-09-21 Richard Sandiford <richard.sandiford@arm.com>
558
559 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
560
f807f43d
CZ		 5612016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
562
563 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
564
fd486b63
PB		 5652016-09-14 Peter Bergner <bergner@vnet.ibm.com>
566
567 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
568 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
569 xor3>: Delete mnemonics.
570 <cp_abort>: Rename mnemonic from ...
571 <cpabort>: ...to this.
572 <setb>: Change to a X form instruction.
573 <sync>: Change to 1 operand form.
574 <copy>: Delete mnemonic.
575 <copy_first>: Rename mnemonic from ...
576 <copy>: ...to this.
577 <paste, paste.>: Delete mnemonics.
578 <paste_last>: Rename mnemonic from ...
579 <paste.>: ...to this.
580
dce08442
AK		 5812016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
582
583 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
584
952c3f51
AK		 5852016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
586
587 * s390-mkopc.c (main): Support alternate arch strings.
588
8b71537b
PS		 5892016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
590
591 * s390-opc.txt: Fix kmctr instruction type.
592
5b64d091
L		 5932016-09-07 H.J. Lu <hongjiu.lu@intel.com>
594
595 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
596 * i386-init.h: Regenerated.
597
7763838e
CM		 5982016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
599
600 * opcodes/arc-dis.c (print_insn_arc): Changed.
601
1b8b6532
JM		 6022016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
603
604 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
605 camellia_fl.
606
1a336194
TP		 6072016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
608
609 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
610 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
611 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
612
6b40c462
L		 6132016-08-24 H.J. Lu <hongjiu.lu@intel.com>
614
615 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
616 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
617 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
618 PREFIX_MOD_3_0FAE_REG_4.
619 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
620 PREFIX_MOD_3_0FAE_REG_4.
621 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
622 (cpu_flags): Add CpuPTWRITE.
623 * i386-opc.h (CpuPTWRITE): New.
624 (i386_cpu_flags): Add cpuptwrite.
625 * i386-opc.tbl: Add ptwrite instruction.
626 * i386-init.h: Regenerated.
627 * i386-tbl.h: Likewise.
628
ab548d2d
AK		 6292016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
630
631 * arc-dis.h: Wrap around in extern "C".
632
344bde0a
RS		 6332016-08-23 Richard Sandiford <richard.sandiford@arm.com>
634
635 * aarch64-tbl.h (V8_2_INSN): New macro.
636 (aarch64_opcode_table): Use it.
637
5ce912d8
RS		 6382016-08-23 Richard Sandiford <richard.sandiford@arm.com>
639
640 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
641 CORE_INSN, __FP_INSN and SIMD_INSN.
642
9d30b0bd
RS		 6432016-08-23 Richard Sandiford <richard.sandiford@arm.com>
644
645 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
646 (aarch64_opcode_table): Update uses accordingly.
647
dfdaec14
AJ		 6482016-07-25 Andrew Jenner <andrew@codesourcery.com>
649 Kwok Cheung Yeung <kcy@codesourcery.com>
650
651 opcodes/
652 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
653 'e_cmplwi' to 'e_cmpli' instead.
654 (OPVUPRT, OPVUPRT_MASK): Define.
655 (powerpc_opcodes): Add E200Z4 insns.
656 (vle_opcodes): Add context save/restore insns.
657
7bd374a4
MR		 6582016-07-27 Maciej W. Rozycki <macro@imgtec.com>
659
660 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
661 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
662 "j".
663
db18dbab
GM		 6642016-07-27 Graham Markall <graham.markall@embecosm.com>
665
666 * arc-nps400-tbl.h: Change block comments to GNU format.
667 * arc-dis.c: Add new globals addrtypenames,
668 addrtypenames_max, and addtypeunknown.
669 (get_addrtype): New function.
670 (print_insn_arc): Print colons and address types when
671 required.
672 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
673 define insert and extract functions for all address types.
674 (arc_operands): Add operands for colon and all address
675 types.
676 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
677 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
678 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
679 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
680 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
681 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
682
fecd57f9
L		 6832016-07-21 H.J. Lu <hongjiu.lu@intel.com>
684
685 * configure: Regenerated.
686
37fd5ef3
CZ		 6872016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
688
689 * arc-dis.c (skipclass): New structure.
690 (decodelist): New variable.
691 (is_compatible_p): New function.
692 (new_element): Likewise.
693 (skip_class_p): Likewise.
694 (find_format_from_table): Use skip_class_p function.
695 (find_format): Decode first the extension instructions.
696 (print_insn_arc): Select either ARCEM or ARCHS based on elf
697 e_flags.
698 (parse_option): New function.
699 (parse_disassembler_options): Likewise.
700 (print_arc_disassembler_options): Likewise.
701 (print_insn_arc): Use parse_disassembler_options function. Proper
702 select ARCv2 cpu variant.
703 * disassemble.c (disassembler_usage): Add ARC disassembler
704 options.
705
92281a5b
MR		 7062016-07-13 Maciej W. Rozycki <macro@imgtec.com>
707
708 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
709 annotation from the "nal" entry and reorder it beyond "bltzal".
710
6e7ced37
JM		 7112016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
712
713 * sparc-opc.c (ldtxa): New macro.
714 (sparc_opcodes): Use the macro defined above to add entries for
715 the LDTXA instructions.
716 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
717 instruction.
718
2f831b9a 7192016-07-07 James Bowman <james.bowman@ftdichip.com>
720
721 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
722 and "jmpc".
723
c07315e0
JB		 7242016-07-01 Jan Beulich <jbeulich@suse.com>
725
726 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
727 (movzb): Adjust to cover all permitted suffixes.
728 (movzw): New.
729 * i386-tbl.h: Re-generate.
730
9243100a
JB		 7312016-07-01 Jan Beulich <jbeulich@suse.com>
732
733 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
734 (lgdt): Remove Tbyte from non-64-bit variant.
735 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
736 xsaves64, xsavec64): Remove Disp16.
737 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
738 Remove Disp32S from non-64-bit variants. Remove Disp16 from
739 64-bit variants.
740 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
741 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
742 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
743 64-bit variants.
744 * i386-tbl.h: Re-generate.
745
8325cc63
JB		 7462016-07-01 Jan Beulich <jbeulich@suse.com>
747
748 * i386-opc.tbl (xlat): Remove RepPrefixOk.
749 * i386-tbl.h: Re-generate.
750
838441e4
YQ		 7512016-06-30 Yao Qi <yao.qi@linaro.org>
752
753 * arm-dis.c (print_insn): Fix typo in comment.
754
dab26bf4
RS		 7552016-06-28 Richard Sandiford <richard.sandiford@arm.com>
756
757 * aarch64-opc.c (operand_general_constraint_met_p): Check the
758 range of ldst_elemlist operands.
759 (print_register_list): Use PRIi64 to print the index.
760 (aarch64_print_operand): Likewise.
761
5703197e
TS		 7622016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
763
764 * mcore-opc.h: Remove sentinal.
765 * mcore-dis.c (print_insn_mcore): Adjust.
766
ce440d63
GM		 7672016-06-23 Graham Markall <graham.markall@embecosm.com>
768
769 * arc-opc.c: Correct description of availability of NPS400
770 features.
771
6fd3a02d
PB		 7722016-06-22 Peter Bergner <bergner@vnet.ibm.com>
773
774 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
775 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
776 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
777 xor3>: New mnemonics.
778 <setb>: Change to a VX form instruction.
779 (insert_sh6): Add support for rldixor.
780 (extract_sh6): Likewise.
781
6b477896
TS		 7822016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
783
784 * arc-ext.h: Wrap in extern C.
785
bdd582db
GM		 7862016-06-21 Graham Markall <graham.markall@embecosm.com>
787
788 * arc-dis.c (arc_insn_length): Add comment on instruction length.
789 Use same method for determining instruction length on ARC700 and
790 NPS-400.
791 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
792 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
793 with the NPS400 subclass.
794 * arc-opc.c: Likewise.
795
96074adc
JM		 7962016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
797
798 * sparc-opc.c (rdasr): New macro.
799 (wrasr): Likewise.
800 (rdpr): Likewise.
801 (wrpr): Likewise.
802 (rdhpr): Likewise.
803 (wrhpr): Likewise.
804 (sparc_opcodes): Use the macros above to fix and expand the
805 definition of read/write instructions from/to
806 asr/privileged/hyperprivileged instructions.
807 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
808 %hva_mask_nz. Prefer softint_set and softint_clear over
809 set_softint and clear_softint.
810 (print_insn_sparc): Support %ver in Rd.
811
7a10c22f
JM		 8122016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
813
814 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
815 architecture according to the hardware capabilities they require.
816
4f26fb3a
JM		 8172016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
818
819 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
820 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
821 bfd_mach_sparc_v9{c,d,e,v,m}.
822 * sparc-opc.c (MASK_V9C): Define.
823 (MASK_V9D): Likewise.
824 (MASK_V9E): Likewise.
825 (MASK_V9V): Likewise.
826 (MASK_V9M): Likewise.
827 (v6): Add MASK_V9{C,D,E,V,M}.
828 (v6notlet): Likewise.
829 (v7): Likewise.
830 (v8): Likewise.
831 (v9): Likewise.
832 (v9andleon): Likewise.
833 (v9a): Likewise.
834 (v9b): Likewise.
835 (v9c): Define.
836 (v9d): Likewise.
837 (v9e): Likewise.
838 (v9v): Likewise.
839 (v9m): Likewise.
840 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
841
3ee6e4fb
NC		 8422016-06-15 Nick Clifton <nickc@redhat.com>
843
844 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
845 constants to match expected behaviour.
846 (nds32_parse_opcode): Likewise. Also for whitespace.
847
02f3be19
AB		 8482016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
849
850 * arc-opc.c (extract_rhv1): Extract value from insn.
851
6f9f37ed 8522016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 853
854 * arc-nps400-tbl.h: Add ldbit instruction.
855 * arc-opc.c: Add flag classes required for ldbit.
856
6f9f37ed 8572016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 858
859 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
860 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
861 support the above instructions.
862
6f9f37ed 8632016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 864
865 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
866 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
867 csma, cbba, zncv, and hofs.
868 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
869 support the above instructions.
870
8712016-06-06 Graham Markall <graham.markall@embecosm.com>
872
873 * arc-nps400-tbl.h: Add andab and orab instructions.
874
8752016-06-06 Graham Markall <graham.markall@embecosm.com>
876
877 * arc-nps400-tbl.h: Add addl-like instructions.
878
8792016-06-06 Graham Markall <graham.markall@embecosm.com>
880
881 * arc-nps400-tbl.h: Add mxb and imxb instructions.
882
8832016-06-06 Graham Markall <graham.markall@embecosm.com>
884
885 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
886 instructions.
887
b2cc3f6f
AK		 8882016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
889
890 * s390-dis.c (option_use_insn_len_bits_p): New file scope
891 variable.
892 (init_disasm): Handle new command line option "insnlength".
893 (print_s390_disassembler_options): Mention new option in help
894 output.
895 (print_insn_s390): Use the encoded insn length when dumping
896 unknown instructions.
897
1857fe72
DC		 8982016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
899
900 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
901 to the address and set as symbol address for LDS/ STS immediate operands.
902
14b57c7c
AM		 9032016-06-07 Alan Modra <amodra@gmail.com>
904
905 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
906 cpu for "vle" to e500.
907 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
908 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
909 (PPCNONE): Delete, substitute throughout.
910 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
911 except for major opcode 4 and 31.
912 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
913
4d1464f2
MW		 9142016-06-07 Matthew Wahab <matthew.wahab@arm.com>
915
916 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
917 ARM_EXT_RAS in relevant entries.
918
026122a6
PB		 9192016-06-03 Peter Bergner <bergner@vnet.ibm.com>
920
921 PR binutils/20196
922 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
923 opcodes for E6500.
924
07f5af7d
L		 9252016-06-03 H.J. Lu <hongjiu.lu@intel.com>
926
927 PR binutis/18386
928 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
929 (indir_v_mode): New.
930 Add comments for '&'.
931 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
932 (putop): Handle '&'.
933 (intel_operand_size): Handle indir_v_mode.
934 (OP_E_register): Likewise.
935 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
936 64-bit indirect call/jmp for AMD64.
937 * i386-tbl.h: Regenerated
938
4eb6f892
AB		 9392016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
940
941 * arc-dis.c (struct arc_operand_iterator): New structure.
942 (find_format_from_table): All the old content from find_format,
943 with some minor adjustments, and parameter renaming.
944 (find_format_long_instructions): New function.
945 (find_format): Rewritten.
946 (arc_insn_length): Add LSB parameter.
947 (extract_operand_value): New function.
948 (operand_iterator_next): New function.
949 (print_insn_arc): Use new functions to find opcode, and iterator
950 over operands.
951 * arc-opc.c (insert_nps_3bit_dst_short): New function.
952 (extract_nps_3bit_dst_short): New function.
953 (insert_nps_3bit_src2_short): New function.
954 (extract_nps_3bit_src2_short): New function.
955 (insert_nps_bitop1_size): New function.
956 (extract_nps_bitop1_size): New function.
957 (insert_nps_bitop2_size): New function.
958 (extract_nps_bitop2_size): New function.
959 (insert_nps_bitop_mod4_msb): New function.
960 (extract_nps_bitop_mod4_msb): New function.
961 (insert_nps_bitop_mod4_lsb): New function.
962 (extract_nps_bitop_mod4_lsb): New function.
963 (insert_nps_bitop_dst_pos3_pos4): New function.
964 (extract_nps_bitop_dst_pos3_pos4): New function.
965 (insert_nps_bitop_ins_ext): New function.
966 (extract_nps_bitop_ins_ext): New function.
967 (arc_operands): Add new operands.
968 (arc_long_opcodes): New global array.
969 (arc_num_long_opcodes): New global.
970 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
971
1fe0971e
TS		 9722016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
973
974 * nds32-asm.h: Add extern "C".
975 * sh-opc.h: Likewise.
976
315f180f
GM		 9772016-06-01 Graham Markall <graham.markall@embecosm.com>
978
979 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
980 0,b,limm to the rflt instruction.
981
a2b5fccc
TS		 9822016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
983
984 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
985 constant.
986
0cbd0046
L		 9872016-05-29 H.J. Lu <hongjiu.lu@intel.com>
988
989 PR gas/20145
990 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
991 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
992 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
993 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
994 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
995 * i386-init.h: Regenerated.
996
1848e567
L		 9972016-05-27 H.J. Lu <hongjiu.lu@intel.com>
998
999 PR gas/20145
1000 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1001 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1002 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1003 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1004 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1005 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1006 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1007 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1008 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1009 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1010 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1011 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1012 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1013 CpuRegMask for AVX512.
1014 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1015 and CpuRegMask.
1016 (set_bitfield_from_cpu_flag_init): New function.
1017 (set_bitfield): Remove const on f. Call
1018 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1019 * i386-opc.h (CpuRegMMX): New.
1020 (CpuRegXMM): Likewise.
1021 (CpuRegYMM): Likewise.
1022 (CpuRegZMM): Likewise.
1023 (CpuRegMask): Likewise.
1024 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1025 and cpuregmask.
1026 * i386-init.h: Regenerated.
1027 * i386-tbl.h: Likewise.
1028
e92bae62
L		 10292016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1030
1031 PR gas/20154
1032 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1033 (opcode_modifiers): Add AMD64 and Intel64.
1034 (main): Properly verify CpuMax.
1035 * i386-opc.h (CpuAMD64): Removed.
1036 (CpuIntel64): Likewise.
1037 (CpuMax): Set to CpuNo64.
1038 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1039 (AMD64): New.
1040 (Intel64): Likewise.
1041 (i386_opcode_modifier): Add amd64 and intel64.
1042 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1043 on call and jmp.
1044 * i386-init.h: Regenerated.
1045 * i386-tbl.h: Likewise.
1046
e89c5eaa
L		 10472016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1048
1049 PR gas/20154
1050 * i386-gen.c (main): Fail if CpuMax is incorrect.
1051 * i386-opc.h (CpuMax): Set to CpuIntel64.
1052 * i386-tbl.h: Regenerated.
1053
77d66e7b
NC		 10542016-05-27 Nick Clifton <nickc@redhat.com>
1055
1056 PR target/20150
1057 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1058 (msp430dis_opcode_unsigned): New function.
1059 (msp430dis_opcode_signed): New function.
1060 (msp430_singleoperand): Use the new opcode reading functions.
1061 Only disassenmble bytes if they were successfully read.
1062 (msp430_doubleoperand): Likewise.
1063 (msp430_branchinstr): Likewise.
1064 (msp430x_callx_instr): Likewise.
1065 (print_insn_msp430): Check that it is safe to read bytes before
1066 attempting disassembly. Use the new opcode reading functions.
1067
19dfcc89
PB		 10682016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1069
1070 * ppc-opc.c (CY): New define. Document it.
1071 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1072
f3ad7637
L		 10732016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1074
1075 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1076 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1077 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1078 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1079 CPU_ANY_AVX_FLAGS.
1080 * i386-init.h: Regenerated.
1081
f1360d58
L		 10822016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1083
1084 PR gas/20141
1085 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1086 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1087 * i386-init.h: Regenerated.
1088
293f5f65
L		 10892016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1090
1091 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1092 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1093 * i386-init.h: Regenerated.
1094
d9eca1df
CZ		 10952016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1096
1097 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1098 information.
1099 (print_insn_arc): Set insn_type information.
1100 * arc-opc.c (C_CC): Add F_CLASS_COND.
1101 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1102 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1103 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1104 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1105 (brne, brne_s, jeq_s, jne_s): Likewise.
1106
87789e08
CZ		 11072016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1108
1109 * arc-tbl.h (neg): New instruction variant.
1110
c810e0b8
CZ		 11112016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1112
1113 * arc-dis.c (find_format, find_format, get_auxreg)
1114 (print_insn_arc): Changed.
1115 * arc-ext.h (INSERT_XOP): Likewise.
1116
3d207518
TS		 11172016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1118
1119 * tic54x-dis.c (sprint_mmr): Adjust.
1120 * tic54x-opc.c: Likewise.
1121
514e58b7
AM		 11222016-05-19 Alan Modra <amodra@gmail.com>
1123
1124 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1125
e43de63c
AM		 11262016-05-19 Alan Modra <amodra@gmail.com>
1127
1128 * ppc-opc.c: Formatting.
1129 (NSISIGNOPT): Define.
1130 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1131
1401d2fe
MR		 11322016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1133
1134 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1135 replacing references to `micromips_ase' throughout.
1136 (_print_insn_mips): Don't use file-level microMIPS annotation to
1137 determine the disassembly mode with the symbol table.
1138
1178da44
PB		 11392016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1140
1141 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1142
8f4f9071
MF		 11432016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1144
1145 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1146 mips64r6.
1147 * mips-opc.c (D34): New macro.
1148 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1149
8bc52696
AF		 11502016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1151
1152 * i386-dis.c (prefix_table): Add RDPID instruction.
1153 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1154 (cpu_flags): Add RDPID bitfield.
1155 * i386-opc.h (enum): Add RDPID element.
1156 (i386_cpu_flags): Add RDPID field.
1157 * i386-opc.tbl: Add RDPID instruction.
1158 * i386-init.h: Regenerate.
1159 * i386-tbl.h: Regenerate.
1160
39d911fc
TP		 11612016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1162
1163 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1164 branch type of a symbol.
1165 (print_insn): Likewise.
1166
16a1fa25
TP		 11672016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1168
1169 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1170 Mainline Security Extensions instructions.
1171 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1172 Extensions instructions.
1173 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1174 instructions.
1175 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1176 special registers.
1177
d751b79e
JM		 11782016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1179
1180 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1181
945e0f82
CZ		 11822016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1183
1184 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1185 (arcExtMap_genOpcode): Likewise.
1186 * arc-opc.c (arg_32bit_rc): Define new variable.
1187 (arg_32bit_u6): Likewise.
1188 (arg_32bit_limm): Likewise.
1189
20f55f38
SN		 11902016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1191
1192 * aarch64-gen.c (VERIFIER): Define.
1193 * aarch64-opc.c (VERIFIER): Define.
1194 (verify_ldpsw): Use static linkage.
1195 * aarch64-opc.h (verify_ldpsw): Remove.
1196 * aarch64-tbl.h: Use VERIFIER for verifiers.
1197
4bd13cde
NC		 11982016-04-28 Nick Clifton <nickc@redhat.com>
1199
1200 PR target/19722
1201 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1202 * aarch64-opc.c (verify_ldpsw): New function.
1203 * aarch64-opc.h (verify_ldpsw): New prototype.
1204 * aarch64-tbl.h: Add initialiser for verifier field.
1205 (LDPSW): Set verifier to verify_ldpsw.
1206
c0f92bf9
L		 12072016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1208
1209 PR binutils/19983
1210 PR binutils/19984
1211 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1212 smaller than address size.
1213
e6c7cdec
TS		 12142016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1215
1216 * alpha-dis.c: Regenerate.
1217 * crx-dis.c: Likewise.
1218 * disassemble.c: Likewise.
1219 * epiphany-opc.c: Likewise.
1220 * fr30-opc.c: Likewise.
1221 * frv-opc.c: Likewise.
1222 * ip2k-opc.c: Likewise.
1223 * iq2000-opc.c: Likewise.
1224 * lm32-opc.c: Likewise.
1225 * lm32-opinst.c: Likewise.
1226 * m32c-opc.c: Likewise.
1227 * m32r-opc.c: Likewise.
1228 * m32r-opinst.c: Likewise.
1229 * mep-opc.c: Likewise.
1230 * mt-opc.c: Likewise.
1231 * or1k-opc.c: Likewise.
1232 * or1k-opinst.c: Likewise.
1233 * tic80-opc.c: Likewise.
1234 * xc16x-opc.c: Likewise.
1235 * xstormy16-opc.c: Likewise.
1236
537aefaf
AB		 12372016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1238
1239 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1240 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1241 calcsd, and calcxd instructions.
1242 * arc-opc.c (insert_nps_bitop_size): Delete.
1243 (extract_nps_bitop_size): Delete.
1244 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1245 (extract_nps_qcmp_m3): Define.
1246 (extract_nps_qcmp_m2): Define.
1247 (extract_nps_qcmp_m1): Define.
1248 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1249 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1250 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1251 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1252 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1253 NPS_QCMP_M3.
1254
c8f785f2
AB		 12552016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1256
1257 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1258
6fd8e7c2
L		 12592016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1260
1261 * Makefile.in: Regenerated with automake 1.11.6.
1262 * aclocal.m4: Likewise.
1263
4b0c052e
AB		 12642016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1265
1266 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1267 instructions.
1268 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1269 (extract_nps_cmem_uimm16): New function.
1270 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1271
cb040366
AB		 12722016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1273
1274 * arc-dis.c (arc_insn_length): New function.
1275 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1276 (find_format): Change insnLen parameter to unsigned.
1277
accc0180
NC		 12782016-04-13 Nick Clifton <nickc@redhat.com>
1279
1280 PR target/19937
1281 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1282 the LD.B and LD.BU instructions.
1283
f36e33da
CZ		 12842016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1285
1286 * arc-dis.c (find_format): Check for extension flags.
1287 (print_flags): New function.
1288 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1289 .extAuxRegister.
1290 * arc-ext.c (arcExtMap_coreRegName): Use
1291 LAST_EXTENSION_CORE_REGISTER.
1292 (arcExtMap_coreReadWrite): Likewise.
1293 (dump_ARC_extmap): Update printing.
1294 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1295 (arc_aux_regs): Add cpu field.
1296 * arc-regs.h: Add cpu field, lower case name aux registers.
1297
1c2e355e
CZ		 12982016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1299
1300 * arc-tbl.h: Add rtsc, sleep with no arguments.
1301
b99747ae
CZ		 13022016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1303
1304 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1305 Initialize.
1306 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1307 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1308 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1309 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1310 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1311 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1312 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1313 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1314 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1315 (arc_opcode arc_opcodes): Null terminate the array.
1316 (arc_num_opcodes): Remove.
1317 * arc-ext.h (INSERT_XOP): Define.
1318 (extInstruction_t): Likewise.
1319 (arcExtMap_instName): Delete.
1320 (arcExtMap_insn): New function.
1321 (arcExtMap_genOpcode): Likewise.
1322 * arc-ext.c (ExtInstruction): Remove.
1323 (create_map): Zero initialize instruction fields.
1324 (arcExtMap_instName): Remove.
1325 (arcExtMap_insn): New function.
1326 (dump_ARC_extmap): More info while debuging.
1327 (arcExtMap_genOpcode): New function.
1328 * arc-dis.c (find_format): New function.
1329 (print_insn_arc): Use find_format.
1330 (arc_get_disassembler): Enable dump_ARC_extmap only when
1331 debugging.
1332
92708cec
MR		 13332016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1334
1335 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1336 instruction bits out.
1337
a42a4f84
AB		 13382016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1339
1340 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1341 * arc-opc.c (arc_flag_operands): Add new flags.
1342 (arc_flag_classes): Add new classes.
1343
1328504b
AB		 13442016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1345
1346 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1347
820f03ff
AB		 13482016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1349
1350 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1351 encode1, rflt, crc16, and crc32 instructions.
1352 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1353 (arc_flag_classes): Add C_NPS_R.
1354 (insert_nps_bitop_size_2b): New function.
1355 (extract_nps_bitop_size_2b): Likewise.
1356 (insert_nps_bitop_uimm8): Likewise.
1357 (extract_nps_bitop_uimm8): Likewise.
1358 (arc_operands): Add new operand entries.
1359
8ddf6b2a
CZ		 13602016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1361
b99747ae
CZ		 1362 * arc-regs.h: Add a new subclass field. Add double assist
1363 accumulator register values.
1364 * arc-tbl.h: Use DPA subclass to mark the double assist
1365 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1366 * arc-opc.c (RSP): Define instead of SP.
1367 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1368
589a7d88
JW		 13692016-04-05 Jiong Wang <jiong.wang@arm.com>
1370
1371 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1372
0a191de9 13732016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1374
1375 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1376 NPS_R_SRC1.
1377
0a106562
AB		 13782016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1379
1380 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1381 issues. No functional changes.
1382
bd05ac5f
CZ		 13832016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1384
b99747ae
CZ		 1385 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1386 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1387 (RTT): Remove duplicate.
1388 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1389 (PCT_CONFIG*): Remove.
1390 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1391
9885948f
CZ		 13922016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1393
b99747ae 1394 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1395
f2dd8838
CZ		 13962016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1397
b99747ae
CZ		 1398 * arc-tbl.h (invld07): Remove.
1399 * arc-ext-tbl.h: New file.
1400 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1401 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1402
0d2f91fe
JK		 14032016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1404
1405 Fix -Wstack-usage warnings.
1406 * aarch64-dis.c (print_operands): Substitute size.
1407 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1408
a6b71f42
JM		 14092016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1410
1411 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1412 to get a proper diagnostic when an invalid ASR register is used.
1413
9780e045
NC		 14142016-03-22 Nick Clifton <nickc@redhat.com>
1415
1416 * configure: Regenerate.
1417
e23e8ebe
AB		 14182016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1419
1420 * arc-nps400-tbl.h: New file.
1421 * arc-opc.c: Add top level comment.
1422 (insert_nps_3bit_dst): New function.
1423 (extract_nps_3bit_dst): New function.
1424 (insert_nps_3bit_src2): New function.
1425 (extract_nps_3bit_src2): New function.
1426 (insert_nps_bitop_size): New function.
1427 (extract_nps_bitop_size): New function.
1428 (arc_flag_operands): Add nps400 entries.
1429 (arc_flag_classes): Add nps400 entries.
1430 (arc_operands): Add nps400 entries.
1431 (arc_opcodes): Add nps400 include.
1432
1ae8ab47
AB		 14332016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1434
1435 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1436 the new class enum values.
1437
8699fc3e
AB		 14382016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1439
1440 * arc-dis.c (print_insn_arc): Handle nps400.
1441
24740d83
AB		 14422016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1443
1444 * arc-opc.c (BASE): Delete.
1445
8678914f
NC		 14462016-03-18 Nick Clifton <nickc@redhat.com>
1447
1448 PR target/19721
1449 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1450 of MOV insn that aliases an ORR insn.
1451
cc933301
JW		 14522016-03-16 Jiong Wang <jiong.wang@arm.com>
1453
1454 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1455
f86f5863
TS		 14562016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1457
1458 * mcore-opc.h: Add const qualifiers.
1459 * microblaze-opc.h (struct op_code_struct): Likewise.
1460 * sh-opc.h: Likewise.
1461 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1462 (tic4x_print_op): Likewise.
1463
62de1c63
AM		 14642016-03-02 Alan Modra <amodra@gmail.com>
1465
d11698cd 1466 * or1k-desc.h: Regenerate.
62de1c63 1467 * fr30-ibld.c: Regenerate.
c697cf0b 1468 * rl78-decode.c: Regenerate.
62de1c63 1469
020efce5
NC		 14702016-03-01 Nick Clifton <nickc@redhat.com>
1471
1472 PR target/19747
1473 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1474
b0c11777
RL		 14752016-02-24 Renlin Li <renlin.li@arm.com>
1476
1477 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1478 (print_insn_coprocessor): Support fp16 instructions.
1479
3e309328
RL		 14802016-02-24 Renlin Li <renlin.li@arm.com>
1481
1482 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1483 vminnm, vrint(mpna).
1484
8afc7bea
RL		 14852016-02-24 Renlin Li <renlin.li@arm.com>
1486
1487 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1488 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1489
4fd7268a
L		 14902016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1491
1492 * i386-dis.c (print_insn): Parenthesize expression to prevent
1493 truncated addresses.
1494 (OP_J): Likewise.
1495
4670103e
CZ		 14962016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1497 Janek van Oirschot <jvanoirs@synopsys.com>
1498
b99747ae
CZ		 1499 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1500 variable.
4670103e 1501
c1d9289f
NC		 15022016-02-04 Nick Clifton <nickc@redhat.com>
1503
1504 PR target/19561
1505 * msp430-dis.c (print_insn_msp430): Add a special case for
1506 decoding an RRC instruction with the ZC bit set in the extension
1507 word.
1508
a143b004
AB		 15092016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1510
1511 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1512 * epiphany-ibld.c: Regenerate.
1513 * fr30-ibld.c: Regenerate.
1514 * frv-ibld.c: Regenerate.
1515 * ip2k-ibld.c: Regenerate.
1516 * iq2000-ibld.c: Regenerate.
1517 * lm32-ibld.c: Regenerate.
1518 * m32c-ibld.c: Regenerate.
1519 * m32r-ibld.c: Regenerate.
1520 * mep-ibld.c: Regenerate.
1521 * mt-ibld.c: Regenerate.
1522 * or1k-ibld.c: Regenerate.
1523 * xc16x-ibld.c: Regenerate.
1524 * xstormy16-ibld.c: Regenerate.
1525
b89807c6
AB		 15262016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1527
1528 * epiphany-dis.c: Regenerated from latest cpu files.
1529
d8c823c8
MM		 15302016-02-01 Michael McConville <mmcco@mykolab.com>
1531
1532 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1533 test bit.
1534
5bc5ae88
RL		 15352016-01-25 Renlin Li <renlin.li@arm.com>
1536
1537 * arm-dis.c (mapping_symbol_for_insn): New function.
1538 (find_ifthen_state): Call mapping_symbol_for_insn().
1539
0bff6e2d
MW		 15402016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1541
1542 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1543 of MSR UAO immediate operand.
1544
100b4f2e
MR		 15452016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1546
1547 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1548 instruction support.
1549
5c14705f
AM		 15502016-01-17 Alan Modra <amodra@gmail.com>
1551
1552 * configure: Regenerate.
1553
4d82fe66
NC		 15542016-01-14 Nick Clifton <nickc@redhat.com>
1555
1556 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1557 instructions that can support stack pointer operations.
1558 * rl78-decode.c: Regenerate.
1559 * rl78-dis.c: Fix display of stack pointer in MOVW based
1560 instructions.
1561
651657fa
MW		 15622016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1563
1564 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1565 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1566 erxtatus_el1 and erxaddr_el1.
1567
105bde57
MW		 15682016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1569
1570 * arm-dis.c (arm_opcodes): Add "esb".
1571 (thumb_opcodes): Likewise.
1572
afa8d405
PB		 15732016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1574
1575 * ppc-opc.c <xscmpnedp>: Delete.
1576 <xvcmpnedp>: Likewise.
1577 <xvcmpnedp.>: Likewise.
1578 <xvcmpnesp>: Likewise.
1579 <xvcmpnesp.>: Likewise.
1580
83c3256e
AS		 15812016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1582
1583 PR gas/13050
1584 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1585 addition to ISA_A.
1586
6f2750fe
AM		 15872016-01-01 Alan Modra <amodra@gmail.com>
1588
1589 Update year range in copyright notice of all files.
1590
3499769a
AM		 1591For older changes see ChangeLog-2015
1592\f
1593Copyright (C) 2016 Free Software Foundation, Inc.
1594
1595Copying and distribution of this file, with or without modification,
1596are permitted in any medium without royalty provided the copyright
1597notice and this notice are preserved.
1598
1599Local Variables:
1600mode: change-log
1601left-margin: 8
1602fill-column: 74
1603version-control: never
1604End:
GDB Binutils - Deliverables
This page took 0.127764 seconds and 4 git commands to generate.