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This set of changes clarifies the conditions for the R5900 short loop fix and extends...
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
66e6f0b7
MM		 12018-10-16 Matthew Malcomson <matthew.malcomson@arm.com>
2
3 * aarch64-opc.c (struct operand_qualifier_data): Change qualifier data
4 corresponding to AARCH64_OPND_QLF_S_4B qualifier.
5
673fe0f0
JB		 62018-10-10 Jan Beulich <jbeulich@suse.com>
7
8 * i386-gen.c (opcode_modifiers): Drop Size16, Size32, and
9 Size64. Add Size.
10 * i386-opc.h (Size16, Size32, Size64): Delete.
11 (Size): New.
12 (SIZE16, SIZE32, SIZE64): Define.
13 (struct i386_opcode_modifier): Drop size16, size32, and size64.
14 Add size.
15 * i386-opc.tbl (Size16, Size32, Size64): Define.
16 * i386-tbl.h: Re-generate.
17
104fefee
SD		 182018-10-09 Sudakshina Das <sudi.das@arm.com>
19
20 * aarch64-opc.c (operand_general_constraint_met_p): Add
21 SSBS in the check for one-bit immediate.
22 (aarch64_sys_regs): New entry for SSBS.
23 (aarch64_sys_reg_supported_p): New check for above.
24 (aarch64_pstatefields): New entry for SSBS.
25 (aarch64_pstatefield_supported_p): New check for above.
26
a97330e7
SD		 272018-10-09 Sudakshina Das <sudi.das@arm.com>
28
29 * aarch64-opc.c (aarch64_sys_regs): New entries for
30 scxtnum_el[0,1,2,3,12] and id_pfr2_el1.
31 (aarch64_sys_reg_supported_p): New checks for above.
32
ff605452
SD		 332018-10-09 Sudakshina Das <sudi.das@arm.com>
34
35 * aarch64-opc.h (HINT_OPD_NOPRINT, HINT_ENCODE): New.
36 (HINT_FLAG, HINT_VALUE): New macros to encode NO_PRINT flag
37 with the hint immediate.
38 * aarch64-opc.c (aarch64_hint_options): New entries for
39 c, j, jc and default (with HINT_OPD_F_NOPRINT flag) for BTI.
40 (aarch64_print_operand): Add case for AARCH64_OPND_BTI_TARGET
41 while checking for HINT_OPD_F_NOPRINT flag.
42 * aarch64-dis.c (aarch64_ext_hint): Use new HINT_VALUE to
43 extract value.
44 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): New.
45 (aarch64_opcode_table): Add entry for BTI.
46 (AARCH64_OPERANDS): Add new description for BTI targets.
47 * aarch64-asm-2.c: Regenerate.
48 * aarch64-dis-2.c: Regenerate.
49 * aarch64-opc-2.c: Regenerate.
50
af4bcb4c
SD		 512018-10-09 Sudakshina Das <sudi.das@arm.com>
52
53 * aarch64-opc.c (aarch64_sys_regs): New entries for
54 rndr and rndrrs.
55 (aarch64_sys_reg_supported_p): New check for above.
56
3fd229a4
SD		 572018-10-09 Sudakshina Das <sudi.das@arm.com>
58
59 * aarch64-opc.c (aarch64_sys_regs_dc): New entry for cvadp.
60 (aarch64_sys_ins_reg_supported_p): New check for above.
61
2ac435d4
SD		 622018-10-09 Sudakshina Das <sudi.das@arm.com>
63
64 * aarch64-dis.c (aarch64_ext_sysins_op): Add case for
65 AARCH64_OPND_SYSREG_SR.
66 * aarch64-opc.c (aarch64_print_operand): Likewise.
67 (aarch64_sys_regs_sr): Define table.
68 (aarch64_sys_ins_reg_supported_p): Check for RCTX with
69 AARCH64_FEATURE_PREDRES.
70 * aarch64-tbl.h (aarch64_feature_predres): New.
71 (PREDRES, PREDRES_INSN): New.
72 (aarch64_opcode_table): Add entries for cfp, dvp and cpp.
73 (AARCH64_OPERANDS): Add new description for SYSREG_SR.
74 * aarch64-asm-2.c: Regenerate.
75 * aarch64-dis-2.c: Regenerate.
76 * aarch64-opc-2.c: Regenerate.
77
68dfbb92
SD		 782018-10-09 Sudakshina Das <sudi.das@arm.com>
79
80 * aarch64-tbl.h (aarch64_feature_sb): New.
81 (SB, SB_INSN): New.
82 (aarch64_opcode_table): Add entry for sb.
83 * aarch64-asm-2.c: Regenerate.
84 * aarch64-dis-2.c: Regenerate.
85 * aarch64-opc-2.c: Regenerate.
86
13c60ad7
SD		 872018-10-09 Sudakshina Das <sudi.das@arm.com>
88
89 * aarch64-tbl.h (aarch64_feature_flagmanip): New.
90 (aarch64_feature_frintts): New.
91 (FLAGMANIP, FRINTTS): New.
92 (aarch64_opcode_table): Add entries for xaflag, axflag
93 and frint[32,64][x,z] instructions.
94 * aarch64-asm-2.c: Regenerate.
95 * aarch64-dis-2.c: Regenerate.
96 * aarch64-opc-2.c: Regenerate.
97
70d56181
SD		 982018-10-09 Sudakshina Das <sudi.das@arm.com>
99
100 * aarch64-tbl.h (aarch64_feature_set aarch64_feature_v8_5): New.
101 (ARMV8_5, V8_5_INSN): New.
102
780f601c
TC		 1032018-10-08 Tamar Christina <tamar.christina@arm.com>
104
105 * aarch64-opc.c (verify_constraints): Use memset instead of {0}.
106
a4e78aa5
L		 1072018-10-05 H.J. Lu <hongjiu.lu@intel.com>
108
109 * i386-dis.c (rm_table): Add enclv.
110 * i386-opc.tbl: Add enclv.
111 * i386-tbl.h: Regenerated.
112
7fadb25d
SD		 1132018-10-05 Sudakshina Das <sudi.das@arm.com>
114
115 * arm-dis.c (arm_opcodes): Add sb.
116 (thumb32_opcodes): Likewise.
117
07f5f4c6
RH		 1182018-10-05 Richard Henderson <rth@twiddle.net>
119 Stafford Horne <shorne@gmail.com>
120
121 * or1k-desc.c: Regenerate.
122 * or1k-desc.h: Regenerate.
123 * or1k-opc.c: Regenerate.
124 * or1k-opc.h: Regenerate.
125 * or1k-opinst.c: Regenerate.
126
c8e98e36
SH		 1272018-10-05 Richard Henderson <rth@twiddle.net>
128
129 * or1k-asm.c: Regenerated.
130 * or1k-desc.c: Regenerated.
131 * or1k-desc.h: Regenerated.
132 * or1k-dis.c: Regenerated.
133 * or1k-ibld.c: Regenerated.
134 * or1k-opc.c: Regenerated.
135 * or1k-opc.h: Regenerated.
136 * or1k-opinst.c: Regenerated.
137
1c4f3780
RH		 1382018-10-05 Richard Henderson <rth@twiddle.net>
139
140 * or1k-asm.c: Regenerate.
141
bde90be2
TC		 1422018-10-03 Tamar Christina <tamar.christina@arm.com>
143
144 * aarch64-asm.c (aarch64_opcode_encode): Apply constraint verifier.
145 * aarch64-dis.c (print_operands): Refactor to take notes.
146 (print_verifier_notes): New.
147 (print_aarch64_insn): Apply constraint verifier.
148 (print_insn_aarch64_word): Update call to print_aarch64_insn.
149 * aarch64-opc.c (aarch64_print_operand): Remove attribute, update notes format.
150
a68f4cd2
TC		 1512018-10-03 Tamar Christina <tamar.christina@arm.com>
152
153 * aarch64-opc.c (init_insn_block): New.
154 (verify_constraints, aarch64_is_destructive_by_operands): New.
155 * aarch64-opc.h (verify_constraints): New.
156
755b748f
TC		 1572018-10-03 Tamar Christina <tamar.christina@arm.com>
158
159 * aarch64-dis.c (aarch64_opcode_decode): Update verifier call.
160 * aarch64-opc.c (verify_ldpsw): Update arguments.
161
1d482394
TC		 1622018-10-03 Tamar Christina <tamar.christina@arm.com>
163
164 * aarch64-dis.c (ERR_OK, ERR_UND, ERR_UNP, ERR_NYI): Remove.
165 (aarch64_decode_insn, print_insn_aarch64_word): Use err_type.
166
7e84b55d
TC		 1672018-10-03 Tamar Christina <tamar.christina@arm.com>
168
169 * aarch64-asm.c (aarch64_opcode_encode): Add insn_sequence.
170 * aarch64-dis.c (insn_sequence): New.
171
eae424ae
TC		 1722018-10-03 Tamar Christina <tamar.christina@arm.com>
173
174 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN, _CRC_INSN,
175 _LSE_INSN, _LOR_INSN, RDMA_INSN, FF16_INSN, SF16_INSN, V8_2_INSN,
176 _SVE_INSN, V8_3_INSN, CNUM_INSN, RCPC_INSN, SHA2_INSN, AES_INSN,
177 V8_4_INSN, SHA3_INSN, SM4_INSN, FP16_V8_2_INSN, DOT_INSN): Initialize
178 constraints.
179 (_SVE_INSNC): New.
180 (struct aarch64_opcode): (fjcvtzs, ldpsw, ldpsw, esb, psb): Initialize
181 constraints.
182 (movprfx): Change _SVE_INSN into _SVE_INSNC, add C_SCAN_MOVPRFX and
183 F_SCAN flags.
184 (msb, mul, neg, not, orr, rbit, revb, revh, revw, sabd, scvtf,
185 sdiv, sdivr, sdot, smax, smin, smulh, splice, sqadd, sqdecd, sqdech,
186 sqdecp, sqdecw, sqincd, sqinch, sqincp, sqincw, sqsub, sub, subr, sxtb,
187 sxth, sxtw, uabd, ucvtf, udiv, udivr, udot, umax, umin, umulh, uqadd,
188 uqdecd, uqdech, uqdecp, uqdecw, uqincd, uqinch, uqincp, uqincw, uqsub,
189 uxtb, uxth, uxtw, bic, eon, orn, mov, fmov): Change _SVE_INSN into _SVE_INSNC and add
190 C_SCAN_MOVPRFX and C_MAX_ELEM constraints.
191
64a336ac
PD		 1922018-10-02 Palmer Dabbelt <palmer@sifive.com>
193
194 * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
195
6031ac35
SL		 1962018-09-23 Sandra Loosemore <sandra@codesourcery.com>
197
198 * nios2-dis.c (nios2_print_insn_arg): Make sure signed conversions
199 are used when extracting signed fields and converting them to
200 potentially 64-bit types.
201
f24ff6e9
SM		 2022018-09-21 Simon Marchi <simon.marchi@ericsson.com>
203
204 * Makefile.am: Remove NO_WMISSING_FIELD_INITIALIZERS.
205 * Makefile.in: Re-generate.
206 * aclocal.m4: Re-generate.
207 * configure: Re-generate.
208 * configure.ac: Remove check for -Wno-missing-field-initializers.
209 * csky-opc.h (csky_v1_opcodes): Initialize all fields of last element.
210 (csky_v2_opcodes): Likewise.
211
53b6d6f5
MR		 2122018-09-20 Maciej W. Rozycki <macro@linux-mips.org>
213
214 * arc-nps400-tbl.h: Append `ull' to large constants throughout.
215
fbaf61ad
NC		 2162018-09-20 Nelson Chu <nelson.chu1990@gmail.com>
217
218 * nds32-asm.c (operand_fields): Remove the unused fields.
219 (nds32_opcodes): Remove the unused instructions.
220 * nds32-dis.c (nds32_ex9_info): Removed.
221 (nds32_parse_opcode): Updated.
222 (print_insn_nds32): Likewise.
223 * nds32-asm.c (config.h, stdlib.h, string.h): New includes.
224 (LEX_SET_FIELD, LEX_GET_FIELD): Update defines.
225 (nds32_asm_init, build_operand_hash_table, build_keyword_hash_table,
226 build_opcode_hash_table): New functions.
227 (nds32_keyword_table, nds32_keyword_count_table, nds32_field_table,
228 nds32_opcode_table): New.
229 (hw_ktabs): Declare it to a pointer rather than an array.
230 (build_hash_table): Removed.
231 * nds32-asm.h (enum): Add SYN_INPUT, SYN_OUTPUT, SYN_LOPT,
232 SYN_ROPT and upadte HW_GPR and HW_INT.
233 * nds32-dis.c (keywords): Remove const.
234 (match_field): New function.
235 (nds32_parse_opcode): Updated.
236 * disassemble.c (disassemble_init_for_target):
237 Add disassemble_init_nds32.
238 * nds32-dis.c (eum map_type): New.
239 (nds32_private_data): Likewise.
240 (get_mapping_symbol_type, is_mapping_symbol, nds32_symbol_is_valid,
241 nds32_add_opcode_hash_table, disassemble_init_nds32): New functions.
242 (print_insn_nds32): Updated.
243 * nds32-asm.c (parse_aext_reg): Add new parameter.
244 (parse_re, parse_re2, parse_aext_reg): Only reduced registers
245 are allowed to use.
246 All callers changed.
247 * nds32-asm.c (keyword_usr, keyword_sr): Updated.
248 (operand_fields): Add new fields.
249 (nds32_opcodes): Add new instructions.
250 (keyword_aridxi_mx): New keyword.
251 * nds32-asm.h (enum): Add NASM_ATTR_DSP_ISAEXT, HW_AEXT_ARIDXI_MX
252 and NASM_ATTR_ZOL.
253 (ALU2_1, ALU2_2, ALU2_3): New macros.
254 * nds32-dis.c (nds32_filter_unknown_insn): Updated.
255
4e2b1898
JW		 2562018-09-17 Kito Cheng <kito@andestech.com>
257
258 * riscv-opc.c (riscv_opcodes): Adjust the order of ble and bleu.
259
04e2a182
L		 2602018-09-17 H.J. Lu <hongjiu.lu@intel.com>
261
262 PR gas/23670
263 * i386-dis-evex.h (evex_table): Use EVEX_LEN_0F6E_P_2,
264 EVEX_LEN_0F7E_P_1, EVEX_LEN_0F7E_P_2 and EVEX_LEN_0FD6_P_2.
265 (EVEX_LEN_0F6E_P_2): New EVEX_LEN_TABLE entry.
266 (EVEX_LEN_0F7E_P_1): Likewise.
267 (EVEX_LEN_0F7E_P_2): Likewise.
268 (EVEX_LEN_0FD6_P_2): Likewise.
269 * i386-dis.c (USE_EVEX_LEN_TABLE): New.
270 (EVEX_LEN_TABLE): Likewise.
271 (EVEX_LEN_0F6E_P_2): New enum.
272 (EVEX_LEN_0F7E_P_1): Likewise.
273 (EVEX_LEN_0F7E_P_2): Likewise.
274 (EVEX_LEN_0FD6_P_2): Likewise.
275 (evex_len_table): New.
276 (get_valid_dis386): Handle USE_EVEX_LEN_TABLE.
277 * i386-opc.tbl: Set EVex=2 on EVEX.128 only vmovd and vmovq.
278 * i386-tbl.h: Regenerated.
279
d5f787c2
L		 2802018-09-17 H.J. Lu <hongjiu.lu@intel.com>
281
282 PR gas/23665
283 * i386-dis.c (vex_len_table): Update VEX_LEN_0F6E_P_2 and
284 VEX_LEN_0F7E_P_2 entries.
285 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovd and vmovq.
286 * i386-tbl.h: Regenerated.
287
ec6f095a
L		 2882018-09-17 H.J. Lu <hongjiu.lu@intel.com>
289
290 * i386-dis.c (VZERO_Fixup): Removed.
291 (VZERO): Likewise.
292 (VEX_LEN_0F10_P_1): Likewise.
293 (VEX_LEN_0F10_P_3): Likewise.
294 (VEX_LEN_0F11_P_1): Likewise.
295 (VEX_LEN_0F11_P_3): Likewise.
296 (VEX_LEN_0F2E_P_0): Likewise.
297 (VEX_LEN_0F2E_P_2): Likewise.
298 (VEX_LEN_0F2F_P_0): Likewise.
299 (VEX_LEN_0F2F_P_2): Likewise.
300 (VEX_LEN_0F51_P_1): Likewise.
301 (VEX_LEN_0F51_P_3): Likewise.
302 (VEX_LEN_0F52_P_1): Likewise.
303 (VEX_LEN_0F53_P_1): Likewise.
304 (VEX_LEN_0F58_P_1): Likewise.
305 (VEX_LEN_0F58_P_3): Likewise.
306 (VEX_LEN_0F59_P_1): Likewise.
307 (VEX_LEN_0F59_P_3): Likewise.
308 (VEX_LEN_0F5A_P_1): Likewise.
309 (VEX_LEN_0F5A_P_3): Likewise.
310 (VEX_LEN_0F5C_P_1): Likewise.
311 (VEX_LEN_0F5C_P_3): Likewise.
312 (VEX_LEN_0F5D_P_1): Likewise.
313 (VEX_LEN_0F5D_P_3): Likewise.
314 (VEX_LEN_0F5E_P_1): Likewise.
315 (VEX_LEN_0F5E_P_3): Likewise.
316 (VEX_LEN_0F5F_P_1): Likewise.
317 (VEX_LEN_0F5F_P_3): Likewise.
318 (VEX_LEN_0FC2_P_1): Likewise.
319 (VEX_LEN_0FC2_P_3): Likewise.
320 (VEX_LEN_0F3A0A_P_2): Likewise.
321 (VEX_LEN_0F3A0B_P_2): Likewise.
322 (VEX_W_0F10_P_0): Likewise.
323 (VEX_W_0F10_P_1): Likewise.
324 (VEX_W_0F10_P_2): Likewise.
325 (VEX_W_0F10_P_3): Likewise.
326 (VEX_W_0F11_P_0): Likewise.
327 (VEX_W_0F11_P_1): Likewise.
328 (VEX_W_0F11_P_2): Likewise.
329 (VEX_W_0F11_P_3): Likewise.
330 (VEX_W_0F12_P_0_M_0): Likewise.
331 (VEX_W_0F12_P_0_M_1): Likewise.
332 (VEX_W_0F12_P_1): Likewise.
333 (VEX_W_0F12_P_2): Likewise.
334 (VEX_W_0F12_P_3): Likewise.
335 (VEX_W_0F13_M_0): Likewise.
336 (VEX_W_0F14): Likewise.
337 (VEX_W_0F15): Likewise.
338 (VEX_W_0F16_P_0_M_0): Likewise.
339 (VEX_W_0F16_P_0_M_1): Likewise.
340 (VEX_W_0F16_P_1): Likewise.
341 (VEX_W_0F16_P_2): Likewise.
342 (VEX_W_0F17_M_0): Likewise.
343 (VEX_W_0F28): Likewise.
344 (VEX_W_0F29): Likewise.
345 (VEX_W_0F2B_M_0): Likewise.
346 (VEX_W_0F2E_P_0): Likewise.
347 (VEX_W_0F2E_P_2): Likewise.
348 (VEX_W_0F2F_P_0): Likewise.
349 (VEX_W_0F2F_P_2): Likewise.
350 (VEX_W_0F50_M_0): Likewise.
351 (VEX_W_0F51_P_0): Likewise.
352 (VEX_W_0F51_P_1): Likewise.
353 (VEX_W_0F51_P_2): Likewise.
354 (VEX_W_0F51_P_3): Likewise.
355 (VEX_W_0F52_P_0): Likewise.
356 (VEX_W_0F52_P_1): Likewise.
357 (VEX_W_0F53_P_0): Likewise.
358 (VEX_W_0F53_P_1): Likewise.
359 (VEX_W_0F58_P_0): Likewise.
360 (VEX_W_0F58_P_1): Likewise.
361 (VEX_W_0F58_P_2): Likewise.
362 (VEX_W_0F58_P_3): Likewise.
363 (VEX_W_0F59_P_0): Likewise.
364 (VEX_W_0F59_P_1): Likewise.
365 (VEX_W_0F59_P_2): Likewise.
366 (VEX_W_0F59_P_3): Likewise.
367 (VEX_W_0F5A_P_0): Likewise.
368 (VEX_W_0F5A_P_1): Likewise.
369 (VEX_W_0F5A_P_3): Likewise.
370 (VEX_W_0F5B_P_0): Likewise.
371 (VEX_W_0F5B_P_1): Likewise.
372 (VEX_W_0F5B_P_2): Likewise.
373 (VEX_W_0F5C_P_0): Likewise.
374 (VEX_W_0F5C_P_1): Likewise.
375 (VEX_W_0F5C_P_2): Likewise.
376 (VEX_W_0F5C_P_3): Likewise.
377 (VEX_W_0F5D_P_0): Likewise.
378 (VEX_W_0F5D_P_1): Likewise.
379 (VEX_W_0F5D_P_2): Likewise.
380 (VEX_W_0F5D_P_3): Likewise.
381 (VEX_W_0F5E_P_0): Likewise.
382 (VEX_W_0F5E_P_1): Likewise.
383 (VEX_W_0F5E_P_2): Likewise.
384 (VEX_W_0F5E_P_3): Likewise.
385 (VEX_W_0F5F_P_0): Likewise.
386 (VEX_W_0F5F_P_1): Likewise.
387 (VEX_W_0F5F_P_2): Likewise.
388 (VEX_W_0F5F_P_3): Likewise.
389 (VEX_W_0F60_P_2): Likewise.
390 (VEX_W_0F61_P_2): Likewise.
391 (VEX_W_0F62_P_2): Likewise.
392 (VEX_W_0F63_P_2): Likewise.
393 (VEX_W_0F64_P_2): Likewise.
394 (VEX_W_0F65_P_2): Likewise.
395 (VEX_W_0F66_P_2): Likewise.
396 (VEX_W_0F67_P_2): Likewise.
397 (VEX_W_0F68_P_2): Likewise.
398 (VEX_W_0F69_P_2): Likewise.
399 (VEX_W_0F6A_P_2): Likewise.
400 (VEX_W_0F6B_P_2): Likewise.
401 (VEX_W_0F6C_P_2): Likewise.
402 (VEX_W_0F6D_P_2): Likewise.
403 (VEX_W_0F6F_P_1): Likewise.
404 (VEX_W_0F6F_P_2): Likewise.
405 (VEX_W_0F70_P_1): Likewise.
406 (VEX_W_0F70_P_2): Likewise.
407 (VEX_W_0F70_P_3): Likewise.
408 (VEX_W_0F71_R_2_P_2): Likewise.
409 (VEX_W_0F71_R_4_P_2): Likewise.
410 (VEX_W_0F71_R_6_P_2): Likewise.
411 (VEX_W_0F72_R_2_P_2): Likewise.
412 (VEX_W_0F72_R_4_P_2): Likewise.
413 (VEX_W_0F72_R_6_P_2): Likewise.
414 (VEX_W_0F73_R_2_P_2): Likewise.
415 (VEX_W_0F73_R_3_P_2): Likewise.
416 (VEX_W_0F73_R_6_P_2): Likewise.
417 (VEX_W_0F73_R_7_P_2): Likewise.
418 (VEX_W_0F74_P_2): Likewise.
419 (VEX_W_0F75_P_2): Likewise.
420 (VEX_W_0F76_P_2): Likewise.
421 (VEX_W_0F77_P_0): Likewise.
422 (VEX_W_0F7C_P_2): Likewise.
423 (VEX_W_0F7C_P_3): Likewise.
424 (VEX_W_0F7D_P_2): Likewise.
425 (VEX_W_0F7D_P_3): Likewise.
426 (VEX_W_0F7E_P_1): Likewise.
427 (VEX_W_0F7F_P_1): Likewise.
428 (VEX_W_0F7F_P_2): Likewise.
429 (VEX_W_0FAE_R_2_M_0): Likewise.
430 (VEX_W_0FAE_R_3_M_0): Likewise.
431 (VEX_W_0FC2_P_0): Likewise.
432 (VEX_W_0FC2_P_1): Likewise.
433 (VEX_W_0FC2_P_2): Likewise.
434 (VEX_W_0FC2_P_3): Likewise.
435 (VEX_W_0FD0_P_2): Likewise.
436 (VEX_W_0FD0_P_3): Likewise.
437 (VEX_W_0FD1_P_2): Likewise.
438 (VEX_W_0FD2_P_2): Likewise.
439 (VEX_W_0FD3_P_2): Likewise.
440 (VEX_W_0FD4_P_2): Likewise.
441 (VEX_W_0FD5_P_2): Likewise.
442 (VEX_W_0FD6_P_2): Likewise.
443 (VEX_W_0FD7_P_2_M_1): Likewise.
444 (VEX_W_0FD8_P_2): Likewise.
445 (VEX_W_0FD9_P_2): Likewise.
446 (VEX_W_0FDA_P_2): Likewise.
447 (VEX_W_0FDB_P_2): Likewise.
448 (VEX_W_0FDC_P_2): Likewise.
449 (VEX_W_0FDD_P_2): Likewise.
450 (VEX_W_0FDE_P_2): Likewise.
451 (VEX_W_0FDF_P_2): Likewise.
452 (VEX_W_0FE0_P_2): Likewise.
453 (VEX_W_0FE1_P_2): Likewise.
454 (VEX_W_0FE2_P_2): Likewise.
455 (VEX_W_0FE3_P_2): Likewise.
456 (VEX_W_0FE4_P_2): Likewise.
457 (VEX_W_0FE5_P_2): Likewise.
458 (VEX_W_0FE6_P_1): Likewise.
459 (VEX_W_0FE6_P_2): Likewise.
460 (VEX_W_0FE6_P_3): Likewise.
461 (VEX_W_0FE7_P_2_M_0): Likewise.
462 (VEX_W_0FE8_P_2): Likewise.
463 (VEX_W_0FE9_P_2): Likewise.
464 (VEX_W_0FEA_P_2): Likewise.
465 (VEX_W_0FEB_P_2): Likewise.
466 (VEX_W_0FEC_P_2): Likewise.
467 (VEX_W_0FED_P_2): Likewise.
468 (VEX_W_0FEE_P_2): Likewise.
469 (VEX_W_0FEF_P_2): Likewise.
470 (VEX_W_0FF0_P_3_M_0): Likewise.
471 (VEX_W_0FF1_P_2): Likewise.
472 (VEX_W_0FF2_P_2): Likewise.
473 (VEX_W_0FF3_P_2): Likewise.
474 (VEX_W_0FF4_P_2): Likewise.
475 (VEX_W_0FF5_P_2): Likewise.
476 (VEX_W_0FF6_P_2): Likewise.
477 (VEX_W_0FF7_P_2): Likewise.
478 (VEX_W_0FF8_P_2): Likewise.
479 (VEX_W_0FF9_P_2): Likewise.
480 (VEX_W_0FFA_P_2): Likewise.
481 (VEX_W_0FFB_P_2): Likewise.
482 (VEX_W_0FFC_P_2): Likewise.
483 (VEX_W_0FFD_P_2): Likewise.
484 (VEX_W_0FFE_P_2): Likewise.
485 (VEX_W_0F3800_P_2): Likewise.
486 (VEX_W_0F3801_P_2): Likewise.
487 (VEX_W_0F3802_P_2): Likewise.
488 (VEX_W_0F3803_P_2): Likewise.
489 (VEX_W_0F3804_P_2): Likewise.
490 (VEX_W_0F3805_P_2): Likewise.
491 (VEX_W_0F3806_P_2): Likewise.
492 (VEX_W_0F3807_P_2): Likewise.
493 (VEX_W_0F3808_P_2): Likewise.
494 (VEX_W_0F3809_P_2): Likewise.
495 (VEX_W_0F380A_P_2): Likewise.
496 (VEX_W_0F380B_P_2): Likewise.
497 (VEX_W_0F3817_P_2): Likewise.
498 (VEX_W_0F381C_P_2): Likewise.
499 (VEX_W_0F381D_P_2): Likewise.
500 (VEX_W_0F381E_P_2): Likewise.
501 (VEX_W_0F3820_P_2): Likewise.
502 (VEX_W_0F3821_P_2): Likewise.
503 (VEX_W_0F3822_P_2): Likewise.
504 (VEX_W_0F3823_P_2): Likewise.
505 (VEX_W_0F3824_P_2): Likewise.
506 (VEX_W_0F3825_P_2): Likewise.
507 (VEX_W_0F3828_P_2): Likewise.
508 (VEX_W_0F3829_P_2): Likewise.
509 (VEX_W_0F382A_P_2_M_0): Likewise.
510 (VEX_W_0F382B_P_2): Likewise.
511 (VEX_W_0F3830_P_2): Likewise.
512 (VEX_W_0F3831_P_2): Likewise.
513 (VEX_W_0F3832_P_2): Likewise.
514 (VEX_W_0F3833_P_2): Likewise.
515 (VEX_W_0F3834_P_2): Likewise.
516 (VEX_W_0F3835_P_2): Likewise.
517 (VEX_W_0F3837_P_2): Likewise.
518 (VEX_W_0F3838_P_2): Likewise.
519 (VEX_W_0F3839_P_2): Likewise.
520 (VEX_W_0F383A_P_2): Likewise.
521 (VEX_W_0F383B_P_2): Likewise.
522 (VEX_W_0F383C_P_2): Likewise.
523 (VEX_W_0F383D_P_2): Likewise.
524 (VEX_W_0F383E_P_2): Likewise.
525 (VEX_W_0F383F_P_2): Likewise.
526 (VEX_W_0F3840_P_2): Likewise.
527 (VEX_W_0F3841_P_2): Likewise.
528 (VEX_W_0F38DB_P_2): Likewise.
529 (VEX_W_0F3A08_P_2): Likewise.
530 (VEX_W_0F3A09_P_2): Likewise.
531 (VEX_W_0F3A0A_P_2): Likewise.
532 (VEX_W_0F3A0B_P_2): Likewise.
533 (VEX_W_0F3A0C_P_2): Likewise.
534 (VEX_W_0F3A0D_P_2): Likewise.
535 (VEX_W_0F3A0E_P_2): Likewise.
536 (VEX_W_0F3A0F_P_2): Likewise.
537 (VEX_W_0F3A21_P_2): Likewise.
538 (VEX_W_0F3A40_P_2): Likewise.
539 (VEX_W_0F3A41_P_2): Likewise.
540 (VEX_W_0F3A42_P_2): Likewise.
541 (VEX_W_0F3A62_P_2): Likewise.
542 (VEX_W_0F3A63_P_2): Likewise.
543 (VEX_W_0F3ADF_P_2): Likewise.
544 (VEX_LEN_0F77_P_0): New.
545 (prefix_table): Update PREFIX_VEX_0F10, PREFIX_VEX_0F11,
546 PREFIX_VEX_0F12, PREFIX_VEX_0F16, PREFIX_VEX_0F2E,
547 PREFIX_VEX_0F2F, PREFIX_VEX_0F51, PREFIX_VEX_0F52,
548 PREFIX_VEX_0F53, PREFIX_VEX_0F58, PREFIX_VEX_0F59,
549 PREFIX_VEX_0F5A, PREFIX_VEX_0F5B, PREFIX_VEX_0F5C,
550 PREFIX_VEX_0F5D, PREFIX_VEX_0F5E, PREFIX_VEX_0F5F,
551 PREFIX_VEX_0F60, PREFIX_VEX_0F61, PREFIX_VEX_0F62,
552 PREFIX_VEX_0F63, PREFIX_VEX_0F64, PREFIX_VEX_0F65,
553 PREFIX_VEX_0F66, PREFIX_VEX_0F67, PREFIX_VEX_0F68,
554 PREFIX_VEX_0F69, PREFIX_VEX_0F6A, PREFIX_VEX_0F6B,
555 PREFIX_VEX_0F6C, PREFIX_VEX_0F6D, PREFIX_VEX_0F6F,
556 PREFIX_VEX_0F70, PREFIX_VEX_0F71_REG_2, PREFIX_VEX_0F71_REG_4,
557 PREFIX_VEX_0F71_REG_6, PREFIX_VEX_0F72_REG_4,
558 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
559 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
560 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74, PREFIX_VEX_0F75,
561 PREFIX_VEX_0F76, PREFIX_VEX_0F77, PREFIX_VEX_0F7C,
562 PREFIX_VEX_0F7D, PREFIX_VEX_0F7F, PREFIX_VEX_0FC2,
563 PREFIX_VEX_0FD0, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
564 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
565 PREFIX_VEX_0FD8, PREFIX_VEX_0FD9, PREFIX_VEX_0FDA,
566 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
567 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
568 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
569 PREFIX_VEX_0FE5, PREFIX_VEX_0FE6, PREFIX_VEX_0FE8,
570 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
571 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
572 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1. PREFIX_VEX_0FF2,
573 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
574 PREFIX_VEX_0FF6, PREFIX_VEX_0FF8, PREFIX_VEX_0FF9,
575 PREFIX_VEX_0FFA, PREFIX_VEX_0FFB, PREFIX_VEX_0FFC,
576 PREFIX_VEX_0FFD, PREFIX_VEX_0FFE, PREFIX_VEX_0F3800,
577 PREFIX_VEX_0F3801, PREFIX_VEX_0F3802, PREFIX_VEX_0F3803,
578 PREFIX_VEX_0F3804, PREFIX_VEX_0F3805, PREFIX_VEX_0F3806,
579 PREFIX_VEX_0F3807, PREFIX_VEX_0F3808, PREFIX_VEX_0F3809,
580 PREFIX_VEX_0F380A, PREFIX_VEX_0F380B, PREFIX_VEX_0F3817,
581 PREFIX_VEX_0F381C, PREFIX_VEX_0F381D, PREFIX_VEX_0F381E,
582 PREFIX_VEX_0F3820, PREFIX_VEX_0F3821, PREFIX_VEX_0F3822,
583 PREFIX_VEX_0F3823, PREFIX_VEX_0F3824, PREFIX_VEX_0F3825,
584 PREFIX_VEX_0F3828, PREFIX_VEX_0F3829, PREFIX_VEX_0F382B,
585 PREFIX_VEX_0F382C, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
586 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
587 PREFIX_VEX_0F3837, PREFIX_VEX_0F3838, PREFIX_VEX_0F3839,
588 PREFIX_VEX_0F383A, PREFIX_VEX_0F383B, PREFIX_VEX_0F383C,
589 PREFIX_VEX_0F383D, PREFIX_VEX_0F383E, PREFIX_VEX_0F383F,
590 PREFIX_VEX_0F3840, PREFIX_VEX_0F3A08, PREFIX_VEX_0F3A09,
591 PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B, PREFIX_VEX_0F3A0C,
592 PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E, PREFIX_VEX_0F3A0F,
593 PREFIX_VEX_0F3A40 and PREFIX_VEX_0F3A42 entries.
594 (vex_table): Update VEX 0F28 and 0F29 entries.
595 (vex_len_table): Update VEX_LEN_0F10_P_1, VEX_LEN_0F10_P_3,
596 VEX_LEN_0F11_P_1, VEX_LEN_0F11_P_3, VEX_LEN_0F2E_P_0,
597 VEX_LEN_0F2E_P_2, VEX_LEN_0F2F_P_0, VEX_LEN_0F2F_P_2,
598 VEX_LEN_0F51_P_1, VEX_LEN_0F51_P_3, VEX_LEN_0F52_P_1,
599 VEX_LEN_0F53_P_1, VEX_LEN_0F58_P_1, VEX_LEN_0F58_P_3,
600 VEX_LEN_0F59_P_1, VEX_LEN_0F59_P_3, VEX_LEN_0F5A_P_1,
601 VEX_LEN_0F5A_P_3, VEX_LEN_0F5C_P_1, VEX_LEN_0F5C_P_3,
602 VEX_LEN_0F5D_P_1, VEX_LEN_0F5D_P_3, VEX_LEN_0F5E_P_1,
603 VEX_LEN_0F5E_P_3, VEX_LEN_0F5F_P_1, VEX_LEN_0F5F_P_3,
604 VEX_LEN_0FC2_P_1, VEX_LEN_0FC2_P_3, VEX_LEN_0F3A0A_P_2 and
605 VEX_LEN_0F3A0B_P_2 entries.
606 (vex_w_table): Remove VEX_W_0F10_P_0, VEX_W_0F10_P_1,
607 VEX_W_0F10_P_2, VEX_W_0F10_P_3, VEX_W_0F11_P_0, VEX_W_0F11_P_1,
608 VEX_W_0F11_P_2, VEX_W_0F11_P_3, VEX_W_0F12_P_0_M_0,
609 VEX_W_0F12_P_0_M_1, VEX_W_0F12_P_1, VEX_W_0F12_P_2,
610 VEX_W_0F12_P_3, VEX_W_0F13_M_0, VEX_W_0F14, VEX_W_0F15,
611 VEX_W_0F16_P_0_M_0, VEX_W_0F16_P_0_M_1, VEX_W_0F16_P_1,
612 VEX_W_0F16_P_2, VEX_W_0F17_M_0, VEX_W_0F28, VEX_W_0F29,
613 VEX_W_0F2B_M_0, VEX_W_0F2E_P_0, VEX_W_0F2E_P_2, VEX_W_0F2F_P_0,
614 VEX_W_0F2F_P_2, VEX_W_0F50_M_0, VEX_W_0F51_P_0, VEX_W_0F51_P_1,
615 VEX_W_0F51_P_2, VEX_W_0F51_P_3, VEX_W_0F52_P_0, VEX_W_0F52_P_1,
616 VEX_W_0F53_P_0, VEX_W_0F53_P_1, VEX_W_0F58_P_0, VEX_W_0F58_P_1,
617 VEX_W_0F58_P_2, VEX_W_0F58_P_3, VEX_W_0F59_P_0, VEX_W_0F59_P_1,
618 VEX_W_0F59_P_2, VEX_W_0F59_P_3, VEX_W_0F5A_P_0, VEX_W_0F5A_P_1,
619 VEX_W_0F5A_P_3, VEX_W_0F5B_P_0, VEX_W_0F5B_P_1, VEX_W_0F5B_P_2,
620 VEX_W_0F5C_P_0, VEX_W_0F5C_P_1, VEX_W_0F5C_P_2, VEX_W_0F5C_P_3,
621 VEX_W_0F5D_P_0, VEX_W_0F5D_P_1, VEX_W_0F5D_P_2, VEX_W_0F5D_P_3,
622 VEX_W_0F5E_P_0, VEX_W_0F5E_P_1, VEX_W_0F5E_P_2, VEX_W_0F5E_P_3,
623 VEX_W_0F5F_P_0, VEX_W_0F5F_P_1, VEX_W_0F5F_P_2, VEX_W_0F5F_P_3,
624 VEX_W_0F60_P_2, VEX_W_0F61_P_2, VEX_W_0F62_P_2, VEX_W_0F63_P_2,
625 VEX_W_0F64_P_2, VEX_W_0F65_P_2, VEX_W_0F66_P_2, VEX_W_0F67_P_2,
626 VEX_W_0F68_P_2, VEX_W_0F69_P_2, VEX_W_0F6A_P_2, VEX_W_0F6B_P_2,
627 VEX_W_0F6C_P_2, VEX_W_0F6D_P_2, VEX_W_0F6F_P_1, VEX_W_0F6F_P_2,
628 VEX_W_0F70_P_1, VEX_W_0F70_P_2, VEX_W_0F70_P_3,
629 VEX_W_0F71_R_2_P_2, VEX_W_0F71_R_4_P_2, VEX_W_0F71_R_6_P_2,
630 VEX_W_0F72_R_2_P_2, VEX_W_0F72_R_4_P_2, VEX_W_0F72_R_6_P_2,
631 VEX_W_0F73_R_2_P_2, VEX_W_0F73_R_3_P_2, VEX_W_0F73_R_6_P_2,
632 VEX_W_0F73_R_7_P_2, VEX_W_0F74_P_2, VEX_W_0F75_P_2,
633 VEX_W_0F76_P_2, VEX_W_0F77_P_0, VEX_W_0F7C_P_2, VEX_W_0F7C_P_3,
634 VEX_W_0F7D_P_2, VEX_W_0F7D_P_3, VEX_W_0F7E_P_1, VEX_W_0F7F_P_1,
635 VEX_W_0F7F_P_2, VEX_W_0FAE_R_2_M_0, VEX_W_0FAE_R_3_M_0,
636 VEX_W_0FC2_P_0, VEX_W_0FC2_P_1, VEX_W_0FC2_P_2, VEX_W_0FC2_P_3,
637 VEX_W_0FD0_P_2, VEX_W_0FD0_P_3, VEX_W_0FD1_P_2, VEX_W_0FD2_P_2,
638 VEX_W_0FD3_P_2, VEX_W_0FD4_P_2, VEX_W_0FD5_P_2, VEX_W_0FD6_P_2,
639 VEX_W_0FD7_P_2_M_1, VEX_W_0FD8_P_2, VEX_W_0FD9_P_2,
640 VEX_W_0FDA_P_2, VEX_W_0FDB_P_2, VEX_W_0FDC_P_2, VEX_W_0FDD_P_2,
641 VEX_W_0FDE_P_2, VEX_W_0FDF_P_2, VEX_W_0FE0_P_2, VEX_W_0FE1_P_2,
642 VEX_W_0FE2_P_2, VEX_W_0FE3_P_2, VEX_W_0FE4_P_2, VEX_W_0FE5_P_2,
643 VEX_W_0FE6_P_1, VEX_W_0FE6_P_2, VEX_W_0FE6_P_3,
644 VEX_W_0FE7_P_2_M_0, VEX_W_0FE8_P_2, VEX_W_0FE9_P_2,
645 VEX_W_0FEA_P_2, VEX_W_0FEB_P_2, VEX_W_0FEC_P_2, VEX_W_0FED_P_2,
646 VEX_W_0FEE_P_2, VEX_W_0FEF_P_2, VEX_W_0FF0_P_3_M_0,
647 VEX_W_0FF1_P_2, VEX_W_0FF2_P_2, VEX_W_0FF3_P_2, VEX_W_0FF4_P_2,
648 VEX_W_0FF5_P_2, VEX_W_0FF6_P_2, VEX_W_0FF7_P_2, VEX_W_0FF8_P_2,
649 VEX_W_0FF9_P_2, VEX_W_0FFA_P_2, VEX_W_0FFB_P_2, VEX_W_0FFC_P_2,
650 VEX_W_0FFD_P_2, VEX_W_0FFE_P_2, VEX_W_0F3800_P_2,
651 VEX_W_0F3801_P_2, VEX_W_0F3802_P_2, VEX_W_0F3803_P_2,
652 VEX_W_0F3804_P_2, VEX_W_0F3805_P_2, VEX_W_0F3806_P_2,
653 VEX_W_0F3807_P_2, VEX_W_0F3808_P_2, VEX_W_0F3809_P_2,
654 VEX_W_0F380A_P_2, VEX_W_0F380B_P_2, VEX_W_0F3817_P_2,
655 VEX_W_0F381C_P_2, VEX_W_0F381D_P_2, VEX_W_0F381E_P_2,
656 VEX_W_0F3820_P_2, VEX_W_0F3821_P_2, VEX_W_0F3822_P_2,
657 VEX_W_0F3823_P_2, VEX_W_0F3824_P_2, VEX_W_0F3825_P_2,
658 VEX_W_0F3828_P_2, VEX_W_0F3829_P_2, VEX_W_0F382A_P_2_M_0,
659 VEX_W_0F382B_P_2, VEX_W_0F3830_P_2, VEX_W_0F3831_P_2,
660 VEX_W_0F3832_P_2, VEX_W_0F3833_P_2, VEX_W_0F3834_P_2,
661 VEX_W_0F3835_P_2, VEX_W_0F3837_P_2, VEX_W_0F3838_P_2,
662 VEX_W_0F3839_P_2, VEX_W_0F383A_P_2, VEX_W_0F383B_P_2,
663 VEX_W_0F383C_P_2, VEX_W_0F383D_P_2, VEX_W_0F383E_P_2,
664 VEX_W_0F383F_P_2, VEX_W_0F3840_P_2, VEX_W_0F3841_P_2,
665 VEX_W_0F38DB_P_2, VEX_W_0F3A08_P_2, VEX_W_0F3A09_P_2,
666 VEX_W_0F3A0A_P_2, VEX_W_0F3A0B_P_2, VEX_W_0F3A0C_P_2,
667 VEX_W_0F3A0D_P_2, VEX_W_0F3A0E_P_2, VEX_W_0F3A0F_P_2,
668 VEX_W_0F3A21_P_2, VEX_W_0F3A40_P_2, VEX_W_0F3A41_P_2,
669 VEX_W_0F3A42_P_2, VEX_W_0F3A62_P_2, VEX_W_0F3A63_P_2 and
670 VEX_W_0F3ADF_P_2 entries.
671 (mod_table): Update MOD_VEX_0F2B, MOD_VEX_0F50,
672 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
673 MOD_VEX_0FF0_PREFIX_3 and MOD_VEX_0F382A_PREFIX_2 entries.
674
6fa52824
L		 6752018-09-17 H.J. Lu <hongjiu.lu@intel.com>
676
677 * i386-opc.tbl (VexWIG): New.
678 Replace VexW=3 with VexWIG.
679
db4cc665
L		 6802018-09-15 H.J. Lu <hongjiu.lu@intel.com>
681
682 * i386-opc.tbl: Set VexW=3 on AVX vrsqrtss.
683 * i386-tbl.h: Regenerated.
684
3c374143
L		 6852018-09-15 H.J. Lu <hongjiu.lu@intel.com>
686
687 PR gas/23665
688 * i386-dis.c (vex_len_table): Update VEX_LEN_0F7E_P_1 and
689 VEX_LEN_0FD6_P_2 entries.
690 * i386-opc.tbl: Set Vex=1 on VEX.128 only vmovq.
691 * i386-tbl.h: Regenerated.
692
6865c043
L		 6932018-09-14 H.J. Lu <hongjiu.lu@intel.com>
694
695 PR gas/23642
696 * i386-opc.h (VEXWIG): New.
697 * i386-opc.tbl: Set VexW=3 on VEX/EVEX WIG instructions.
698 * i386-tbl.h: Regenerated.
699
70df6fc9
L		 7002018-09-14 H.J. Lu <hongjiu.lu@intel.com>
701
702 PR binutils/23655
703 * i386-dis-evex.h: Replace EXxEVexR with EXxEVexR64 for
704 vcvtsi2sd%LQ and vcvtusi2sd%LQ.
705 * i386-dis.c (EXxEVexR64): New.
706 (evex_rounding_64_mode): Likewise.
707 (OP_Rounding): Handle evex_rounding_64_mode.
708
d20dee9e
L		 7092018-09-14 H.J. Lu <hongjiu.lu@intel.com>
710
711 PR binutils/23655
712 * i386-dis-evex.h (evex_table): Replace Eq with Edqa for
713 vcvtsi2ss%LQ, vcvtsi2sd%LQ, vcvtusi2ss%LQ and vcvtusi2sd%LQ.
714 * i386-dis.c (Edqa): New.
715 (dqa_mode): Likewise.
716 (intel_operand_size): Handle dqa_mode as m_mode.
717 (OP_E_register): Handle dqa_mode as dq_mode.
718 (OP_E_memory): Set shift for dqa_mode based on address_mode.
719
5074ad8a
L		 7202018-09-14 H.J. Lu <hongjiu.lu@intel.com>
721
722 * i386-dis.c (OP_E_memory): Reformat.
723
556059dd
JB		 7242018-09-14 Jan Beulich <jbeulich@suse.com>
725
726 * i386-opc.tbl (crc32): Fold byte and word forms.
727 * i386-tbl.h: Re-generate.
728
41d1ab6a
L		 7292018-09-13 H.J. Lu <hongjiu.lu@intel.com>
730
731 * i386-opc.tbl: Add VexW=1 to VEX.W0 VEX movd, cvtsi2ss, cvtsi2sd,
732 pextrd, pinsrd, vcvtsi2sd, vcvtsi2ss, vmovd, vpextrd and vpinsrd.
733 Add VexW=2 to VEX.W1 VEX movq, pextrq, pinsrq, vmovq, vpextrq and
734 vpinsrq. Remove VexW=1 from WIG VEX movq and vmovq.
735 * i386-tbl.h: Regenerated.
736
57f6375e
JB		 7372018-09-13 Jan Beulich <jbeulich@suse.com>
738
739 * i386-opc.tbl (mov, movq, movdir64b): Drop IgnoreSize where
740 meaningless.
741 (invept, invvpid, vcvtph2ps, vcvtps2ph, bndmov, xrstors,
742 xrstors64, xsaves, xsaves64, xsavec, xsavec64, rdpid, incsspq,
743 rdsspq, saveprevssp, setssbsy, endbr32, endbr64): Drop IgnoreSize.
744 * i386-tbl.h: Re-generate.
745
2589a7e5
JB		 7462018-09-13 Jan Beulich <jbeulich@suse.com>
747
748 * i386-opc.tbl: Drop IgnoreSize from AVX512_4FMAPS and
749 AVX512_4VNNIW insns.
750 * i386-tbl.h: Re-generate.
751
a760eb41
JB		 7522018-09-13 Jan Beulich <jbeulich@suse.com>
753
754 * i386-opc.tbl: Drop IgnoreSize from AVX512DQ insns where
755 meaningless.
756 * i386-tbl.h: Re-generate.
757
e9042658
JB		 7582018-09-13 Jan Beulich <jbeulich@suse.com>
759
760 * i386-opc.tbl: Drop IgnoreSize from AVX512BW insns where
761 meaningless.
762 * i386-tbl.h: Re-generate.
763
9caa306f
JB		 7642018-09-13 Jan Beulich <jbeulich@suse.com>
765
766 * i386-opc.tbl: Drop IgnoreSize from AVX512VL insns where
767 meaningless.
768 * i386-tbl.h: Re-generate.
769
fb6ce599
JB		 7702018-09-13 Jan Beulich <jbeulich@suse.com>
771
772 * i386-opc.tbl: Drop IgnoreSize from AVX512ER insns where
773 meaningless.
774 * i386-tbl.h: Re-generate.
775
6a8da886
JB		 7762018-09-13 Jan Beulich <jbeulich@suse.com>
777
778 * i386-opc.tbl: Drop IgnoreSize from AVX512F insns where
779 meaningless.
780 * i386-tbl.h: Re-generate.
781
c7f27919
JB		 7822018-09-13 Jan Beulich <jbeulich@suse.com>
783
784 * i386-opc.tbl: Drop IgnoreSize from SHA insns.
785 * i386-tbl.h: Re-generate.
786
0f407ee9
JB		 7872018-09-13 Jan Beulich <jbeulich@suse.com>
788
789 * i386-opc.tbl: Drop IgnoreSize from XOP and SSE4a insns.
790 * i386-tbl.h: Re-generate.
791
2fbbbee5
JB		 7922018-09-13 Jan Beulich <jbeulich@suse.com>
793
794 * i386-opc.tbl: Drop IgnoreSize from AVX2 insns where
795 meaningless.
796 * i386-tbl.h: Re-generate.
797
2b02b9a2
JB		 7982018-09-13 Jan Beulich <jbeulich@suse.com>
799
800 * i386-opc.tbl: Drop IgnoreSize from AVX insns where
801 meaningless.
802 * i386-tbl.h: Re-generate.
803
963c68aa
JB		 8042018-09-13 Jan Beulich <jbeulich@suse.com>
805
806 * i386-opc.tbl: Drop IgnoreSize from GNFI insns.
807 * i386-tbl.h: Re-generate.
808
64e025c3
JB		 8092018-09-13 Jan Beulich <jbeulich@suse.com>
810
811 * i386-opc.tbl: Drop IgnoreSize from PCLMUL/VPCLMUL insns.
812 * i386-tbl.h: Re-generate.
813
47603f88
JB		 8142018-09-13 Jan Beulich <jbeulich@suse.com>
815
816 * i386-opc.tbl: Drop IgnoreSize from AES/VAES insns.
817 * i386-tbl.h: Re-generate.
818
0001cfd0
JB		 8192018-09-13 Jan Beulich <jbeulich@suse.com>
820
821 * i386-opc.tbl: Drop IgnoreSize from SSE4.2 insns where
822 meaningless.
823 * i386-tbl.h: Re-generate.
824
be4b452e
JB		 8252018-09-13 Jan Beulich <jbeulich@suse.com>
826
827 * i386-opc.tbl: Drop IgnoreSize from SSE4.1 insns where
828 meaningless.
829 * i386-tbl.h: Re-generate.
830
d09a1394
JB		 8312018-09-13 Jan Beulich <jbeulich@suse.com>
832
833 * i386-opc.tbl: Drop IgnoreSize from SSSE3 insns where
834 meaningless.
835 * i386-tbl.h: Re-generate.
836
07599e13
JB		 8372018-09-13 Jan Beulich <jbeulich@suse.com>
838
839 * i386-opc.tbl: Drop IgnoreSize from SSE3 insns where meaningless.
840 * i386-tbl.h: Re-generate.
841
1ee3e487
JB		 8422018-09-13 Jan Beulich <jbeulich@suse.com>
843
844 * i386-opc.tbl: Drop IgnoreSize from SSE2 insns where meaningless.
845 * i386-tbl.h: Re-generate.
846
a5f580e5
JB		 8472018-09-13 Jan Beulich <jbeulich@suse.com>
848
849 * i386-opc.tbl: Drop IgnoreSize from SSE insns where meaningless.
850 * i386-tbl.h: Re-generate.
851
49d5d12d
JB		 8522018-09-13 Jan Beulich <jbeulich@suse.com>
853
854 * i386-opc.tbl (crc32, incsspq, rdsspq): Drop Rex64.
855 (vpbroadcastw, rdpid): Drop NoRex64.
856 * i386-tbl.h: Re-generate.
857
f5eb1d70
JB		 8582018-09-13 Jan Beulich <jbeulich@suse.com>
859
860 * i386-opc.tbl (vmovsd, vmovss): Fold register form load and
861 store templates, adding D.
862 * i386-tbl.h: Re-generate.
863
dbbc8b7e
JB		 8642018-09-13 Jan Beulich <jbeulich@suse.com>
865
866 * i386-opc.tbl (bndmov, kmovb, kmovd, kmovq, kmovw, movapd,
867 movaps, movd, movdqa, movdqu, movhpd, movhps, movlpd, movlps,
868 movq, movsd, movss, movupd, movups, vmovapd, vmovaps, vmovd,
869 vmovdqa, vmovdqa32, vmovdqa64, vmovdqu, vmovdqu16, vmovdqu32,
870 vmovdqu64, vmovdqu8, vmovq, vmovsd, vmovss, vmovupd, vmovups):
871 Fold load and store templates where possible, adding D. Drop
872 IgnoreSize where it was pointlessly present. Drop redundant
873 *word.
874 * i386-tbl.h: Re-generate.
875
d276ec69
JB		 8762018-09-13 Jan Beulich <jbeulich@suse.com>
877
878 * i386-dis.c (Mv_bnd, v_bndmk_mode): New.
879 (mod_table): Use Mv_bnd for bndldx, bndstx, and bndmk.
880 (intel_operand_size): Handle v_bndmk_mode.
881 (OP_E_memory): Likewise. Produce (bad) when also riprel.
882
9da4dfd6
JD		 8832018-09-08 John Darrington <john@darrington.wattle.id.au>
884
885 * disassemble.c (ARCH_s12z): Define if ARCH_all.
886
be192bc2
JW		 8872018-08-31 Kito Cheng <kito@andestech.com>
888
889 * riscv-opc.c (riscv_opcodes): Fix incorrect subset info for
890 compressed floating point instructions.
891
43135d3b
JW		 8922018-08-30 Kito Cheng <kito@andestech.com>
893
894 * riscv-dis.c (riscv_disassemble_insn): Check XLEN by
895 riscv_opcode.xlen_requirement.
896 * riscv-opc.c (riscv_opcodes): Update for struct change.
897
df28970f
MA		 8982018-08-29 Martin Aberg <maberg@gaisler.com>
899
900 * sparc-opc.c (sparc_opcodes): Add Leon specific partial write
901 psr (PWRPSR) instruction.
902
9108bc33
CX		 9032018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
904
905 * mips-dis.c (mips_arch_choices): Add gs264e descriptors.
906
bd782c07
CX		 9072018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
908
909 * mips-dis.c (mips_arch_choices): Add gs464e descriptors.
910
ac8cb70f
CX		 9112018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
912
913 * mips-dis.c (mips_arch_choices): Add gs464 descriptors, Keep
914 loongson3a as an alias of gs464 for compatibility.
915 * mips-opc.c (mips_opcodes): Change Comments.
916
a693765e
CX		 9172018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
918
919 * mips-dis.c (parse_mips_ase_option): Handle -M loongson-ext
920 option.
921 (print_mips_disassembler_options): Document -M loongson-ext.
922 * mips-opc.c (LEXT2): New macro.
923 (mips_opcodes): Add cto, ctz, dcto, dctz instructions.
924
bdc6c06e
CX		 9252018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
926
927 * mips-dis.c (mips_arch_choices): Add EXT to loongson3a
928 descriptors.
929 (parse_mips_ase_option): Handle -M loongson-ext option.
930 (print_mips_disassembler_options): Document -M loongson-ext.
931 * mips-opc.c (IL3A): Delete.
932 * mips-opc.c (LEXT): New macro.
933 (mips_opcodes): Replace IL2F|IL3A marking with LEXT for EXT
934 instructions.
935
716c08de
CX		 9362018-08-29 Chenghua Xu <paul.hua.gm@gmail.com>
937
938 * mips-dis.c (mips_arch_choices): Add CAM to loongson3a
939 descriptors.
940 (parse_mips_ase_option): Handle -M loongson-cam option.
941 (print_mips_disassembler_options): Document -M loongson-cam.
942 * mips-opc.c (LCAM): New macro.
943 (mips_opcodes): Replace IL2F|IL3A marking with LCAM for CAM
944 instructions.
945
9cf7e568
AM		 9462018-08-21 Alan Modra <amodra@gmail.com>
947
948 * ppc-dis.c (operand_value_powerpc): Init "invalid".
949 (skip_optional_operands): Count optional operands, and update
950 ppc_optional_operand_value call.
951 * ppc-opc.c (extract_dxdn): Remove ATTRIBUTE_UNUSED from used arg.
952 (extract_vlensi): Likewise.
953 (extract_fxm): Return default value for missing optional operand.
954 (extract_ls, extract_raq, extract_tbr): Likewise.
955 (insert_sxl, extract_sxl): New functions.
956 (insert_esync, extract_esync): Remove Power9 handling and simplify.
957 (powerpc_operands <FXM4, TBR>): Delete PPC_OPERAND_OPTIONAL_VALUE
958 flag and extra entry.
959 (powerpc_operands <SXL>): Likewise, and use insert_sxl and
960 extract_sxl.
961
d203b41a 9622018-08-20 Alan Modra <amodra@gmail.com>
f4107842 963
d203b41a 964 * sh-opc.h (MASK): Simplify.
f4107842 965
08a8fe2f 9662018-08-18 John Darrington <john@darrington.wattle.id.au>
7ba3ba91 967
d203b41a
AM		 968 * s12z-dis.c (bm_decode): Deal with cases where the mode is
969 BM_RESERVED0 or BM_RESERVED1
08a8fe2f 970 (bm_rel_decode, bm_n_bytes): Ditto.
d203b41a 971
08a8fe2f 9722018-08-18 John Darrington <john@darrington.wattle.id.au>
d203b41a
AM		 973
974 * s12z.h: Delete.
7ba3ba91 975
1bc60e56
L		 9762018-08-14 H.J. Lu <hongjiu.lu@intel.com>
977
978 * i386-dis.c (OP_E_memory): In 64-bit mode, display eiz for
979 address with the addr32 prefix and without base nor index
980 registers.
981
d871f3f4
L		 9822018-08-11 H.J. Lu <hongjiu.lu@intel.com>
983
984 * i386-gen.c (cpu_flag_init): Add CpuCMOV and CpuFXSR to
985 CPU_I686_FLAGS. Add CPU_CMOV_FLAGS, CPU_FXSR_FLAGS,
986 CPU_ANY_CMOV_FLAGS and CPU_ANY_FXSR_FLAGS.
987 (cpu_flags): Add CpuCMOV and CpuFXSR.
988 * i386-opc.tbl: Replace Cpu686 with CpuFXSR on fxsave, fxsave64,
989 fxrstor and fxrstor64. Replace Cpu686 with CpuCMOV on cmovCC.
990 * i386-init.h: Regenerated.
991 * i386-tbl.h: Likewise.
992
b6523c37 9932018-08-06 Claudiu Zissulescu <claziss@synopsys.com>
994
995 * arc-regs.h: Update auxiliary registers.
996
e968fc9b
JB		 9972018-08-06 Jan Beulich <jbeulich@suse.com>
998
999 * i386-opc.h (RegRip, RegEip, RegEiz, RegRiz): Drop defines.
1000 (RegIP, RegIZ): Define.
1001 * i386-reg.tbl: Adjust comments.
1002 (rip): Use Qword instead of BaseIndex. Use RegIP.
1003 (eip): Use Dword instead of BaseIndex. Use RegIP.
1004 (riz): Add Qword. Use RegIZ.
1005 (eiz): Add Dword. Use RegIZ.
1006 * i386-tbl.h: Re-generate.
1007
dbf8be89
JB		 10082018-08-03 Jan Beulich <jbeulich@suse.com>
1009
1010 * i386-opc.tbl (pmovsxbw, pmovsxdq, pmovsxwd, pmovzxbw,
1011 pmovzxdq, pmovzxwd, vpmovsxbw, vpmovsxdq, vpmovsxwd, vpmovzxbw,
1012 vpmovzxdq, vpmovzxwd): Remove NoRex64.
1013 * i386-tbl.h: Re-generate.
1014
c48dadc9
JB		 10152018-08-03 Jan Beulich <jbeulich@suse.com>
1016
1017 * i386-gen.c (operand_types): Remove Mem field.
1018 * i386-opc.h (union i386_operand_type): Remove mem field.
1019 * i386-init.h, i386-tbl.h: Re-generate.
1020
cb86a42a
AM		 10212018-08-01 Alan Modra <amodra@gmail.com>
1022
1023 * po/POTFILES.in: Regenerate.
1024
07cc0450
NC		 10252018-07-31 Nick Clifton <nickc@redhat.com>
1026
1027 * po/sv.po: Updated Swedish translation.
1028
1424ad86
JB		 10292018-07-31 Jan Beulich <jbeulich@suse.com>
1030
1031 * i386-opc.tbl (kandnd, kandnq, kxord, kxorq): Add Optimize.
1032 * i386-init.h, i386-tbl.h: Re-generate.
1033
ae2387fe
JB		 10342018-07-31 Jan Beulich <jbeulich@suse.com>
1035
1036 * i386-opc.h (ZEROING_MASKING) Rename to ...
1037 (DYNAMIC_MASKING): ... this. Adjust comment.
1038 * i386-opc.tbl (MaskingMorZ): Define.
1039 (vcompresspd, vcompressps, vcvtps2ph, vextractf32x4,
1040 vextractf32x8, vextractf64x2, vextractf64x4, vextracti32x4,
1041 vextracti32x8, vextracti64x2, vextracti64x4, vmovapd, vmovaps,
1042 vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16, vmovdqu32, vmovdqu64,
1043 vmovupd, vmovups, vpcompressb, vpcompressw, vpcompressd,
1044 vpcompressq, vpmovdb, vpmovdw, vpmovqb, vpmovqd, vpmovqw,
1045 vpmovsdb, vpmovsdw, vpmovsqb, vpmovsqd, vpmovsqw, vpmovswb,
1046 vpmovusdb, vpmovusdw, vpmovusqb, vpmovusqd, vpmovusqw,
1047 vpmovuswb, vpmovwb): Fold AVX512 register and memory forms.
1048
6ff00b5e
JB		 10492018-07-31 Jan Beulich <jbeulich@suse.com>
1050
1051 * i386-opc.tbl: Use element rather than vector size for AVX512*
1052 scatter/gather insns.
1053 * i386-tbl.h: Re-generate.
1054
e951d5ca
JB		 10552018-07-31 Jan Beulich <jbeulich@suse.com>
1056
1057 * i386-gen.c (cpu_flag_init): Drop CpuVREX uses.
1058 (cpu_flags): Drop CpuVREX.
1059 * i386-opc.h (CpuVREX): Delete.
1060 (union i386_cpu_flags): Remove cpuvrex.
1061 * i386-init.h, i386-tbl.h: Re-generate.
1062
eb41b248
JW		 10632018-07-30 Jim Wilson <jimw@sifive.com>
1064
1065 * riscv-dis.c (riscv_disassemble_insn): Set insn_type and data_size
1066 fields.
1067 * riscv-opc.c (riscv_opcodes): Use new INSN_* flags to annotate insns.
1068
b8891f8d
AJ		 10692018-07-30 Andrew Jenner <andrew@codesourcery.com>
1070
1071 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add csky-dis.c.
1072 * Makefile.in: Regenerated.
1073 * configure.ac: Add C-SKY.
1074 * configure: Regenerated.
1075 * csky-dis.c: New file.
1076 * csky-opc.h: New file.
1077 * disassemble.c (ARCH_csky): Define.
1078 (disassembler, disassemble_init_for_target): Add case for ARCH_csky.
1079 * disassemble.h (print_insn_csky, csky_get_disassembler): Declare.
1080
16065af1
AM		 10812018-07-27 Alan Modra <amodra@gmail.com>
1082
1083 * ppc-opc.c (insert_sprbat): Correct function parameter and
1084 return type.
1085 (extract_sprbat): Likewise, variable too.
1086
fa758a70
AC		 10872018-07-26 Alex Chadwick <Alex.Chadwick@cl.cam.ac.uk>
1088 Alan Modra <amodra@gmail.com>
1089
1090 * ppc-dis.c (ppc_opts): Add -mgekko and -mbroadway.
1091 (powerpc_init_dialect): Handle bfd_mach_ppc_750.
1092 * ppc-opc.c (insert_sprbat, extract_sprbat): New functions to
1093 support disjointed BAT.
1094 (powerpc_operands): Allow extra bit in SPRBAT_MASK. Add SPRGQR.
1095 (XSPRGQR_MASK, GEKKO, BROADWAY): Define.
1096 (powerpc_opcodes): Add 750cl extended mnemonics for spr access.
1097
4a1b91ea
L		 10982018-07-25 H.J. Lu <hongjiu.lu@intel.com>
1099 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1100
1101 * i386-gen.c (adjust_broadcast_modifier): New function.
1102 (process_i386_opcode_modifier): Add an argument for operands.
1103 Adjust the Broadcast value based on operands.
1104 (output_i386_opcode): Pass operand_types to
1105 process_i386_opcode_modifier.
1106 (process_i386_opcodes): Pass NULL as operands to
1107 process_i386_opcode_modifier.
1108 * i386-opc.h (BYTE_BROADCAST): New.
1109 (WORD_BROADCAST): Likewise.
1110 (DWORD_BROADCAST): Likewise.
1111 (QWORD_BROADCAST): Likewise.
1112 (i386_opcode_modifier): Expand broadcast to 3 bits.
1113 * i386-tbl.h: Regenerated.
1114
67ce483b
AM		 11152018-07-24 Alan Modra <amodra@gmail.com>
1116
1117 PR 23430
1118 * or1k-desc.h: Regenerate.
1119
4174bfff
JB		 11202018-07-24 Jan Beulich <jbeulich@suse.com>
1121
1122 * i386-dis-evex.h (evex_table): Add %LQ to vcvtsi2ss, vcvtsi2sd,
1123 vcvtusi2ss, and vcvtusi2sd.
1124 * i386-opc.tbl (vcvtsi2sd, vcvtusi2sd, vcvtsi2ss, vcvtusi2ss):
1125 Convert AVX512F variants to distinct CpuNo64 and Cpu64 forms.
1126 * i386-tbl.h: Re-generate.
1127
04e65276
CZ		 11282018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1129
1130 * arc-opc.c (extract_w6): Fix extending the sign.
1131
47e6f81c
CZ		 11322018-07-23 Claudiu Zissulescu <claziss@synopsys.com>
1133
1134 * arc-tbl.h (vewt): Allow it for ARC EM family.
1135
bb71536f
AM		 11362018-07-23 Alan Modra <amodra@gmail.com>
1137
1138 PR 23419
1139 * ppc-opc.c (powerpc_opcodes): Add mtupmc/mfupmc/mfpmc extended
1140 opcode variants for mtspr/mfspr encodings.
1141
8095d2f7
CX		 11422018-07-20 Chenghua Xu <paul.hua.gm@gmail.com>
1143 Maciej W. Rozycki <macro@mips.com>
1144
1145 * mips-dis.c (mips_arch_choices): Add MMI to loongson2f and
1146 loongson3a descriptors.
1147 (parse_mips_ase_option): Handle -M loongson-mmi option.
1148 (print_mips_disassembler_options): Document -M loongson-mmi.
1149 * mips-opc.c (LMMI): New macro.
1150 (mips_opcodes): Replace IL2F|IL3A marking with LMMI for MMI
1151 instructions.
1152
5f32791e
JB		 11532018-07-19 Jan Beulich <jbeulich@suse.com>
1154
1155 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1156 vcvtqq2ps, vcvtuqq2ps): Fold 128- and 256-bit templates. Drop
1157 IgnoreSize and [XYZ]MMword where applicable.
1158 * i386-tbl.h: Re-generate.
1159
625cbd7a
JB		 11602018-07-19 Jan Beulich <jbeulich@suse.com>
1161
1162 * i386-opc.tbl (vfpclasspd, vfpclassps): Fold.
1163 (vfpclasspdz, vfpclasspsz): Drop IgnoreSize and ZmmWord.
1164 (vfpclasspdx, vfpclasspsx): Drop IgnoreSize and XmmWord.
1165 (vfpclasspdy, vfpclasspsy): Drop IgnoreSize and YmmWord.
1166 * i386-tbl.h: Re-generate.
1167
86b15c32
JB		 11682018-07-19 Jan Beulich <jbeulich@suse.com>
1169
1170 * i386-opc.tbl: Fold AVX512IFMA, AVX512VBMI, AVX512_VPOPCNTDQ,
1171 AVX512_VBMI2, AVX512_VNNI, AVX512_BITALG, GFNI, VAES, and
1172 VPCLMULQDQ templates into their respective AVX512VL counterparts
1173 where possible, using Disp8ShiftVL and CheckRegSize instead of
1174 Evex= plus Disp8MemShift= (plus often IgnoreSize) as appropriate.
1175 * i386-tbl.h: Re-generate.
1176
cf769ed5
JB		 11772018-07-19 Jan Beulich <jbeulich@suse.com>
1178
1179 * i386-opc.tbl: Fold AVX512DQ templates into their respective
1180 AVX512VL counterparts where possible, using Disp8ShiftVL and
1181 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1182 IgnoreSize) as appropriate.
1183 * i386-tbl.h: Re-generate.
1184
8282b7ad
JB		 11852018-07-19 Jan Beulich <jbeulich@suse.com>
1186
1187 * i386-opc.tbl: Fold AVX512BW templates into their respective
1188 AVX512VL counterparts where possible, using Disp8ShiftVL and
1189 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1190 IgnoreSize) as appropriate.
1191 * i386-tbl.h: Re-generate.
1192
755908cc
JB		 11932018-07-19 Jan Beulich <jbeulich@suse.com>
1194
1195 * i386-opc.tbl: Fold AVX512CD templates into their respective
1196 AVX512VL counterparts where possible, using Disp8ShiftVL and
1197 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1198 IgnoreSize) as appropriate.
1199 * i386-tbl.h: Re-generate.
1200
7091c612
JB		 12012018-07-19 Jan Beulich <jbeulich@suse.com>
1202
1203 * i386-opc.h (DISP8_SHIFT_VL): New.
1204 * i386-opc.tbl (Disp8ShiftVL): Define.
1205 (various): Fold AVX512VL templates into their respective
1206 AVX512F counterparts where possible, using Disp8ShiftVL and
1207 CheckRegSize instead of Evex= plus Disp8MemShift= (plus often
1208 IgnoreSize) as appropriate.
1209 * i386-tbl.h: Re-generate.
1210
c30be56e
JB		 12112018-07-19 Jan Beulich <jbeulich@suse.com>
1212
1213 * Makefile.am: Change dependencies and rule for
1214 $(srcdir)/i386-init.h.
1215 * Makefile.in: Re-generate.
1216 * i386-gen.c (process_i386_opcodes): New local variable
1217 "marker". Drop opening of input file. Recognize marker and line
1218 number directives.
1219 * i386-opc.tbl (OPCODE_I386_H): Define.
1220 (i386-opc.h): Include it.
1221 (None): Undefine.
1222
11a322db
L		 12232018-07-18 H.J. Lu <hongjiu.lu@intel.com>
1224
1225 PR gas/23418
1226 * i386-opc.h (Byte): Update comments.
1227 (Word): Likewise.
1228 (Dword): Likewise.
1229 (Fword): Likewise.
1230 (Qword): Likewise.
1231 (Tbyte): Likewise.
1232 (Xmmword): Likewise.
1233 (Ymmword): Likewise.
1234 (Zmmword): Likewise.
1235 * i386-opc.tbl: Split vcvtps2qq, vcvtps2uqq, vcvttps2qq and
1236 vcvttps2uqq.
1237 * i386-tbl.h: Regenerated.
1238
cde3679e
NC		 12392018-07-12 Sudakshina Das <sudi.das@arm.com>
1240
1241 * aarch64-tbl.h (aarch64_opcode_table): Add entry for
1242 ssbb and pssbb and update dsb flags to F_HAS_ALIAS.
1243 * aarch64-asm-2.c: Regenerate.
1244 * aarch64-dis-2.c: Regenerate.
1245 * aarch64-opc-2.c: Regenerate.
1246
45a28947
TC		 12472018-07-12 Tamar Christina <tamar.christina@arm.com>
1248
1249 PR binutils/23192
1250 * aarch64-tbl.h (sqdmlal, sqdmlal2, smlsl, smlsl2, sqdmlsl, sqdmlsl2,
1251 mul, smull, smull2, sqdmull, sqdmull2, sqdmulh, sqrdmulh, mla, umlal,
1252 umlal2, mls, umlsl, umlsl2, umull, umull2, sqdmlal, sqdmlsl, sqdmull,
1253 sqdmulh, sqrdmulh): Use Em16.
1254
c597cc3d
SD		 12552018-07-11 Sudakshina Das <sudi.das@arm.com>
1256
1257 * arm-dis.c (arm_opcodes): Add ssbb and pssbb and move
1258 csdb together with them.
1259 (thumb32_opcodes): Likewise.
1260
a79eaed6
JB		 12612018-07-11 Jan Beulich <jbeulich@suse.com>
1262
1263 * i386-opc.tbl (monitor, monitorx): Add 64-bit template
1264 requiring 32-bit registers as operands 2 and 3. Improve
1265 comments.
1266 (mwait, mwaitx): Fold templates. Improve comments.
1267 OPERAND_TYPE_INOUTPORTREG.
1268 * i386-tbl.h: Re-generate.
1269
2fb5be8d
JB		 12702018-07-11 Jan Beulich <jbeulich@suse.com>
1271
1272 * i386-gen.c (operand_type_init): Remove
1273 OPERAND_TYPE_REG16_INOUTPORTREG entry and one instance of
1274 OPERAND_TYPE_INOUTPORTREG.
1275 * i386-init.h: Re-generate.
1276
7f5cad30
JB		 12772018-07-11 Jan Beulich <jbeulich@suse.com>
1278
1279 * i386-opc.tbl (wrssd, wrussd): Add Dword.
1280 (wrssq, wrussq): Add Qword.
1281 * i386-tbl.h: Re-generate.
1282
f0a85b07
JB		 12832018-07-11 Jan Beulich <jbeulich@suse.com>
1284
1285 * i386-opc.h: Rename OTMax to OTNum.
1286 (OTNumOfUints): Adjust calculation.
1287 (OTUnused): Directly alias to OTNum.
1288
9dcb0ba4
MR		 12892018-07-09 Maciej W. Rozycki <macro@mips.com>
1290
1291 * s12z-dis.c (lea_reg_xys_opr): Rename `reg' local variable to
1292 `reg_xys'.
1293 (lea_reg_xys): Likewise.
1294 (print_insn_loop_primitive): Rename `reg' local variable to
1295 `reg_dxy'.
1296
f311ba7e
TC		 12972018-07-06 Tamar Christina <tamar.christina@arm.com>
1298
1299 PR binutils/23242
1300 * aarch64-tbl.h (ldarh): Fix disassembly mask.
1301
cba05feb
TC		 13022018-07-06 Tamar Christina <tamar.christina@arm.com>
1303
1304 PR binutils/23369
1305 * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
1306 vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
1307
471b9d15
MR		 13082018-07-02 Maciej W. Rozycki <macro@mips.com>
1309
1310 PR tdep/8282
1311 * mips-dis.c (mips_option_arg_t): New enumeration.
1312 (mips_options): New variable.
1313 (disassembler_options_mips): New function.
1314 (print_mips_disassembler_options): Reimplement in terms of
1315 `disassembler_options_mips'.
1316 * arm-dis.c (disassembler_options_arm): Adapt to using the
1317 `disasm_options_and_args_t' structure.
1318 * ppc-dis.c (disassembler_options_powerpc): Likewise.
1319 * s390-dis.c (disassembler_options_s390): Likewise.
1320
c0c468d5
TP		 13212018-07-02 Thomas Preud'homme <thomas.preudhomme@arm.com>
1322
1323 * testsuite/ld-arm/tls-descrelax-be8.d: Add architecture version in
1324 expected result.
1325 * testsuite/ld-arm/tls-descrelax-v7.d: Likewise.
1326 * testsuite/ld-arm/tls-longplt-lib.d: Likewise.
1327 * testsuite/ld-arm/tls-longplt.d: Likewise.
1328
369c9167
TC		 13292018-06-29 Tamar Christina <tamar.christina@arm.com>
1330
1331 PR binutils/23192
1332 * aarch64-asm-2.c: Regenerate.
1333 * aarch64-dis-2.c: Likewise.
1334 * aarch64-opc-2.c: Likewise.
1335 * aarch64-dis.c (aarch64_ext_reglane): Add AARCH64_OPND_Em16 constraint.
1336 * aarch64-opc.c (operand_general_constraint_met_p,
1337 aarch64_print_operand): Likewise.
1338 * aarch64-tbl.h (aarch64_opcode_table): Change Em to Em16 for smlal,
1339 smlal2, fmla, fmls, fmul, fmulx, sqrdmlah, sqrdlsh, fmlal, fmlsl,
1340 fmlal2, fmlsl2.
1341 (AARCH64_OPERANDS): Add Em2.
1342
30aa1306
NC		 13432018-06-26 Nick Clifton <nickc@redhat.com>
1344
1345 * po/uk.po: Updated Ukranian translation.
1346 * po/de.po: Updated German translation.
1347 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1348
eca4b721
NC		 13492018-06-26 Nick Clifton <nickc@redhat.com>
1350
1351 * nfp-dis.c: Fix spelling mistake.
1352
71300e2c
NC		 13532018-06-24 Nick Clifton <nickc@redhat.com>
1354
1355 * configure: Regenerate.
1356 * po/opcodes.pot: Regenerate.
1357
719d8288
NC		 13582018-06-24 Nick Clifton <nickc@redhat.com>
1359
1360 2.31 branch created.
1361
514cd3a0
TC		 13622018-06-19 Tamar Christina <tamar.christina@arm.com>
1363
1364 * aarch64-tbl.h (aarch64_opcode_table): Fix alias flag for negs
1365 * aarch64-asm-2.c: Regenerate.
1366 * aarch64-dis-2.c: Likewise.
1367
385e4d0f
MR		 13682018-06-21 Maciej W. Rozycki <macro@mips.com>
1369
1370 * mips-dis.c (print_mips_disassembler_options): Fix a typo in
1371 `-M ginv' option description.
1372
160d1b3d
SH		 13732018-06-20 Sebastian Huber <sebastian.huber@embedded-brains.de>
1374
1375 PR gas/23305
1376 * riscv-opc.c (riscv_opcodes): Use new format specifier 'B' for
1377 la and lla.
1378
d0ac1c44
SM		 13792018-06-19 Simon Marchi <simon.marchi@ericsson.com>
1380
1381 * Makefile.am (AUTOMAKE_OPTIONS): Remove 1.11.
1382 * configure.ac: Remove AC_PREREQ.
1383 * Makefile.in: Re-generate.
1384 * aclocal.m4: Re-generate.
1385 * configure: Re-generate.
1386
6f20c942
FS		 13872018-06-14 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1388
1389 * mips-dis.c (mips_arch_choices): Add GINV to mips32r6 and
1390 mips64r6 descriptors.
1391 (parse_mips_ase_option): Handle -Mginv option.
1392 (print_mips_disassembler_options): Document -Mginv.
1393 * mips-opc.c (decode_mips_operand) <+\>: New operand format.
1394 (GINV): New macro.
1395 (mips_opcodes): Define ginvi and ginvt.
1396
730c3174
SE		 13972018-06-13 Scott Egerton <scott.egerton@imgtec.com>
1398 Faraz Shahbazker <Faraz.Shahbazker@mips.com>
1399
1400 * mips-dis.c (mips_arch_choices): Add CRC and CRC64 ASEs.
1401 * mips-opc.c (CRC, CRC64): New macros.
1402 (mips_builtin_opcodes): Define crc32b, crc32h, crc32w,
1403 crc32cb, crc32ch and crc32cw for CRC. Define crc32d and
1404 crc32cd for CRC64.
1405
cb366992
EB		 14062018-06-08 Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
1407
1408 PR 20319
1409 * aarch64-tbl.h: Introduce QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1410 (aarch64_opcode_table) : Use QL_INT2FP_FMOV and QL_FP2INT_FMOV.
1411
ce72cd46
AM		 14122018-06-06 Alan Modra <amodra@gmail.com>
1413
1414 * xtensa-dis.c (print_insn_xtensa): Init fmt and valid_insn after
1415 setjmp. Move init for some other vars later too.
1416
4b8e28c7
MF		 14172018-06-04 Max Filippov <jcmvbkbc@gmail.com>
1418
1419 * xtensa-dis.c (bfd.h, elf/xtensa.h): New includes.
1420 (dis_private): Add new fields for property section tracking.
1421 (xtensa_coalesce_insn_tables, xtensa_find_table_entry)
1422 (xtensa_instruction_fits): New functions.
1423 (fetch_data): Bump minimal fetch size to 4.
1424 (print_insn_xtensa): Make struct dis_private static.
1425 Load and prepare property table on section change.
1426 Don't disassemble literals. Don't disassemble instructions that
1427 cross property table boundaries.
1428
55e99962
L		 14292018-06-01 H.J. Lu <hongjiu.lu@intel.com>
1430
1431 * configure: Regenerated.
1432
733bd0ab
JB		 14332018-06-01 Jan Beulich <jbeulich@suse.com>
1434
1435 * i386-opc.tbl (mov, movq): Fold to/from SReg* forms.
1436 * i386-tbl.h: Re-generate.
1437
dfd27d41
JB		 14382018-06-01 Jan Beulich <jbeulich@suse.com>
1439
1440 * i386-opc.tbl (sldt, str): Add NoRex64.
1441 * i386-tbl.h: Re-generate.
1442
64795710
JB		 14432018-06-01 Jan Beulich <jbeulich@suse.com>
1444
1445 * i386-opc.tbl (invpcid): Add Oword.
1446 * i386-tbl.h: Re-generate.
1447
030157d8
AM		 14482018-06-01 Alan Modra <amodra@gmail.com>
1449
1450 * sysdep.h (_bfd_error_handler): Don't declare.
1451 * msp430-decode.opc: Include bfd.h. Don't include ansidecl.h here.
1452 * rl78-decode.opc: Likewise.
1453 * msp430-decode.c: Regenerate.
1454 * rl78-decode.c: Regenerate.
1455
a9660a6f
AP		 14562018-05-30 Amit Pawar <Amit.Pawar@amd.com>
1457
1458 * i386-gen.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.
1459 * i386-init.h : Regenerated.
1460
277eb7f6
AM		 14612018-05-25 Alan Modra <amodra@gmail.com>
1462
1463 * Makefile.in: Regenerate.
1464 * po/POTFILES.in: Regenerate.
1465
98553ad3
PB		 14662018-05-21 Peter Bergner <bergner@vnet.ibm.com.com>
1467
1468 * ppc-opc.c (insert_bat, extract_bat, insert_bba, extract_bba,
1469 insert_rbs, extract_rbs, insert_xb6s, extract_xb6s): Delete functions.
1470 (insert_bab, extract_bab, insert_btab, extract_btab,
1471 insert_rsb, extract_rsb, insert_xab6, extract_xab6): New functions.
1472 (BAT, BBA VBA RBS XB6S): Delete macros.
1473 (BTAB, BAB, VAB, RAB, RSB, XAB6): New macros.
1474 (BB, BD, RBX, XC6): Update for new macros.
1475 (powerpc_opcodes) <evmr, evnot, vmr, vnot, crnot, crclr, crset,
1476 crmove, not, not., mr, mr., xxspltd, xxswapd, xvmovsp, xvmovdp,
1477 e_crnot, e_crclr, e_crset, e_crmove>: Likewise.
1478 * ppc-dis.c (print_insn_powerpc): Delete handling of fake operands.
1479
7b4ae824
JD		 14802018-05-18 John Darrington <john@darrington.wattle.id.au>
1481
1482 * Makefile.am: Add support for s12z architecture.
1483 * configure.ac: Likewise.
1484 * disassemble.c: Likewise.
1485 * disassemble.h: Likewise.
1486 * Makefile.in: Regenerate.
1487 * configure: Regenerate.
1488 * s12z-dis.c: New file.
1489 * s12z.h: New file.
1490
29e0f0a1
AM		 14912018-05-18 Alan Modra <amodra@gmail.com>
1492
1493 * nfp-dis.c: Don't #include libbfd.h.
1494 (init_nfp3200_priv): Use bfd_get_section_contents.
1495 (nit_nfp6000_mecsr_sec): Likewise.
1496
809276d2
NC		 14972018-05-17 Nick Clifton <nickc@redhat.com>
1498
1499 * po/zh_CN.po: Updated simplified Chinese translation.
1500
ff329288
TC		 15012018-05-16 Tamar Christina <tamar.christina@arm.com>
1502
1503 PR binutils/23109
1504 * aarch64-tbl.h (aarch64_opcode_table): Correct sdot and udot.
1505 * aarch64-dis-2.c: Regenerate.
1506
f9830ec1
TC		 15072018-05-15 Tamar Christina <tamar.christina@arm.com>
1508
1509 PR binutils/21446
1510 * aarch64-asm.c (opintl.h): Include.
1511 (aarch64_ins_sysreg): Enforce read/write constraints.
1512 * aarch64-dis.c (aarch64_ext_sysreg): Likewise.
1513 * aarch64-opc.h (F_DEPRECATED, F_ARCHEXT, F_HASXT): Moved here.
1514 (F_REG_READ, F_REG_WRITE): New.
1515 * aarch64-opc.c (aarch64_print_operand): Generate notes for
1516 AARCH64_OPND_SYSREG.
1517 (F_DEPRECATED, F_ARCHEXT, F_HASXT): Move to aarch64-opc.h.
1518 (aarch64_sys_regs): Add constraints to currentel, midr_el1, ctr_el0,
1519 mpidr_el1, revidr_el1, aidr_el1, dczid_el0, id_dfr0_el1, id_pfr0_el1,
1520 id_pfr1_el1, id_afr0_el1, id_mmfr0_el1, id_mmfr1_el1, id_mmfr2_el1,
1521 id_mmfr3_el1, id_mmfr4_el1, id_isar0_el1, id_isar1_el1, id_isar2_el1,
1522 id_isar3_el1, id_isar4_el1, id_isar5_el1, mvfr0_el1, mvfr1_el1,
1523 mvfr2_el1, ccsidr_el1, id_aa64pfr0_el1, id_aa64pfr1_el1,
1524 id_aa64dfr0_el1, id_aa64dfr1_el1, id_aa64isar0_el1, id_aa64isar1_el1,
1525 id_aa64mmfr0_el1, id_aa64mmfr1_el1, id_aa64mmfr2_el1, id_aa64afr0_el1,
1526 id_aa64afr0_el1, id_aa64afr1_el1, id_aa64zfr0_el1, clidr_el1,
1527 csselr_el1, vsesr_el2, erridr_el1, erxfr_el1, rvbar_el1, rvbar_el2,
1528 rvbar_el3, isr_el1, tpidrro_el0, cntfrq_el0, cntpct_el0, cntvct_el0,
1529 mdccsr_el0, dbgdtrrx_el0, dbgdtrtx_el0, osdtrrx_el1, osdtrtx_el1,
1530 mdrar_el1, oslar_el1, oslsr_el1, dbgauthstatus_el1, pmbidr_el1,
1531 pmsidr_el1, pmswinc_el0, pmceid0_el0, pmceid1_el0.
1532 * aarch64-tbl.h (aarch64_opcode_table): Add constraints to
1533 msr (F_SYS_WRITE), mrs (F_SYS_READ).
1534
7d02540a
TC		 15352018-05-15 Tamar Christina <tamar.christina@arm.com>
1536
1537 PR binutils/21446
1538 * aarch64-dis.c (no_notes: New.
1539 (parse_aarch64_dis_option): Support notes.
1540 (aarch64_decode_insn, print_operands): Likewise.
1541 (print_aarch64_disassembler_options): Document notes.
1542 * aarch64-opc.c (aarch64_print_operand): Support notes.
1543
561a72d4
TC		 15442018-05-15 Tamar Christina <tamar.christina@arm.com>
1545
1546 PR binutils/21446
1547 * aarch64-asm.h (aarch64_insert_operand, aarch64_##x): Return boolean
1548 and take error struct.
1549 * aarch64-asm.c (aarch64_ext_regno, aarch64_ins_reglane,
1550 aarch64_ins_reglist, aarch64_ins_ldst_reglist,
1551 aarch64_ins_ldst_reglist_r, aarch64_ins_ldst_elemlist,
1552 aarch64_ins_advsimd_imm_shift, aarch64_ins_imm, aarch64_ins_imm_half,
1553 aarch64_ins_advsimd_imm_modified, aarch64_ins_fpimm,
1554 aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2, aarch64_ins_fbits,
1555 aarch64_ins_aimm, aarch64_ins_limm_1, aarch64_ins_limm,
1556 aarch64_ins_inv_limm, aarch64_ins_ft, aarch64_ins_addr_simple,
1557 aarch64_ins_addr_regoff, aarch64_ins_addr_offset, aarch64_ins_addr_simm,
1558 aarch64_ins_addr_simm10, aarch64_ins_addr_uimm12,
1559 aarch64_ins_simd_addr_post, aarch64_ins_cond, aarch64_ins_sysreg,
1560 aarch64_ins_pstatefield, aarch64_ins_sysins_op, aarch64_ins_barrier,
1561 aarch64_ins_prfop, aarch64_ins_hint, aarch64_ins_reg_extended,
1562 aarch64_ins_reg_shifted, aarch64_ins_sve_addr_ri_s4xvl,
1563 aarch64_ins_sve_addr_ri_s6xvl, aarch64_ins_sve_addr_ri_s9xvl,
1564 aarch64_ins_sve_addr_ri_s4, aarch64_ins_sve_addr_ri_u6,
1565 aarch64_ins_sve_addr_rr_lsl, aarch64_ins_sve_addr_rz_xtw,
1566 aarch64_ins_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1567 aarch64_ins_sve_addr_zz_lsl, aarch64_ins_sve_addr_zz_sxtw,
1568 aarch64_ins_sve_addr_zz_uxtw, aarch64_ins_sve_aimm,
1569 aarch64_ins_sve_asimm, aarch64_ins_sve_index, aarch64_ins_sve_limm_mov,
1570 aarch64_ins_sve_quad_index, aarch64_ins_sve_reglist,
1571 aarch64_ins_sve_scale, aarch64_ins_sve_shlimm, aarch64_ins_sve_shrimm,
1572 aarch64_ins_sve_float_half_one, aarch64_ins_sve_float_half_two,
1573 aarch64_ins_sve_float_zero_one, aarch64_opcode_encode): Likewise.
1574 * aarch64-dis.h (aarch64_extract_operand, aarch64_##x): Likewise.
1575 * aarch64-dis.c (aarch64_ext_regno, aarch64_ext_reglane,
1576 aarch64_ext_reglist, aarch64_ext_ldst_reglist,
1577 aarch64_ext_ldst_reglist_r, aarch64_ext_ldst_elemlist,
1578 aarch64_ext_advsimd_imm_shift, aarch64_ext_imm, aarch64_ext_imm_half,
1579 aarch64_ext_advsimd_imm_modified, aarch64_ext_fpimm,
1580 aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2, aarch64_ext_fbits,
1581 aarch64_ext_aimm, aarch64_ext_limm_1, aarch64_ext_limm, decode_limm,
1582 aarch64_ext_inv_limm, aarch64_ext_ft, aarch64_ext_addr_simple,
1583 aarch64_ext_addr_regoff, aarch64_ext_addr_offset, aarch64_ext_addr_simm,
1584 aarch64_ext_addr_simm10, aarch64_ext_addr_uimm12,
1585 aarch64_ext_simd_addr_post, aarch64_ext_cond, aarch64_ext_sysreg,
1586 aarch64_ext_pstatefield, aarch64_ext_sysins_op, aarch64_ext_barrier,
1587 aarch64_ext_prfop, aarch64_ext_hint, aarch64_ext_reg_extended,
1588 aarch64_ext_reg_shifted, aarch64_ext_sve_addr_ri_s4xvl,
1589 aarch64_ext_sve_addr_ri_s6xvl, aarch64_ext_sve_addr_ri_s9xvl,
1590 aarch64_ext_sve_addr_ri_s4, aarch64_ext_sve_addr_ri_u6,
1591 aarch64_ext_sve_addr_rr_lsl, aarch64_ext_sve_addr_rz_xtw,
1592 aarch64_ext_sve_addr_zi_u5, aarch64_ext_sve_addr_zz,
1593 aarch64_ext_sve_addr_zz_lsl, aarch64_ext_sve_addr_zz_sxtw,
1594 aarch64_ext_sve_addr_zz_uxtw, aarch64_ext_sve_aimm,
1595 aarch64_ext_sve_asimm, aarch64_ext_sve_index, aarch64_ext_sve_limm_mov,
1596 aarch64_ext_sve_quad_index, aarch64_ext_sve_reglist,
1597 aarch64_ext_sve_scale, aarch64_ext_sve_shlimm, aarch64_ext_sve_shrimm,
1598 aarch64_ext_sve_float_half_one, aarch64_ext_sve_float_half_two,
1599 aarch64_ext_sve_float_zero_one, aarch64_opcode_decode): Likewise.
1600 (determine_disassembling_preference, aarch64_decode_insn,
1601 print_insn_aarch64_word, print_insn_data): Take errors struct.
1602 (print_insn_aarch64): Use errors.
1603 * aarch64-asm-2.c: Regenerate.
1604 * aarch64-dis-2.c: Regenerate.
1605 * aarch64-gen.c (print_operand_inserter): Use errors and change type to
1606 boolean in aarch64_insert_operan.
1607 (print_operand_extractor): Likewise.
1608 * aarch64-opc.c (aarch64_print_operand): Use sysreg struct.
1609
1678bd35
FT		 16102018-05-15 Francois H. Theron <francois.theron@netronome.com>
1611
1612 * nfp-dis.c: Use uint64_t for instruction variables, not bfd_vma.
1613
06cfb1c8
L		 16142018-05-09 H.J. Lu <hongjiu.lu@intel.com>
1615
1616 * i386-opc.tbl: Remove Disp<N> from movidir{i,64b}.
1617
84f9f8c3
AM		 16182018-05-09 Sebastian Rasmussen <sebras@gmail.com>
1619
1620 * cr16-opc.c (cr16_instruction): Comment typo fix.
1621 * hppa-dis.c (print_insn_hppa): Likewise.
1622
e6f372ba
JW		 16232018-05-08 Jim Wilson <jimw@sifive.com>
1624
1625 * riscv-opc.c (match_c_slli, match_slli_as_c_slli): New.
1626 (match_c_slli64, match_srxi_as_c_srxi): New.
1627 (riscv_opcodes) <slli, sll>: Use match_slli_as_c_slli.
1628 <srli, srl, srai, sra>: Use match_srxi_as_c_srxi.
1629 <c.slli, c.srli, c.srai>: Use match_s_slli.
1630 <c.slli64, c.srli64, c.srai64>: New.
1631
f413a913
AM		 16322018-05-08 Alan Modra <amodra@gmail.com>
1633
1634 * ppc-dis.c (PPC_OPCD_SEGS): Define using PPC_OP.
1635 (VLE_OPCD_SEGS, SPE2_OPCD_SEGS): Similarly, using macros used to
1636 partition opcode space for index lookup.
1637
a87a6478
PB		 16382018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1639
1640 * ppc-dis.c (print_insn_powerpc) <insn_is_short>: Replace this...
1641 <insn_length>: ...with this. Update usage.
1642 Remove duplicate call to *info->memory_error_func.
1643
c0a30a9f
L		 16442018-05-07 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1645 H.J. Lu <hongjiu.lu@intel.com>
1646
1647 * i386-dis.c (Gva): New.
1648 (enum): Add PREFIX_0F38F8, PREFIX_0F38F9,
1649 MOD_0F38F8_PREFIX_2, MOD_0F38F9_PREFIX_0.
1650 (prefix_table): New instructions (see prefix above).
1651 (mod_table): New instructions (see prefix above).
1652 (OP_G): Handle va_mode.
1653 * i386-gen.c (cpu_flag_init): Add CPU_MOVDIRI_FLAGS,
1654 CPU_MOVDIR64B_FLAGS.
1655 (cpu_flags): Add CpuMOVDIRI and CpuMOVDIR64B.
1656 * i386-opc.h (enum): Add CpuMOVDIRI, CpuMOVDIR64B.
1657 (i386_cpu_flags): Add cpumovdiri and cpumovdir64b.
1658 * i386-opc.tbl: Add movidir{i,64b}.
1659 * i386-init.h: Regenerated.
1660 * i386-tbl.h: Likewise.
1661
75c0a438
L		 16622018-05-07 H.J. Lu <hongjiu.lu@intel.com>
1663
1664 * i386-gen.c (opcode_modifiers): Replace AddrPrefixOp0 with
1665 AddrPrefixOpReg.
1666 * i386-opc.h (AddrPrefixOp0): Renamed to ...
1667 (AddrPrefixOpReg): This.
1668 (i386_opcode_modifier): Rename addrprefixop0 to addrprefixopreg.
1669 * i386-opc.tbl: Replace AddrPrefixOp0 with AddrPrefixOpReg.
1670
2ceb7719
PB		 16712018-05-07 Peter Bergner <bergner@vnet.ibm.com.com>
1672
1673 * ppc-opc.c (powerpc_num_opcodes): Change type to unsigned.
1674 (vle_num_opcodes): Likewise.
1675 (spe2_num_opcodes): Likewise.
1676 * ppc-dis.c (disassemble_init_powerpc) <powerpc_opcd_indices>: Rewrite
1677 initialization loop.
1678 (disassemble_init_powerpc) <vle_opcd_indices>: Likewise.
1679 (disassemble_init_powerpc) <spe2_opcd_indices>: Likewise. Initialize
1680 only once.
1681
b3ac5c6c
TC		 16822018-05-01 Tamar Christina <tamar.christina@arm.com>
1683
1684 * aarch64-dis.c (aarch64_opcode_decode): Moved memory clear code.
1685
fe944acf
FT		 16862018-04-30 Francois H. Theron <francois.theron@netronome.com>
1687
1688 Makefile.am: Added nfp-dis.c.
1689 configure.ac: Added bfd_nfp_arch.
1690 disassemble.h: Added print_insn_nfp prototype.
1691 disassemble.c: Added ARCH_nfp and call to print_insn_nfp
1692 nfp-dis.c: New, for NFP support.
1693 po/POTFILES.in: Added nfp-dis.c to the list.
1694 Makefile.in: Regenerate.
1695 configure: Regenerate.
1696
e2195274
JB		 16972018-04-26 Jan Beulich <jbeulich@suse.com>
1698
1699 * i386-opc.tbl: Fold various non-memory operand AVX512VL
1700 templates into their base ones.
1701 * i386-tlb.h: Re-generate.
1702
59ef5df4
JB		 17032018-04-26 Jan Beulich <jbeulich@suse.com>
1704
1705 * i386-gen.c (cpu_flag_init): Use CPU_XOP_FLAGS for
1706 CPU_BDVER1_FLAGS. Use CPU_AVX2_FLAGS for CPU_ZNVER1_FLAGS. Use
1707 CPU_AVX_FLAGS for CPU_BTVER1_FLAGS. Add CPU_XSAVE_FLAGS to
1708 CPU_LWP_FLAGS, CPU_AVX_FLAGS, CPU_MPX_FLAGS, and CPU_OSPKE_FLAGS.
1709 * i386-init.h: Re-generate.
1710
6e041cf4
JB		 17112018-04-26 Jan Beulich <jbeulich@suse.com>
1712
1713 * i386-gen.c (cpu_flag_init): Drop all uses of CpuRegMMX,
1714 CpuRegXMM, CpuRegYMM, CpuRegZMM, and CpuRegMask. Use
1715 CPU_AVX2_FLAGS for CPU_AVX512F_FLAGS and drop bogus comment.
1716 Don't use CPU_AVX2_FLAGS for CPU_AVX512VL_FLAGS and drop bogus
1717 comment.
1718 (cpu_flags): Drop CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1719 and CpuRegMask.
1720 * i386-opc.h: CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM,
1721 CpuRegMask: Delete.
1722 (union i386_cpu_flags): Remove cpuregmmx, cpuregxmm, cpuregymm,
1723 cpuregzmm, and cpuregmask.
1724 * i386-init.h: Re-generate.
1725 * i386-tbl.h: Re-generate.
1726
0e0eea78
JB		 17272018-04-26 Jan Beulich <jbeulich@suse.com>
1728
1729 * i386-gen.c (cpu_flag_init): CPU_I586_FLAGS inherits Cpu387 only.
1730 CPU_287_FLAGS is Cpu287 only. CPU_387_FLAGS is Cpu387 only.
1731 * i386-init.h: Re-generate.
1732
2f1bada2
JB		 17332018-04-26 Jan Beulich <jbeulich@suse.com>
1734
1735 * i386-gen.c (VexImmExt): Delete.
1736 * i386-opc.h (VexImmExt, veximmext): Delete.
1737 * i386-opc.tbl: Drop all VexImmExt uses.
1738 * i386-tlb.h: Re-generate.
1739
bacd1457
JB		 17402018-04-25 Jan Beulich <jbeulich@suse.com>
1741
1742 * i386-opc.tbl (vpslld, vpsrad, vpsrld): Drop AVX512VL
1743 register-only forms.
1744 * i386-tlb.h: Re-generate.
1745
10bba94b
TC		 17462018-04-25 Tamar Christina <tamar.christina@arm.com>
1747
1748 * aarch64-tbl.h (sqrdmlah, sqrdmlsh): Fix masks.
1749
c48935d7
IT		 17502018-04-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1751
1752 * i386-dis.c: Add REG_0F1C_MOD_0, MOD_0F1C_PREFIX_0,
1753 PREFIX_0F1C.
1754 * i386-gen.c (cpu_flag_init): Add CPU_CLDEMOTE_FLAGS,
1755 (cpu_flags): Add CpuCLDEMOTE.
1756 * i386-init.h: Regenerate.
1757 * i386-opc.h (enum): Add CpuCLDEMOTE,
1758 (i386_cpu_flags): Add cpucldemote.
1759 * i386-opc.tbl: Add cldemote.
1760 * i386-tbl.h: Regenerate.
1761
211dc24b
AM		 17622018-04-16 Alan Modra <amodra@gmail.com>
1763
1764 * Makefile.am: Remove sh5 and sh64 support.
1765 * configure.ac: Likewise.
1766 * disassemble.c: Likewise.
1767 * disassemble.h: Likewise.
1768 * sh-dis.c: Likewise.
1769 * sh64-dis.c: Delete.
1770 * sh64-opc.c: Delete.
1771 * sh64-opc.h: Delete.
1772 * Makefile.in: Regenerate.
1773 * configure: Regenerate.
1774 * po/POTFILES.in: Regenerate.
1775
a9a4b302
AM		 17762018-04-16 Alan Modra <amodra@gmail.com>
1777
1778 * Makefile.am: Remove w65 support.
1779 * configure.ac: Likewise.
1780 * disassemble.c: Likewise.
1781 * disassemble.h: Likewise.
1782 * w65-dis.c: Delete.
1783 * w65-opc.h: Delete.
1784 * Makefile.in: Regenerate.
1785 * configure: Regenerate.
1786 * po/POTFILES.in: Regenerate.
1787
04cb01fd
AM		 17882018-04-16 Alan Modra <amodra@gmail.com>
1789
1790 * configure.ac: Remove we32k support.
1791 * configure: Regenerate.
1792
c2bf1eec
AM		 17932018-04-16 Alan Modra <amodra@gmail.com>
1794
1795 * Makefile.am: Remove m88k support.
1796 * configure.ac: Likewise.
1797 * disassemble.c: Likewise.
1798 * disassemble.h: Likewise.
1799 * m88k-dis.c: Delete.
1800 * Makefile.in: Regenerate.
1801 * configure: Regenerate.
1802 * po/POTFILES.in: Regenerate.
1803
6793974d
AM		 18042018-04-16 Alan Modra <amodra@gmail.com>
1805
1806 * Makefile.am: Remove i370 support.
1807 * configure.ac: Likewise.
1808 * disassemble.c: Likewise.
1809 * disassemble.h: Likewise.
1810 * i370-dis.c: Delete.
1811 * i370-opc.c: Delete.
1812 * Makefile.in: Regenerate.
1813 * configure: Regenerate.
1814 * po/POTFILES.in: Regenerate.
1815
e82aa794
AM		 18162018-04-16 Alan Modra <amodra@gmail.com>
1817
1818 * Makefile.am: Remove h8500 support.
1819 * configure.ac: Likewise.
1820 * disassemble.c: Likewise.
1821 * disassemble.h: Likewise.
1822 * h8500-dis.c: Delete.
1823 * h8500-opc.h: Delete.
1824 * Makefile.in: Regenerate.
1825 * configure: Regenerate.
1826 * po/POTFILES.in: Regenerate.
1827
fceadf09
AM		 18282018-04-16 Alan Modra <amodra@gmail.com>
1829
1830 * configure.ac: Remove tahoe support.
1831 * configure: Regenerate.
1832
ae1d3843
L		 18332018-04-15 H.J. Lu <hongjiu.lu@intel.com>
1834
1835 * i386-dis.c (prefix_table): Replace Em with Edq on tpause and
1836 umwait.
1837 * i386-opc.tbl: Allow 32-bit registers for tpause and umwait in
1838 64-bit mode.
1839 * i386-tbl.h: Regenerated.
1840
de89d0a3
IT		 18412018-04-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1842
1843 * i386-dis.c (enum): Add PREFIX_MOD_0_0FAE_REG_6,
1844 PREFIX_MOD_1_0FAE_REG_6.
1845 (va_mode): New.
1846 (OP_E_register): Use va_mode.
1847 * i386-dis-evex.h (prefix_table):
1848 New instructions (see prefixes above).
1849 * i386-gen.c (cpu_flag_init): Add WAITPKG.
1850 (cpu_flags): Likewise.
1851 * i386-opc.h (enum): Likewise.
1852 (i386_cpu_flags): Likewise.
1853 * i386-opc.tbl: Add umonitor, umwait, tpause.
1854 * i386-init.h: Regenerate.
1855 * i386-tbl.h: Likewise.
1856
a8eb42a8
AM		 18572018-04-11 Alan Modra <amodra@gmail.com>
1858
1859 * opcodes/i860-dis.c: Delete.
1860 * opcodes/i960-dis.c: Delete.
1861 * Makefile.am: Remove i860 and i960 support.
1862 * configure.ac: Likewise.
1863 * disassemble.c: Likewise.
1864 * disassemble.h: Likewise.
1865 * Makefile.in: Regenerate.
1866 * configure: Regenerate.
1867 * po/POTFILES.in: Regenerate.
1868
caf0678c
L		 18692018-04-04 H.J. Lu <hongjiu.lu@intel.com>
1870
1871 PR binutils/23025
1872 * i386-dis.c (get_valid_dis386): Don't set vex.prefix nor vex.w
1873 to 0.
1874 (print_insn): Clear vex instead of vex.evex.
1875
4fb0d2b9
NC		 18762018-04-04 Nick Clifton <nickc@redhat.com>
1877
1878 * po/es.po: Updated Spanish translation.
1879
c39e5b26
JB		 18802018-03-28 Jan Beulich <jbeulich@suse.com>
1881
1882 * i386-gen.c (opcode_modifiers): Delete VecESize.
1883 * i386-opc.h (VecESize): Delete.
1884 (struct i386_opcode_modifier): Delete vecesize.
1885 * i386-opc.tbl: Drop VecESize.
1886 * i386-tlb.h: Re-generate.
1887
8e6e0792
JB		 18882018-03-28 Jan Beulich <jbeulich@suse.com>
1889
1890 * i386-opc.h (NO_BROADCAST, BROADCAST_1TO16, BROADCAST_1TO8,
1891 BROADCAST_1TO4, BROADCAST_1TO2): Delete.
1892 (struct i386_opcode_modifier): Shrink broadcast field to 1 bit.
1893 * i386-opc.tbl: Replace Broadcast=<N> by Broadcast.
1894 * i386-tlb.h: Re-generate.
1895
9f123b91
JB		 18962018-03-28 Jan Beulich <jbeulich@suse.com>
1897
1898 * i386-opc.tbl (vcvt*d2si, vcvt*d2usi, vcvt*s2si, vcvt*s2usi):
1899 Fold AVX512 forms
1900 * i386-tlb.h: Re-generate.
1901
9646c87b
JB		 19022018-03-28 Jan Beulich <jbeulich@suse.com>
1903
1904 * i386-dis.c (prefix_table): Drop Y for cvt*2si.
1905 (vex_len_table): Drop Y for vcvt*2si.
1906 (putop): Replace plain 'Y' handling by abort().
1907
c8d59609
NC		 19082018-03-28 Nick Clifton <nickc@redhat.com>
1909
1910 PR 22988
1911 * aarch64-tbl.h (aarch64_opcode_table): Add entries for LDFF1xx
1912 instructions with only a base address register.
1913 * aarch64-opc.c (operand_general_constraint_met_p): Add code to
1914 handle AARHC64_OPND_SVE_ADDR_R.
1915 (aarch64_print_operand): Likewise.
1916 * aarch64-asm-2.c: Regenerate.
1917 * aarch64_dis-2.c: Regenerate.
1918 * aarch64-opc-2.c: Regenerate.
1919
b8c169f3
JB		 19202018-03-22 Jan Beulich <jbeulich@suse.com>
1921
1922 * i386-opc.tbl: Drop VecESize from register only insn forms and
1923 memory forms not allowing broadcast.
1924 * i386-tlb.h: Re-generate.
1925
96bc132a
JB		 19262018-03-22 Jan Beulich <jbeulich@suse.com>
1927
1928 * i386-opc.tbl (vfrczs*, vphadd*, vphsub*, vpmacs*, vpmadcs*,
1929 vprot*, vpsha*, vpshl*, bextr, blc*, bls*, t1mskc, tzmsk, sha1*,
1930 sha256*): Drop Disp<N>.
1931
9f79e886
JB		 19322018-03-22 Jan Beulich <jbeulich@suse.com>
1933
1934 * i386-dis.c (EbndS, bnd_swap_mode): New.
1935 (prefix_table): Use EbndS.
1936 (OP_E_register, OP_E_memory): Also handle bnd_swap_mode.
1937 * i386-opc.tbl (bndmov): Move misplaced Load.
1938 * i386-tlb.h: Re-generate.
1939
d6793fa1
JB		 19402018-03-22 Jan Beulich <jbeulich@suse.com>
1941
1942 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd): Use separate
1943 templates allowing memory operands and folded ones for register
1944 only flavors.
1945 * i386-tlb.h: Re-generate.
1946
f7768225
JB		 19472018-03-22 Jan Beulich <jbeulich@suse.com>
1948
1949 * i386-opc.tbl (vfrczp*, vpcmov, vpermil2p*): Fold 128- and
1950 256-bit templates. Drop redundant leftover Disp<N>.
1951 * i386-tlb.h: Re-generate.
1952
0e35537d
JW		 19532018-03-14 Kito Cheng <kito.cheng@gmail.com>
1954
1955 * riscv-opc.c (riscv_insn_types): New.
1956
b4a3689a
NC		 19572018-03-13 Nick Clifton <nickc@redhat.com>
1958
1959 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1960
d3d50934
L		 19612018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1962
1963 * i386-opc.tbl: Add Optimize to clr.
1964 * i386-tbl.h: Regenerated.
1965
bd5dea88
L		 19662018-03-08 H.J. Lu <hongjiu.lu@intel.com>
1967
1968 * i386-gen.c (opcode_modifiers): Remove OldGcc.
1969 * i386-opc.h (OldGcc): Removed.
1970 (i386_opcode_modifier): Remove oldgcc.
1971 * i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
1972 instructions for old (<= 2.8.1) versions of gcc.
1973 * i386-tbl.h: Regenerated.
1974
e771e7c9
JB		 19752018-03-08 Jan Beulich <jbeulich@suse.com>
1976
1977 * i386-opc.h (EVEXDYN): New.
1978 * i386-opc.tbl: Fold various AVX512VL templates.
1979 * i386-tlb.h: Re-generate.
1980
ed438a93
JB		 19812018-03-08 Jan Beulich <jbeulich@suse.com>
1982
1983 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1984 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1985 vpexpandd, vpexpandq): Fold AFX512VF templates.
1986 * i386-tlb.h: Re-generate.
1987
454172a9
JB		 19882018-03-08 Jan Beulich <jbeulich@suse.com>
1989
1990 * i386-opc.tbl (vgf2p8affineinvqb, vgf2p8affineqb, vgf2p8mulb):
1991 Fold 128- and 256-bit VEX-encoded templates.
1992 * i386-tlb.h: Re-generate.
1993
36824150
JB		 19942018-03-08 Jan Beulich <jbeulich@suse.com>
1995
1996 * i386-opc.tbl (vexpandpd, vexpandps, vmovapd, vmovaps,
1997 vmovdqa32, vmovdqa64, vmovdqu32, vmovdqu64, vmovupd, vmovups,
1998 vpexpandd, vpexpandq): Fold AVX512F templates.
1999 * i386-tlb.h: Re-generate.
2000
e7f5c0a9
JB		 20012018-03-08 Jan Beulich <jbeulich@suse.com>
2002
2003 * i386-opc.tbl (llwpcb, slwpcb, lwpval, lwpins): Fold 32- and
2004 64-bit templates. Drop Disp<N>.
2005 * i386-tlb.h: Re-generate.
2006
25a4277f
JB		 20072018-03-08 Jan Beulich <jbeulich@suse.com>
2008
2009 * i386-opc.tbl (vfmadd*, vfmsub*, vfnmadd*, vfnmsub*): Fold 128-
2010 and 256-bit templates.
2011 * i386-tlb.h: Re-generate.
2012
d2224064
JB		 20132018-03-08 Jan Beulich <jbeulich@suse.com>
2014
2015 * i386-opc.tbl (cmpxchg8b): Add NoRex64.
2016 * i386-tlb.h: Re-generate.
2017
1b193f0b
JB		 20182018-03-08 Jan Beulich <jbeulich@suse.com>
2019
2020 * i386-opc.tbl (cmpxchg16b, fisttp, fisttpll, bndmov, mwaitx):
2021 Drop NoAVX.
2022 * i386-tlb.h: Re-generate.
2023
f2f6a710
JB		 20242018-03-08 Jan Beulich <jbeulich@suse.com>
2025
2026 * i386-opc.tbl (ldmxcsr, stmxcsr): Add NoAVX.
2027 * i386-tlb.h: Re-generate.
2028
38e314eb
JB		 20292018-03-08 Jan Beulich <jbeulich@suse.com>
2030
2031 * i386-gen.c (opcode_modifiers): Delete FloatD.
2032 * i386-opc.h (FloatD): Delete.
2033 (struct i386_opcode_modifier): Delete floatd.
2034 * i386-opc.tbl (fadd, fsub, fsubr, fmul, fdiv, fdivr): Replace
2035 FloatD by D.
2036 * i386-tlb.h: Re-generate.
2037
d53e6b98
JB		 20382018-03-08 Jan Beulich <jbeulich@suse.com>
2039
2040 * i386-dis.c (float_reg): Adjust DC and DE fsub*/fdiv* patterns.
2041
2907c2f5
JB		 20422018-03-08 Jan Beulich <jbeulich@suse.com>
2043
2044 * i386-opc.tbl (vmovd): Disallow Qword memory operands.
2045 * i386-tlb.h: Re-generate.
2046
73053c1f
JB		 20472018-03-08 Jan Beulich <jbeulich@suse.com>
2048
2049 * i386-opc.tbl (vcvtpd2ps): Fold AVX 128- and 256-bit memory
2050 forms.
2051 * i386-tlb.h: Re-generate.
2052
52fe4420
AM		 20532018-03-07 Alan Modra <amodra@gmail.com>
2054
2055 * disassemble.c (disassembler): Use bfd_arch_powerpc entry for
2056 bfd_arch_rs6000.
2057 * disassemble.h (print_insn_rs6000): Delete.
2058 * ppc-dis.c (powerpc_init_dialect): Handle rs6000.
2059 (disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
2060 (print_insn_rs6000): Delete.
2061
a6743a54
AM		 20622018-03-03 Alan Modra <amodra@gmail.com>
2063
2064 * sysdep.h (opcodes_error_handler): Define.
2065 (_bfd_error_handler): Declare.
2066 * Makefile.am: Remove stray #.
2067 * opc2c.c (main): Remove bogus -l arg handling. Print "DO NOT
2068 EDIT" comment.
2069 * aarch64-dis.c, * arc-dis.c, * arm-dis.c, * avr-dis.c,
2070 * d30v-dis.c, * h8300-dis.c, * mmix-dis.c, * ppc-dis.c,
2071 * riscv-dis.c, * s390-dis.c, * sparc-dis.c, * v850-dis.c: Use
2072 opcodes_error_handler to print errors. Standardize error messages.
2073 * msp430-decode.opc, * nios2-dis.c, * rl78-decode.opc: Likewise,
2074 and include opintl.h.
2075 * nds32-asm.c: Likewise, and include sysdep.h and opintl.h.
2076 * i386-gen.c: Standardize error messages.
2077 * msp430-decode.c, * rl78-decode.c, rx-decode.c: Regenerate.
2078 * Makefile.in: Regenerate.
2079 * epiphany-asm.c, * epiphany-desc.c, * epiphany-dis.c,
2080 * epiphany-ibld.c, * fr30-asm.c, * fr30-desc.c, * fr30-dis.c,
2081 * fr30-ibld.c, * frv-asm.c, * frv-desc.c, * frv-dis.c, * frv-ibld.c,
2082 * frv-opc.c, * ip2k-asm.c, * ip2k-desc.c, * ip2k-dis.c, * ip2k-ibld.c,
2083 * iq2000-asm.c, * iq2000-desc.c, * iq2000-dis.c, * iq2000-ibld.c,
2084 * lm32-asm.c, * lm32-desc.c, * lm32-dis.c, * lm32-ibld.c,
2085 * m32c-asm.c, * m32c-desc.c, * m32c-dis.c, * m32c-ibld.c,
2086 * m32r-asm.c, * m32r-desc.c, * m32r-dis.c, * m32r-ibld.c,
2087 * mep-asm.c, * mep-desc.c, * mep-dis.c, * mep-ibld.c, * mt-asm.c,
2088 * mt-desc.c, * mt-dis.c, * mt-ibld.c, * or1k-asm.c, * or1k-desc.c,
2089 * or1k-dis.c, * or1k-ibld.c, * xc16x-asm.c, * xc16x-desc.c,
2090 * xc16x-dis.c, * xc16x-ibld.c, * xstormy16-asm.c, * xstormy16-desc.c,
2091 * xstormy16-dis.c, * xstormy16-ibld.c: Regenerate.
2092
8305403a
L		 20932018-03-01 H.J. Lu <hongjiu.lu@intel.com>
2094
2095 * * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
2096 vpsub[bwdq] instructions.
2097 * i386-tbl.h: Regenerated.
2098
e184813f
AM		 20992018-03-01 Alan Modra <amodra@gmail.com>
2100
2101 * configure.ac (ALL_LINGUAS): Sort.
2102 * configure: Regenerate.
2103
5b616bef
TP		 21042018-02-27 Thomas Preud'homme <thomas.preudhomme@arm.com>
2105
2106 * arm-dis.c (print_insn_coprocessor): Replace uses of ARM_FEATURE_COPY
2107 macro by assignements.
2108
b6f8c7c4
L		 21092018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2110
2111 PR gas/22871
2112 * i386-gen.c (opcode_modifiers): Add Optimize.
2113 * i386-opc.h (Optimize): New enum.
2114 (i386_opcode_modifier): Add optimize.
2115 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
2116 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
2117 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
2118 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
2119 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
2120 vpxord and vpxorq.
2121 * i386-tbl.h: Regenerated.
2122
e95b887f
AM		 21232018-02-26 Alan Modra <amodra@gmail.com>
2124
2125 * crx-dis.c (getregliststring): Allocate a large enough buffer
2126 to silence false positive gcc8 warning.
2127
0bccfb29
JW		 21282018-02-22 Shea Levy <shea@shealevy.com>
2129
2130 * disassemble.c (ARCH_riscv): Define if ARCH_all.
2131
6b6b6807
L		 21322018-02-22 H.J. Lu <hongjiu.lu@intel.com>
2133
2134 * i386-opc.tbl: Add {rex},
2135 * i386-tbl.h: Regenerated.
2136
75f31665
MR		 21372018-02-20 Maciej W. Rozycki <macro@mips.com>
2138
2139 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
2140 (mips16_opcodes): Replace `M' with `m' for "restore".
2141
e207bc53
TP		 21422018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
2143
2144 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
2145
87993319
MR		 21462018-02-13 Maciej W. Rozycki <macro@mips.com>
2147
2148 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
2149 variable to `function_index'.
2150
68d20676
NC		 21512018-02-13 Nick Clifton <nickc@redhat.com>
2152
2153 PR 22823
2154 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
2155 about truncation of printing.
2156
d2159fdc
HW		 21572018-02-12 Henry Wong <henry@stuffedcow.net>
2158
2159 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
2160
f174ef9f
NC		 21612018-02-05 Nick Clifton <nickc@redhat.com>
2162
2163 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2164
be3a8dca
IT		 21652018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2166
2167 * i386-dis.c (enum): Add pconfig.
2168 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
2169 (cpu_flags): Add CpuPCONFIG.
2170 * i386-opc.h (enum): Add CpuPCONFIG.
2171 (i386_cpu_flags): Add cpupconfig.
2172 * i386-opc.tbl: Add PCONFIG instruction.
2173 * i386-init.h: Regenerate.
2174 * i386-tbl.h: Likewise.
2175
3233d7d0
IT		 21762018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2177
2178 * i386-dis.c (enum): Add PREFIX_0F09.
2179 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
2180 (cpu_flags): Add CpuWBNOINVD.
2181 * i386-opc.h (enum): Add CpuWBNOINVD.
2182 (i386_cpu_flags): Add cpuwbnoinvd.
2183 * i386-opc.tbl: Add WBNOINVD instruction.
2184 * i386-init.h: Regenerate.
2185 * i386-tbl.h: Likewise.
2186
e925c834
JW		 21872018-01-17 Jim Wilson <jimw@sifive.com>
2188
2189 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
2190
d777820b
IT		 21912018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2192
2193 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
2194 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
2195 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
2196 (cpu_flags): Add CpuIBT, CpuSHSTK.
2197 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
2198 (i386_cpu_flags): Add cpuibt, cpushstk.
2199 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
2200 * i386-init.h: Regenerate.
2201 * i386-tbl.h: Likewise.
2202
f6efed01
NC		 22032018-01-16 Nick Clifton <nickc@redhat.com>
2204
2205 * po/pt_BR.po: Updated Brazilian Portugese translation.
2206 * po/de.po: Updated German translation.
2207
2721d702
JW		 22082018-01-15 Jim Wilson <jimw@sifive.com>
2209
2210 * riscv-opc.c (match_c_nop): New.
2211 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
2212
616dcb87
NC		 22132018-01-15 Nick Clifton <nickc@redhat.com>
2214
2215 * po/uk.po: Updated Ukranian translation.
2216
3957a496
NC		 22172018-01-13 Nick Clifton <nickc@redhat.com>
2218
2219 * po/opcodes.pot: Regenerated.
2220
769c7ea5
NC		 22212018-01-13 Nick Clifton <nickc@redhat.com>
2222
2223 * configure: Regenerate.
2224
faf766e3
NC		 22252018-01-13 Nick Clifton <nickc@redhat.com>
2226
2227 2.30 branch created.
2228
888a89da
IT		 22292018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
2230
2231 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
2232 * i386-tbl.h: Regenerate.
2233
cbda583a
JB		 22342018-01-10 Jan Beulich <jbeulich@suse.com>
2235
2236 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
2237 * i386-tbl.h: Re-generate.
2238
c9e92278
JB		 22392018-01-10 Jan Beulich <jbeulich@suse.com>
2240
2241 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
2242 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
2243 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
2244 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
2245 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
2246 Disp8MemShift of AVX512VL forms.
2247 * i386-tbl.h: Re-generate.
2248
35fd2b2b
JW		 22492018-01-09 Jim Wilson <jimw@sifive.com>
2250
2251 * riscv-dis.c (maybe_print_address): If base_reg is zero,
2252 then the hi_addr value is zero.
2253
91d8b670
JG		 22542018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2255
2256 * arm-dis.c (arm_opcodes): Add csdb.
2257 (thumb32_opcodes): Add csdb.
2258
be2e7d95
JG		 22592018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
2260
2261 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
2262 * aarch64-asm-2.c: Regenerate.
2263 * aarch64-dis-2.c: Regenerate.
2264 * aarch64-opc-2.c: Regenerate.
2265
704a705d
L		 22662018-01-08 H.J. Lu <hongjiu.lu@intel.com>
2267
2268 PR gas/22681
2269 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
2270 Remove AVX512 vmovd with 64-bit operands.
2271 * i386-tbl.h: Regenerated.
2272
35eeb78f
JW		 22732018-01-05 Jim Wilson <jimw@sifive.com>
2274
2275 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
2276 jalr.
2277
219d1afa
AM		 22782018-01-03 Alan Modra <amodra@gmail.com>
2279
2280 Update year range in copyright notice of all files.
2281
1508bbf5
JB		 22822018-01-02 Jan Beulich <jbeulich@suse.com>
2283
2284 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
2285 and OPERAND_TYPE_REGZMM entries.
2286
1e563868 2287For older changes see ChangeLog-2017
3499769a 2288\f
1e563868 2289Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
AM		 2290
2291Copying and distribution of this file, with or without modification,
2292are permitted in any medium without royalty provided the copyright
2293notice and this notice are preserved.
2294
2295Local Variables:
2296mode: change-log
2297left-margin: 8
2298fill-column: 74
2299version-control: never
2300End:
GDB Binutils - Deliverables
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