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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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2d2dbad0
NC		 12017-07-20 Nick Clifton <nickc@redhat.com>
2
3 * po/de.po: Updated German translation.
4
70b448ba 52017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
6
7 * arc-regs.h (sec_stat): New aux register.
8 (aux_kernel_sp): Likewise.
9 (aux_sec_u_sp): Likewise.
10 (aux_sec_k_sp): Likewise.
11 (sec_vecbase_build): Likewise.
12 (nsc_table_top): Likewise.
13 (nsc_table_base): Likewise.
14 (ersec_stat): Likewise.
15 (aux_sec_except): Likewise.
16
7179e0e6
CZ		 172017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
18
19 * arc-opc.c (extract_uimm12_20): New function.
20 (UIMM12_20): New operand.
21 (SIMM3_5_S): Adjust.
22 * arc-tbl.h (sjli): Add new instruction.
23
684d5a10
JEM		 242017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
25 John Eric Martin <John.Martin@emmicro-us.com>
26
27 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
28 (UIMM3_23): Adjust accordingly.
29 * arc-regs.h: Add/correct jli_base register.
30 * arc-tbl.h (jli_s): Likewise.
31
de194d85
YC		 322017-07-18 Nick Clifton <nickc@redhat.com>
33
34 PR 21775
35 * aarch64-opc.c: Fix spelling typos.
36 * i386-dis.c: Likewise.
37
0f6329bd
RB		 382017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
39
40 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
41 max_addr_offset and octets variables to size_t.
42
429d795d
AM		 432017-07-12 Alan Modra <amodra@gmail.com>
44
45 * po/da.po: Update from translationproject.org/latest/opcodes/.
46 * po/de.po: Likewise.
47 * po/es.po: Likewise.
48 * po/fi.po: Likewise.
49 * po/fr.po: Likewise.
50 * po/id.po: Likewise.
51 * po/it.po: Likewise.
52 * po/nl.po: Likewise.
53 * po/pt_BR.po: Likewise.
54 * po/ro.po: Likewise.
55 * po/sv.po: Likewise.
56 * po/tr.po: Likewise.
57 * po/uk.po: Likewise.
58 * po/vi.po: Likewise.
59 * po/zh_CN.po: Likewise.
60
4162bb66
AM		 612017-07-11 Yao Qi <yao.qi@linaro.org>
62 Alan Modra <amodra@gmail.com>
63
64 * cgen.sh: Mark generated files read-only.
65 * epiphany-asm.c: Regenerate.
66 * epiphany-desc.c: Regenerate.
67 * epiphany-desc.h: Regenerate.
68 * epiphany-dis.c: Regenerate.
69 * epiphany-ibld.c: Regenerate.
70 * epiphany-opc.c: Regenerate.
71 * epiphany-opc.h: Regenerate.
72 * fr30-asm.c: Regenerate.
73 * fr30-desc.c: Regenerate.
74 * fr30-desc.h: Regenerate.
75 * fr30-dis.c: Regenerate.
76 * fr30-ibld.c: Regenerate.
77 * fr30-opc.c: Regenerate.
78 * fr30-opc.h: Regenerate.
79 * frv-asm.c: Regenerate.
80 * frv-desc.c: Regenerate.
81 * frv-desc.h: Regenerate.
82 * frv-dis.c: Regenerate.
83 * frv-ibld.c: Regenerate.
84 * frv-opc.c: Regenerate.
85 * frv-opc.h: Regenerate.
86 * ip2k-asm.c: Regenerate.
87 * ip2k-desc.c: Regenerate.
88 * ip2k-desc.h: Regenerate.
89 * ip2k-dis.c: Regenerate.
90 * ip2k-ibld.c: Regenerate.
91 * ip2k-opc.c: Regenerate.
92 * ip2k-opc.h: Regenerate.
93 * iq2000-asm.c: Regenerate.
94 * iq2000-desc.c: Regenerate.
95 * iq2000-desc.h: Regenerate.
96 * iq2000-dis.c: Regenerate.
97 * iq2000-ibld.c: Regenerate.
98 * iq2000-opc.c: Regenerate.
99 * iq2000-opc.h: Regenerate.
100 * lm32-asm.c: Regenerate.
101 * lm32-desc.c: Regenerate.
102 * lm32-desc.h: Regenerate.
103 * lm32-dis.c: Regenerate.
104 * lm32-ibld.c: Regenerate.
105 * lm32-opc.c: Regenerate.
106 * lm32-opc.h: Regenerate.
107 * lm32-opinst.c: Regenerate.
108 * m32c-asm.c: Regenerate.
109 * m32c-desc.c: Regenerate.
110 * m32c-desc.h: Regenerate.
111 * m32c-dis.c: Regenerate.
112 * m32c-ibld.c: Regenerate.
113 * m32c-opc.c: Regenerate.
114 * m32c-opc.h: Regenerate.
115 * m32r-asm.c: Regenerate.
116 * m32r-desc.c: Regenerate.
117 * m32r-desc.h: Regenerate.
118 * m32r-dis.c: Regenerate.
119 * m32r-ibld.c: Regenerate.
120 * m32r-opc.c: Regenerate.
121 * m32r-opc.h: Regenerate.
122 * m32r-opinst.c: Regenerate.
123 * mep-asm.c: Regenerate.
124 * mep-desc.c: Regenerate.
125 * mep-desc.h: Regenerate.
126 * mep-dis.c: Regenerate.
127 * mep-ibld.c: Regenerate.
128 * mep-opc.c: Regenerate.
129 * mep-opc.h: Regenerate.
130 * mt-asm.c: Regenerate.
131 * mt-desc.c: Regenerate.
132 * mt-desc.h: Regenerate.
133 * mt-dis.c: Regenerate.
134 * mt-ibld.c: Regenerate.
135 * mt-opc.c: Regenerate.
136 * mt-opc.h: Regenerate.
137 * or1k-asm.c: Regenerate.
138 * or1k-desc.c: Regenerate.
139 * or1k-desc.h: Regenerate.
140 * or1k-dis.c: Regenerate.
141 * or1k-ibld.c: Regenerate.
142 * or1k-opc.c: Regenerate.
143 * or1k-opc.h: Regenerate.
144 * or1k-opinst.c: Regenerate.
145 * xc16x-asm.c: Regenerate.
146 * xc16x-desc.c: Regenerate.
147 * xc16x-desc.h: Regenerate.
148 * xc16x-dis.c: Regenerate.
149 * xc16x-ibld.c: Regenerate.
150 * xc16x-opc.c: Regenerate.
151 * xc16x-opc.h: Regenerate.
152 * xstormy16-asm.c: Regenerate.
153 * xstormy16-desc.c: Regenerate.
154 * xstormy16-desc.h: Regenerate.
155 * xstormy16-dis.c: Regenerate.
156 * xstormy16-ibld.c: Regenerate.
157 * xstormy16-opc.c: Regenerate.
158 * xstormy16-opc.h: Regenerate.
159
7639175c
AM		 1602017-07-07 Alan Modra <amodra@gmail.com>
161
162 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
163 * m32c-dis.c: Regenerate.
164 * mep-dis.c: Regenerate.
165
e4bdd679
BP		 1662017-07-05 Borislav Petkov <bp@suse.de>
167
168 * i386-dis.c: Enable ModRM.reg /6 aliases.
169
60c96dbf
RR		 1702017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
171
172 * opcodes/arm-dis.c: Support MVFR2 in disassembly
173 with vmrs and vmsr.
174
0d702cfe
TG		 1752017-07-04 Tristan Gingold <gingold@adacore.com>
176
177 * configure: Regenerate.
178
15e6ed8c
TG		 1792017-07-03 Tristan Gingold <gingold@adacore.com>
180
181 * po/opcodes.pot: Regenerate.
182
b1d3c886
MR		 1832017-06-30 Maciej W. Rozycki <macro@imgtec.com>
184
185 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
186 entries to the MSA ASE instruction block.
187
909b4e3d
MR		 1882017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
189 Maciej W. Rozycki <macro@imgtec.com>
190
191 * micromips-opc.c (XPA, XPAVZ): New macros.
192 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
193 "mthgc0".
194
f5b2fd52
MR		 1952017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
196 Maciej W. Rozycki <macro@imgtec.com>
197
198 * micromips-opc.c (I36): New macro.
199 (micromips_opcodes): Add "eretnc".
200
9785fc2a
MR		 2012017-06-30 Maciej W. Rozycki <macro@imgtec.com>
202 Andrew Bennett <andrew.bennett@imgtec.com>
203
204 * mips-dis.c (mips_calculate_combination_ases): Handle the
205 ASE_XPA_VIRT flag.
206 (parse_mips_ase_option): New function.
207 (parse_mips_dis_option): Factor out ASE option handling to the
208 new function. Call `mips_calculate_combination_ases'.
209 * mips-opc.c (XPAVZ): New macro.
210 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
211 "mfhgc0", "mthc0" and "mthgc0".
212
60804c53
MR		 2132017-06-29 Maciej W. Rozycki <macro@imgtec.com>
214
215 * mips-dis.c (mips_calculate_combination_ases): New function.
216 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
217 calculation to the new function.
218 (set_default_mips_dis_options): Call the new function.
219
2e74f9dd
AK		 2202017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
221
222 * arc-dis.c (parse_disassembler_options): Use
223 FOR_EACH_DISASSEMBLER_OPTION.
224
e1e94c49
AK		 2252017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
226
227 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
228 disassembler option strings.
229 (parse_cpu_option): Likewise.
230
65a55fbb
TC		 2312017-06-28 Tamar Christina <tamar.christina@arm.com>
232
233 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
234 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
235 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
236 (aarch64_feature_dotprod, DOT_INSN): New.
237 (udot, sdot): New.
238 * aarch64-dis-2.c: Regenerated.
239
c604a79a
JW		 2402017-06-28 Jiong Wang <jiong.wang@arm.com>
241
242 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
243
38bf472a
MR		 2442017-06-28 Maciej W. Rozycki <macro@imgtec.com>
245 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 246 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 247
248 * mips-formats.h (INT_BIAS): New macro.
249 (INT_ADJ): Redefine in INT_BIAS terms.
250 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
251 (mips_print_save_restore): New function.
252 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
253 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
254 call.
255 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
256 (print_mips16_insn_arg): Call `mips_print_save_restore' for
257 OP_SAVE_RESTORE_LIST handling, factored out from here.
258 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
259 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
260 (mips_builtin_opcodes): Add "restore" and "save" entries.
261 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
262 (IAMR2): New macro.
263 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
264
9bdfdbf9
AW		 2652017-06-23 Andrew Waterman <andrew@sifive.com>
266
267 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
268 alias; do not mark SLTI instruction as an alias.
269
2234eee6
L		 2702017-06-21 H.J. Lu <hongjiu.lu@intel.com>
271
272 * i386-dis.c (RM_0FAE_REG_5): Removed.
273 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
274 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
275 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
276 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
277 PREFIX_MOD_3_0F01_REG_5_RM_0.
278 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
279 PREFIX_MOD_3_0FAE_REG_5.
280 (mod_table): Update MOD_0FAE_REG_5.
281 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
282 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
283 * i386-tbl.h: Regenerated.
284
c2f76402
L		 2852017-06-21 H.J. Lu <hongjiu.lu@intel.com>
286
287 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
288 * i386-opc.tbl: Likewise.
289 * i386-tbl.h: Regenerated.
290
9fef80d6
L		 2912017-06-21 H.J. Lu <hongjiu.lu@intel.com>
292
293 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
294 and "jmp{&|}".
295 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
296 prefix.
297
0f6d864d
NC		 2982017-06-19 Nick Clifton <nickc@redhat.com>
299
300 PR binutils/21614
301 * score-dis.c (score_opcodes): Add sentinel.
302
e197589b
AM		 3032017-06-16 Alan Modra <amodra@gmail.com>
304
305 * rx-decode.c: Regenerate.
306
0d96e4df
L		 3072017-06-15 H.J. Lu <hongjiu.lu@intel.com>
308
309 PR binutils/21594
310 * i386-dis.c (OP_E_register): Check valid bnd register.
311 (OP_G): Likewise.
312
cd3ea7c6
NC		 3132017-06-15 Nick Clifton <nickc@redhat.com>
314
315 PR binutils/21595
316 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
317 range value.
318
63323b5b
NC		 3192017-06-15 Nick Clifton <nickc@redhat.com>
320
321 PR binutils/21588
322 * rl78-decode.opc (OP_BUF_LEN): Define.
323 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
324 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
325 array.
326 * rl78-decode.c: Regenerate.
327
08c7881b
NC		 3282017-06-15 Nick Clifton <nickc@redhat.com>
329
330 PR binutils/21586
331 * bfin-dis.c (gregs): Clip index to prevent overflow.
332 (regs): Likewise.
333 (regs_lo): Likewise.
334 (regs_hi): Likewise.
335
e64519d1
NC		 3362017-06-14 Nick Clifton <nickc@redhat.com>
337
338 PR binutils/21576
339 * score7-dis.c (score_opcodes): Add sentinel.
340
6394c606
YQ		 3412017-06-14 Yao Qi <yao.qi@linaro.org>
342
343 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
344 * arm-dis.c: Likewise.
345 * ia64-dis.c: Likewise.
346 * mips-dis.c: Likewise.
347 * spu-dis.c: Likewise.
348 * disassemble.h (print_insn_aarch64): New declaration, moved from
349 include/dis-asm.h.
350 (print_insn_big_arm, print_insn_big_mips): Likewise.
351 (print_insn_i386, print_insn_ia64): Likewise.
352 (print_insn_little_arm, print_insn_little_mips): Likewise.
353
db5fa770
NC		 3542017-06-14 Nick Clifton <nickc@redhat.com>
355
356 PR binutils/21587
357 * rx-decode.opc: Include libiberty.h
358 (GET_SCALE): New macro - validates access to SCALE array.
359 (GET_PSCALE): New macro - validates access to PSCALE array.
360 (DIs, SIs, S2Is, rx_disp): Use new macros.
361 * rx-decode.c: Regenerate.
362
05c966f3
AV		 3632017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
364
365 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
366
10045478
AK		 3672017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
368
369 * arc-dis.c (enforced_isa_mask): Declare.
370 (cpu_types): Likewise.
371 (parse_cpu_option): New function.
372 (parse_disassembler_options): Use it.
373 (print_insn_arc): Use enforced_isa_mask.
374 (print_arc_disassembler_options): Document new options.
375
88c1242d
YQ		 3762017-05-24 Yao Qi <yao.qi@linaro.org>
377
378 * alpha-dis.c: Include disassemble.h, don't include
379 dis-asm.h.
380 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
381 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
382 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
383 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
384 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
385 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
386 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
387 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
388 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
389 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
390 * moxie-dis.c, msp430-dis.c, mt-dis.c:
391 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
392 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
393 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
394 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
395 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
396 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
397 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
398 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
399 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
400 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
401 * z80-dis.c, z8k-dis.c: Likewise.
402 * disassemble.h: New file.
403
ab20fa4a
YQ		 4042017-05-24 Yao Qi <yao.qi@linaro.org>
405
406 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
407 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
408
003ca0fd
YQ		 4092017-05-24 Yao Qi <yao.qi@linaro.org>
410
411 * disassemble.c (disassembler): Add arguments a, big and mach.
412 Use them.
413
04ef582a
L		 4142017-05-22 H.J. Lu <hongjiu.lu@intel.com>
415
416 * i386-dis.c (NOTRACK_Fixup): New.
417 (NOTRACK): Likewise.
418 (NOTRACK_PREFIX): Likewise.
419 (last_active_prefix): Likewise.
420 (reg_table): Use NOTRACK on indirect call and jmp.
421 (ckprefix): Set last_active_prefix.
422 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
423 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
424 * i386-opc.h (NoTrackPrefixOk): New.
425 (i386_opcode_modifier): Add notrackprefixok.
426 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
427 Add notrack.
428 * i386-tbl.h: Regenerated.
429
64517994
JM		 4302017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
431
432 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
433 (X_IMM2): Define.
434 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
435 bfd_mach_sparc_v9m8.
436 (print_insn_sparc): Handle new operand types.
437 * sparc-opc.c (MASK_M8): Define.
438 (v6): Add MASK_M8.
439 (v6notlet): Likewise.
440 (v7): Likewise.
441 (v8): Likewise.
442 (v9): Likewise.
443 (v9a): Likewise.
444 (v9b): Likewise.
445 (v9c): Likewise.
446 (v9d): Likewise.
447 (v9e): Likewise.
448 (v9v): Likewise.
449 (v9m): Likewise.
450 (v9andleon): Likewise.
451 (m8): Define.
452 (HWS_VM8): Define.
453 (HWS2_VM8): Likewise.
454 (sparc_opcode_archs): Add entry for "m8".
455 (sparc_opcodes): Add OSA2017 and M8 instructions
456 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
457 fpx{ll,ra,rl}64x,
458 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
459 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
460 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
461 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
462 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
463 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
464 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
465 ASI_CORE_SELECT_COMMIT_NHT.
466
535b785f
AM		 4672017-05-18 Alan Modra <amodra@gmail.com>
468
469 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
470 * aarch64-dis.c: Likewise.
471 * aarch64-gen.c: Likewise.
472 * aarch64-opc.c: Likewise.
473
25499ac7
MR		 4742017-05-15 Maciej W. Rozycki <macro@imgtec.com>
475 Matthew Fortune <matthew.fortune@imgtec.com>
476
477 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
478 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
479 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
480 (print_insn_arg) <OP_REG28>: Add handler.
481 (validate_insn_args) <OP_REG28>: Handle.
482 (print_mips16_insn_arg): Handle MIPS16 instructions that require
483 32-bit encoding and 9-bit immediates.
484 (print_insn_mips16): Handle MIPS16 instructions that require
485 32-bit encoding and MFC0/MTC0 operand decoding.
486 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
487 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
488 (RD_C0, WR_C0, E2, E2MT): New macros.
489 (mips16_opcodes): Add entries for MIPS16e2 instructions:
490 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
491 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
492 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
493 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
494 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
495 instructions, "swl", "swr", "sync" and its "sync_acquire",
496 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
497 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
498 regular/extended entries for original MIPS16 ISA revision
499 instructions whose extended forms are subdecoded in the MIPS16e2
500 ISA revision: "li", "sll" and "srl".
501
fdfb4752
MR		 5022017-05-15 Maciej W. Rozycki <macro@imgtec.com>
503
504 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
505 reference in CP0 move operand decoding.
506
a4f89915
MR		 5072017-05-12 Maciej W. Rozycki <macro@imgtec.com>
508
509 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
510 type to hexadecimal.
511 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
512
99e2d67a
MR		 5132017-05-11 Maciej W. Rozycki <macro@imgtec.com>
514
515 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
516 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
517 "sync_rmb" and "sync_wmb" as aliases.
518 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
519 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
520
53a346d8
CZ		 5212017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
522
523 * arc-dis.c (parse_option): Update quarkse_em option..
524 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
525 QUARKSE1.
526 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
527
f91d48de
KC		 5282017-05-03 Kito Cheng <kito.cheng@gmail.com>
529
530 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
531
43e379d7
MC		 5322017-05-01 Michael Clark <michaeljclark@mac.com>
533
534 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
535 register.
536
a4ddc54e
MR		 5372017-05-02 Maciej W. Rozycki <macro@imgtec.com>
538
539 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
540 and branches and not synthetic data instructions.
541
fe50e98c
BE		 5422017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
543
544 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
545
126124cc
CZ		 5462017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
547
548 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
549 * arc-opc.c (insert_r13el): New function.
550 (R13_EL): Define.
551 * arc-tbl.h: Add new enter/leave variants.
552
be6a24d8
CZ		 5532017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
554
555 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
556
0348fd79
MR		 5572017-04-25 Maciej W. Rozycki <macro@imgtec.com>
558
559 * mips-dis.c (print_mips_disassembler_options): Add
560 `no-aliases'.
561
6e3d1f07
MR		 5622017-04-25 Maciej W. Rozycki <macro@imgtec.com>
563
564 * mips16-opc.c (AL): New macro.
565 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
566 of "ld" and "lw" as aliases.
567
957f6b39
TC		 5682017-04-24 Tamar Christina <tamar.christina@arm.com>
569
570 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
571 arguments.
572
a8cc8a54
AM		 5732017-04-22 Alexander Fedotov <alfedotov@gmail.com>
574 Alan Modra <amodra@gmail.com>
575
576 * ppc-opc.c (ELEV): Define.
577 (vle_opcodes): Add se_rfgi and e_sc.
578 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
579 for E200Z4.
580
3ab87b68
JM		 5812017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
582
583 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
584
792f174f
NC		 5852017-04-21 Nick Clifton <nickc@redhat.com>
586
587 PR binutils/21380
588 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
589 LD3R and LD4R.
590
42742084
AM		 5912017-04-13 Alan Modra <amodra@gmail.com>
592
593 * epiphany-desc.c: Regenerate.
594 * fr30-desc.c: Regenerate.
595 * frv-desc.c: Regenerate.
596 * ip2k-desc.c: Regenerate.
597 * iq2000-desc.c: Regenerate.
598 * lm32-desc.c: Regenerate.
599 * m32c-desc.c: Regenerate.
600 * m32r-desc.c: Regenerate.
601 * mep-desc.c: Regenerate.
602 * mt-desc.c: Regenerate.
603 * or1k-desc.c: Regenerate.
604 * xc16x-desc.c: Regenerate.
605 * xstormy16-desc.c: Regenerate.
606
9a85b496
AM		 6072017-04-11 Alan Modra <amodra@gmail.com>
608
ef85eab0 609 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 610 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
611 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 612 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
613 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 614 (PPCVSX2): Define as PPC_OPCODE_POWER8.
615 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 616 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 617 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 618
62adc510
AM		 6192017-04-10 Alan Modra <amodra@gmail.com>
620
621 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
622 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
623 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
624 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
625
aa808707
PC		 6262017-04-09 Pip Cet <pipcet@gmail.com>
627
628 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
629 appropriate floating-point precision directly.
630
ac8f0f72
AM		 6312017-04-07 Alan Modra <amodra@gmail.com>
632
633 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
634 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
635 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
636 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
637 vector instructions with E6500 not PPCVEC2.
638
62ecb94c
PC		 6392017-04-06 Pip Cet <pipcet@gmail.com>
640
641 * Makefile.am: Add wasm32-dis.c.
642 * configure.ac: Add wasm32-dis.c to wasm32 target.
643 * disassemble.c: Add wasm32 disassembler code.
644 * wasm32-dis.c: New file.
645 * Makefile.in: Regenerate.
646 * configure: Regenerate.
647 * po/POTFILES.in: Regenerate.
648 * po/opcodes.pot: Regenerate.
649
f995bbe8
PA		 6502017-04-05 Pedro Alves <palves@redhat.com>
651
652 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
653 * arm-dis.c (parse_arm_disassembler_options): Constify.
654 * ppc-dis.c (powerpc_init_dialect): Constify local.
655 * vax-dis.c (parse_disassembler_options): Constify.
656
b5292032
PD		 6572017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
658
659 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
660 RISCV_GP_SYMBOL.
661
f96bd6c2
PC		 6622017-03-30 Pip Cet <pipcet@gmail.com>
663
664 * configure.ac: Add (empty) bfd_wasm32_arch target.
665 * configure: Regenerate
666 * po/opcodes.pot: Regenerate.
667
f7c514a3
JM		 6682017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
669
670 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
671 OSA2015.
672 * opcodes/sparc-opc.c (asi_table): New ASIs.
673
52be03fd
AM		 6742017-03-29 Alan Modra <amodra@gmail.com>
675
676 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
677 "raw" option.
678 (lookup_powerpc): Don't special case -1 dialect. Handle
679 PPC_OPCODE_RAW.
680 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
681 lookup_powerpc call, pass it on second.
682
9b753937
AM		 6832017-03-27 Alan Modra <amodra@gmail.com>
684
685 PR 21303
686 * ppc-dis.c (struct ppc_mopt): Comment.
687 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
688
c0c31e91
RZ		 6892017-03-27 Rinat Zelig <rinat@mellanox.com>
690
691 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
692 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
693 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
694 (insert_nps_misc_imm_offset): New function.
695 (extract_nps_misc imm_offset): New function.
696 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
697 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
698
2253c8f0
AK		 6992017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
700
701 * s390-mkopc.c (main): Remove vx2 check.
702 * s390-opc.txt: Remove vx2 instruction flags.
703
645d3342
RZ		 7042017-03-21 Rinat Zelig <rinat@mellanox.com>
705
706 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
707 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
708 (insert_nps_imm_offset): New function.
709 (extract_nps_imm_offset): New function.
710 (insert_nps_imm_entry): New function.
711 (extract_nps_imm_entry): New function.
712
4b94dd2d
AM		 7132017-03-17 Alan Modra <amodra@gmail.com>
714
715 PR 21248
716 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
717 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
718 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
719
b416fe87
KC		 7202017-03-14 Kito Cheng <kito.cheng@gmail.com>
721
722 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
723 <c.andi>: Likewise.
724 <c.addiw> Likewise.
725
03b039a5
KC		 7262017-03-14 Kito Cheng <kito.cheng@gmail.com>
727
728 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
729
2c232b83
AW		 7302017-03-13 Andrew Waterman <andrew@sifive.com>
731
732 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
733 <srl> Likewise.
734 <srai> Likewise.
735 <sra> Likewise.
736
86fa6981
L		 7372017-03-09 H.J. Lu <hongjiu.lu@intel.com>
738
739 * i386-gen.c (opcode_modifiers): Replace S with Load.
740 * i386-opc.h (S): Removed.
741 (Load): New.
742 (i386_opcode_modifier): Replace s with load.
743 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
744 and {evex}. Replace S with Load.
745 * i386-tbl.h: Regenerated.
746
c1fe188b
L		 7472017-03-09 H.J. Lu <hongjiu.lu@intel.com>
748
749 * i386-opc.tbl: Use CpuCET on rdsspq.
750 * i386-tbl.h: Regenerated.
751
4b8b687e
PB		 7522017-03-08 Peter Bergner <bergner@vnet.ibm.com>
753
754 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
755 <vsx>: Do not use PPC_OPCODE_VSX3;
756
1437d063
PB		 7572017-03-08 Peter Bergner <bergner@vnet.ibm.com>
758
759 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
760
603555e5
L		 7612017-03-06 H.J. Lu <hongjiu.lu@intel.com>
762
763 * i386-dis.c (REG_0F1E_MOD_3): New enum.
764 (MOD_0F1E_PREFIX_1): Likewise.
765 (MOD_0F38F5_PREFIX_2): Likewise.
766 (MOD_0F38F6_PREFIX_0): Likewise.
767 (RM_0F1E_MOD_3_REG_7): Likewise.
768 (PREFIX_MOD_0_0F01_REG_5): Likewise.
769 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
770 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
771 (PREFIX_0F1E): Likewise.
772 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
773 (PREFIX_0F38F5): Likewise.
774 (dis386_twobyte): Use PREFIX_0F1E.
775 (reg_table): Add REG_0F1E_MOD_3.
776 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
777 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
778 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
779 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
780 (three_byte_table): Use PREFIX_0F38F5.
781 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
782 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
783 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
784 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
785 PREFIX_MOD_3_0F01_REG_5_RM_2.
786 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
787 (cpu_flags): Add CpuCET.
788 * i386-opc.h (CpuCET): New enum.
789 (CpuUnused): Commented out.
790 (i386_cpu_flags): Add cpucet.
791 * i386-opc.tbl: Add Intel CET instructions.
792 * i386-init.h: Regenerated.
793 * i386-tbl.h: Likewise.
794
73f07bff
AM		 7952017-03-06 Alan Modra <amodra@gmail.com>
796
797 PR 21124
798 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
799 (extract_raq, extract_ras, extract_rbx): New functions.
800 (powerpc_operands): Use opposite corresponding insert function.
801 (Q_MASK): Define.
802 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
803 register restriction.
804
65b48a81
PB		 8052017-02-28 Peter Bergner <bergner@vnet.ibm.com>
806
807 * disassemble.c Include "safe-ctype.h".
808 (disassemble_init_for_target): Handle s390 init.
809 (remove_whitespace_and_extra_commas): New function.
810 (disassembler_options_cmp): Likewise.
811 * arm-dis.c: Include "libiberty.h".
812 (NUM_ELEM): Delete.
813 (regnames): Use long disassembler style names.
814 Add force-thumb and no-force-thumb options.
815 (NUM_ARM_REGNAMES): Rename from this...
816 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
817 (get_arm_regname_num_options): Delete.
818 (set_arm_regname_option): Likewise.
819 (get_arm_regnames): Likewise.
820 (parse_disassembler_options): Likewise.
821 (parse_arm_disassembler_option): Rename from this...
822 (parse_arm_disassembler_options): ...to this. Make static.
823 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
824 (print_insn): Use parse_arm_disassembler_options.
825 (disassembler_options_arm): New function.
826 (print_arm_disassembler_options): Handle updated regnames.
827 * ppc-dis.c: Include "libiberty.h".
828 (ppc_opts): Add "32" and "64" entries.
829 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
830 (powerpc_init_dialect): Add break to switch statement.
831 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
832 (disassembler_options_powerpc): New function.
833 (print_ppc_disassembler_options): Use ARRAY_SIZE.
834 Remove printing of "32" and "64".
835 * s390-dis.c: Include "libiberty.h".
836 (init_flag): Remove unneeded variable.
837 (struct s390_options_t): New structure type.
838 (options): New structure.
839 (init_disasm): Rename from this...
840 (disassemble_init_s390): ...to this. Add initializations for
841 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
842 (print_insn_s390): Delete call to init_disasm.
843 (disassembler_options_s390): New function.
844 (print_s390_disassembler_options): Print using information from
845 struct 'options'.
846 * po/opcodes.pot: Regenerate.
847
15c7c1d8
JB		 8482017-02-28 Jan Beulich <jbeulich@suse.com>
849
850 * i386-dis.c (PCMPESTR_Fixup): New.
851 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
852 (prefix_table): Use PCMPESTR_Fixup.
853 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
854 PCMPESTR_Fixup.
855 (vex_w_table): Delete VPCMPESTR{I,M} entries.
856 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
857 Split 64-bit and non-64-bit variants.
858 * opcodes/i386-tbl.h: Re-generate.
859
582e12bf
RS		 8602017-02-24 Richard Sandiford <richard.sandiford@arm.com>
861
862 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
863 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
864 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
865 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
866 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
867 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
868 (OP_SVE_V_HSD): New macros.
869 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
870 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
871 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
872 (aarch64_opcode_table): Add new SVE instructions.
873 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
874 for rotation operands. Add new SVE operands.
875 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
876 (ins_sve_quad_index): Likewise.
877 (ins_imm_rotate): Split into...
878 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
879 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
880 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
881 functions.
882 (aarch64_ins_sve_addr_ri_s4): New function.
883 (aarch64_ins_sve_quad_index): Likewise.
884 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
885 * aarch64-asm-2.c: Regenerate.
886 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
887 (ext_sve_quad_index): Likewise.
888 (ext_imm_rotate): Split into...
889 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
890 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
891 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
892 functions.
893 (aarch64_ext_sve_addr_ri_s4): New function.
894 (aarch64_ext_sve_quad_index): Likewise.
895 (aarch64_ext_sve_index): Allow quad indices.
896 (do_misc_decoding): Likewise.
897 * aarch64-dis-2.c: Regenerate.
898 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
899 aarch64_field_kinds.
900 (OPD_F_OD_MASK): Widen by one bit.
901 (OPD_F_NO_ZR): Bump accordingly.
902 (get_operand_field_width): New function.
903 * aarch64-opc.c (fields): Add new SVE fields.
904 (operand_general_constraint_met_p): Handle new SVE operands.
905 (aarch64_print_operand): Likewise.
906 * aarch64-opc-2.c: Regenerate.
907
f482d304
RS		 9082017-02-24 Richard Sandiford <richard.sandiford@arm.com>
909
910 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
911 (aarch64_feature_compnum): ...this.
912 (SIMD_V8_3): Replace with...
913 (COMPNUM): ...this.
914 (CNUM_INSN): New macro.
915 (aarch64_opcode_table): Use it for the complex number instructions.
916
7db2c588
JB		 9172017-02-24 Jan Beulich <jbeulich@suse.com>
918
919 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
920
1e9d41d4
SL		 9212017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
922
923 Add support for associating SPARC ASIs with an architecture level.
924 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
925 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
926 decoding of SPARC ASIs.
927
53c4d625
JB		 9282017-02-23 Jan Beulich <jbeulich@suse.com>
929
930 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
931 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
932
11648de5
JB		 9332017-02-21 Jan Beulich <jbeulich@suse.com>
934
935 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
936 1 (instead of to itself). Correct typo.
937
f98d33be
AW		 9382017-02-14 Andrew Waterman <andrew@sifive.com>
939
940 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
941 pseudoinstructions.
942
773fb663
RS		 9432017-02-15 Richard Sandiford <richard.sandiford@arm.com>
944
945 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
946 (aarch64_sys_reg_supported_p): Handle them.
947
cc07cda6
CZ		 9482017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
949
950 * arc-opc.c (UIMM6_20R): Define.
951 (SIMM12_20): Use above.
952 (SIMM12_20R): Define.
953 (SIMM3_5_S): Use above.
954 (UIMM7_A32_11R_S): Define.
955 (UIMM7_9_S): Use above.
956 (UIMM3_13R_S): Define.
957 (SIMM11_A32_7_S): Use above.
958 (SIMM9_8R): Define.
959 (UIMM10_A32_8_S): Use above.
960 (UIMM8_8R_S): Define.
961 (W6): Use above.
962 (arc_relax_opcodes): Use all above defines.
963
66a5a740
VG		 9642017-02-15 Vineet Gupta <vgupta@synopsys.com>
965
966 * arc-regs.h: Distinguish some of the registers different on
967 ARC700 and HS38 cpus.
968
7e0de605
AM		 9692017-02-14 Alan Modra <amodra@gmail.com>
970
971 PR 21118
972 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
973 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
974
54064fdb
AM		 9752017-02-11 Stafford Horne <shorne@gmail.com>
976 Alan Modra <amodra@gmail.com>
977
978 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
979 Use insn_bytes_value and insn_int_value directly instead. Don't
980 free allocated memory until function exit.
981
dce75bf9
NP		 9822017-02-10 Nicholas Piggin <npiggin@gmail.com>
983
984 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
985
1b7e3d2f
NC		 9862017-02-03 Nick Clifton <nickc@redhat.com>
987
988 PR 21096
989 * aarch64-opc.c (print_register_list): Ensure that the register
990 list index will fir into the tb buffer.
991 (print_register_offset_address): Likewise.
992 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
993
8ec5cf65
AD		 9942017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
995
996 PR 21056
997 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
998 instructions when the previous fetch packet ends with a 32-bit
999 instruction.
1000
a1aa5e81
DD		 10012017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1002
1003 * pru-opc.c: Remove vague reference to a future GDB port.
1004
add3afb2
NC		 10052017-01-20 Nick Clifton <nickc@redhat.com>
1006
1007 * po/ga.po: Updated Irish translation.
1008
c13a63b0
SN		 10092017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1010
1011 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1012
9608051a
YQ		 10132017-01-13 Yao Qi <yao.qi@linaro.org>
1014
1015 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1016 if FETCH_DATA returns 0.
1017 (m68k_scan_mask): Likewise.
1018 (print_insn_m68k): Update code to handle -1 return value.
1019
f622ea96
YQ		 10202017-01-13 Yao Qi <yao.qi@linaro.org>
1021
1022 * m68k-dis.c (enum print_insn_arg_error): New.
1023 (NEXTBYTE): Replace -3 with
1024 PRINT_INSN_ARG_MEMORY_ERROR.
1025 (NEXTULONG): Likewise.
1026 (NEXTSINGLE): Likewise.
1027 (NEXTDOUBLE): Likewise.
1028 (NEXTDOUBLE): Likewise.
1029 (NEXTPACKED): Likewise.
1030 (FETCH_ARG): Likewise.
1031 (FETCH_DATA): Update comments.
1032 (print_insn_arg): Update comments. Replace magic numbers with
1033 enum.
1034 (match_insn_m68k): Likewise.
1035
620214f7
IT		 10362017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1037
1038 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1039 * i386-dis-evex.h (evex_table): Updated.
1040 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1041 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1042 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1043 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1044 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1045 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1046 * i386-init.h: Regenerate.
1047 * i386-tbl.h: Ditto.
1048
d95014a2
YQ		 10492017-01-12 Yao Qi <yao.qi@linaro.org>
1050
1051 * msp430-dis.c (msp430_singleoperand): Return -1 if
1052 msp430dis_opcode_signed returns false.
1053 (msp430_doubleoperand): Likewise.
1054 (msp430_branchinstr): Return -1 if
1055 msp430dis_opcode_unsigned returns false.
1056 (msp430x_calla_instr): Likewise.
1057 (print_insn_msp430): Likewise.
1058
0ae60c3e
NC		 10592017-01-05 Nick Clifton <nickc@redhat.com>
1060
1061 PR 20946
1062 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1063 could not be matched.
1064 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1065 NULL.
1066
d74d4880
SN		 10672017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1068
1069 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1070 (aarch64_opcode_table): Use RCPC_INSN.
1071
cc917fd9
KC		 10722017-01-03 Kito Cheng <kito.cheng@gmail.com>
1073
1074 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1075 extension.
1076 * riscv-opcodes/all-opcodes: Likewise.
1077
b52d3cfc
DP		 10782017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1079
1080 * riscv-dis.c (print_insn_args): Add fall through comment.
1081
f90c58d5
NC		 10822017-01-03 Nick Clifton <nickc@redhat.com>
1083
1084 * po/sr.po: New Serbian translation.
1085 * configure.ac (ALL_LINGUAS): Add sr.
1086 * configure: Regenerate.
1087
f47b0d4a
AM		 10882017-01-02 Alan Modra <amodra@gmail.com>
1089
1090 * epiphany-desc.h: Regenerate.
1091 * epiphany-opc.h: Regenerate.
1092 * fr30-desc.h: Regenerate.
1093 * fr30-opc.h: Regenerate.
1094 * frv-desc.h: Regenerate.
1095 * frv-opc.h: Regenerate.
1096 * ip2k-desc.h: Regenerate.
1097 * ip2k-opc.h: Regenerate.
1098 * iq2000-desc.h: Regenerate.
1099 * iq2000-opc.h: Regenerate.
1100 * lm32-desc.h: Regenerate.
1101 * lm32-opc.h: Regenerate.
1102 * m32c-desc.h: Regenerate.
1103 * m32c-opc.h: Regenerate.
1104 * m32r-desc.h: Regenerate.
1105 * m32r-opc.h: Regenerate.
1106 * mep-desc.h: Regenerate.
1107 * mep-opc.h: Regenerate.
1108 * mt-desc.h: Regenerate.
1109 * mt-opc.h: Regenerate.
1110 * or1k-desc.h: Regenerate.
1111 * or1k-opc.h: Regenerate.
1112 * xc16x-desc.h: Regenerate.
1113 * xc16x-opc.h: Regenerate.
1114 * xstormy16-desc.h: Regenerate.
1115 * xstormy16-opc.h: Regenerate.
1116
2571583a
AM		 11172017-01-02 Alan Modra <amodra@gmail.com>
1118
1119 Update year range in copyright notice of all files.
1120
5c1ad6b5 1121For older changes see ChangeLog-2016
3499769a 1122\f
5c1ad6b5 1123Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1124
1125Copying and distribution of this file, with or without modification,
1126are permitted in any medium without royalty provided the copyright
1127notice and this notice are preserved.
1128
1129Local Variables:
1130mode: change-log
1131left-margin: 8
1132fill-column: 74
1133version-control: never
1134End:
GDB Binutils - Deliverables
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