RISC-V: Disassemble x0 based addresses as 0.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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12018-01-09 Jim Wilson <jimw@sifive.com>
2
3 * riscv-dis.c (maybe_print_address): If base_reg is zero,
4 then the hi_addr value is zero.
5
91d8b670
JG
62018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
7
8 * arm-dis.c (arm_opcodes): Add csdb.
9 (thumb32_opcodes): Add csdb.
10
be2e7d95
JG
112018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
12
13 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
14 * aarch64-asm-2.c: Regenerate.
15 * aarch64-dis-2.c: Regenerate.
16 * aarch64-opc-2.c: Regenerate.
17
704a705d
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182018-01-08 H.J. Lu <hongjiu.lu@intel.com>
19
20 PR gas/22681
21 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
22 Remove AVX512 vmovd with 64-bit operands.
23 * i386-tbl.h: Regenerated.
24
35eeb78f
JW
252018-01-05 Jim Wilson <jimw@sifive.com>
26
27 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
28 jalr.
29
219d1afa
AM
302018-01-03 Alan Modra <amodra@gmail.com>
31
32 Update year range in copyright notice of all files.
33
1508bbf5
JB
342018-01-02 Jan Beulich <jbeulich@suse.com>
35
36 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
37 and OPERAND_TYPE_REGZMM entries.
38
1e563868 39For older changes see ChangeLog-2017
3499769a 40\f
1e563868 41Copyright (C) 2018 Free Software Foundation, Inc.
3499769a
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42
43Copying and distribution of this file, with or without modification,
44are permitted in any medium without royalty provided the copyright
45notice and this notice are preserved.
46
47Local Variables:
48mode: change-log
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