projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 26d97720 NS |
1 | 2011-06-02 Jie Zhang <jie@codesourcery.com> |
| 2 | Nathan Sidwell <nathan@codesourcery.com> | |
| 3 | Maciej Rozycki <macro@codesourcery.com> | |
| 4 | ||
| 5 | * arm-dis.c (print_insn_coprocessor): Explicitly print #-0 | |
| 6 | as address offset. | |
| 7 | (print_arm_address): Likewise. Elide positive #0 appropriately. | |
| 8 | (print_insn_arm): Likewise. | |
| 9 | ||
| cc643b88 NC |
10 | 2011-06-02 Nick Clifton <nickc@redhat.com> |
| 11 | ||
| 12 | * arm-dis.c: Fix spelling mistakes. | |
| 13 | * op/opcodes.pot: Regenerate. | |
| 14 | ||
| c8fa16ed AK |
15 | 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
| 16 | ||
| 17 | * s390-opc.c: Replace S390_OPERAND_REG_EVEN with | |
| 18 | S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type. | |
| 19 | * s390-opc.txt: Fix cxr instruction type. | |
| 20 | ||
| 5e4b319c AK |
21 | 2011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com> |
| 22 | ||
| 23 | * s390-opc.c: Add new instruction types marking register pair | |
| 24 | operands. | |
| 25 | * s390-opc.txt: Match instructions having register pair operands | |
| 26 | to the new instruction types. | |
| 27 | ||
| fda544a2 NC |
28 | 2011-05-19 Nick Clifton <nickc@redhat.com> |
| 29 | ||
| 30 | * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2 | |
| 31 | operands. | |
| 32 | ||
| 4cab4add QN |
33 | 2011-05-10 Quentin Neill <quentin.neill@amd.com> |
| 34 | ||
| 35 | * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS. | |
| 36 | * i386-init.h: Regenerated. | |
| 37 | ||
| b4e7b885 NC |
38 | 2011-04-27 Nick Clifton <nickc@redhat.com> |
| 39 | ||
| 40 | * po/da.po: Updated Danish translation. | |
| 41 | ||
| 2f7f7710 AM |
42 | 2011-04-26 Anton Blanchard <anton@samba.org> |
| 43 | ||
| 44 | * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7. | |
| 45 | ||
| 9887672f DD |
46 | 2011-04-21 DJ Delorie <dj@redhat.com> |
| 47 | ||
| 48 | * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs. | |
| 49 | * rx-decode.c: Regenerate. | |
| 50 | ||
| 3251b375 L |
51 | 2011-04-20 H.J. Lu <hongjiu.lu@intel.com> |
| 52 | ||
| 53 | * i386-init.h: Regenerated. | |
| 54 | ||
| b13a3ca6 QN |
55 | 2011-04-19 Quentin Neill <quentin.neill@amd.com> |
| 56 | ||
| 57 | * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits | |
| 58 | from bdver1 flags. | |
| 59 | ||
| 7d063384 NC |
60 | 2011-04-13 Nick Clifton <nickc@redhat.com> |
| 61 | ||
| 62 | * v850-dis.c (disassemble): Always print a closing square brace if | |
| 63 | an opening square brace was printed. | |
| 64 | ||
| 32a94698 NC |
65 | 2011-04-12 Nick Clifton <nickc@redhat.com> |
| 66 | ||
| 67 | PR binutils/12534 | |
| 68 | * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn | |
| 69 | patterns. | |
| 70 | (print_insn_thumb32): Handle %L. | |
| 71 | ||
| d2cd1205 JB |
72 | 2011-04-11 Julian Brown <julian@codesourcery.com> |
| 73 | ||
| 74 | * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX. | |
| 75 | (print_insn_thumb32): Add APSR bitmask support. | |
| 76 | ||
| 1fbaefec PB |
77 | 2011-04-07 Paul Carroll<pcarroll@codesourcery.com> |
| 78 | ||
| 79 | * arm-dis.c (print_insn): init vars moved into private_data structure. | |
| 80 | ||
| 67171547 MF |
81 | 2011-03-24 Mike Frysinger <vapier@gentoo.org> |
| 82 | ||
| 83 | * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic. | |
| 84 | ||
| 8cc66334 EW |
85 | 2011-03-22 Eric B. Weddington <eric.weddington@atmel.com> |
| 86 | ||
| 87 | * avr-dis.c (avr_operand): Add opcode_str parameter. Check for | |
| 88 | post-increment to support LPM Z+ instruction. Add support for 'E' | |
| 89 | constraint for DES instruction. | |
| 90 | (print_insn_avr): Adjust calls to avr_operand. Rename variable. | |
| 91 | ||
| 34e77a92 RS |
92 | 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org> |
| 93 | ||
| 94 | * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code. | |
| 95 | ||
| 35fc36a8 RS |
96 | 2011-03-14 Richard Sandiford <richard.sandiford@linaro.org> |
| 97 | ||
| 98 | * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC. | |
| 99 | Use branch types instead. | |
| 100 | (print_insn): Likewise. | |
| 101 | ||
| 0067d8fc MR |
102 | 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com> |
| 103 | ||
| 104 | * mips-opc.c (mips_builtin_opcodes): Correct register use | |
| 105 | annotation of "alnv.ps". | |
| 106 | ||
| 3eebd5eb MR |
107 | 2011-02-28 Maciej W. Rozycki <macro@codesourcery.com> |
| 108 | ||
| 109 | * mips-opc.c (mips_builtin_opcodes): Add "pref" macro. | |
| 110 | ||
| 500cccad MF |
111 | 2011-02-22 Mike Frysinger <vapier@gentoo.org> |
| 112 | ||
| 113 | * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check. | |
| 114 | ||
| f5caf9f4 MF |
115 | 2011-02-22 Mike Frysinger <vapier@gentoo.org> |
| 116 | ||
| 117 | * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS. | |
| 118 | ||
| e5bc4265 MF |
119 | 2011-02-19 Mike Frysinger <vapier@gentoo.org> |
| 120 | ||
| 121 | * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and | |
| 122 | a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1, | |
| 123 | av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts, | |
| 124 | exception, end_of_registers, msize, memory, bfd_mach. | |
| 125 | (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG, | |
| 126 | LB0REG, LC1REG, LT1REG, LB1REG): Delete | |
| 127 | (AXREG, AWREG, LCREG, LTREG, LBREG): Define. | |
| 128 | (get_allreg): Change to new defines. Fallback to abort(). | |
| 129 | ||
| 602427c4 MF |
130 | 2011-02-14 Mike Frysinger <vapier@gentoo.org> |
| 131 | ||
| 132 | * bfin-dis.c: Add whitespace/parenthesis where needed. | |
| 133 | ||
| 298c1ec2 MF |
134 | 2011-02-14 Mike Frysinger <vapier@gentoo.org> |
| 135 | ||
| 136 | * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater | |
| 137 | than 7. | |
| 138 | ||
| 822ce8ee RW |
139 | 2011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de> |
| 140 | ||
| 141 | * configure: Regenerate. | |
| 142 | ||
| 13c02f06 MF |
143 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
| 144 | ||
| 145 | * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg. | |
| 146 | ||
| 4db66394 MF |
147 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
| 148 | ||
| 149 | * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output | |
| 150 | dregs only when P is set, and dregs_lo otherwise. | |
| 151 | ||
| 36f44611 MF |
152 | 2011-02-13 Mike Frysinger <vapier@gentoo.org> |
| 153 | ||
| 154 | * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code. | |
| 155 | ||
| 9805c0a5 MF |
156 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
| 157 | ||
| 158 | * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT. | |
| 159 | ||
| 43a6aa65 MF |
160 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
| 161 | ||
| 162 | * bfin-dis.c (machine_registers): Delete REG_GP. | |
| 163 | (reg_names): Delete "GP". | |
| 164 | (decode_allregs): Change REG_GP to REG_LASTREG. | |
| 165 | ||
| 26bb3ddd MF |
166 | 2011-02-12 Mike Frysinger <vapier@gentoo.org> |
| 167 | ||
| 89c0d58c MR |
168 | * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2, |
| 169 | M_IH, M_IU): Delete. | |
| 26bb3ddd | 170 | |
| 69b8ea4a MF |
171 | 2011-02-11 Mike Frysinger <vapier@gentoo.org> |
| 172 | ||
| 173 | * bfin-dis.c (reg_names): Add const. | |
| 174 | (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte, | |
| 175 | decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs, | |
| 176 | decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits, | |
| 177 | decode_counters, decode_allregs): Likewise. | |
| 178 | ||
| 42d5f9c6 MS |
179 | 2011-02-09 Michael Snyder <msnyder@vmware.com> |
| 180 | ||
| 181 | * i386-dis.c (OP_J): Parenthesize expression to prevent | |
| 182 | truncated addresses. | |
| 183 | (print_insn): Fix indentation off-by-one. | |
| 184 | ||
| 4be0c941 NC |
185 | 2011-02-01 Nick Clifton <nickc@redhat.com> |
| 186 | ||
| 187 | * po/da.po: Updated Danish translation. | |
| 188 | ||
| 6b069ee7 AM |
189 | 2011-01-21 Dave Murphy <davem@devkitpro.org> |
| 190 | ||
| 191 | * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS. | |
| 192 | ||
| e3949f17 L |
193 | 2011-01-18 H.J. Lu <hongjiu.lu@intel.com> |
| 194 | ||
| 195 | * i386-dis.c (sIbT): New. | |
| 196 | (b_T_mode): Likewise. | |
| 197 | (dis386): Replace sIb with sIbT on "pushT". | |
| 198 | (x86_64_table): Replace sIb with Ib on "aam" and "aad". | |
| 199 | (OP_sI): Handle b_T_mode. Properly sign-extend byte. | |
| 200 | ||
| 752573b2 JK |
201 | 2011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com> |
| 202 | ||
| 203 | * i386-init.h: Regenerated. | |
| 204 | * i386-tbl.h: Regenerated | |
| 205 | ||
| 2a2a0f38 QN |
206 | 2011-01-17 Quentin Neill <quentin.neill@amd.com> |
| 207 | ||
| 208 | * i386-dis.c (REG_XOP_TBM_01): New. | |
| 209 | (REG_XOP_TBM_02): New. | |
| 210 | (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables. | |
| 211 | (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02 | |
| 212 | entries, and add bextr instruction. | |
| 213 | ||
| 214 | * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM. | |
| 215 | (cpu_flags): Add CpuTBM. | |
| 216 | ||
| 217 | * i386-opc.h (CpuTBM) New. | |
| 218 | (i386_cpu_flags): Add bit cputbm. | |
| 219 | ||
| 220 | * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk, | |
| 221 | blcs, blsfill, blsic, t1mskc, and tzmsk. | |
| 222 | ||
| 90d6ff62 DD |
223 | 2011-01-12 DJ Delorie <dj@redhat.com> |
| 224 | ||
| 225 | * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg. | |
| 226 | ||
| c95354ed MX |
227 | 2011-01-11 Mingjie Xing <mingjie.xing@gmail.com> |
| 228 | ||
| 229 | * mips-dis.c (print_insn_args): Adjust the value to print the real | |
| 230 | offset for "+c" argument. | |
| 231 | ||
| f7465604 NC |
232 | 2011-01-10 Nick Clifton <nickc@redhat.com> |
| 233 | ||
| 234 | * po/da.po: Updated Danish translation. | |
| 235 | ||
| 639e30d2 NS |
236 | 2011-01-05 Nathan Sidwell <nathan@codesourcery.com> |
| 237 | ||
| 238 | * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear. | |
| 239 | ||
| f12dc422 L |
240 | 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> |
| 241 | ||
| 242 | * i386-dis.c (REG_VEX_38F3): New. | |
| 243 | (PREFIX_0FBC): Likewise. | |
| 244 | (PREFIX_VEX_38F2): Likewise. | |
| 245 | (PREFIX_VEX_38F3_REG_1): Likewise. | |
| 246 | (PREFIX_VEX_38F3_REG_2): Likewise. | |
| 247 | (PREFIX_VEX_38F3_REG_3): Likewise. | |
| 248 | (PREFIX_VEX_38F7): Likewise. | |
| 249 | (VEX_LEN_38F2_P_0): Likewise. | |
| 250 | (VEX_LEN_38F3_R_1_P_0): Likewise. | |
| 251 | (VEX_LEN_38F3_R_2_P_0): Likewise. | |
| 252 | (VEX_LEN_38F3_R_3_P_0): Likewise. | |
| 253 | (VEX_LEN_38F7_P_0): Likewise. | |
| 254 | (dis386_twobyte): Use PREFIX_0FBC. | |
| 255 | (reg_table): Add REG_VEX_38F3. | |
| 256 | (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2, | |
| 257 | PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2, | |
| 258 | PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7. | |
| 259 | (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and | |
| 260 | PREFIX_VEX_38F7. | |
| 261 | (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0, | |
| 262 | VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and | |
| 263 | VEX_LEN_38F7_P_0. | |
| 264 | ||
| 265 | * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS. | |
| 266 | (cpu_flags): Add CpuBMI. | |
| 267 | ||
| 268 | * i386-opc.h (CpuBMI): New. | |
| 269 | (i386_cpu_flags): Add cpubmi. | |
| 270 | ||
| 271 | * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt. | |
| 272 | * i386-init.h: Regenerated. | |
| 273 | * i386-tbl.h: Likewise. | |
| 274 | ||
| cb21baef L |
275 | 2011-01-04 H.J. Lu <hongjiu.lu@intel.com> |
| 276 | ||
| 277 | * i386-dis.c (VexGdq): New. | |
| 278 | (OP_VEX): Handle dq_mode. | |
| 279 | ||
| 0db46eb4 L |
280 | 2011-01-01 H.J. Lu <hongjiu.lu@intel.com> |
| 281 | ||
| 282 | * i386-gen.c (process_copyright): Update copyright to 2011. | |
| 283 | ||
| 9e9e0820 | 284 | For older changes see ChangeLog-2010 |
| 252b5132 RH |
285 | \f |
| 286 | Local Variables: | |
| 2f6d2f85 NC |
287 | mode: change-log |
| 288 | left-margin: 8 | |
| 289 | fill-column: 74 | |
| 252b5132 RH |
290 | version-control: never |
| 291 | End: |