projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| bcc5a6eb NC |
1 | 2019-06-14 Nick Clifton <nickc@redhat.com> |
| 2 | ||
| 3 | * po/fr.po; Updated French translation. | |
| 4 | ||
| e4c4ac46 SH |
5 | 2019-06-13 Stafford Horne <shorne@gmail.com> |
| 6 | ||
| 7 | * or1k-asm.c: Regenerated. | |
| 8 | * or1k-desc.c: Regenerated. | |
| 9 | * or1k-desc.h: Regenerated. | |
| 10 | * or1k-dis.c: Regenerated. | |
| 11 | * or1k-ibld.c: Regenerated. | |
| 12 | * or1k-opc.c: Regenerated. | |
| 13 | * or1k-opc.h: Regenerated. | |
| 14 | * or1k-opinst.c: Regenerated. | |
| 15 | ||
| a0e44ef5 PB |
16 | 2019-06-12 Peter Bergner <bergner@linux.ibm.com> |
| 17 | ||
| 18 | * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic. | |
| 19 | ||
| 12efd68d L |
20 | 2019-06-05 H.J. Lu <hongjiu.lu@intel.com> |
| 21 | ||
| 22 | PR binutils/24633 | |
| 23 | * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2, | |
| 24 | EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2. | |
| 25 | (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0, | |
| 26 | EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0, | |
| 27 | EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0, | |
| 28 | EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0, | |
| 29 | EVEX_LEN_0F3A1B_P_2_W_1. | |
| 30 | * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum. | |
| 31 | (EVEX_LEN_0F3A18_P_2_W_1): Likewise. | |
| 32 | (EVEX_LEN_0F3A19_P_2_W_0): Likewise. | |
| 33 | (EVEX_LEN_0F3A19_P_2_W_1): Likewise. | |
| 34 | (EVEX_LEN_0F3A1A_P_2_W_0): Likewise. | |
| 35 | (EVEX_LEN_0F3A1A_P_2_W_1): Likewise. | |
| 36 | (EVEX_LEN_0F3A1B_P_2_W_0): Likewise. | |
| 37 | (EVEX_LEN_0F3A1B_P_2_W_1): Likewise. | |
| 38 | ||
| 63c6fc6c L |
39 | 2019-06-04 H.J. Lu <hongjiu.lu@intel.com> |
| 40 | ||
| 41 | PR binutils/24626 | |
| 42 | * i386-dis.c (print_insn): Check for unused VEX.vvvv and | |
| 43 | EVEX.vvvv when disassembling VEX and EVEX instructions. | |
| 44 | (OP_VEX): Set vex.register_specifier to 0 after readding | |
| 45 | vex.register_specifier. | |
| 46 | (OP_Vex_2src_1): Likewise. | |
| 47 | (OP_Vex_2src_2): Likewise. | |
| 48 | (OP_LWP_E): Likewise. | |
| 49 | (OP_EX_Vex): Don't check vex.register_specifier. | |
| 50 | (OP_XMM_Vex): Likewise. | |
| 51 | ||
| 9186c494 L |
52 | 2019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 53 | Lili Cui <lili.cui@intel.com> | |
| 54 | ||
| 55 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3. | |
| 56 | * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT | |
| 57 | instructions. | |
| 58 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS, | |
| 59 | CPU_ANY_AVX512_VP2INTERSECT_FLAGS. | |
| 60 | (cpu_flags): Add CpuAVX512_VP2INTERSECT. | |
| 61 | * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT. | |
| 62 | (i386_cpu_flags): Add cpuavx512_vp2intersect. | |
| 63 | * i386-opc.tbl: Add AVX512_VP2INTERSECT insns. | |
| 64 | * i386-init.h: Regenerated. | |
| 65 | * i386-tbl.h: Likewise. | |
| 66 | ||
| 5d79adc4 L |
67 | 2019-06-04 Xuepeng Guo <xuepeng.guo@intel.com> |
| 68 | Lili Cui <lili.cui@intel.com> | |
| 69 | ||
| 70 | * doc/c-i386.texi: Document enqcmd. | |
| 71 | * testsuite/gas/i386/enqcmd-intel.d: New file. | |
| 72 | * testsuite/gas/i386/enqcmd-inval.l: Likewise. | |
| 73 | * testsuite/gas/i386/enqcmd-inval.s: Likewise. | |
| 74 | * testsuite/gas/i386/enqcmd.d: Likewise. | |
| 75 | * testsuite/gas/i386/enqcmd.s: Likewise. | |
| 76 | * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise. | |
| 77 | * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise. | |
| 78 | * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise. | |
| 79 | * testsuite/gas/i386/x86-64-enqcmd.d: Likewise. | |
| 80 | * testsuite/gas/i386/x86-64-enqcmd.s: Likewise. | |
| 81 | * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval, | |
| 82 | enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval, | |
| 83 | and x86-64-enqcmd. | |
| 84 | ||
| a9d96ab9 AH |
85 | 2019-06-04 Alan Hayward <alan.hayward@arm.com> |
| 86 | ||
| 87 | * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis. | |
| 88 | ||
| 4f6d070a AM |
89 | 2019-06-03 Alan Modra <amodra@gmail.com> |
| 90 | ||
| 91 | * ppc-dis.c (prefix_opcd_indices): Correct size. | |
| 92 | ||
| a2f4b66c L |
93 | 2019-05-28 H.J. Lu <hongjiu.lu@intel.com> |
| 94 | ||
| 95 | PR gas/24625 | |
| 96 | * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with | |
| 97 | Disp8ShiftVL. | |
| 98 | * i386-tbl.h: Regenerated. | |
| 99 | ||
| 405b5bd8 AM |
100 | 2019-05-24 Alan Modra <amodra@gmail.com> |
| 101 | ||
| 102 | * po/POTFILES.in: Regenerate. | |
| 103 | ||
| 8acf1435 PB |
104 | 2019-05-24 Peter Bergner <bergner@linux.ibm.com> |
| 105 | Alan Modra <amodra@gmail.com> | |
| 106 | ||
| 107 | * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34), | |
| 108 | (insert_pcrel, extract_pcrel, extract_pcrel0): New functions. | |
| 109 | (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment. | |
| 110 | (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0, | |
| 111 | XTOP>): Define and add entries. | |
| 112 | (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define. | |
| 113 | (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw, | |
| 114 | pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd, | |
| 115 | plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq. | |
| 116 | ||
| dd7efa79 PB |
117 | 2019-05-24 Peter Bergner <bergner@linux.ibm.com> |
| 118 | Alan Modra <amodra@gmail.com> | |
| 119 | ||
| 120 | * ppc-dis.c (ppc_opts): Add "future" entry. | |
| 121 | (PREFIX_OPCD_SEGS): Define. | |
| 122 | (prefix_opcd_indices): New array. | |
| 123 | (disassemble_init_powerpc): Initialize prefix_opcd_indices. | |
| 124 | (lookup_prefix): New function. | |
| 125 | (print_insn_powerpc): Handle 64-bit prefix instructions. | |
| 126 | * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK), | |
| 127 | (PMRR, POWERXX): Define. | |
| 128 | (prefix_opcodes): New instruction table. | |
| 129 | (prefix_num_opcodes): New constant. | |
| 130 | ||
| 79472b45 JM |
131 | 2019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 132 | ||
| 133 | * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch. | |
| 134 | * configure: Regenerated. | |
| 135 | * Makefile.am: Add rules for the files generated from cpu/bpf.cpu | |
| 136 | and cpu/bpf.opc. | |
| 137 | (HFILES): Add bpf-desc.h and bpf-opc.h. | |
| 138 | (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c, | |
| 139 | bpf-ibld.c and bpf-opc.c. | |
| 140 | (BPF_DEPS): Define. | |
| 141 | * Makefile.in: Regenerated. | |
| 142 | * disassemble.c (ARCH_bpf): Define. | |
| 143 | (disassembler): Add case for bfd_arch_bpf. | |
| 144 | (disassemble_init_for_target): Likewise. | |
| 145 | (enum epbf_isa_attr): Define. | |
| 146 | * disassemble.h: extern print_insn_bpf. | |
| 147 | * bpf-asm.c: Generated. | |
| 148 | * bpf-opc.h: Likewise. | |
| 149 | * bpf-opc.c: Likewise. | |
| 150 | * bpf-ibld.c: Likewise. | |
| 151 | * bpf-dis.c: Likewise. | |
| 152 | * bpf-desc.h: Likewise. | |
| 153 | * bpf-desc.c: Likewise. | |
| 154 | ||
| ba6cd17f SD |
155 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
| 156 | ||
| 157 | * arm-dis.c (coprocessor_opcodes): New instructions for VMRS | |
| 158 | and VMSR with the new operands. | |
| 159 | ||
| e39c1607 SD |
160 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
| 161 | ||
| 162 | * arm-dis.c (enum mve_instructions): New enum | |
| 163 | for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv | |
| 164 | and cneg. | |
| 165 | (mve_opcodes): New instructions as above. | |
| 166 | (is_mve_encoding_conflict): Add cases for csinc, csinv, | |
| 167 | csneg and csel. | |
| 168 | (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C. | |
| 169 | ||
| 23d00a41 SD |
170 | 2019-05-21 Sudakshina Das <sudi.das@arm.com> |
| 171 | ||
| 172 | * arm-dis.c (emun mve_instructions): Updated for new instructions. | |
| 173 | (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl, | |
| 174 | sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll, | |
| 175 | uqshl, urshrl and urshr. | |
| 176 | (is_mve_okay_in_it): Add new instructions to TRUE list. | |
| 177 | (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15. | |
| 178 | (print_insn_mve): Updated to accept new %j, | |
| 179 | %<bitfield>m and %<bitfield>n patterns. | |
| 180 | ||
| cd4797ee FS |
181 | 2019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com> |
| 182 | ||
| 183 | * mips-opc.c (mips_builtin_opcodes): Change source register | |
| 184 | constraint for DAUI. | |
| 185 | ||
| 999b073b NC |
186 | 2019-05-20 Nick Clifton <nickc@redhat.com> |
| 187 | ||
| 188 | * po/fr.po: Updated French translation. | |
| 189 | ||
| 14b456f2 AV |
190 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 191 | Michael Collison <michael.collison@arm.com> | |
| 192 | ||
| 193 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
| 194 | (enum mve_instructions): Likewise. | |
| 195 | (enum mve_undefined): Add new reasons. | |
| 196 | (is_mve_encoding_conflict): Handle new instructions. | |
| 197 | (is_mve_undefined): Likewise. | |
| 198 | (is_mve_unpredictable): Likewise. | |
| 199 | (print_mve_undefined): Likewise. | |
| 200 | (print_mve_size): Likewise. | |
| 201 | ||
| f49bb598 AV |
202 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 203 | Michael Collison <michael.collison@arm.com> | |
| 204 | ||
| 205 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
| 206 | (enum mve_instructions): Likewise. | |
| 207 | (is_mve_encoding_conflict): Handle new instructions. | |
| 208 | (is_mve_undefined): Likewise. | |
| 209 | (is_mve_unpredictable): Likewise. | |
| 210 | (print_mve_size): Likewise. | |
| 211 | ||
| 56858bea AV |
212 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 213 | Michael Collison <michael.collison@arm.com> | |
| 214 | ||
| 215 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
| 216 | (enum mve_instructions): Likewise. | |
| 217 | (is_mve_encoding_conflict): Likewise. | |
| 218 | (is_mve_unpredictable): Likewise. | |
| 219 | (print_mve_size): Likewise. | |
| 220 | ||
| e523f101 AV |
221 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 222 | Michael Collison <michael.collison@arm.com> | |
| 223 | ||
| 224 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
| 225 | (enum mve_instructions): Likewise. | |
| 226 | (is_mve_encoding_conflict): Handle new instructions. | |
| 227 | (is_mve_undefined): Likewise. | |
| 228 | (is_mve_unpredictable): Likewise. | |
| 229 | (print_mve_size): Likewise. | |
| 230 | ||
| 66dcaa5d AV |
231 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 232 | Michael Collison <michael.collison@arm.com> | |
| 233 | ||
| 234 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
| 235 | (enum mve_instructions): Likewise. | |
| 236 | (is_mve_encoding_conflict): Handle new instructions. | |
| 237 | (is_mve_undefined): Likewise. | |
| 238 | (is_mve_unpredictable): Likewise. | |
| 239 | (print_mve_size): Likewise. | |
| 240 | (print_insn_mve): Likewise. | |
| 241 | ||
| d052b9b7 AV |
242 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 243 | Michael Collison <michael.collison@arm.com> | |
| 244 | ||
| 245 | * arm-dis.c (thumb32_opcodes): Add new instructions. | |
| 246 | (print_insn_thumb32): Handle new instructions. | |
| 247 | ||
| ed63aa17 AV |
248 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 249 | Michael Collison <michael.collison@arm.com> | |
| 250 | ||
| 251 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 252 | (enum mve_undefined): Add new reasons. | |
| 253 | (is_mve_encoding_conflict): Handle new instructions. | |
| 254 | (is_mve_undefined): Likewise. | |
| 255 | (is_mve_unpredictable): Likewise. | |
| 256 | (print_mve_undefined): Likewise. | |
| 257 | (print_mve_size): Likewise. | |
| 258 | (print_mve_shift_n): Likewise. | |
| 259 | (print_insn_mve): Likewise. | |
| 260 | ||
| 897b9bbc AV |
261 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 262 | Michael Collison <michael.collison@arm.com> | |
| 263 | ||
| 264 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 265 | (is_mve_encoding_conflict): Handle new instructions. | |
| 266 | (is_mve_unpredictable): Likewise. | |
| 267 | (print_mve_rotate): Likewise. | |
| 268 | (print_mve_size): Likewise. | |
| 269 | (print_insn_mve): Likewise. | |
| 270 | ||
| 1c8f2df8 AV |
271 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 272 | Michael Collison <michael.collison@arm.com> | |
| 273 | ||
| 274 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 275 | (is_mve_encoding_conflict): Handle new instructions. | |
| 276 | (is_mve_unpredictable): Likewise. | |
| 277 | (print_mve_size): Likewise. | |
| 278 | (print_insn_mve): Likewise. | |
| 279 | ||
| d3b63143 AV |
280 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 281 | Michael Collison <michael.collison@arm.com> | |
| 282 | ||
| 283 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 284 | (enum mve_undefined): Add new reasons. | |
| 285 | (is_mve_encoding_conflict): Handle new instructions. | |
| 286 | (is_mve_undefined): Likewise. | |
| 287 | (is_mve_unpredictable): Likewise. | |
| 288 | (print_mve_undefined): Likewise. | |
| 289 | (print_mve_size): Likewise. | |
| 290 | (print_insn_mve): Likewise. | |
| 291 | ||
| 14925797 AV |
292 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 293 | Michael Collison <michael.collison@arm.com> | |
| 294 | ||
| 295 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 296 | (is_mve_encoding_conflict): Handle new instructions. | |
| 297 | (is_mve_undefined): Likewise. | |
| 298 | (is_mve_unpredictable): Likewise. | |
| 299 | (print_mve_size): Likewise. | |
| 300 | (print_insn_mve): Likewise. | |
| 301 | ||
| c507f10b AV |
302 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 303 | Michael Collison <michael.collison@arm.com> | |
| 304 | ||
| 305 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 306 | (enum mve_unpredictable): Add new reasons. | |
| 307 | (enum mve_undefined): Likewise. | |
| 308 | (is_mve_okay_in_it): Handle new isntructions. | |
| 309 | (is_mve_encoding_conflict): Likewise. | |
| 310 | (is_mve_undefined): Likewise. | |
| 311 | (is_mve_unpredictable): Likewise. | |
| 312 | (print_mve_vmov_index): Likewise. | |
| 313 | (print_simd_imm8): Likewise. | |
| 314 | (print_mve_undefined): Likewise. | |
| 315 | (print_mve_unpredictable): Likewise. | |
| 316 | (print_mve_size): Likewise. | |
| 317 | (print_insn_mve): Likewise. | |
| 318 | ||
| bf0b396d AV |
319 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 320 | Michael Collison <michael.collison@arm.com> | |
| 321 | ||
| 322 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 323 | (enum mve_unpredictable): Add new reasons. | |
| 324 | (enum mve_undefined): Likewise. | |
| 325 | (is_mve_encoding_conflict): Handle new instructions. | |
| 326 | (is_mve_undefined): Likewise. | |
| 327 | (is_mve_unpredictable): Likewise. | |
| 328 | (print_mve_undefined): Likewise. | |
| 329 | (print_mve_unpredictable): Likewise. | |
| 330 | (print_mve_rounding_mode): Likewise. | |
| 331 | (print_mve_vcvt_size): Likewise. | |
| 332 | (print_mve_size): Likewise. | |
| 333 | (print_insn_mve): Likewise. | |
| 334 | ||
| ef1576a1 AV |
335 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 336 | Michael Collison <michael.collison@arm.com> | |
| 337 | ||
| 338 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 339 | (enum mve_unpredictable): Add new reasons. | |
| 340 | (enum mve_undefined): Likewise. | |
| 341 | (is_mve_undefined): Handle new instructions. | |
| 342 | (is_mve_unpredictable): Likewise. | |
| 343 | (print_mve_undefined): Likewise. | |
| 344 | (print_mve_unpredictable): Likewise. | |
| 345 | (print_mve_size): Likewise. | |
| 346 | (print_insn_mve): Likewise. | |
| 347 | ||
| aef6d006 AV |
348 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 349 | Michael Collison <michael.collison@arm.com> | |
| 350 | ||
| 351 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 352 | (enum mve_undefined): Add new reasons. | |
| 353 | (insns): Add new instructions. | |
| 354 | (is_mve_encoding_conflict): | |
| 355 | (print_mve_vld_str_addr): New print function. | |
| 356 | (is_mve_undefined): Handle new instructions. | |
| 357 | (is_mve_unpredictable): Likewise. | |
| 358 | (print_mve_undefined): Likewise. | |
| 359 | (print_mve_size): Likewise. | |
| 360 | (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions. | |
| 361 | (print_insn_mve): Handle new operands. | |
| 362 | ||
| 04d54ace AV |
363 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 364 | Michael Collison <michael.collison@arm.com> | |
| 365 | ||
| 366 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 367 | (enum mve_unpredictable): Add new reasons. | |
| 368 | (is_mve_encoding_conflict): Handle new instructions. | |
| 369 | (is_mve_unpredictable): Likewise. | |
| 370 | (mve_opcodes): Add new instructions. | |
| 371 | (print_mve_unpredictable): Handle new reasons. | |
| 372 | (print_mve_register_blocks): New print function. | |
| 373 | (print_mve_size): Handle new instructions. | |
| 374 | (print_insn_mve): Likewise. | |
| 375 | ||
| 9743db03 AV |
376 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 377 | Michael Collison <michael.collison@arm.com> | |
| 378 | ||
| 379 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 380 | (enum mve_unpredictable): Add new reasons. | |
| 381 | (enum mve_undefined): Likewise. | |
| 382 | (is_mve_encoding_conflict): Handle new instructions. | |
| 383 | (is_mve_undefined): Likewise. | |
| 384 | (is_mve_unpredictable): Likewise. | |
| 385 | (coprocessor_opcodes): Move NEON VDUP from here... | |
| 386 | (neon_opcodes): ... to here. | |
| 387 | (mve_opcodes): Add new instructions. | |
| 388 | (print_mve_undefined): Handle new reasons. | |
| 389 | (print_mve_unpredictable): Likewise. | |
| 390 | (print_mve_size): Handle new instructions. | |
| 391 | (print_insn_neon): Handle vdup. | |
| 392 | (print_insn_mve): Handle new operands. | |
| 393 | ||
| 143275ea AV |
394 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 395 | Michael Collison <michael.collison@arm.com> | |
| 396 | ||
| 397 | * arm-dis.c (enum mve_instructions): Add new instructions. | |
| 398 | (enum mve_unpredictable): Add new values. | |
| 399 | (mve_opcodes): Add new instructions. | |
| 400 | (vec_condnames): New array with vector conditions. | |
| 401 | (mve_predicatenames): New array with predicate suffixes. | |
| 402 | (mve_vec_sizename): New array with vector sizes. | |
| 403 | (enum vpt_pred_state): New enum with vector predication states. | |
| 404 | (struct vpt_block): New struct type for vpt blocks. | |
| 405 | (vpt_block_state): Global struct to keep track of state. | |
| 406 | (mve_extract_pred_mask): New helper function. | |
| 407 | (num_instructions_vpt_block): Likewise. | |
| 408 | (mark_outside_vpt_block): Likewise. | |
| 409 | (mark_inside_vpt_block): Likewise. | |
| 410 | (invert_next_predicate_state): Likewise. | |
| 411 | (update_next_predicate_state): Likewise. | |
| 412 | (update_vpt_block_state): Likewise. | |
| 413 | (is_vpt_instruction): Likewise. | |
| 414 | (is_mve_encoding_conflict): Add entries for new instructions. | |
| 415 | (is_mve_unpredictable): Likewise. | |
| 416 | (print_mve_unpredictable): Handle new cases. | |
| 417 | (print_instruction_predicate): Likewise. | |
| 418 | (print_mve_size): New function. | |
| 419 | (print_vec_condition): New function. | |
| 420 | (print_insn_mve): Handle vpt blocks and new print operands. | |
| 421 | ||
| f08d8ce3 AV |
422 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 423 | ||
| 424 | * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors | |
| 425 | 8, 14 and 15 for Armv8.1-M Mainline. | |
| 426 | ||
| 73cd51e5 AV |
427 | 2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 428 | Michael Collison <michael.collison@arm.com> | |
| 429 | ||
| 430 | * arm-dis.c (enum mve_instructions): New enum. | |
| 431 | (enum mve_unpredictable): Likewise. | |
| 432 | (enum mve_undefined): Likewise. | |
| 433 | (struct mopcode32): New struct. | |
| 434 | (is_mve_okay_in_it): New function. | |
| 435 | (is_mve_architecture): Likewise. | |
| 436 | (arm_decode_field): Likewise. | |
| 437 | (arm_decode_field_multiple): Likewise. | |
| 438 | (is_mve_encoding_conflict): Likewise. | |
| 439 | (is_mve_undefined): Likewise. | |
| 440 | (is_mve_unpredictable): Likewise. | |
| 441 | (print_mve_undefined): Likewise. | |
| 442 | (print_mve_unpredictable): Likewise. | |
| 443 | (print_insn_coprocessor_1): Use arm_decode_field_multiple. | |
| 444 | (print_insn_mve): New function. | |
| 445 | (print_insn_thumb32): Handle MVE architecture. | |
| 446 | (select_arm_features): Force thumb for Armv8.1-m Mainline. | |
| 447 | ||
| 3076e594 NC |
448 | 2019-05-10 Nick Clifton <nickc@redhat.com> |
| 449 | ||
| 450 | PR 24538 | |
| 451 | * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the | |
| 452 | end of the table prematurely. | |
| 453 | ||
| 387e7624 FS |
454 | 2019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com> |
| 455 | ||
| 456 | * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB | |
| 457 | macros for R6. | |
| 458 | ||
| 0067be51 AM |
459 | 2019-05-11 Alan Modra <amodra@gmail.com> |
| 460 | ||
| 461 | * ppc-dis.c (print_insn_powerpc) Don't skip optional operands | |
| 462 | when -Mraw is in effect. | |
| 463 | ||
| 42e6288f MM |
464 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 465 | ||
| 466 | * aarch64-dis-2.c: Regenerate. | |
| 467 | * aarch64-tbl.h (OP_SVE_BBU): New variant set. | |
| 468 | (OP_SVE_BBB): New variant set. | |
| 469 | (OP_SVE_DDDD): New variant set. | |
| 470 | (OP_SVE_HHH): New variant set. | |
| 471 | (OP_SVE_HHHU): New variant set. | |
| 472 | (OP_SVE_SSS): New variant set. | |
| 473 | (OP_SVE_SSSU): New variant set. | |
| 474 | (OP_SVE_SHH): New variant set. | |
| 475 | (OP_SVE_SBBU): New variant set. | |
| 476 | (OP_SVE_DSS): New variant set. | |
| 477 | (OP_SVE_DHHU): New variant set. | |
| 478 | (OP_SVE_VMV_HSD_BHS): New variant set. | |
| 479 | (OP_SVE_VVU_HSD_BHS): New variant set. | |
| 480 | (OP_SVE_VVVU_SD_BH): New variant set. | |
| 481 | (OP_SVE_VVVU_BHSD): New variant set. | |
| 482 | (OP_SVE_VVV_QHD_DBS): New variant set. | |
| 483 | (OP_SVE_VVV_HSD_BHS): New variant set. | |
| 484 | (OP_SVE_VVV_HSD_BHS2): New variant set. | |
| 485 | (OP_SVE_VVV_BHS_HSD): New variant set. | |
| 486 | (OP_SVE_VV_BHS_HSD): New variant set. | |
| 487 | (OP_SVE_VVV_SD): New variant set. | |
| 488 | (OP_SVE_VVU_BHS_HSD): New variant set. | |
| 489 | (OP_SVE_VZVV_SD): New variant set. | |
| 490 | (OP_SVE_VZVV_BH): New variant set. | |
| 491 | (OP_SVE_VZV_SD): New variant set. | |
| 492 | (aarch64_opcode_table): Add sve2 instructions. | |
| 493 | ||
| 28ed815a MM |
494 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 495 | ||
| 496 | * aarch64-asm-2.c: Regenerated. | |
| 497 | * aarch64-dis-2.c: Regenerated. | |
| 498 | * aarch64-opc-2.c: Regenerated. | |
| 499 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 500 | for SVE_SHLIMM_UNPRED_22. | |
| 501 | (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22. | |
| 502 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22 | |
| 503 | operand. | |
| 504 | ||
| fd1dc4a0 MM |
505 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 506 | ||
| 507 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 508 | sve_size_tsz_bhs iclass encode. | |
| 509 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 510 | sve_size_tsz_bhs iclass decode. | |
| 511 | ||
| 31e36ab3 MM |
512 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 513 | ||
| 514 | * aarch64-asm-2.c: Regenerated. | |
| 515 | * aarch64-dis-2.c: Regenerated. | |
| 516 | * aarch64-opc-2.c: Regenerated. | |
| 517 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 518 | for SVE_Zm4_11_INDEX. | |
| 519 | (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX. | |
| 520 | (fields): Handle SVE_i2h field. | |
| 521 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field. | |
| 522 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand. | |
| 523 | ||
| 1be5f94f MM |
524 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 525 | ||
| 526 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 527 | sve_shift_tsz_bhsd iclass encode. | |
| 528 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 529 | sve_shift_tsz_bhsd iclass decode. | |
| 530 | ||
| 3c17238b MM |
531 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 532 | ||
| 533 | * aarch64-asm-2.c: Regenerated. | |
| 534 | * aarch64-dis-2.c: Regenerated. | |
| 535 | * aarch64-opc-2.c: Regenerated. | |
| 536 | * aarch64-asm.c (aarch64_ins_sve_shrimm): | |
| 537 | (aarch64_encode_variant_using_iclass): Handle | |
| 538 | sve_shift_tsz_hsd iclass encode. | |
| 539 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 540 | sve_shift_tsz_hsd iclass decode. | |
| 541 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 542 | for SVE_SHRIMM_UNPRED_22. | |
| 543 | (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22. | |
| 544 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22 | |
| 545 | operand. | |
| 546 | ||
| cd50a87a MM |
547 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 548 | ||
| 549 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 550 | sve_size_013 iclass encode. | |
| 551 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 552 | sve_size_013 iclass decode. | |
| 553 | ||
| 3c705960 MM |
554 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 555 | ||
| 556 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 557 | sve_size_bh iclass encode. | |
| 558 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 559 | sve_size_bh iclass decode. | |
| 560 | ||
| 0a57e14f MM |
561 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 562 | ||
| 563 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 564 | sve_size_sd2 iclass encode. | |
| 565 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 566 | sve_size_sd2 iclass decode. | |
| 567 | * aarch64-opc.c (fields): Handle SVE_sz2 field. | |
| 568 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field. | |
| 569 | ||
| c469c864 MM |
570 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 571 | ||
| 572 | * aarch64-asm-2.c: Regenerated. | |
| 573 | * aarch64-dis-2.c: Regenerated. | |
| 574 | * aarch64-opc-2.c: Regenerated. | |
| 575 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 576 | for SVE_ADDR_ZX. | |
| 577 | (aarch64_print_operand): Add printing for SVE_ADDR_ZX. | |
| 578 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand. | |
| 579 | ||
| 116adc27 MM |
580 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 581 | ||
| 582 | * aarch64-asm-2.c: Regenerated. | |
| 583 | * aarch64-dis-2.c: Regenerated. | |
| 584 | * aarch64-opc-2.c: Regenerated. | |
| 585 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 586 | for SVE_Zm3_11_INDEX. | |
| 587 | (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX. | |
| 588 | (fields): Handle SVE_i3l and SVE_i3h2 fields. | |
| 589 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2 | |
| 590 | fields. | |
| 591 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand. | |
| 592 | ||
| 3bd82c86 MM |
593 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 594 | ||
| 595 | * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle | |
| 596 | sve_size_hsd2 iclass encode. | |
| 597 | * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle | |
| 598 | sve_size_hsd2 iclass decode. | |
| 599 | * aarch64-opc.c (fields): Handle SVE_size field. | |
| 600 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field. | |
| 601 | ||
| adccc507 MM |
602 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 603 | ||
| 604 | * aarch64-asm-2.c: Regenerated. | |
| 605 | * aarch64-dis-2.c: Regenerated. | |
| 606 | * aarch64-opc-2.c: Regenerated. | |
| 607 | * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking | |
| 608 | for SVE_IMM_ROT3. | |
| 609 | (aarch64_print_operand): Add printing for SVE_IMM_ROT3. | |
| 610 | (fields): Handle SVE_rot3 field. | |
| 611 | * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field. | |
| 612 | * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand. | |
| 613 | ||
| 5cd99750 MM |
614 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 615 | ||
| 616 | * aarch64-opc.c (verify_constraints): Check for movprfx for sve2 | |
| 617 | instructions. | |
| 618 | ||
| 7ce2460a MM |
619 | 2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com> |
| 620 | ||
| 621 | * aarch64-tbl.h | |
| 622 | (aarch64_feature_sve2, aarch64_feature_sve2aes, | |
| 623 | aarch64_feature_sve2sha3, aarch64_feature_sve2sm4, | |
| 624 | aarch64_feature_sve2bitperm): New feature sets. | |
| 625 | (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros | |
| 626 | for feature set addresses. | |
| 627 | (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN, | |
| 628 | SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros. | |
| 629 | ||
| 41cee089 FS |
630 | 2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com> |
| 631 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
| 632 | ||
| 633 | * mips-dis.c (mips_calculate_combination_ases): Add ISA | |
| 634 | argument and set ASE_EVA_R6 appropriately. | |
| 635 | (set_default_mips_dis_options): Pass ISA to above. | |
| 636 | (parse_mips_dis_option): Likewise. | |
| 637 | * mips-opc.c (EVAR6): New macro. | |
| 638 | (mips_builtin_opcodes): Add llwpe, scwpe. | |
| 639 | ||
| b83b4b13 SD |
640 | 2019-05-01 Sudakshina Das <sudi.das@arm.com> |
| 641 | ||
| 642 | * aarch64-asm-2.c: Regenerated. | |
| 643 | * aarch64-dis-2.c: Regenerated. | |
| 644 | * aarch64-opc-2.c: Regenerated. | |
| 645 | * aarch64-opc.c (operand_general_constraint_met_p): Add case for | |
| 646 | AARCH64_OPND_TME_UIMM16. | |
| 647 | (aarch64_print_operand): Likewise. | |
| 648 | * aarch64-tbl.h (QL_IMM_NIL): New. | |
| 649 | (TME): New. | |
| 650 | (_TME_INSN): New. | |
| 651 | (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel. | |
| 652 | ||
| 4a90ce95 JD |
653 | 2019-04-29 John Darrington <john@darrington.wattle.id.au> |
| 654 | ||
| 655 | * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails. | |
| 656 | ||
| a45328b9 AB |
657 | 2019-04-26 Andrew Bennett <andrew.bennett@imgtec.com> |
| 658 | Faraz Shahbazker <fshahbazker@wavecomp.com> | |
| 659 | ||
| 660 | * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp. | |
| 661 | ||
| d10be0cb JD |
662 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
| 663 | ||
| 664 | * s12z-opc.h: Add extern "C" bracketing to help | |
| 665 | users who wish to use this interface in c++ code. | |
| 666 | ||
| a679f24e JD |
667 | 2019-04-24 John Darrington <john@darrington.wattle.id.au> |
| 668 | ||
| 669 | * s12z-opc.c (bm_decode): Handle bit map operations with the | |
| 670 | "reserved0" mode. | |
| 671 | ||
| 32c36c3c AV |
672 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 673 | ||
| 674 | * arm-dis.c (coprocessor_opcodes): Document new %J and %K format | |
| 675 | specifier. Add entries for VLDR and VSTR of system registers. | |
| 676 | (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in | |
| 677 | coprocessor instructions on Armv8.1-M Mainline targets. Add handling | |
| 678 | of %J and %K format specifier. | |
| 679 | ||
| efd6b359 AV |
680 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 681 | ||
| 682 | * arm-dis.c (coprocessor_opcodes): Document new %C format control code. | |
| 683 | Add new entries for VSCCLRM instruction. | |
| 684 | (print_insn_coprocessor): Handle new %C format control code. | |
| 685 | ||
| 6b0dd094 AV |
686 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 687 | ||
| 688 | * arm-dis.c (enum isa): New enum. | |
| 689 | (struct sopcode32): New structure. | |
| 690 | (coprocessor_opcodes): change type of entries to struct sopcode32 and | |
| 691 | set isa field of all current entries to ANY. | |
| 692 | (print_insn_coprocessor): Change type of insn to struct sopcode32. | |
| 693 | Only match an entry if its isa field allows the current mode. | |
| 694 | ||
| 4b5a202f AV |
695 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 696 | ||
| 697 | * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for | |
| 698 | CLRM. | |
| 699 | (print_insn_thumb32): Add logic to print %n CLRM register list. | |
| 700 | ||
| 60f993ce AV |
701 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 702 | ||
| 703 | * arm-dis.c (print_insn_thumb32): Updated to accept new %P | |
| 704 | and %Q patterns. | |
| 705 | ||
| f6b2b12d AV |
706 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 707 | ||
| 708 | * arm-dis.c (thumb32_opcodes): New instruction bfcsel. | |
| 709 | (print_insn_thumb32): Edit the switch case for %Z. | |
| 710 | ||
| 1889da70 AV |
711 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 712 | ||
| 713 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern. | |
| 714 | ||
| 65d1bc05 AV |
715 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 716 | ||
| 717 | * arm-dis.c (thumb32_opcodes): New instruction bfl. | |
| 718 | ||
| 1caf72a5 AV |
719 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 720 | ||
| 721 | * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern. | |
| 722 | ||
| f1c7f421 AV |
723 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 724 | ||
| 725 | * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an | |
| 726 | Arm register with r13 and r15 unpredictable. | |
| 727 | (thumb32_opcodes): New instructions for bfx and bflx. | |
| 728 | ||
| 4389b29a AV |
729 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 730 | ||
| 731 | * arm-dis.c (thumb32_opcodes): New instructions for bf. | |
| 732 | ||
| e5d6e09e AV |
733 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 734 | ||
| 735 | * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern. | |
| 736 | ||
| e12437dc AV |
737 | 2019-04-15 Sudakshina Das <sudi.das@arm.com> |
| 738 | ||
| 739 | * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern. | |
| 740 | ||
| 031254f2 AV |
741 | 2019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com> |
| 742 | ||
| 743 | * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline. | |
| 744 | ||
| e5a557ac JD |
745 | 2019-04-12 John Darrington <john@darrington.wattle.id.au> |
| 746 | ||
| 747 | s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with | |
| 748 | "optr". ("operator" is a reserved word in c++). | |
| 749 | ||
| bd7ceb8d SD |
750 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
| 751 | ||
| 752 | * aarch64-opc.c (aarch64_print_operand): Add case for | |
| 753 | AARCH64_OPND_Rt_SP. | |
| 754 | (verify_constraints): Likewise. | |
| 755 | * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier. | |
| 756 | (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions | |
| 757 | to accept Rt|SP as first operand. | |
| 758 | (AARCH64_OPERANDS): Add new Rt_SP. | |
| 759 | * aarch64-asm-2.c: Regenerated. | |
| 760 | * aarch64-dis-2.c: Regenerated. | |
| 761 | * aarch64-opc-2.c: Regenerated. | |
| 762 | ||
| e54010f1 SD |
763 | 2019-04-11 Sudakshina Das <sudi.das@arm.com> |
| 764 | ||
| 765 | * aarch64-asm-2.c: Regenerated. | |
| 766 | * aarch64-dis-2.c: Likewise. | |
| 767 | * aarch64-opc-2.c: Likewise. | |
| 768 | * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm. | |
| 769 | ||
| 7e96e219 RS |
770 | 2019-04-09 Robert Suchanek <robert.suchanek@mips.com> |
| 771 | ||
| 772 | * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel. | |
| 773 | ||
| 6f2791d5 L |
774 | 2019-04-08 H.J. Lu <hongjiu.lu@intel.com> |
| 775 | ||
| 776 | * i386-opc.tbl: Consolidate AVX512 BF16 entries. | |
| 777 | * i386-init.h: Regenerated. | |
| 778 | ||
| e392bad3 AM |
779 | 2019-04-07 Alan Modra <amodra@gmail.com> |
| 780 | ||
| 781 | * ppc-dis.c (print_insn_powerpc): Use a tiny state machine | |
| 782 | op_separator to control printing of spaces, comma and parens | |
| 783 | rather than need_comma, need_paren and spaces vars. | |
| 784 | ||
| dffaa15c AM |
785 | 2019-04-07 Alan Modra <amodra@gmail.com> |
| 786 | ||
| 787 | PR 24421 | |
| 788 | * arm-dis.c (print_insn_coprocessor): Correct bracket placement. | |
| 789 | (print_insn_neon, print_insn_arm): Likewise. | |
| 790 | ||
| d6aab7a1 XG |
791 | 2019-04-05 Xuepeng Guo <xuepeng.guo@intel.com> |
| 792 | ||
| 793 | * i386-dis-evex.h (evex_table): Updated to support BF16 | |
| 794 | instructions. | |
| 795 | * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1 | |
| 796 | and EVEX_W_0F3872_P_3. | |
| 797 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS. | |
| 798 | (cpu_flags): Add bitfield for CpuAVX512_BF16. | |
| 799 | * i386-opc.h (enum): Add CpuAVX512_BF16. | |
| 800 | (i386_cpu_flags): Add bitfield for cpuavx512_bf16. | |
| 801 | * i386-opc.tbl: Add AVX512 BF16 instructions. | |
| 802 | * i386-init.h: Regenerated. | |
| 803 | * i386-tbl.h: Likewise. | |
| 804 | ||
| 66e85460 AM |
805 | 2019-04-05 Alan Modra <amodra@gmail.com> |
| 806 | ||
| 807 | * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK. | |
| 808 | (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics | |
| 809 | to favour printing of "-" branch hint when using the "y" bit. | |
| 810 | Allow BH field on bc{ctr,lr,tar}{,l}{-,+}. | |
| 811 | ||
| c2b1c275 AM |
812 | 2019-04-05 Alan Modra <amodra@gmail.com> |
| 813 | ||
| 814 | * ppc-dis.c (print_insn_powerpc): Delay printing spaces after | |
| 815 | opcode until first operand is output. | |
| 816 | ||
| aae9718e PB |
817 | 2019-04-04 Peter Bergner <bergner@linux.ibm.com> |
| 818 | ||
| 819 | PR gas/24349 | |
| 820 | * ppc-opc.c (valid_bo_pre_v2): Add comments. | |
| 821 | (valid_bo_post_v2): Add support for 'at' branch hints. | |
| 822 | (insert_bo): Only error on branch on ctr. | |
| 823 | (get_bo_hint_mask): New function. | |
| 824 | (insert_boe): Add new 'branch_taken' formal argument. Add support | |
| 825 | for inserting 'at' branch hints. | |
| 826 | (extract_boe): Add new 'branch_taken' formal argument. Add support | |
| 827 | for extracting 'at' branch hints. | |
| 828 | (insert_bom, extract_bom, insert_bop, extract_bop): New functions. | |
| 829 | (BOE): Delete operand. | |
| 830 | (BOM, BOP): New operands. | |
| 831 | (RM): Update value. | |
| 832 | (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete. | |
| 833 | (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-, | |
| 834 | bcctrl-, bctar-, bctarl->: Replace BOE with BOM. | |
| 835 | (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+, | |
| 836 | bcctrl+, bctar+, bctarl+>: Replace BOE with BOP. | |
| 837 | <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-, | |
| 838 | bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar, | |
| 839 | bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar, | |
| 840 | bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-, | |
| 841 | bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-, | |
| 842 | bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+, | |
| 843 | bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+, | |
| 844 | bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl, | |
| 845 | beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-, | |
| 846 | bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-, | |
| 847 | buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+, | |
| 848 | bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar, | |
| 849 | bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar, | |
| 850 | bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+, | |
| 851 | bttarl+>: New extended mnemonics. | |
| 852 | ||
| 96a86c01 AM |
853 | 2019-03-28 Alan Modra <amodra@gmail.com> |
| 854 | ||
| 855 | PR 24390 | |
| 856 | * ppc-opc.c (BTF): Define. | |
| 857 | (powerpc_opcodes): Use for mtfsb*. | |
| 858 | * ppc-dis.c (print_insn_powerpc): Print fields with both | |
| 859 | PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number. | |
| 860 | ||
| 796d6298 TC |
861 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 862 | ||
| 863 | * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols. | |
| 864 | (mapping_symbol_for_insn): Implement new algorithm. | |
| 865 | (print_insn): Remove duplicate code. | |
| 866 | ||
| 60df3720 TC |
867 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 868 | ||
| 869 | * aarch64-dis.c (print_insn_aarch64): | |
| 870 | Implement override. | |
| 871 | ||
| 51457761 TC |
872 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 873 | ||
| 874 | * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search | |
| 875 | order. | |
| 876 | ||
| 53b2f36b TC |
877 | 2019-03-25 Tamar Christina <tamar.christina@arm.com> |
| 878 | ||
| 879 | * aarch64-dis.c (last_stop_offset): New. | |
| 880 | (print_insn_aarch64): Use stop_offset. | |
| 881 | ||
| 89199bb5 L |
882 | 2019-03-19 H.J. Lu <hongjiu.lu@intel.com> |
| 883 | ||
| 884 | PR gas/24359 | |
| 885 | * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to | |
| 886 | CPU_ANY_AVX2_FLAGS. | |
| 887 | * i386-init.h: Regenerated. | |
| 888 | ||
| 97ed31ae L |
889 | 2019-03-18 H.J. Lu <hongjiu.lu@intel.com> |
| 890 | ||
| 891 | PR gas/24348 | |
| 892 | * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8, | |
| 893 | vmovdqu16, vmovdqu32 and vmovdqu64. | |
| 894 | * i386-tbl.h: Regenerated. | |
| 895 | ||
| 0919bfe9 AK |
896 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> |
| 897 | ||
| 898 | * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand | |
| 899 | from vstrszb, vstrszh, and vstrszf. | |
| 900 | ||
| 901 | 2019-03-12 Andreas Krebbel <krebbel@linux.ibm.com> | |
| 902 | ||
| 903 | * s390-opc.txt: Add instruction descriptions. | |
| 904 | ||
| 21820ebe JW |
905 | 2019-02-08 Jim Wilson <jimw@sifive.com> |
| 906 | ||
| 907 | * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form. | |
| 908 | <bne>: Likewise. | |
| 909 | ||
| f7dd2fb2 TC |
910 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
| 911 | ||
| 912 | * arm-dis.c (arm_opcodes): Redefine hlt to armv1. | |
| 913 | ||
| 6456d318 TC |
914 | 2019-02-07 Tamar Christina <tamar.christina@arm.com> |
| 915 | ||
| 916 | PR binutils/23212 | |
| 917 | * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz. | |
| 918 | * aarch64-opc.c (verify_elem_sd): New. | |
| 919 | (fields): Add FLD_sz entr. | |
| 920 | * aarch64-tbl.h (_SIMD_INSN): New. | |
| 921 | (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and | |
| 922 | fmulx scalar and vector by element isns. | |
| 923 | ||
| 4a83b610 NC |
924 | 2019-02-07 Nick Clifton <nickc@redhat.com> |
| 925 | ||
| 926 | * po/sv.po: Updated Swedish translation. | |
| 927 | ||
| fc60b8c8 AK |
928 | 2019-01-31 Andreas Krebbel <krebbel@linux.ibm.com> |
| 929 | ||
| 930 | * s390-mkopc.c (main): Accept arch13 as cpu string. | |
| 931 | * s390-opc.c: Add new instruction formats and instruction opcode | |
| 932 | masks. | |
| 933 | * s390-opc.txt: Add new arch13 instructions. | |
| 934 | ||
| e10620d3 TC |
935 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 936 | ||
| 937 | * aarch64-tbl.h (QL_LDST_AT): Update macro. | |
| 938 | (aarch64_opcode): Change encoding for stg, stzg | |
| 939 | st2g and st2zg. | |
| 940 | * aarch64-asm-2.c: Regenerated. | |
| 941 | * aarch64-dis-2.c: Regenerated. | |
| 942 | * aarch64-opc-2.c: Regenerated. | |
| 943 | ||
| 20a4ca55 SD |
944 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 945 | ||
| 946 | * aarch64-asm-2.c: Regenerated. | |
| 947 | * aarch64-dis-2.c: Likewise. | |
| 948 | * aarch64-opc-2.c: Likewise. | |
| 949 | * aarch64-tbl.h (aarch64_opcode): Add new stzgm. | |
| 950 | ||
| 550fd7bf SD |
951 | 2019-01-25 Sudakshina Das <sudi.das@arm.com> |
| 952 | Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> | |
| 953 | ||
| 954 | * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove. | |
| 955 | * aarch64-asm.h (ins_addr_simple_2): Likeiwse. | |
| 956 | * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise. | |
| 957 | * aarch64-dis.h (ext_addr_simple_2): Likewise. | |
| 958 | * aarch64-opc.c (operand_general_constraint_met_p): Remove | |
| 959 | case for ldstgv_indexed. | |
| 960 | (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2. | |
| 961 | * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv. | |
| 962 | (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2. | |
| 963 | * aarch64-asm-2.c: Regenerated. | |
| 964 | * aarch64-dis-2.c: Regenerated. | |
| 965 | * aarch64-opc-2.c: Regenerated. | |
| 966 | ||
| d9938630 NC |
967 | 2019-01-23 Nick Clifton <nickc@redhat.com> |
| 968 | ||
| 969 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
| 970 | ||
| 375cd423 NC |
971 | 2019-01-21 Nick Clifton <nickc@redhat.com> |
| 972 | ||
| 973 | * po/de.po: Updated German translation. | |
| 974 | * po/uk.po: Updated Ukranian translation. | |
| 975 | ||
| 57299f48 CX |
976 | 2019-01-20 Chenghua Xu <paul.hua.gm@gmail.com> |
| 977 | * mips-dis.c (mips_arch_choices): Fix typo in | |
| 978 | gs464, gs464e and gs264e descriptors. | |
| 979 | ||
| f48dfe41 NC |
980 | 2019-01-19 Nick Clifton <nickc@redhat.com> |
| 981 | ||
| 982 | * configure: Regenerate. | |
| 983 | * po/opcodes.pot: Regenerate. | |
| 984 | ||
| f974f26c NC |
985 | 2018-06-24 Nick Clifton <nickc@redhat.com> |
| 986 | ||
| 987 | 2.32 branch created. | |
| 988 | ||
| 39f286cd JD |
989 | 2019-01-09 John Darrington <john@darrington.wattle.id.au> |
| 990 | ||
| 448b8ca8 JD |
991 | * s12z-dis.c (print_insn_s12z): Do not dereference an operand |
| 992 | if it is null. | |
| 993 | -dis.c (opr_emit_disassembly): Do not omit an index if it is | |
| 39f286cd JD |
994 | zero. |
| 995 | ||
| 3107326d AP |
996 | 2019-01-09 Andrew Paprocki <andrew@ishiboo.com> |
| 997 | ||
| 998 | * configure: Regenerate. | |
| 999 | ||
| 7e9ca91e AM |
1000 | 2019-01-07 Alan Modra <amodra@gmail.com> |
| 1001 | ||
| 1002 | * configure: Regenerate. | |
| 1003 | * po/POTFILES.in: Regenerate. | |
| 1004 | ||
| ef1ad42b JD |
1005 | 2019-01-03 John Darrington <john@darrington.wattle.id.au> |
| 1006 | ||
| 1007 | * s12z-opc.c: New file. | |
| 1008 | * s12z-opc.h: New file. | |
| 1009 | * s12z-dis.c: Removed all code not directly related to display | |
| 1010 | of instructions. Used the interface provided by the new files | |
| 1011 | instead. | |
| 1012 | * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c. | |
| 7e9ca91e | 1013 | * Makefile.in: Regenerate. |
| ef1ad42b | 1014 | * configure.ac (bfd_s12z_arch): Correct the dependencies. |
| 7e9ca91e | 1015 | * configure: Regenerate. |
| ef1ad42b | 1016 | |
| 82704155 AM |
1017 | 2019-01-01 Alan Modra <amodra@gmail.com> |
| 1018 | ||
| 1019 | Update year range in copyright notice of all files. | |
| 1020 | ||
| d5c04e1b | 1021 | For older changes see ChangeLog-2018 |
| 3499769a | 1022 | \f |
| d5c04e1b | 1023 | Copyright (C) 2019 Free Software Foundation, Inc. |
| 3499769a AM |
1024 | |
| 1025 | Copying and distribution of this file, with or without modification, | |
| 1026 | are permitted in any medium without royalty provided the copyright | |
| 1027 | notice and this notice are preserved. | |
| 1028 | ||
| 1029 | Local Variables: | |
| 1030 | mode: change-log | |
| 1031 | left-margin: 8 | |
| 1032 | fill-column: 74 | |
| 1033 | version-control: never | |
| 1034 | End: |