Regenerate.
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3bb0c887
AM
12006-09-29 Alan Modra <amodra@bigpond.net.au>
2
3 * po/POTFILES.in: Regenerate.
4
2d447fca
JM
52006-09-26 Mark Shinwell <shinwell@codesourcery.com>
6 Joseph Myers <joseph@codesourcery.com>
7 Ian Lance Taylor <ian@wasabisystems.com>
8 Ben Elliston <bje@wasabisystems.com>
9
10 * arm-dis.c (coprocessor_opcodes): The X-qualifier to WMADD may
11 only be used with the default multiply-add operation, so if N is
12 set, don't bother printing X. Add new iwmmxt instructions.
13 (IWMMXT_INSN_COUNT): Update.
14 (iwmmxt_wwssnames): Qualify "wwss" names at index 2, 6, 10 and 14
15 with a 'c' suffix.
16 (print_insn_coprocessor): Check for iWMMXt2. Handle format
17 specifiers 'r', 'i'.
18
c4b5fff9
L
192006-09-24 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
20
21 PR binutils/3100
22 * i386-dis.c (prefix_user_table): Fix the second operand of
23 maskmovdqu instruction to allow only %xmm register instead of
24 both %xmm register and memory.
25
539e75ad
L
262006-09-23 H.J. Lu <hongjiu.lu@intel.com>
27
28 PR binutils/3235
29 * i386-dis.c (OP_OFF64): Get 32bit offset if there is an
30 address size prefix.
31
1c0d3aa6
NC
322006-09-17 Mei Ligang <ligang@sunnorth.com.cn>
33
34 * score-dis.c: New file.
35 * score-opc.h: New file.
36 * Makefile.am: Add Score files.
37 * Makefile.in: Regenerate.
38 * configure.in: Add support for Score target.
39 * configure: Regenerate.
40 * disassemble.c: Add support for Score target.
41
0112cd26
NC
422006-09-16 Nick Clifton <nickc@redhat.com>
43 Pedro Alves <pedro_alves@portugalmail.pt>
44
45 * arm-dis.c: Make use of new STRING_COMMA_LEN and CONST_STRNEQ
46 macros defined in bfd.h.
47 * cris-dis.c: Likewise.
48 * h8300-dis.c: Likewise.
49 * i386-dis.c: Likewise.
50 * ia64-gen.c: Likewise.
51 * mips-dis: Likewise.
52
428e3f1f
PB
532006-09-04 Paul Brook <paul@codesourcery.com>
54
55 * arm-dis.c (neon_opcode): Fix suffix on VMOVN.
56
96fbad73
L
572006-08-23 H.J. Lu <hongjiu.lu@intel.com>
58
59 * i386-dis.c (three_byte_table): Expand to 256 elements.
60
612006-08-04 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
4d9567e0 62
a7a8d8e5 63 PR binutils/3000
4d9567e0
MM
64 * i386-dis.c (MXC,EMC): Define.
65 (OP_MXC): New function to handle cvt* (convert instructions) between
66 %xmm and %mm register correctly.
67 (OP_EMC): ditto.
96fbad73 68 (prefix_user_table): Modified cvtpi2pd,cvtpd2pi and cvttpd2pi
4d9567e0
MM
69 instruction operands in PREGRP2,PREGRP3,PREGRP4 appropriately
70 with EMC/MXC.
71
777b13b9
RS
722006-07-29 Richard Sandiford <richard@codesourcery.com>
73
74 * m68k-opc.c (m68k_opcodes): Fix operand specificer in the Coldfire
75 "fdaddl" entry.
76
401a54cf
PB
772006-07-19 Paul Brook <paul@codesourcery.com>
78
79 * armd-dis.c (arm_opcodes): Fix rbit opcode.
80
2b516b72
L
812006-07-18 H.J. Lu <hongjiu.lu@intel.com>
82
83 * i386-dis.c (grps): Change "sldtQ", "strQ" and "smswQ" to
84 "sldt", "str" and "smsw".
85
10505f38
L
862006-07-15 H.J. Lu <hongjiu.lu@intel.com>
87
88 PR binutils/2829
89 * i386-dis.c (GRP11_C6): NEW.
90 (GRP11_C7): Likewise.
91 (GRP12): Updated.
92 (GRP13): Likewise.
93 (GRP14): Likewise.
94 (GRP15): Likewise.
95 (GRP16): Likewise.
96 (GRPAMD): Likewise.
97 (GRPPADLCK1): Likewise.
98 (GRPPADLCK2): Likewise.
99 (dis386): Use GRP11_C6 and GRP11_C7 for entres 0xc6 and 0xc7,
100 respectively.
101 (grps): Add entries for GRP11_C6 and GRP11_C7.
102
050dfa73
MM
1032006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
104 Michael Meissner <michael.meissner@amd.com>
105
106 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
107 support for amdfam10 SSE4a/ABM instructions. Modify all
108 initializer macros to have additional arguments. Disallow REP
109 prefix for non-string instructions.
110 (print_insn): Ditto.
111
112
e8b42ce4
JB
1132006-07-05 Julian Brown <julian@codesourcery.com>
114
115 * arm-dis.c (coprocessor): Alter fmsrr disassembly syntax.
116
15965411
L
1172006-06-12 H.J. Lu <hongjiu.lu@intel.com>
118
119 * i386-dis.c (dis386_twobyte): Use "nopQ" for 0x1f.
120 (twobyte_has_modrm): Set 1 for 0x1f.
121
46e883c5
L
1222006-06-12 H.J. Lu <hongjiu.lu@intel.com>
123
124 * i386-dis.c (NOP_Fixup): Removed.
125 (NOP_Fixup1): New.
126 (NOP_Fixup2): Likewise.
127 (dis386): Use NOP_Fixup1 and NOP_Fixup2 on 0x90.
128
4e9d3b81
JB
1292006-06-12 Julian Brown <julian@codesourcery.com>
130
131 * arm-dis.c (print_insn_neon): Disassemble 32-bit immediates as signed
132 on 64-bit hosts.
133
b3882df9
L
1342006-06-10 H.J. Lu <hongjiu.lu@intel.com>
135
136 * i386.c (GRP10): Renamed to ...
137 (GRP12): This.
138 (GRP11): Renamed to ...
139 (GRP13): This.
140 (GRP12): Renamed to ...
141 (GRP14): This.
142 (GRP13): Renamed to ...
143 (GRP15): This.
144 (GRP14): Renamed to ...
145 (GRP16): This.
146 (dis386_twobyte): Updated.
147 (grps): Likewise.
148
5f4df3dd
NC
1492006-06-09 Nick Clifton <nickc@redhat.com>
150
151 * po/fi.po: Updated Finnish translation.
152
6648b7cf
JM
1532006-06-07 Joseph S. Myers <joseph@codesourcery.com>
154
155 * po/Make-in (pdf, ps): New dummy targets.
156
c22aaad1
PB
1572006-06-06 Paul Brook <paul@codesourcery.com>
158
159 * arm-dis.c (coprocessor_opcodes): Add %c to unconditional arm
160 instructions.
161 (neon_opcodes): Add conditional execution specifiers.
162 (thumb_opcodes): Ditto.
163 (thumb32_opcodes): Ditto.
164 (arm_conditional): Change 0xe to "al" and add "" to end.
165 (ifthen_state, ifthen_next_state, ifthen_address): New.
166 (IFTHEN_COND): Define.
167 (print_insn_coprocessor, print_insn_neon): Print thumb conditions.
168 (print_insn_arm): Change %c to use new values of arm_conditional.
169 (print_insn_thumb16): Print thumb conditions. Add %I.
170 (print_insn_thumb32): Print thumb conditions.
171 (find_ifthen_state): New function.
172 (print_insn): Track IT block state.
173
9622b051
AM
1742006-06-06 Ben Elliston <bje@au.ibm.com>
175 Anton Blanchard <anton@samba.org>
176 Peter Bergner <bergner@vnet.ibm.com>
177
178 * ppc-dis.c (powerpc_dialect): Handle power6 option.
179 (print_ppc_disassembler_options): Mention power6.
180
65263ce3
TS
1812006-06-06 Thiemo Seufer <ths@mips.com>
182 Chao-ying Fu <fu@mips.com>
183
184 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
185 * mips-opc.c: Add DSP64 instructions.
186
92ce91bb
AM
1872006-06-06 Alan Modra <amodra@bigpond.net.au>
188
189 * m68hc11-dis.c (print_insn): Warning fix.
190
4cfe2c59
DJ
1912006-06-05 Daniel Jacobowitz <dan@codesourcery.com>
192
193 * po/Make-in (top_builddir): Define.
194
7ff1a5b5
AM
1952006-06-05 Alan Modra <amodra@bigpond.net.au>
196
197 * Makefile.am: Run "make dep-am".
198 * Makefile.in: Regenerate.
199 * config.in: Regenerate.
200
20e95c23
DJ
2012006-05-31 Daniel Jacobowitz <dan@codesourcery.com>
202
203 * Makefile.am (INCLUDES): Use @INCINTL@.
204 * acinclude.m4: Include new gettext macros.
205 * configure.in: Use ZW_GNU_GETTEXT_SISTER_DIR and AM_PO_SUBDIRS.
206 Remove local code for po/Makefile.
207 * Makefile.in, aclocal.m4, configure: Regenerated.
208
eebf07fb
NC
2092006-05-30 Nick Clifton <nickc@redhat.com>
210
211 * po/es.po: Updated Spanish translation.
212
a596001e
RS
2132006-05-25 Richard Sandiford <richard@codesourcery.com>
214
215 * m68k-opc.c (m68k_opcodes): Fix the masks of the Coldfire fmovemd
216 and fmovem entries. Put register list entries before immediate
217 mask entries. Use "l" rather than "L" in the fmovem entries.
218 * m68k-dis.c (match_insn_m68k): Remove the PRIV argument and work it
219 out from INFO.
220 (m68k_scan_mask): New function, split out from...
221 (print_insn_m68k): ...here. If no architecture has been set,
222 first try printing an m680x0 instruction, then try a Coldfire one.
223
4a4d496a
NC
2242006-05-24 Nick Clifton <nickc@redhat.com>
225
226 * po/ga.po: Updated Irish translation.
227
a854efa3
NC
2282006-05-22 Nick Clifton <nickc@redhat.com>
229
230 * crx-dis.c (EXTRACT): Make macro work on 64-bit hosts.
231
0bd79061
NC
2322006-05-22 Nick Clifton <nickc@redhat.com>
233
234 * po/nl.po: Updated translation.
235
00988f49
AM
2362006-05-18 Alan Modra <amodra@bigpond.net.au>
237
238 * avr-dis.c: Formatting fix.
239
9b3f89ee
TS
2402006-05-14 Thiemo Seufer <ths@mips.com>
241
242 * mips16-opc.c (I1, I32, I64): New shortcut defines.
243 (mips16_opcodes): Change membership of instructions to their
244 lowest baseline ISA.
245
cb6d3433
L
2462006-05-09 H.J. Lu <hongjiu.lu@intel.com>
247
248 * i386-dis.c (grps): Update sgdt/sidt for 64bit.
249
1f3c39b9
JB
2502006-05-05 Julian Brown <julian@codesourcery.com>
251
252 * arm-dis.c (coprocessor_opcodes): Don't interpret fldmx/fstmx as
253 vldm/vstm.
254
d43b4baf
TS
2552006-05-05 Thiemo Seufer <ths@mips.com>
256 David Ung <davidu@mips.com>
257
258 * mips-opc.c: Add macro for cache instruction.
259
39a7806d
TS
2602006-05-04 Thiemo Seufer <ths@mips.com>
261 Nigel Stephens <nigel@mips.com>
262 David Ung <davidu@mips.com>
263
264 * mips-dis.c (mips_arch_choices): Add smartmips instruction
265 decoding to MIPS32 and MIPS32R2. Limit DSP decoding to release
266 2 ISAs. Add MIPS3D decoding to MIPS32R2. Add MT decoding to
267 MIPS64R2.
268 * mips-opc.c: fix random typos in comments.
269 (INSN_SMARTMIPS): New defines.
270 (mips_builtin_opcodes): Add paired single support for MIPS32R2.
271 Move bc3f, bc3fl, bc3t, bc3tl downwards. Move flushi, flushd,
272 flushid, wb upwards. Move cfc3, ctc3 downwards. Rework the
273 FP_S and FP_D flags to denote single and double register
274 accesses separately. Move dmfc3, dmtc3, mfc3, mtc3 downwards.
275 Allow jr.hb and jalr.hb for release 1 ISAs. Allow luxc1, suxc1
276 for MIPS32R2. Add SmartMIPS instructions. Add two-argument
277 variants of bc2f, bc2fl, bc2t, bc2tl. Add mfhc2, mthc2 to
278 release 2 ISAs.
279 * mips16-opc.c (mips16_opcodes): Add sdbbp instruction.
280
104b4fab
TS
2812006-05-03 Thiemo Seufer <ths@mips.com>
282
283 * mips-opc.c (mips_builtin_opcodes): Fix mftr argument order.
284
022fac6d
TS
2852006-05-02 Thiemo Seufer <ths@mips.com>
286 Nigel Stephens <nigel@mips.com>
287 David Ung <davidu@mips.com>
288
289 * mips-dis.c (print_insn_args): Force mips16 to odd addresses.
290 (print_mips16_insn_arg): Force mips16 to odd addresses.
291
9bcd4f99
TS
2922006-04-30 Thiemo Seufer <ths@mips.com>
293 David Ung <davidu@mips.com>
294
295 * mips-opc.c (mips_builtin_opcodes): Add udi instructions
296 "udi0" to "udi15".
297 * mips-dis.c (print_insn_args): Adds udi argument handling.
298
f095b97b
JW
2992006-04-28 James E Wilson <wilson@specifix.com>
300
301 * m68k-dis.c (match_insn_m68k): Restore fprintf_func before printing
302 error message.
303
59c455b3
TS
3042006-04-28 Thiemo Seufer <ths@mips.com>
305 David Ung <davidu@mips.com>
bdb09db1 306 Nigel Stephens <nigel@mips.com>
59c455b3
TS
307
308 * mips-dis.c (mips_cp0sel_names_mips3264r2): Add MT register
309 names.
310
cc0ca239 3112006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 312 Nigel Stephens <nigel@mips.com>
cc0ca239
TS
313 David Ung <davidu@mips.com>
314
315 * mips-dis.c (print_insn_args): Add mips_opcode argument.
316 (print_insn_mips): Adjust print_insn_args call.
317
0d09bfe6 3182006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 319 Nigel Stephens <nigel@mips.com>
0d09bfe6
TS
320
321 * mips-dis.c (print_insn_args): Print $fcc only for FP
322 instructions, use $cc elsewise.
323
654c225a 3242006-04-28 Thiemo Seufer <ths@mips.com>
bdb09db1 325 Nigel Stephens <nigel@mips.com>
654c225a
TS
326
327 * opcodes/mips-dis.c (mips16_to_32_reg_map, mips16_reg_names):
328 Map MIPS16 registers to O32 names.
329 (print_mips16_insn_arg): Use mips16_reg_names.
330
0dbde4cf
JB
3312006-04-26 Julian Brown <julian@codesourcery.com>
332
333 * arm-dis.c (print_insn_neon): Disassemble floating-point constant
334 VMOV.
335
16980d0b
JB
3362006-04-26 Nathan Sidwell <nathan@codesourcery.com>
337 Julian Brown <julian@codesourcery.com>
338
339 * opcodes/arm-dis.c (coprocessor_opcodes): Add %A, %B, %k, convert
340 %<code>[zy] into %[zy]<code>. Expand meaning of %<bitfield>['`?].
341 Add unified load/store instruction names.
342 (neon_opcode_table): New.
343 (arm_opcodes): Expand meaning of %<bitfield>['`?].
344 (arm_decode_bitfield): New.
345 (print_insn_coprocessor): Add pc argument. Add %A & %B specifiers.
346 Use arm_decode_bitfield and adjust numeric specifiers. Adjust %z & %y.
347 (print_insn_neon): New.
348 (print_insn_arm): Adjust print_insn_coprocessor call. Call
349 print_insn_neon. Use arm_decode_bitfield and adjust numeric specifiers.
350 (print_insn_thumb32): Likewise.
351
ec3fcc56
AM
3522006-04-19 Alan Modra <amodra@bigpond.net.au>
353
354 * Makefile.am: Run "make dep-am".
355 * Makefile.in: Regenerate.
356
241a6c40
AM
3572006-04-19 Alan Modra <amodra@bigpond.net.au>
358
7c6646cd
AM
359 * avr-dis.c (avr_operand): Warning fix.
360
241a6c40
AM
361 * configure: Regenerate.
362
e7403566
DJ
3632006-04-16 Daniel Jacobowitz <dan@codesourcery.com>
364
365 * po/POTFILES.in: Regenerated.
366
52f16a0e
NC
3672006-04-12 Hochstein <hochstein@algo.informatik.tu-darmstadt.de>
368
369 PR binutils/2454
370 * avr-dis.c (avr_operand): Arrange for a comment to appear before
371 the symolic form of an address, so that the output of objdump -d
372 can be reassembled.
373
e78efa90
DD
3742006-04-10 DJ Delorie <dj@redhat.com>
375
376 * m32c-asm.c: Regenerate.
377
108a6f8e
CD
3782006-04-06 Carlos O'Donell <carlos@codesourcery.com>
379
380 * Makefile.am: Add install-html target.
381 * Makefile.in: Regenerate.
382
a135cb2c
NC
3832006-04-06 Nick Clifton <nickc@redhat.com>
384
385 * po/vi/po: Updated Vietnamese translation.
386
47426b41
AM
3872006-03-31 Paul Koning <ni1d@arrl.net>
388
389 * pdp11-opc.c (pdp11_opcodes): Fix opcode for SEC instruction.
390
331f1cbe
BS
3912006-03-16 Bernd Schmidt <bernd.schmidt@analog.com>
392
393 * bfin-dis.c (decode_dsp32shiftimm_0): Simplify and correct the
394 logic to identify halfword shifts.
395
c16d2bf0
PB
3962006-03-16 Paul Brook <paul@codesourcery.com>
397
398 * arm-dis.c (arm_opcodes): Rename swi to svc.
399 (thumb_opcodes): Ditto.
400
5348b81e
DD
4012006-03-13 DJ Delorie <dj@redhat.com>
402
5398310a
DD
403 * m32c-asm.c: Regenerate.
404 * m32c-desc.c: Likewise.
405 * m32c-desc.h: Likewise.
406 * m32c-dis.c: Likewise.
407 * m32c-ibld.c: Likewise.
5348b81e
DD
408 * m32c-opc.c: Likewise.
409 * m32c-opc.h: Likewise.
410
253d272c
DD
4112006-03-10 DJ Delorie <dj@redhat.com>
412
413 * m32c-desc.c: Regenerate with mul.l, mulu.l.
414 * m32c-opc.c: Likewise.
415 * m32c-opc.h: Likewise.
416
417
f530741d
NC
4182006-03-09 Nick Clifton <nickc@redhat.com>
419
420 * po/sv.po: Updated Swedish translation.
421
35c52694
L
4222006-03-07 H.J. Lu <hongjiu.lu@intel.com>
423
424 PR binutils/2428
425 * i386-dis.c (REP_Fixup): New function.
426 (AL): Remove duplicate.
427 (Xbr): New.
428 (Xvr): Likewise.
429 (Ybr): Likewise.
430 (Yvr): Likewise.
431 (indirDXr): Likewise.
432 (ALr): Likewise.
433 (eAXr): Likewise.
434 (dis386): Updated entries of ins, outs, movs, lods and stos.
435
ed963e2d
NC
4362006-03-05 Nick Clifton <nickc@redhat.com>
437
438 * cgen-ibld.in (insert_normal): Cope with attempts to insert a
439 signed 32-bit value into an unsigned 32-bit field when the host is
440 a 64-bit machine.
441 * fr30-ibld.c: Regenerate.
442 * frv-ibld.c: Regenerate.
443 * ip2k-ibld.c: Regenerate.
444 * iq2000-asm.c: Regenerate.
445 * iq2000-ibld.c: Regenerate.
446 * m32c-ibld.c: Regenerate.
447 * m32r-ibld.c: Regenerate.
448 * openrisc-ibld.c: Regenerate.
449 * xc16x-ibld.c: Regenerate.
450 * xstormy16-ibld.c: Regenerate.
451
c7d41dc5
NC
4522006-03-03 Shrirang Khisti <shrirangk@kpitcummins.com)
453
454 * xc16x-asm.c: Regenerate.
455 * xc16x-dis.c: Regenerate.
c7d41dc5 456
f7d9e5c3
CD
4572006-02-27 Carlos O'Donell <carlos@codesourcery.com>
458
459 * po/Make-in: Add html target.
460
331d2d0d
L
4612006-02-27 H.J. Lu <hongjiu.lu@intel.com>
462
463 * i386-dis.c (IS_3BYTE_OPCODE): New for 3-byte opcodes used by
464 Intel Merom New Instructions.
465 (THREE_BYTE_0): Likewise.
466 (THREE_BYTE_1): Likewise.
467 (three_byte_table): Likewise.
468 (dis386_twobyte): Use THREE_BYTE_0 for entry 0x38. Use
469 THREE_BYTE_1 for entry 0x3a.
470 (twobyte_has_modrm): Updated.
471 (twobyte_uses_SSE_prefix): Likewise.
472 (print_insn): Handle 3-byte opcodes used by Intel Merom New
473 Instructions.
474
ff3f9d5b
DM
4752006-02-24 David S. Miller <davem@sunset.davemloft.net>
476
477 * sparc-dis.c (v9_priv_reg_names): Add "gl" entry.
478 (v9_hpriv_reg_names): New table.
479 (print_insn_sparc): Allow values up to 16 for '?' and '!'.
480 New cases '$' and '%' for read/write hyperprivileged register.
481 * sparc-opc.c (sparc_opcodes): Add new entries for UA2005
482 window handling and rdhpr/wrhpr instructions.
483
6772dd07
DD
4842006-02-24 DJ Delorie <dj@redhat.com>
485
486 * m32c-desc.c: Regenerate with linker relaxation attributes.
487 * m32c-desc.h: Likewise.
488 * m32c-dis.c: Likewise.
489 * m32c-opc.c: Likewise.
490
62b3e311
PB
4912006-02-24 Paul Brook <paul@codesourcery.com>
492
493 * arm-dis.c (arm_opcodes): Add V7 instructions.
494 (thumb32_opcodes): Ditto. Handle V7M MSR/MRS variants.
495 (print_arm_address): New function.
496 (print_insn_arm): Use it. Add 'P' and 'U' cases.
497 (psr_name): New function.
498 (print_insn_thumb32): Add 'U', 'C' and 'D' cases.
499
59cf82fe
L
5002006-02-23 H.J. Lu <hongjiu.lu@intel.com>
501
502 * ia64-opc-i.c (bXc): New.
503 (mXc): Likewise.
504 (OpX2TaTbYaXcC): Likewise.
505 (TF). Likewise.
506 (TFCM). Likewise.
507 (ia64_opcodes_i): Add instructions for tf.
508
509 * ia64-opc.h (IMMU5b): New.
510
511 * ia64-asmtab.c: Regenerated.
512
19a7219f
L
5132006-02-23 H.J. Lu <hongjiu.lu@intel.com>
514
515 * ia64-gen.c: Update copyright years.
516 * ia64-opc-b.c: Likewise.
517
7f3dfb9c
L
5182006-02-22 H.J. Lu <hongjiu.lu@intel.com>
519
520 * ia64-gen.c (lookup_regindex): Handle ".vm".
521 (print_dependency_table): Handle '\"'.
522
523 * ia64-ic.tbl: Updated from SDM 2.2.
524 * ia64-raw.tbl: Likewise.
525 * ia64-waw.tbl: Likewise.
526 * ia64-asmtab.c: Regenerated.
527
528 * ia64-opc-b.c (ia64_opcodes_b): Add vmsw.0 and vmsw.1.
529
d70c5fc7
NC
5302006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com>
531 Anil Paranjape <anilp1@kpitcummins.com>
532 Shilin Shakti <shilins@kpitcummins.com>
533
534 * xc16x-desc.h: New file
535 * xc16x-desc.c: New file
536 * xc16x-opc.h: New file
537 * xc16x-opc.c: New file
538 * xc16x-ibld.c: New file
539 * xc16x-asm.c: New file
540 * xc16x-dis.c: New file
541 * Makefile.am: Entries for xc16x
542 * Makefile.in: Regenerate
543 * cofigure.in: Add xc16x target information.
544 * configure: Regenerate.
545 * disassemble.c: Add xc16x target information.
546
a1cfb73e
L
5472006-02-11 H.J. Lu <hongjiu.lu@intel.com>
548
549 * i386-dis.c (dis386_twobyte): Use "movZ" for debug register
550 moves.
551
6dd5059a
L
5522006-02-11 H.J. Lu <hongjiu.lu@intel.com>
553
554 * i386-dis.c ('Z'): Add a new macro.
555 (dis386_twobyte): Use "movZ" for control register moves.
556
8536c657
NC
5572006-02-10 Nick Clifton <nickc@redhat.com>
558
559 * iq2000-asm.c: Regenerate.
560
266abb8f
NS
5612006-02-07 Nathan Sidwell <nathan@codesourcery.com>
562
563 * m68k-dis.c (print_insn_m68k): Use bfd_m68k_mach_to_features.
564
f1a64f49
DU
5652006-01-26 David Ung <davidu@mips.com>
566
567 * mips-opc.c: Add I33 masks to these MIPS32R2 instructions: prefx,
568 ceil.l.d, ceil.l.s, cvt.d.l, cvt.l.d, cvt.l.s, cvt.s.l, floor.l.d,
569 floor.l.s, ldxc1, lwxc1, madd.d, madd.s, msub.d, msub.s, nmadd.d,
570 nmadd.s, nmsub.d, nmsub.s, recip.d, recip.s, round.l.d, rsqrt.d,
571 rsqrt.s, sdxc1, swxc1, trunc.l.d, trunc.l.s.
572
9e919b5f
AM
5732006-01-18 Arnold Metselaar <arnoldm@sourceware.org>
574
575 * z80-dis.c (struct buffer, prt_d, prt_d_n, arit_d, ld_r_d,
576 ld_d_r, pref_xd_cb): Use signed char to hold data to be
577 disassembled.
578 * z80-dis.c (TXTSIZ): Increase buffer size to 24, this fixes
579 buffer overflows when disassembling instructions like
580 ld (ix+123),0x23
581 * z80-dis.c (opc_ind, pref_xd_cb): Suppress '+' in an indexed
582 operand, if the offset is negative.
583
c9021189
AM
5842006-01-17 Arnold Metselaar <arnoldm@sourceware.org>
585
586 * z80-dis.c (struct buffer, prt_d, prt_d_n, pref_xd_cb): Use
587 unsigned char to hold data to be disassembled.
588
d99b6465
AS
5892006-01-17 Andreas Schwab <schwab@suse.de>
590
591 PR binutils/1486
592 * disassemble.c (disassemble_init_for_target): Set
593 disassembler_needs_relocs for bfd_arch_arm.
594
c2fe9327
PB
5952006-01-16 Paul Brook <paul@codesourcery.com>
596
e88d958a 597 * m68k-opc.c (m68k_opcodes): Fix opcodes for ColdFire f?abss,
c2fe9327
PB
598 f?add?, and f?sub? instructions.
599
32fba81d
NC
6002006-01-16 Nick Clifton <nickc@redhat.com>
601
602 * po/zh_CN.po: New Chinese (simplified) translation.
603 * configure.in (ALL_LINGUAS): Add "zh_CH".
604 * configure: Regenerate.
605
1b3a26b5
PB
6062006-01-05 Paul Brook <paul@codesourcery.com>
607
608 * m68k-opc.c (m68k_opcodes): Add missing ColdFire fdsqrtd entry.
609
db313fa6
DD
6102006-01-06 DJ Delorie <dj@redhat.com>
611
612 * m32c-desc.c: Regenerate.
613 * m32c-opc.c: Regenerate.
614 * m32c-opc.h: Regenerate.
615
54d46aca
DD
6162006-01-03 DJ Delorie <dj@redhat.com>
617
618 * cgen-ibld.in (extract_normal): Avoid memory range errors.
619 * m32c-ibld.c: Regenerated.
620
e88d958a 621For older changes see ChangeLog-2005
252b5132
RH
622\f
623Local Variables:
2f6d2f85
NC
624mode: change-log
625left-margin: 8
626fill-column: 74
252b5132
RH
627version-control: never
628End:
This page took 0.380247 seconds and 4 git commands to generate.