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[AArch64] Increase max_num_aliases in aarch64-gen
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3d731f69
SN		 12016-11-11 Szabolcs Nagy <szabolcs.nagy@arm.com>
2
3 * aarch64-gen.c (find_alias_opcode): Increase max_num_aliases to 32.
4
60227d64
L		 52016-11-09 H.J. Lu <hongjiu.lu@intel.com>
6
7 PR binutils/20799
8 * i386-dis-evex.h (evex_table): Replace EdqwS with Edqw.
9 * i386-dis.c (EdqwS): Removed.
10 (dqw_swap_mode): Likewise.
11 (intel_operand_size): Don't check dqw_swap_mode.
12 (OP_E_register): Likewise.
13 (OP_E_memory): Likewise.
14 (OP_G): Likewise.
15 (OP_EX): Likewise.
16 * i386-opc.tbl: Remove "S" from EVEX vpextrw.
17 * i386-tbl.h: Regerated.
18
7efeed17
L		 192016-11-09 H.J. Lu <hongjiu.lu@intel.com>
20
21 * i386-opc.tbl: Merge AVX512F vmovq.
1032d6eb 22 * i386-tbl.h: Regerated.
7efeed17 23
1f334aeb
L		 242016-11-08 H.J. Lu <hongjiu.lu@intel.com>
25
26 PR binutils/20701
27 * i386-dis.c (THREE_BYTE_0F7A): Removed.
28 (dis386_twobyte): Don't use THREE_BYTE_0F7A.
29 (three_byte_table): Remove THREE_BYTE_0F7A.
30
48c97fa1
L		 312016-11-07 H.J. Lu <hongjiu.lu@intel.com>
32
33 PR binutils/20775
34 * i386-dis.c (FGRPd9_2): Replace 0 with 1.
35 (FGRPd9_4): Replace 1 with 2.
36 (FGRPd9_5): Replace 2 with 3.
37 (FGRPd9_6): Replace 3 with 4.
38 (FGRPd9_7): Replace 4 with 5.
39 (FGRPda_5): Replace 5 with 6.
40 (FGRPdb_4): Replace 6 with 7.
41 (FGRPde_3): Replace 7 with 8.
42 (FGRPdf_4): Replace 8 with 9.
43 (fgrps): Add an entry for Bad_Opcode.
44
b437d035
AB		 452016-11-04 Andrew Burgess <andrew.burgess@embecosm.com>
46
47 * arc-opc.c (arc_flag_operands): Add F_DI14.
48 (arc_flag_classes): Add C_DI14.
49 * arc-nps400-tbl.h: Add new exc instructions.
50
5a736821
GM		 512016-11-03 Graham Markall <graham.markall@embecosm.com>
52
53 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
54 major opcode 0xa.
55 * arc-nps-400-tbl.h: Add dcmac instruction.
56 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
57 (insert_nps_rbdouble_64): Added.
58 (extract_nps_rbdouble_64): Added.
59 (insert_nps_proto_size): Added.
60 (extract_nps_proto_size): Added.
61
bdfe53e3
AB		 622016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
63
64 * arc-dis.c (struct arc_operand_iterator): Remove all fields
65 relating to long instruction processing, add new limm field.
66 (OPCODE): Rename to...
67 (OPCODE_32BIT_INSN): ...this.
68 (OPCODE_AC): Delete.
69 (skip_this_opcode): Handle different instruction lengths, update
70 macro name.
71 (special_flag_p): Update parameter type.
72 (find_format_from_table): Update for more instruction lengths.
73 (find_format_long_instructions): Delete.
74 (find_format): Update for more instruction lengths.
75 (arc_insn_length): Likewise.
76 (extract_operand_value): Update for more instruction lengths.
77 (operand_iterator_next): Remove code relating to long
78 instructions.
79 (arc_opcode_to_insn_type): New function.
80 (print_insn_arc):Update for more instructions lengths.
81 * arc-ext.c (extInstruction_t): Change argument type.
82 * arc-ext.h (extInstruction_t): Change argument type.
83 * arc-fxi.h: Change type unsigned to unsigned long long
84 extensively throughout.
85 * arc-nps400-tbl.h: Add long instructions taken from
86 arc_long_opcodes table in arc-opc.c.
87 * arc-opc.c: Update parameter types on insert/extract handlers.
88 (arc_long_opcodes): Delete.
89 (arc_num_long_opcodes): Delete.
90 (arc_opcode_len): Update for more instruction lengths.
91
90f61cce
GM		 922016-11-03 Graham Markall <graham.markall@embecosm.com>
93
94 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
95
06fe285f
GM		 962016-11-03 Graham Markall <graham.markall@embecosm.com>
97
98 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
99 with arc_opcode_len.
100 (find_format_long_instructions): Likewise.
101 * arc-opc.c (arc_opcode_len): New function.
102
ecf64ec6
AB		 1032016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
104
105 * arc-nps400-tbl.h: Fix some instruction masks.
106
d039fef3
L		 1072016-11-03 H.J. Lu <hongjiu.lu@intel.com>
108
109 * i386-dis.c (REG_82): Removed.
110 (X86_64_82_REG_0): Likewise.
111 (X86_64_82_REG_1): Likewise.
112 (X86_64_82_REG_2): Likewise.
113 (X86_64_82_REG_3): Likewise.
114 (X86_64_82_REG_4): Likewise.
115 (X86_64_82_REG_5): Likewise.
116 (X86_64_82_REG_6): Likewise.
117 (X86_64_82_REG_7): Likewise.
118 (X86_64_82): New.
119 (dis386): Use X86_64_82 instead of REG_82.
120 (reg_table): Remove REG_82.
121 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
122 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
123 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
124 X86_64_82_REG_7.
125
8b89fe14
L		 1262016-11-03 H.J. Lu <hongjiu.lu@intel.com>
127
128 PR binutils/20754
129 * i386-dis.c (REG_82): New.
130 (X86_64_82_REG_0): Likewise.
131 (X86_64_82_REG_1): Likewise.
132 (X86_64_82_REG_2): Likewise.
133 (X86_64_82_REG_3): Likewise.
134 (X86_64_82_REG_4): Likewise.
135 (X86_64_82_REG_5): Likewise.
136 (X86_64_82_REG_6): Likewise.
137 (X86_64_82_REG_7): Likewise.
138 (dis386): Use REG_82.
139 (reg_table): Add REG_82.
140 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
141 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
142 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
143
7148c369
L		 1442016-11-03 H.J. Lu <hongjiu.lu@intel.com>
145
146 * i386-dis.c (REG_82): Renamed to ...
147 (REG_83): This.
148 (dis386): Updated.
149 (reg_table): Likewise.
150
47acf0bd
IT		 1512016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
152
153 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
154 * i386-dis-evex.h (evex_table): Updated.
155 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
156 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
157 (cpu_flags): Add CpuAVX512_4VNNIW.
158 * i386-opc.h (enum): (AVX512_4VNNIW): New.
159 (i386_cpu_flags): Add cpuavx512_4vnniw.
160 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
161 * i386-init.h: Regenerate.
162 * i386-tbl.h: Ditto.
163
920d2ddc
IT		 1642016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
165
166 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
167 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
168 * i386-dis-evex.h (evex_table): Updated.
169 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
170 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
171 (cpu_flags): Add CpuAVX512_4FMAPS.
172 (opcode_modifiers): Add ImplicitQuadGroup modifier.
173 * i386-opc.h (AVX512_4FMAP): New.
174 (i386_cpu_flags): Add cpuavx512_4fmaps.
175 (ImplicitQuadGroup): New.
176 (i386_opcode_modifier): Add implicitquadgroup.
177 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
178 * i386-init.h: Regenerate.
179 * i386-tbl.h: Ditto.
180
e23eba97
NC		 1812016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
182 Andrew Waterman <andrew@sifive.com>
183
184 Add support for RISC-V architecture.
185 * configure.ac: Add entry for bfd_riscv_arch.
186 * configure: Regenerate.
187 * disassemble.c (disassembler): Add support for riscv.
188 (disassembler_usage): Likewise.
189 * riscv-dis.c: New file.
190 * riscv-opc.c: New file.
191
b5cefcca
L		 1922016-10-21 H.J. Lu <hongjiu.lu@intel.com>
193
194 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
195 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
196 (rm_table): Update the RM_0FAE_REG_7 entry.
197 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
198 (cpu_flags): Remove CpuPCOMMIT.
199 * i386-opc.h (CpuPCOMMIT): Removed.
200 (i386_cpu_flags): Remove cpupcommit.
201 * i386-opc.tbl: Remove pcommit.
202 * i386-init.h: Regenerated.
203 * i386-tbl.h: Likewise.
204
9889cbb1
L		 2052016-10-20 H.J. Lu <hongjiu.lu@intel.com>
206
207 PR binutis/20705
208 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
209 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
210 32-bit mode. Don't check vex.register_specifier in 32-bit
211 mode.
212 (OP_VEX): Check for invalid mask registers.
213
28596323
L		 2142016-10-18 H.J. Lu <hongjiu.lu@intel.com>
215
216 PR binutis/20699
217 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
218 sizeflag.
219
da8d7d66
L		 2202016-10-18 H.J. Lu <hongjiu.lu@intel.com>
221
222 PR binutis/20704
223 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
224
eaf02703
MR		 2252016-10-18 Maciej W. Rozycki <macro@imgtec.com>
226
227 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
228 local variable to `index_regno'.
229
decf5bd1
CM		 2302016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
231
232 * arc-tbl.h: Removed any "inv.+" instructions from the table.
233
e5b06ef0
CZ		 2342016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
235
236 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
237 usage on ISA basis.
238
93562a34
JW		 2392016-10-11 Jiong Wang <jiong.wang@arm.com>
240
241 PR target/20666
242 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
243
362c0c4d
JW		 2442016-10-07 Jiong Wang <jiong.wang@arm.com>
245
246 PR target/20667
247 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
248 available.
249
1047201f
AM		 2502016-10-07 Alan Modra <amodra@gmail.com>
251
252 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
253
1a0670f3
AM		 2542016-10-06 Alan Modra <amodra@gmail.com>
255
256 * aarch64-opc.c: Spell fall through comments consistently.
257 * i386-dis.c: Likewise.
258 * aarch64-dis.c: Add missing fall through comments.
259 * aarch64-opc.c: Likewise.
260 * arc-dis.c: Likewise.
261 * arm-dis.c: Likewise.
262 * i386-dis.c: Likewise.
263 * m68k-dis.c: Likewise.
264 * mep-asm.c: Likewise.
265 * ns32k-dis.c: Likewise.
266 * sh-dis.c: Likewise.
267 * tic4x-dis.c: Likewise.
268 * tic6x-dis.c: Likewise.
269 * vax-dis.c: Likewise.
270
2b804145
AM		 2712016-10-06 Alan Modra <amodra@gmail.com>
272
273 * arc-ext.c (create_map): Add missing break.
274 * msp430-decode.opc (encode_as): Likewise.
275 * msp430-decode.c: Regenerate.
276
616ec358
AM		 2772016-10-06 Alan Modra <amodra@gmail.com>
278
279 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
280 * crx-dis.c (print_insn_crx): Likewise.
281
72da393d
L		 2822016-09-30 H.J. Lu <hongjiu.lu@intel.com>
283
284 PR binutils/20657
285 * i386-dis.c (putop): Don't assign alt twice.
286
744ce302
JW		 2872016-09-29 Jiong Wang <jiong.wang@arm.com>
288
289 PR target/20553
290 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
291
a5721ba2
AM		 2922016-09-29 Alan Modra <amodra@gmail.com>
293
294 * ppc-opc.c (L): Make compulsory.
295 (LOPT): New, optional form of L.
296 (HTM_R): Define as LOPT.
297 (L0, L1): Delete.
298 (L32OPT): New, optional for 32-bit L.
299 (L2OPT): New, 2-bit L for dcbf.
300 (SVC_LEC): Update.
301 (L2): Define.
302 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
303 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
304 <dcbf>: Use L2OPT.
305 <tlbiel, tlbie>: Use LOPT.
306 <wclr, wclrall>: Use L2.
307
c5da1932
VZ		 3082016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
309
310 * Makefile.in: Regenerate.
311 * configure: Likewise.
312
2b848ebd
CZ		 3132016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
314
315 * arc-ext-tbl.h (EXTINSN2OPF): Define.
316 (EXTINSN2OP): Use EXTINSN2OPF.
317 (bspeekm, bspop, modapp): New extension instructions.
318 * arc-opc.c (F_DNZ_ND): Define.
319 (F_DNZ_D): Likewise.
320 (F_SIZEB1): Changed.
321 (C_DNZ_D): Define.
322 (C_HARD): Changed.
323 * arc-tbl.h (dbnz): New instruction.
324 (prealloc): Allow it for ARC EM.
325 (xbfu): Likewise.
326
ad43e107
RS		 3272016-09-21 Richard Sandiford <richard.sandiford@arm.com>
328
329 * aarch64-opc.c (print_immediate_offset_address): Print spaces
330 after commas in addresses.
331 (aarch64_print_operand): Likewise.
332
ab3b8fcf
RS		 3332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
334
335 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
336 rather than "should be" or "expected to be" in error messages.
337
bb7eff52
RS		 3382016-09-21 Richard Sandiford <richard.sandiford@arm.com>
339
340 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
341 (print_mnemonic_name): ...here.
342 (print_comment): New function.
343 (print_aarch64_insn): Call it.
344 * aarch64-opc.c (aarch64_conds): Add SVE names.
345 (aarch64_print_operand): Print alternative condition names in
346 a comment.
347
c0890d26
RS		 3482016-09-21 Richard Sandiford <richard.sandiford@arm.com>
349
350 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
351 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
352 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
353 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
354 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
355 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
356 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
357 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
358 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
359 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
360 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
361 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
362 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
363 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
364 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
365 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
366 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
367 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
368 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
369 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
370 (OP_SVE_XWU, OP_SVE_XXU): New macros.
371 (aarch64_feature_sve): New variable.
372 (SVE): New macro.
373 (_SVE_INSN): Likewise.
374 (aarch64_opcode_table): Add SVE instructions.
375 * aarch64-opc.h (extract_fields): Declare.
376 * aarch64-opc-2.c: Regenerate.
377 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
378 * aarch64-asm-2.c: Regenerate.
379 * aarch64-dis.c (extract_fields): Make global.
380 (do_misc_decoding): Handle the new SVE aarch64_ops.
381 * aarch64-dis-2.c: Regenerate.
382
116b6019
RS		 3832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
384
385 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
386 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
387 aarch64_field_kinds.
388 * aarch64-opc.c (fields): Add corresponding entries.
389 * aarch64-asm.c (aarch64_get_variant): New function.
390 (aarch64_encode_variant_using_iclass): Likewise.
391 (aarch64_opcode_encode): Call it.
392 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
393 (aarch64_opcode_decode): Call it.
394
047cd301
RS		 3952016-09-21 Richard Sandiford <richard.sandiford@arm.com>
396
397 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
398 and FP register operands.
399 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
400 (FLD_SVE_Vn): New aarch64_field_kinds.
401 * aarch64-opc.c (fields): Add corresponding entries.
402 (aarch64_print_operand): Handle the new SVE core and FP register
403 operands.
404 * aarch64-opc-2.c: Regenerate.
405 * aarch64-asm-2.c: Likewise.
406 * aarch64-dis-2.c: Likewise.
407
165d4950
RS		 4082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
409
410 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
411 immediate operands.
412 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
413 * aarch64-opc.c (fields): Add corresponding entry.
414 (operand_general_constraint_met_p): Handle the new SVE FP immediate
415 operands.
416 (aarch64_print_operand): Likewise.
417 * aarch64-opc-2.c: Regenerate.
418 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
419 (ins_sve_float_zero_one): New inserters.
420 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
421 (aarch64_ins_sve_float_half_two): Likewise.
422 (aarch64_ins_sve_float_zero_one): Likewise.
423 * aarch64-asm-2.c: Regenerate.
424 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
425 (ext_sve_float_zero_one): New extractors.
426 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
427 (aarch64_ext_sve_float_half_two): Likewise.
428 (aarch64_ext_sve_float_zero_one): Likewise.
429 * aarch64-dis-2.c: Regenerate.
430
e950b345
RS		 4312016-09-21 Richard Sandiford <richard.sandiford@arm.com>
432
433 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
434 integer immediate operands.
435 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
436 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
437 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
438 * aarch64-opc.c (fields): Add corresponding entries.
439 (operand_general_constraint_met_p): Handle the new SVE integer
440 immediate operands.
441 (aarch64_print_operand): Likewise.
442 (aarch64_sve_dupm_mov_immediate_p): New function.
443 * aarch64-opc-2.c: Regenerate.
444 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
445 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
446 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
447 (aarch64_ins_limm): ...here.
448 (aarch64_ins_inv_limm): New function.
449 (aarch64_ins_sve_aimm): Likewise.
450 (aarch64_ins_sve_asimm): Likewise.
451 (aarch64_ins_sve_limm_mov): Likewise.
452 (aarch64_ins_sve_shlimm): Likewise.
453 (aarch64_ins_sve_shrimm): Likewise.
454 * aarch64-asm-2.c: Regenerate.
455 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
456 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
457 * aarch64-dis.c (decode_limm): New function, split out from...
458 (aarch64_ext_limm): ...here.
459 (aarch64_ext_inv_limm): New function.
460 (decode_sve_aimm): Likewise.
461 (aarch64_ext_sve_aimm): Likewise.
462 (aarch64_ext_sve_asimm): Likewise.
463 (aarch64_ext_sve_limm_mov): Likewise.
464 (aarch64_top_bit): Likewise.
465 (aarch64_ext_sve_shlimm): Likewise.
466 (aarch64_ext_sve_shrimm): Likewise.
467 * aarch64-dis-2.c: Regenerate.
468
98907a70
RS		 4692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
470
471 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
472 operands.
473 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
474 the AARCH64_MOD_MUL_VL entry.
475 (value_aligned_p): Cope with non-power-of-two alignments.
476 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
477 (print_immediate_offset_address): Likewise.
478 (aarch64_print_operand): Likewise.
479 * aarch64-opc-2.c: Regenerate.
480 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
481 (ins_sve_addr_ri_s9xvl): New inserters.
482 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
483 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
484 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
485 * aarch64-asm-2.c: Regenerate.
486 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
487 (ext_sve_addr_ri_s9xvl): New extractors.
488 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
489 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
490 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
491 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
492 * aarch64-dis-2.c: Regenerate.
493
4df068de
RS		 4942016-09-21 Richard Sandiford <richard.sandiford@arm.com>
495
496 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
497 address operands.
498 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
499 (FLD_SVE_xs_22): New aarch64_field_kinds.
500 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
501 (get_operand_specific_data): New function.
502 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
503 FLD_SVE_xs_14 and FLD_SVE_xs_22.
504 (operand_general_constraint_met_p): Handle the new SVE address
505 operands.
506 (sve_reg): New array.
507 (get_addr_sve_reg_name): New function.
508 (aarch64_print_operand): Handle the new SVE address operands.
509 * aarch64-opc-2.c: Regenerate.
510 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
511 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
512 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
513 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
514 (aarch64_ins_sve_addr_rr_lsl): Likewise.
515 (aarch64_ins_sve_addr_rz_xtw): Likewise.
516 (aarch64_ins_sve_addr_zi_u5): Likewise.
517 (aarch64_ins_sve_addr_zz): Likewise.
518 (aarch64_ins_sve_addr_zz_lsl): Likewise.
519 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
520 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
521 * aarch64-asm-2.c: Regenerate.
522 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
523 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
524 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
525 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
526 (aarch64_ext_sve_addr_ri_u6): Likewise.
527 (aarch64_ext_sve_addr_rr_lsl): Likewise.
528 (aarch64_ext_sve_addr_rz_xtw): Likewise.
529 (aarch64_ext_sve_addr_zi_u5): Likewise.
530 (aarch64_ext_sve_addr_zz): Likewise.
531 (aarch64_ext_sve_addr_zz_lsl): Likewise.
532 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
533 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
534 * aarch64-dis-2.c: Regenerate.
535
2442d846
RS		 5362016-09-21 Richard Sandiford <richard.sandiford@arm.com>
537
538 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
539 AARCH64_OPND_SVE_PATTERN_SCALED.
540 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
541 * aarch64-opc.c (fields): Add a corresponding entry.
542 (set_multiplier_out_of_range_error): New function.
543 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
544 (operand_general_constraint_met_p): Handle
545 AARCH64_OPND_SVE_PATTERN_SCALED.
546 (print_register_offset_address): Use PRIi64 to print the
547 shift amount.
548 (aarch64_print_operand): Likewise. Handle
549 AARCH64_OPND_SVE_PATTERN_SCALED.
550 * aarch64-opc-2.c: Regenerate.
551 * aarch64-asm.h (ins_sve_scale): New inserter.
552 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
553 * aarch64-asm-2.c: Regenerate.
554 * aarch64-dis.h (ext_sve_scale): New inserter.
555 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
556 * aarch64-dis-2.c: Regenerate.
557
245d2e3f
RS		 5582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
559
560 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
561 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
562 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
563 (FLD_SVE_prfop): Likewise.
564 * aarch64-opc.c: Include libiberty.h.
565 (aarch64_sve_pattern_array): New variable.
566 (aarch64_sve_prfop_array): Likewise.
567 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
568 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
569 AARCH64_OPND_SVE_PRFOP.
570 * aarch64-asm-2.c: Regenerate.
571 * aarch64-dis-2.c: Likewise.
572 * aarch64-opc-2.c: Likewise.
573
d50c751e
RS		 5742016-09-21 Richard Sandiford <richard.sandiford@arm.com>
575
576 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
577 AARCH64_OPND_QLF_P_[ZM].
578 (aarch64_print_operand): Print /z and /m where appropriate.
579
f11ad6bc
RS		 5802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
581
582 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
583 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
584 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
585 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
586 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
587 * aarch64-opc.c (fields): Add corresponding entries here.
588 (operand_general_constraint_met_p): Check that SVE register lists
589 have the correct length. Check the ranges of SVE index registers.
590 Check for cases where p8-p15 are used in 3-bit predicate fields.
591 (aarch64_print_operand): Handle the new SVE operands.
592 * aarch64-opc-2.c: Regenerate.
593 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
594 * aarch64-asm.c (aarch64_ins_sve_index): New function.
595 (aarch64_ins_sve_reglist): Likewise.
596 * aarch64-asm-2.c: Regenerate.
597 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
598 * aarch64-dis.c (aarch64_ext_sve_index): New function.
599 (aarch64_ext_sve_reglist): Likewise.
600 * aarch64-dis-2.c: Regenerate.
601
0c608d6b
RS		 6022016-09-21 Richard Sandiford <richard.sandiford@arm.com>
603
604 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
605 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
606 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
607 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
608 tied operands.
609
01dbfe4c
RS		 6102016-09-21 Richard Sandiford <richard.sandiford@arm.com>
611
612 * aarch64-opc.c (get_offset_int_reg_name): New function.
613 (print_immediate_offset_address): Likewise.
614 (print_register_offset_address): Take the base and offset
615 registers as parameters.
616 (aarch64_print_operand): Update caller accordingly. Use
617 print_immediate_offset_address.
618
72e9f319
RS		 6192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
620
621 * aarch64-opc.c (BANK): New macro.
622 (R32, R64): Take a register number as argument
623 (int_reg): Use BANK.
624
8a7f0c1b
RS		 6252016-09-21 Richard Sandiford <richard.sandiford@arm.com>
626
627 * aarch64-opc.c (print_register_list): Add a prefix parameter.
628 (aarch64_print_operand): Update accordingly.
629
aa2aa4c6
RS		 6302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
631
632 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
633 for FPIMM.
634 * aarch64-asm.h (ins_fpimm): New inserter.
635 * aarch64-asm.c (aarch64_ins_fpimm): New function.
636 * aarch64-asm-2.c: Regenerate.
637 * aarch64-dis.h (ext_fpimm): New extractor.
638 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
639 (aarch64_ext_fpimm): New function.
640 * aarch64-dis-2.c: Regenerate.
641
b5464a68
RS		 6422016-09-21 Richard Sandiford <richard.sandiford@arm.com>
643
644 * aarch64-asm.c: Include libiberty.h.
645 (insert_fields): New function.
646 (aarch64_ins_imm): Use it.
647 * aarch64-dis.c (extract_fields): New function.
648 (aarch64_ext_imm): Use it.
649
42408347
RS		 6502016-09-21 Richard Sandiford <richard.sandiford@arm.com>
651
652 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
653 with an esize parameter.
654 (operand_general_constraint_met_p): Update accordingly.
655 Fix misindented code.
656 * aarch64-asm.c (aarch64_ins_limm): Update call to
657 aarch64_logical_immediate_p.
658
4989adac
RS		 6592016-09-21 Richard Sandiford <richard.sandiford@arm.com>
660
661 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
662
bd11d5d8
RS		 6632016-09-21 Richard Sandiford <richard.sandiford@arm.com>
664
665 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
666
f807f43d
CZ		 6672016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
668
669 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
670
fd486b63
PB		 6712016-09-14 Peter Bergner <bergner@vnet.ibm.com>
672
673 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
674 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
675 xor3>: Delete mnemonics.
676 <cp_abort>: Rename mnemonic from ...
677 <cpabort>: ...to this.
678 <setb>: Change to a X form instruction.
679 <sync>: Change to 1 operand form.
680 <copy>: Delete mnemonic.
681 <copy_first>: Rename mnemonic from ...
682 <copy>: ...to this.
683 <paste, paste.>: Delete mnemonics.
684 <paste_last>: Rename mnemonic from ...
685 <paste.>: ...to this.
686
dce08442
AK		 6872016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
688
689 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
690
952c3f51
AK		 6912016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
692
693 * s390-mkopc.c (main): Support alternate arch strings.
694
8b71537b
PS		 6952016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
696
697 * s390-opc.txt: Fix kmctr instruction type.
698
5b64d091
L		 6992016-09-07 H.J. Lu <hongjiu.lu@intel.com>
700
701 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
702 * i386-init.h: Regenerated.
703
7763838e
CM		 7042016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
705
706 * opcodes/arc-dis.c (print_insn_arc): Changed.
707
1b8b6532
JM		 7082016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
709
710 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
711 camellia_fl.
712
1a336194
TP		 7132016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
714
715 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
716 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
717 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
718
6b40c462
L		 7192016-08-24 H.J. Lu <hongjiu.lu@intel.com>
720
721 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
722 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
723 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
724 PREFIX_MOD_3_0FAE_REG_4.
725 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
726 PREFIX_MOD_3_0FAE_REG_4.
727 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
728 (cpu_flags): Add CpuPTWRITE.
729 * i386-opc.h (CpuPTWRITE): New.
730 (i386_cpu_flags): Add cpuptwrite.
731 * i386-opc.tbl: Add ptwrite instruction.
732 * i386-init.h: Regenerated.
733 * i386-tbl.h: Likewise.
734
ab548d2d
AK		 7352016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
736
737 * arc-dis.h: Wrap around in extern "C".
738
344bde0a
RS		 7392016-08-23 Richard Sandiford <richard.sandiford@arm.com>
740
741 * aarch64-tbl.h (V8_2_INSN): New macro.
742 (aarch64_opcode_table): Use it.
743
5ce912d8
RS		 7442016-08-23 Richard Sandiford <richard.sandiford@arm.com>
745
746 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
747 CORE_INSN, __FP_INSN and SIMD_INSN.
748
9d30b0bd
RS		 7492016-08-23 Richard Sandiford <richard.sandiford@arm.com>
750
751 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
752 (aarch64_opcode_table): Update uses accordingly.
753
dfdaec14
AJ		 7542016-07-25 Andrew Jenner <andrew@codesourcery.com>
755 Kwok Cheung Yeung <kcy@codesourcery.com>
756
757 opcodes/
758 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
759 'e_cmplwi' to 'e_cmpli' instead.
760 (OPVUPRT, OPVUPRT_MASK): Define.
761 (powerpc_opcodes): Add E200Z4 insns.
762 (vle_opcodes): Add context save/restore insns.
763
7bd374a4
MR		 7642016-07-27 Maciej W. Rozycki <macro@imgtec.com>
765
766 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
767 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
768 "j".
769
db18dbab
GM		 7702016-07-27 Graham Markall <graham.markall@embecosm.com>
771
772 * arc-nps400-tbl.h: Change block comments to GNU format.
773 * arc-dis.c: Add new globals addrtypenames,
774 addrtypenames_max, and addtypeunknown.
775 (get_addrtype): New function.
776 (print_insn_arc): Print colons and address types when
777 required.
778 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
779 define insert and extract functions for all address types.
780 (arc_operands): Add operands for colon and all address
781 types.
782 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
783 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
784 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
785 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
786 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
787 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
788
fecd57f9
L		 7892016-07-21 H.J. Lu <hongjiu.lu@intel.com>
790
791 * configure: Regenerated.
792
37fd5ef3
CZ		 7932016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
794
795 * arc-dis.c (skipclass): New structure.
796 (decodelist): New variable.
797 (is_compatible_p): New function.
798 (new_element): Likewise.
799 (skip_class_p): Likewise.
800 (find_format_from_table): Use skip_class_p function.
801 (find_format): Decode first the extension instructions.
802 (print_insn_arc): Select either ARCEM or ARCHS based on elf
803 e_flags.
804 (parse_option): New function.
805 (parse_disassembler_options): Likewise.
806 (print_arc_disassembler_options): Likewise.
807 (print_insn_arc): Use parse_disassembler_options function. Proper
808 select ARCv2 cpu variant.
809 * disassemble.c (disassembler_usage): Add ARC disassembler
810 options.
811
92281a5b
MR		 8122016-07-13 Maciej W. Rozycki <macro@imgtec.com>
813
814 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
815 annotation from the "nal" entry and reorder it beyond "bltzal".
816
6e7ced37
JM		 8172016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
818
819 * sparc-opc.c (ldtxa): New macro.
820 (sparc_opcodes): Use the macro defined above to add entries for
821 the LDTXA instructions.
822 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
823 instruction.
824
2f831b9a 8252016-07-07 James Bowman <james.bowman@ftdichip.com>
826
827 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
828 and "jmpc".
829
c07315e0
JB		 8302016-07-01 Jan Beulich <jbeulich@suse.com>
831
832 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
833 (movzb): Adjust to cover all permitted suffixes.
834 (movzw): New.
835 * i386-tbl.h: Re-generate.
836
9243100a
JB		 8372016-07-01 Jan Beulich <jbeulich@suse.com>
838
839 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
840 (lgdt): Remove Tbyte from non-64-bit variant.
841 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
842 xsaves64, xsavec64): Remove Disp16.
843 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
844 Remove Disp32S from non-64-bit variants. Remove Disp16 from
845 64-bit variants.
846 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
847 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
848 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
849 64-bit variants.
850 * i386-tbl.h: Re-generate.
851
8325cc63
JB		 8522016-07-01 Jan Beulich <jbeulich@suse.com>
853
854 * i386-opc.tbl (xlat): Remove RepPrefixOk.
855 * i386-tbl.h: Re-generate.
856
838441e4
YQ		 8572016-06-30 Yao Qi <yao.qi@linaro.org>
858
859 * arm-dis.c (print_insn): Fix typo in comment.
860
dab26bf4
RS		 8612016-06-28 Richard Sandiford <richard.sandiford@arm.com>
862
863 * aarch64-opc.c (operand_general_constraint_met_p): Check the
864 range of ldst_elemlist operands.
865 (print_register_list): Use PRIi64 to print the index.
866 (aarch64_print_operand): Likewise.
867
5703197e
TS		 8682016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
869
870 * mcore-opc.h: Remove sentinal.
871 * mcore-dis.c (print_insn_mcore): Adjust.
872
ce440d63
GM		 8732016-06-23 Graham Markall <graham.markall@embecosm.com>
874
875 * arc-opc.c: Correct description of availability of NPS400
876 features.
877
6fd3a02d
PB		 8782016-06-22 Peter Bergner <bergner@vnet.ibm.com>
879
880 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
881 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
882 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
883 xor3>: New mnemonics.
884 <setb>: Change to a VX form instruction.
885 (insert_sh6): Add support for rldixor.
886 (extract_sh6): Likewise.
887
6b477896
TS		 8882016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
889
890 * arc-ext.h: Wrap in extern C.
891
bdd582db
GM		 8922016-06-21 Graham Markall <graham.markall@embecosm.com>
893
894 * arc-dis.c (arc_insn_length): Add comment on instruction length.
895 Use same method for determining instruction length on ARC700 and
896 NPS-400.
897 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
898 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
899 with the NPS400 subclass.
900 * arc-opc.c: Likewise.
901
96074adc
JM		 9022016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
903
904 * sparc-opc.c (rdasr): New macro.
905 (wrasr): Likewise.
906 (rdpr): Likewise.
907 (wrpr): Likewise.
908 (rdhpr): Likewise.
909 (wrhpr): Likewise.
910 (sparc_opcodes): Use the macros above to fix and expand the
911 definition of read/write instructions from/to
912 asr/privileged/hyperprivileged instructions.
913 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
914 %hva_mask_nz. Prefer softint_set and softint_clear over
915 set_softint and clear_softint.
916 (print_insn_sparc): Support %ver in Rd.
917
7a10c22f
JM		 9182016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
919
920 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
921 architecture according to the hardware capabilities they require.
922
4f26fb3a
JM		 9232016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
924
925 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
926 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
927 bfd_mach_sparc_v9{c,d,e,v,m}.
928 * sparc-opc.c (MASK_V9C): Define.
929 (MASK_V9D): Likewise.
930 (MASK_V9E): Likewise.
931 (MASK_V9V): Likewise.
932 (MASK_V9M): Likewise.
933 (v6): Add MASK_V9{C,D,E,V,M}.
934 (v6notlet): Likewise.
935 (v7): Likewise.
936 (v8): Likewise.
937 (v9): Likewise.
938 (v9andleon): Likewise.
939 (v9a): Likewise.
940 (v9b): Likewise.
941 (v9c): Define.
942 (v9d): Likewise.
943 (v9e): Likewise.
944 (v9v): Likewise.
945 (v9m): Likewise.
946 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
947
3ee6e4fb
NC		 9482016-06-15 Nick Clifton <nickc@redhat.com>
949
950 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
951 constants to match expected behaviour.
952 (nds32_parse_opcode): Likewise. Also for whitespace.
953
02f3be19
AB		 9542016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
955
956 * arc-opc.c (extract_rhv1): Extract value from insn.
957
6f9f37ed 9582016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 959
960 * arc-nps400-tbl.h: Add ldbit instruction.
961 * arc-opc.c: Add flag classes required for ldbit.
962
6f9f37ed 9632016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 964
965 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
966 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
967 support the above instructions.
968
6f9f37ed 9692016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 970
971 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
972 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
973 csma, cbba, zncv, and hofs.
974 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
975 support the above instructions.
976
9772016-06-06 Graham Markall <graham.markall@embecosm.com>
978
979 * arc-nps400-tbl.h: Add andab and orab instructions.
980
9812016-06-06 Graham Markall <graham.markall@embecosm.com>
982
983 * arc-nps400-tbl.h: Add addl-like instructions.
984
9852016-06-06 Graham Markall <graham.markall@embecosm.com>
986
987 * arc-nps400-tbl.h: Add mxb and imxb instructions.
988
9892016-06-06 Graham Markall <graham.markall@embecosm.com>
990
991 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
992 instructions.
993
b2cc3f6f
AK		 9942016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
995
996 * s390-dis.c (option_use_insn_len_bits_p): New file scope
997 variable.
998 (init_disasm): Handle new command line option "insnlength".
999 (print_s390_disassembler_options): Mention new option in help
1000 output.
1001 (print_insn_s390): Use the encoded insn length when dumping
1002 unknown instructions.
1003
1857fe72
DC		 10042016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
1005
1006 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
1007 to the address and set as symbol address for LDS/ STS immediate operands.
1008
14b57c7c
AM		 10092016-06-07 Alan Modra <amodra@gmail.com>
1010
1011 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
1012 cpu for "vle" to e500.
1013 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
1014 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
1015 (PPCNONE): Delete, substitute throughout.
1016 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
1017 except for major opcode 4 and 31.
1018 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
1019
4d1464f2
MW		 10202016-06-07 Matthew Wahab <matthew.wahab@arm.com>
1021
1022 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
1023 ARM_EXT_RAS in relevant entries.
1024
026122a6
PB		 10252016-06-03 Peter Bergner <bergner@vnet.ibm.com>
1026
1027 PR binutils/20196
1028 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
1029 opcodes for E6500.
1030
07f5af7d
L		 10312016-06-03 H.J. Lu <hongjiu.lu@intel.com>
1032
1033 PR binutis/18386
1034 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
1035 (indir_v_mode): New.
1036 Add comments for '&'.
1037 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
1038 (putop): Handle '&'.
1039 (intel_operand_size): Handle indir_v_mode.
1040 (OP_E_register): Likewise.
1041 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
1042 64-bit indirect call/jmp for AMD64.
1043 * i386-tbl.h: Regenerated
1044
4eb6f892
AB		 10452016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
1046
1047 * arc-dis.c (struct arc_operand_iterator): New structure.
1048 (find_format_from_table): All the old content from find_format,
1049 with some minor adjustments, and parameter renaming.
1050 (find_format_long_instructions): New function.
1051 (find_format): Rewritten.
1052 (arc_insn_length): Add LSB parameter.
1053 (extract_operand_value): New function.
1054 (operand_iterator_next): New function.
1055 (print_insn_arc): Use new functions to find opcode, and iterator
1056 over operands.
1057 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1058 (extract_nps_3bit_dst_short): New function.
1059 (insert_nps_3bit_src2_short): New function.
1060 (extract_nps_3bit_src2_short): New function.
1061 (insert_nps_bitop1_size): New function.
1062 (extract_nps_bitop1_size): New function.
1063 (insert_nps_bitop2_size): New function.
1064 (extract_nps_bitop2_size): New function.
1065 (insert_nps_bitop_mod4_msb): New function.
1066 (extract_nps_bitop_mod4_msb): New function.
1067 (insert_nps_bitop_mod4_lsb): New function.
1068 (extract_nps_bitop_mod4_lsb): New function.
1069 (insert_nps_bitop_dst_pos3_pos4): New function.
1070 (extract_nps_bitop_dst_pos3_pos4): New function.
1071 (insert_nps_bitop_ins_ext): New function.
1072 (extract_nps_bitop_ins_ext): New function.
1073 (arc_operands): Add new operands.
1074 (arc_long_opcodes): New global array.
1075 (arc_num_long_opcodes): New global.
1076 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1077
1fe0971e
TS		 10782016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1079
1080 * nds32-asm.h: Add extern "C".
1081 * sh-opc.h: Likewise.
1082
315f180f
GM		 10832016-06-01 Graham Markall <graham.markall@embecosm.com>
1084
1085 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1086 0,b,limm to the rflt instruction.
1087
a2b5fccc
TS		 10882016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1089
1090 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1091 constant.
1092
0cbd0046
L		 10932016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1094
1095 PR gas/20145
1096 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1097 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1098 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1099 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1100 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1101 * i386-init.h: Regenerated.
1102
1848e567
L		 11032016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1104
1105 PR gas/20145
1106 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1107 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1108 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1109 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1110 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1111 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1112 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1113 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1114 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1115 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1116 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1117 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1118 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1119 CpuRegMask for AVX512.
1120 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1121 and CpuRegMask.
1122 (set_bitfield_from_cpu_flag_init): New function.
1123 (set_bitfield): Remove const on f. Call
1124 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1125 * i386-opc.h (CpuRegMMX): New.
1126 (CpuRegXMM): Likewise.
1127 (CpuRegYMM): Likewise.
1128 (CpuRegZMM): Likewise.
1129 (CpuRegMask): Likewise.
1130 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1131 and cpuregmask.
1132 * i386-init.h: Regenerated.
1133 * i386-tbl.h: Likewise.
1134
e92bae62
L		 11352016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1136
1137 PR gas/20154
1138 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1139 (opcode_modifiers): Add AMD64 and Intel64.
1140 (main): Properly verify CpuMax.
1141 * i386-opc.h (CpuAMD64): Removed.
1142 (CpuIntel64): Likewise.
1143 (CpuMax): Set to CpuNo64.
1144 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1145 (AMD64): New.
1146 (Intel64): Likewise.
1147 (i386_opcode_modifier): Add amd64 and intel64.
1148 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1149 on call and jmp.
1150 * i386-init.h: Regenerated.
1151 * i386-tbl.h: Likewise.
1152
e89c5eaa
L		 11532016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1154
1155 PR gas/20154
1156 * i386-gen.c (main): Fail if CpuMax is incorrect.
1157 * i386-opc.h (CpuMax): Set to CpuIntel64.
1158 * i386-tbl.h: Regenerated.
1159
77d66e7b
NC		 11602016-05-27 Nick Clifton <nickc@redhat.com>
1161
1162 PR target/20150
1163 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1164 (msp430dis_opcode_unsigned): New function.
1165 (msp430dis_opcode_signed): New function.
1166 (msp430_singleoperand): Use the new opcode reading functions.
1167 Only disassenmble bytes if they were successfully read.
1168 (msp430_doubleoperand): Likewise.
1169 (msp430_branchinstr): Likewise.
1170 (msp430x_callx_instr): Likewise.
1171 (print_insn_msp430): Check that it is safe to read bytes before
1172 attempting disassembly. Use the new opcode reading functions.
1173
19dfcc89
PB		 11742016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1175
1176 * ppc-opc.c (CY): New define. Document it.
1177 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1178
f3ad7637
L		 11792016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1180
1181 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1182 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1183 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1184 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1185 CPU_ANY_AVX_FLAGS.
1186 * i386-init.h: Regenerated.
1187
f1360d58
L		 11882016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1189
1190 PR gas/20141
1191 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1192 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1193 * i386-init.h: Regenerated.
1194
293f5f65
L		 11952016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1196
1197 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1198 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1199 * i386-init.h: Regenerated.
1200
d9eca1df
CZ		 12012016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1202
1203 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1204 information.
1205 (print_insn_arc): Set insn_type information.
1206 * arc-opc.c (C_CC): Add F_CLASS_COND.
1207 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1208 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1209 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1210 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1211 (brne, brne_s, jeq_s, jne_s): Likewise.
1212
87789e08
CZ		 12132016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1214
1215 * arc-tbl.h (neg): New instruction variant.
1216
c810e0b8
CZ		 12172016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1218
1219 * arc-dis.c (find_format, find_format, get_auxreg)
1220 (print_insn_arc): Changed.
1221 * arc-ext.h (INSERT_XOP): Likewise.
1222
3d207518
TS		 12232016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1224
1225 * tic54x-dis.c (sprint_mmr): Adjust.
1226 * tic54x-opc.c: Likewise.
1227
514e58b7
AM		 12282016-05-19 Alan Modra <amodra@gmail.com>
1229
1230 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1231
e43de63c
AM		 12322016-05-19 Alan Modra <amodra@gmail.com>
1233
1234 * ppc-opc.c: Formatting.
1235 (NSISIGNOPT): Define.
1236 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1237
1401d2fe
MR		 12382016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1239
1240 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1241 replacing references to `micromips_ase' throughout.
1242 (_print_insn_mips): Don't use file-level microMIPS annotation to
1243 determine the disassembly mode with the symbol table.
1244
1178da44
PB		 12452016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1246
1247 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1248
8f4f9071
MF		 12492016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1250
1251 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1252 mips64r6.
1253 * mips-opc.c (D34): New macro.
1254 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1255
8bc52696
AF		 12562016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1257
1258 * i386-dis.c (prefix_table): Add RDPID instruction.
1259 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1260 (cpu_flags): Add RDPID bitfield.
1261 * i386-opc.h (enum): Add RDPID element.
1262 (i386_cpu_flags): Add RDPID field.
1263 * i386-opc.tbl: Add RDPID instruction.
1264 * i386-init.h: Regenerate.
1265 * i386-tbl.h: Regenerate.
1266
39d911fc
TP		 12672016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1268
1269 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1270 branch type of a symbol.
1271 (print_insn): Likewise.
1272
16a1fa25
TP		 12732016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1274
1275 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1276 Mainline Security Extensions instructions.
1277 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1278 Extensions instructions.
1279 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1280 instructions.
1281 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1282 special registers.
1283
d751b79e
JM		 12842016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1285
1286 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1287
945e0f82
CZ		 12882016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1289
1290 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1291 (arcExtMap_genOpcode): Likewise.
1292 * arc-opc.c (arg_32bit_rc): Define new variable.
1293 (arg_32bit_u6): Likewise.
1294 (arg_32bit_limm): Likewise.
1295
20f55f38
SN		 12962016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1297
1298 * aarch64-gen.c (VERIFIER): Define.
1299 * aarch64-opc.c (VERIFIER): Define.
1300 (verify_ldpsw): Use static linkage.
1301 * aarch64-opc.h (verify_ldpsw): Remove.
1302 * aarch64-tbl.h: Use VERIFIER for verifiers.
1303
4bd13cde
NC		 13042016-04-28 Nick Clifton <nickc@redhat.com>
1305
1306 PR target/19722
1307 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1308 * aarch64-opc.c (verify_ldpsw): New function.
1309 * aarch64-opc.h (verify_ldpsw): New prototype.
1310 * aarch64-tbl.h: Add initialiser for verifier field.
1311 (LDPSW): Set verifier to verify_ldpsw.
1312
c0f92bf9
L		 13132016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1314
1315 PR binutils/19983
1316 PR binutils/19984
1317 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1318 smaller than address size.
1319
e6c7cdec
TS		 13202016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1321
1322 * alpha-dis.c: Regenerate.
1323 * crx-dis.c: Likewise.
1324 * disassemble.c: Likewise.
1325 * epiphany-opc.c: Likewise.
1326 * fr30-opc.c: Likewise.
1327 * frv-opc.c: Likewise.
1328 * ip2k-opc.c: Likewise.
1329 * iq2000-opc.c: Likewise.
1330 * lm32-opc.c: Likewise.
1331 * lm32-opinst.c: Likewise.
1332 * m32c-opc.c: Likewise.
1333 * m32r-opc.c: Likewise.
1334 * m32r-opinst.c: Likewise.
1335 * mep-opc.c: Likewise.
1336 * mt-opc.c: Likewise.
1337 * or1k-opc.c: Likewise.
1338 * or1k-opinst.c: Likewise.
1339 * tic80-opc.c: Likewise.
1340 * xc16x-opc.c: Likewise.
1341 * xstormy16-opc.c: Likewise.
1342
537aefaf
AB		 13432016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1344
1345 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1346 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1347 calcsd, and calcxd instructions.
1348 * arc-opc.c (insert_nps_bitop_size): Delete.
1349 (extract_nps_bitop_size): Delete.
1350 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1351 (extract_nps_qcmp_m3): Define.
1352 (extract_nps_qcmp_m2): Define.
1353 (extract_nps_qcmp_m1): Define.
1354 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1355 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1356 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1357 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1358 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1359 NPS_QCMP_M3.
1360
c8f785f2
AB		 13612016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1362
1363 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1364
6fd8e7c2
L		 13652016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1366
1367 * Makefile.in: Regenerated with automake 1.11.6.
1368 * aclocal.m4: Likewise.
1369
4b0c052e
AB		 13702016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1371
1372 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1373 instructions.
1374 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1375 (extract_nps_cmem_uimm16): New function.
1376 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1377
cb040366
AB		 13782016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1379
1380 * arc-dis.c (arc_insn_length): New function.
1381 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1382 (find_format): Change insnLen parameter to unsigned.
1383
accc0180
NC		 13842016-04-13 Nick Clifton <nickc@redhat.com>
1385
1386 PR target/19937
1387 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1388 the LD.B and LD.BU instructions.
1389
f36e33da
CZ		 13902016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1391
1392 * arc-dis.c (find_format): Check for extension flags.
1393 (print_flags): New function.
1394 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1395 .extAuxRegister.
1396 * arc-ext.c (arcExtMap_coreRegName): Use
1397 LAST_EXTENSION_CORE_REGISTER.
1398 (arcExtMap_coreReadWrite): Likewise.
1399 (dump_ARC_extmap): Update printing.
1400 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1401 (arc_aux_regs): Add cpu field.
1402 * arc-regs.h: Add cpu field, lower case name aux registers.
1403
1c2e355e
CZ		 14042016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1405
1406 * arc-tbl.h: Add rtsc, sleep with no arguments.
1407
b99747ae
CZ		 14082016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1409
1410 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1411 Initialize.
1412 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1413 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1414 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1415 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1416 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1417 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1418 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1419 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1420 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1421 (arc_opcode arc_opcodes): Null terminate the array.
1422 (arc_num_opcodes): Remove.
1423 * arc-ext.h (INSERT_XOP): Define.
1424 (extInstruction_t): Likewise.
1425 (arcExtMap_instName): Delete.
1426 (arcExtMap_insn): New function.
1427 (arcExtMap_genOpcode): Likewise.
1428 * arc-ext.c (ExtInstruction): Remove.
1429 (create_map): Zero initialize instruction fields.
1430 (arcExtMap_instName): Remove.
1431 (arcExtMap_insn): New function.
1432 (dump_ARC_extmap): More info while debuging.
1433 (arcExtMap_genOpcode): New function.
1434 * arc-dis.c (find_format): New function.
1435 (print_insn_arc): Use find_format.
1436 (arc_get_disassembler): Enable dump_ARC_extmap only when
1437 debugging.
1438
92708cec
MR		 14392016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1440
1441 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1442 instruction bits out.
1443
a42a4f84
AB		 14442016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1445
1446 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1447 * arc-opc.c (arc_flag_operands): Add new flags.
1448 (arc_flag_classes): Add new classes.
1449
1328504b
AB		 14502016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1451
1452 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1453
820f03ff
AB		 14542016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1455
1456 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1457 encode1, rflt, crc16, and crc32 instructions.
1458 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1459 (arc_flag_classes): Add C_NPS_R.
1460 (insert_nps_bitop_size_2b): New function.
1461 (extract_nps_bitop_size_2b): Likewise.
1462 (insert_nps_bitop_uimm8): Likewise.
1463 (extract_nps_bitop_uimm8): Likewise.
1464 (arc_operands): Add new operand entries.
1465
8ddf6b2a
CZ		 14662016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1467
b99747ae
CZ		 1468 * arc-regs.h: Add a new subclass field. Add double assist
1469 accumulator register values.
1470 * arc-tbl.h: Use DPA subclass to mark the double assist
1471 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1472 * arc-opc.c (RSP): Define instead of SP.
1473 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1474
589a7d88
JW		 14752016-04-05 Jiong Wang <jiong.wang@arm.com>
1476
1477 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1478
0a191de9 14792016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1480
1481 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1482 NPS_R_SRC1.
1483
0a106562
AB		 14842016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1485
1486 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1487 issues. No functional changes.
1488
bd05ac5f
CZ		 14892016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1490
b99747ae
CZ		 1491 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1492 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1493 (RTT): Remove duplicate.
1494 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1495 (PCT_CONFIG*): Remove.
1496 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1497
9885948f
CZ		 14982016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1499
b99747ae 1500 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1501
f2dd8838
CZ		 15022016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1503
b99747ae
CZ		 1504 * arc-tbl.h (invld07): Remove.
1505 * arc-ext-tbl.h: New file.
1506 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1507 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1508
0d2f91fe
JK		 15092016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1510
1511 Fix -Wstack-usage warnings.
1512 * aarch64-dis.c (print_operands): Substitute size.
1513 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1514
a6b71f42
JM		 15152016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1516
1517 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1518 to get a proper diagnostic when an invalid ASR register is used.
1519
9780e045
NC		 15202016-03-22 Nick Clifton <nickc@redhat.com>
1521
1522 * configure: Regenerate.
1523
e23e8ebe
AB		 15242016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1525
1526 * arc-nps400-tbl.h: New file.
1527 * arc-opc.c: Add top level comment.
1528 (insert_nps_3bit_dst): New function.
1529 (extract_nps_3bit_dst): New function.
1530 (insert_nps_3bit_src2): New function.
1531 (extract_nps_3bit_src2): New function.
1532 (insert_nps_bitop_size): New function.
1533 (extract_nps_bitop_size): New function.
1534 (arc_flag_operands): Add nps400 entries.
1535 (arc_flag_classes): Add nps400 entries.
1536 (arc_operands): Add nps400 entries.
1537 (arc_opcodes): Add nps400 include.
1538
1ae8ab47
AB		 15392016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1540
1541 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1542 the new class enum values.
1543
8699fc3e
AB		 15442016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1545
1546 * arc-dis.c (print_insn_arc): Handle nps400.
1547
24740d83
AB		 15482016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1549
1550 * arc-opc.c (BASE): Delete.
1551
8678914f
NC		 15522016-03-18 Nick Clifton <nickc@redhat.com>
1553
1554 PR target/19721
1555 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1556 of MOV insn that aliases an ORR insn.
1557
cc933301
JW		 15582016-03-16 Jiong Wang <jiong.wang@arm.com>
1559
1560 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1561
f86f5863
TS		 15622016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1563
1564 * mcore-opc.h: Add const qualifiers.
1565 * microblaze-opc.h (struct op_code_struct): Likewise.
1566 * sh-opc.h: Likewise.
1567 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1568 (tic4x_print_op): Likewise.
1569
62de1c63
AM		 15702016-03-02 Alan Modra <amodra@gmail.com>
1571
d11698cd 1572 * or1k-desc.h: Regenerate.
62de1c63 1573 * fr30-ibld.c: Regenerate.
c697cf0b 1574 * rl78-decode.c: Regenerate.
62de1c63 1575
020efce5
NC		 15762016-03-01 Nick Clifton <nickc@redhat.com>
1577
1578 PR target/19747
1579 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1580
b0c11777
RL		 15812016-02-24 Renlin Li <renlin.li@arm.com>
1582
1583 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1584 (print_insn_coprocessor): Support fp16 instructions.
1585
3e309328
RL		 15862016-02-24 Renlin Li <renlin.li@arm.com>
1587
1588 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1589 vminnm, vrint(mpna).
1590
8afc7bea
RL		 15912016-02-24 Renlin Li <renlin.li@arm.com>
1592
1593 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1594 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1595
4fd7268a
L		 15962016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1597
1598 * i386-dis.c (print_insn): Parenthesize expression to prevent
1599 truncated addresses.
1600 (OP_J): Likewise.
1601
4670103e
CZ		 16022016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1603 Janek van Oirschot <jvanoirs@synopsys.com>
1604
b99747ae
CZ		 1605 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1606 variable.
4670103e 1607
c1d9289f
NC		 16082016-02-04 Nick Clifton <nickc@redhat.com>
1609
1610 PR target/19561
1611 * msp430-dis.c (print_insn_msp430): Add a special case for
1612 decoding an RRC instruction with the ZC bit set in the extension
1613 word.
1614
a143b004
AB		 16152016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1616
1617 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1618 * epiphany-ibld.c: Regenerate.
1619 * fr30-ibld.c: Regenerate.
1620 * frv-ibld.c: Regenerate.
1621 * ip2k-ibld.c: Regenerate.
1622 * iq2000-ibld.c: Regenerate.
1623 * lm32-ibld.c: Regenerate.
1624 * m32c-ibld.c: Regenerate.
1625 * m32r-ibld.c: Regenerate.
1626 * mep-ibld.c: Regenerate.
1627 * mt-ibld.c: Regenerate.
1628 * or1k-ibld.c: Regenerate.
1629 * xc16x-ibld.c: Regenerate.
1630 * xstormy16-ibld.c: Regenerate.
1631
b89807c6
AB		 16322016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1633
1634 * epiphany-dis.c: Regenerated from latest cpu files.
1635
d8c823c8
MM		 16362016-02-01 Michael McConville <mmcco@mykolab.com>
1637
1638 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1639 test bit.
1640
5bc5ae88
RL		 16412016-01-25 Renlin Li <renlin.li@arm.com>
1642
1643 * arm-dis.c (mapping_symbol_for_insn): New function.
1644 (find_ifthen_state): Call mapping_symbol_for_insn().
1645
0bff6e2d
MW		 16462016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1647
1648 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1649 of MSR UAO immediate operand.
1650
100b4f2e
MR		 16512016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1652
1653 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1654 instruction support.
1655
5c14705f
AM		 16562016-01-17 Alan Modra <amodra@gmail.com>
1657
1658 * configure: Regenerate.
1659
4d82fe66
NC		 16602016-01-14 Nick Clifton <nickc@redhat.com>
1661
1662 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1663 instructions that can support stack pointer operations.
1664 * rl78-decode.c: Regenerate.
1665 * rl78-dis.c: Fix display of stack pointer in MOVW based
1666 instructions.
1667
651657fa
MW		 16682016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1669
1670 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1671 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1672 erxtatus_el1 and erxaddr_el1.
1673
105bde57
MW		 16742016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1675
1676 * arm-dis.c (arm_opcodes): Add "esb".
1677 (thumb_opcodes): Likewise.
1678
afa8d405
PB		 16792016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1680
1681 * ppc-opc.c <xscmpnedp>: Delete.
1682 <xvcmpnedp>: Likewise.
1683 <xvcmpnedp.>: Likewise.
1684 <xvcmpnesp>: Likewise.
1685 <xvcmpnesp.>: Likewise.
1686
83c3256e
AS		 16872016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1688
1689 PR gas/13050
1690 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1691 addition to ISA_A.
1692
6f2750fe
AM		 16932016-01-01 Alan Modra <amodra@gmail.com>
1694
1695 Update year range in copyright notice of all files.
1696
3499769a
AM		 1697For older changes see ChangeLog-2015
1698\f
1699Copyright (C) 2016 Free Software Foundation, Inc.
1700
1701Copying and distribution of this file, with or without modification,
1702are permitted in any medium without royalty provided the copyright
1703notice and this notice are preserved.
1704
1705Local Variables:
1706mode: change-log
1707left-margin: 8
1708fill-column: 74
1709version-control: never
1710End:
GDB Binutils - Deliverables
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