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[deliverable/binutils-gdb.git] / opcodes / ChangeLog
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d3da7741
ME		 12012-11-14 David Holsgrove <david.holsgrove@xilinx.com>
2
3 * microblaze-opc.h: Define new instruction type INST_TYPE_IMM5,
4 update OPCODE_MASK_H13S, add OPCODE_MASK_HN, define MIN_IMM5 / MAX_IMM5,
5 and increase MAX_OPCODES.
6 (op_code_struct): add mbar and sleep
7 * microblaze-opcm.h (microblaze_instr): add mbar
8 Define IMM_MBAR and IMM5_MBAR_MASK
9 * microblaze-dis.c: Add get_field_imm5_mbar
10 (print_insn_microblaze): Add support for INST_TYPE_IMM5 and INST_TYPE_NONE
11
ed8ec0ec
ME		 122012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
13
14 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add clz insn
15 * microblaze-opcm.h (microblaze_instr): add clz
16
e692c217
ME		 172012-11-14 Edgar E. Iglesias <edgar.iglesias@gmail.com>
18
19 * microblaze-opc.h: Increase MAX_OPCODES (op_code_struct): add lbur,
20 lhur, lwr, sbr, shr, swr
21 * microblaze-opcm.h (microblaze_instr): add lbur, lhur, lwr, sbr, shr,
22 swr
23
de863c74
NC		 242012-11-09 Nick Clifton <nickc@redhat.com>
25
26 * configure.in: Add bfd_v850_rh850_arch.
27 * configure: Regenerate.
28 * disassemble.c (disassembler): Likewise.
29
5bb3703f
L		 302012-11-09 H.J. Lu <hongjiu.lu@intel.com>
31
32 * aarch64-opc.h (gen_mask): Remove trailing redundant `;'.
33 * ia64-gen.c (fetch_insn_class): Likewise.
34
6febeb74
AM		 352012-11-08 Alan Modra <amodra@gmail.com>
36
37 * po/POTFILES.in: Regenerate.
38
d17dce55
AM		 392012-11-05 Alan Modra <amodra@gmail.com>
40
41 * configure.in: Apply 2012-09-10 change to config.in here.
42
aac129d7
AK		 432012-10-26 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
44
45 * s390-mkopc.c: Accept empty lines in s390-opc.txt.
d17dce55
AM		 46 * s390-opc.c: Add M_20OPT field. New instruction formats RRF_RURR2
47 and RRF_RMRR.
aac129d7
AK		 48 * s390-opc.txt: Add new instructions. New instruction type for lptea.
49
747a4ac1
CG		 502012-10-26 Christian Groessler <chris@groessler.org>
51
52 * z8kgen.c (struct op): Fix encoding for translate opcodes (trdb,
53 trdrb, trib, trirb, trtdb, trtdrb, trtib, trtirb). Remove
54 non-existing opcode trtrb.
55 * z8k-opc.h: Regenerate.
56
62082a42
AM		 572012-10-26 Alan Modra <amodra@gmail.com>
58
59 * ppc-opc (powerpc_opcodes): "lfdp" and "stfdp" use DS offset.
60
6c067bbb
RM		 612012-10-24 Roland McGrath <mcgrathr@google.com>
62
63 * i386-dis.c (ckprefix): When bailing out for fwait with prefixes,
64 set rex_used to rex.
65
ab4437c3
PB		 662012-10-22 Peter Bergner <bergner@vnet.ibm.com>
67
68 * ppc-opc.c (powerpc_opcodes) <vcfpsxws>: Fix opcode spelling.
69
9a176a4a
TT		 702012-10-18 Tom Tromey <tromey@redhat.com>
71
72 * tic54x-dis.c (print_instruction): Don't use K&R style.
73 (print_parallel_instruction, sprint_dual_address)
74 (sprint_indirect_address, sprint_direct_address, sprint_mmr)
75 (sprint_cc2, sprint_condition): Likewise.
76
4ad3b7ef
KT		 772012-10-18 Kai Tietz <ktietz@redhat.com>
78
79 * aarch64-asm.c (aarch64_ins_ldst_reglist): Initialize
80 value with a default.
81 (do_special_encoding): Likewise.
82 (aarch64_ins_ldst_elemlist): Pre-initialize QSsize, and opcodeh2
83 variables with default.
84 * arc-dis.c (write_comments_): Don't use strncat due
85 size of state->commentBuffer pointer isn't predictable.
86
b7a54b55
YZ		 872012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
88
89 * aarch64-opc.c (aarch64_sys_regs): Add rmr_el1, rmr_el2 and
90 rmr_el3; remove daifset and daifclr.
91
9b61754a
YZ		 922012-10-15 Yufeng Zhang <yufeng.zhang@arm.com>
93
94 * aarch64-opc.c (operand_general_constraint_met_p): Change to check
95 the alignment of addr.offset.imm instead of that of shifter.amount for
96 operand type AARCH64_OPND_ADDR_UIMM12.
97
f8ece37f
RE		 982012-10-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
99
100 * arm-dis.c: Use preferred form of vrint instruction variants
101 for disassembly.
102
5e5c50d3
NE		 1032012-10-09 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
104
105 * i386-gen.c (cpu_flag_init): Add CPU_BDVER3_FLAGS.
106 * i386-init.h: Regenerated.
107
c7a5aa9c
PB		 1082012-10-05 Peter Bergner <bergner@vnet.ibm.com>
109
110 * ppc-dis.c (ppc_opts) <altivec>: Use PPC_OPCODE_ALTIVEC2;
111 * ppc-opc.c (VBA): New define.
112 (powerpc_opcodes) <vcuxwfp, vcsxwfp, vcfpuxws, vcfpsxsw, vmr, vnot,
113 mfppr, mfppr32, mtppr, mtppr32>: New extended mnemonics.
114
04ee5257
NC		 1152012-10-04 Nick Clifton <nickc@redhat.com>
116
117 * v850-dis.c (disassemble): Place square parentheses around second
118 register operand of clr1, not1, set1 and tst1 instructions.
119
cfc72779
AK		 1202012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
121
122 * s390-mkopc.c: Support new option zEC12.
123 * s390-opc.c: Add new instruction formats.
124 * s390-opc.txt: Add new instructions for zEC12.
125
1415a2a7
AG		 1262012-09-27 Anthony Green <green@moxielogic.com>
127
128 * moxie-dis.c (print_insn_moxie): Print 'bad' instructions.
129 * moxie-opc.c: All 'bad' instructions have the itype MOXIE_BAD.
130
160a30bb
L		 1312012-09-25 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
132
04ee5257
NC		 133 * i386-gen.c (cpu_flag_init): Add missing Cpu flags in
134 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS
160a30bb
L		 135 and CPU_BTVER2_FLAGS.
136 * i386-init.h: Regenerated.
137
60aa667e
L		 1382012-09-20 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
139
140 * i386-gen.c (cpu_flag_init): Add CpuCX16 to CPU_NOCONA_FLAGS,
141 CPU_CORE_FLAGS, CPU_CORE2_FLAGS, CPU_COREI7_FLAGS,
142 CPU_BDVER1_FLAGS, CPU_BDVER2_FLAGS, CPU_BTVER1_FLAGS,
143 CPU_BTVER2_FLAGS. Add CPU_CX16_FLAGS.
144 (cpu_flags): Add CpuCX16.
145 * i386-opc.h (CpuCX16): New.
146 (i386_cpu_flags): Add cpucx16.
147 * i386-opc.tbl: Replace CpuSSE3 with CpuCX16 for cmpxchg16b.
148 * i386-tbl.h: Regenerate.
149 * i386-init.h: Likewise.
150
4b8c8c02
RE		 1512012-09-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
152
60aa667e 153 * arm-dis.c: Changed ldra and strl-form mnemonics
4b8c8c02
RE		 154 to lda and stl-form.
155
83ea18d0
MR		 1562012-09-18 Chao-ying Fu <fu@mips.com>
157
158 * micromips-opc.c (micromips_opcodes): Correct the encoding of
159 the "swxc1" instruction.
160
062f38fa
RE		 1612012-09-17 Yufeng Zhang <yufeng.zhang@arm.com>
162
163 * aarch64-asm.c (aarch64_ins_imm_half): Remove ATTRIBUTE_UNUSED from
164 the parameter 'inst'.
165 (aarch64_ins_addr_simm): Add ATTRIBUTE_UNUSED to the parameter 'inst'.
166 (convert_mov_to_movewide): Change to assert (0) when
167 aarch64_wide_constant_p returns FALSE.
168
b132a67d
DE		 1692012-09-14 David Edelsohn <dje.gcc@gmail.com>
170
171 * configure: Regenerate.
172
1f9b75dd
AG		 1732012-09-14 Anthony Green <green@moxielogic.com>
174
175 * moxie-dis.c (print_insn_moxie): Branch targets are relative to
176 the address after the branch instruction.
177
e202fa84
AG		 1782012-09-13 Anthony Green <green@moxielogic.com>
179
180 * moxie-dis.c (print_insn_moxie): Handle bi-endian encodings.
181
00716ab1
AM		 1822012-09-10 Matthias Klose <doko@ubuntu.com>
183
184 * config.in: Disable sanity check for kfreebsd.
185
6d2920c8
L		 1862012-09-10 H.J. Lu <hongjiu.lu@intel.com>
187
188 * configure: Regenerated.
189
b3e14eda
L		 1902012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
191
192 * ia64-asmtab.h (completer_index): Extend bitfield to full uint.
193 * ia64-gen.c: Promote completer index type to longlong.
194 (irf_operand): Add new register recognition.
195 (in_iclass_mov_x): Add an entry for the new mov_* instruction type.
196 (lookup_specifier): Add new resource recognition.
197 (insert_bit_table_ent): Relax abort condition according to the
198 changed completer index type.
199 (print_dis_table): Fix printf format for completer index.
200 * ia64-ic.tbl: Add a new instruction class.
201 * ia64-opc-i.c (ia64_opcodes_i): Define new I-instructions.
202 * ia64-opc-m.c (ia64_opcodes_m): Define new M-instructions.
203 * ia64-opc.h: Define short names for new operand types.
204 * ia64-raw.tbl: Add new RAW resource for DAHR register.
205 * ia64-waw.tbl: Add new WAW resource for DAHR register.
206 * ia64-asmtab.c: Regenerate.
207
382c72e9
PB		 2082012-08-29 Peter Bergner <bergner@vnet.ibm.com>
209
210 * ppc-opc.c (VXASHB_MASK): New define.
211 (powerpc_opcodes) <vsldoi>: Use VXASHB_MASK.
212
fb048c26
PB		 2132012-08-28 Peter Bergner <bergner@vnet.ibm.com>
214
215 * ppc-opc.c (UIMM4, UIMM3, UIMM2, VXVA_MASK, VXVB_MASK, VXVAVB_MASK,
216 VXVDVA_MASK, VXUIMM4_MASK, VXUIMM3_MASK, VXUIMM2_MASK): New defines.
217 (powerpc_opcodes) <vexptefp, vlogefp, vrefp, vrfim, vrfin, vrfip,
218 vrfiz, vrsqrtefp, vupkhpx, vupkhsb, vupkhsh, vupklpx, vupklsb,
219 vupklsh>: Use VXVA_MASK.
220 <vspltisb, vspltish, vspltisw>: Use VXVB_MASK.
221 <mfvscr>: Use VXVAVB_MASK.
222 <mtvscr>: Use VXVDVA_MASK.
223 <vspltb>: Use VXUIMM4_MASK.
224 <vsplth>: Use VXUIMM3_MASK.
225 <vspltw>: Use VXUIMM2_MASK.
226
3c9017d2
MGD		 2272012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
228
229 * arm-dis.c (neon_opcodes): Add 2 operand sha instructions.
230
48adcd8e
MGD		 2312012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
232
233 * arm-dis.c (neon_opcodes): Add SHA 3-operand instructions.
234
4f51b4bd
MGD		 2352012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
236
237 * arm-dis.c (neon_opcodes): Handle VMULL.P64.
238
91ff7894
MGD		 2392012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
240
241 * arm-dis.c (neon_opcodes): Add support for AES instructions.
242
c70a8987
MGD		 2432012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
244
245 * arm-dis.c (coprocessor_opcodes): Add support for HP/DP
246 conversions.
247
30bdf752
MGD		 2482012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
249
250 * arm-dis.c (coprocessor_opcodes): Add VRINT.
251 (neon_opcodes): Likewise.
252
7e8e6784
MGD		 2532012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
254
255 * arm-dis.c (coprocessor_opcodes): Add support for new VCVT
256 variants.
257 (neon_opcodes): Likewise.
258
73924fbc
MGD		 2592012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
260
261 * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
262 (neon_opcodes): Likewise.
263
33399f07
MGD		 2642012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
265
266 * arm-dis.c (coprocessor_opcodes): Add VSEL.
267 (print_insn_coprocessor): Add new %<>c bitfield format
268 specifier.
269
9eb6c0f1
MGD		 2702012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
271
272 * arm-dis.c (arm_opcodes): Add LDRA/STRL instructions.
273 (thumb32_opcodes): Likewise.
274 (print_arm_insn): Add support for %<>T formatter.
275
8884b720
MGD		 2762012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
277
278 * arm-dis.c (arm_opcodes): Add HLT.
279 (thumb_opcodes): Likewise.
280
b79f7053
MGD		 2812012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
282
283 * arm-dis.c (thumb32_opcodes): Add DCPS instruction.
284
53c4b28b
MGD		 2852012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
286
287 * arm-dis.c (arm_opcodes): Add SEVL.
288 (thumb_opcodes): Likewise.
289 (thumb32_opcodes): Likewise.
290
e797f7e0
MGD		 2912012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
292
293 * arm-dis.c (data_barrier_option): New function.
294 (print_insn_arm): Use data_barrier_option.
295 (print_insn_thumb32): Use data_barrier_option.
296
e2efe87d
MGD		 2972012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com
298
299 * arm-dis.c (COND_UNCOND): New constant.
300 (print_insn_coprocessor): Add support for %u format specifier.
301 (print_insn_neon): Likewise.
302
2c63854f
DM		 3032012-08-21 David S. Miller <davem@davemloft.net>
304
305 * sparc-opc.c (4-argument crypto instructions): Fix encoding using
306 F3F4 macro.
307
e67ed0e8
AM		 3082012-08-20 Edmar Wienskoski <edmar@freescale.com>
309
310 * ppc-opc.c (powerpc_opcodes): Changed opcode for vabsdub,
311 vabsduh, vabsduw, mviwsplt.
312
7b458c12
L		 3132012-08-17 Nagajyothi Eggone <nagajyothi.eggone@amd.com>
314
315 * i386-gen.c (cpu_flag_init): Add CPU_BTVER1_FLAGS and
316 CPU_BTVER2_FLAGS.
317
e67ed0e8 318 * i386-opc.h: Update CpuPRFCHW comment.
7b458c12
L		 319
320 * i386-opc.tbl: Enable prefetch instruction for CpuPRFCHW.
321 * i386-init.h: Regenerated.
322 * i386-tbl.h: Likewise.
323
eb80cb87
NC		 3242012-08-17 Nick Clifton <nickc@redhat.com>
325
326 * po/uk.po: New Ukranian translation.
327 * configure.in (ALL_LINGUAS): Add uk.
328 * configure: Regenerate.
329
8baf7b78
PB		 3302012-08-16 Peter Bergner <bergner@vnet.ibm.com>
331
332 * ppc-opc.c (powerpc_opcodes) <"lswx">: Use RAX for the second and
333 RBX for the third operand.
334 <"lswi">: Use RAX for second and NBI for the third operand.
335
3d557b4c
DD		 3362012-08-15 DJ Delorie <dj@redhat.com>
337
338 * rl78-decode.opc (rl78_decode_opcode): Merge %e and %[01]
339 operands, so that data addresses can be corrected when not
340 ES-overridden.
341 * rl78-decode.c: Regenerate.
342 * rl78-dis.c (print_insn_rl78): Make order of modifiers
343 irrelevent. When the 'e' specifier is used on an operand and no
344 ES prefix is provided, adjust address to make it absolute.
345
588925d0
PB		 3462012-08-15 Peter Bergner <bergner@vnet.ibm.com>
347
348 * ppc-opc.c <RSQ, RTQ>: Use PPC_OPERAND_GPR.
349
9f6a6cc0
PB		 3502012-08-15 Peter Bergner <bergner@vnet.ibm.com>
351
352 * ppc-opc.c <xnop, yield, mdoio, mdoom>: New extended mnemonics.
353
fc8c4fd1
MR		 3542012-08-14 Maciej W. Rozycki <macro@codesourcery.com>
355
356 * mips-dis.c (print_insn_args): Add GET_OP and GET_OP_S local
357 macros, use local variables for info struct member accesses,
358 update the type of the variable used to hold the instruction
359 word.
360 (print_insn_mips, print_mips16_insn_arg): Likewise.
361 (print_insn_mips16): Add GET_OP and GET_OP_S local macros, use
362 local variables for info struct member accesses.
363 (print_insn_micromips): Add GET_OP_S local macro.
364 (_print_insn_mips): Update the type of the variable used to hold
365 the instruction word.
366
a06ea964 3672012-08-13 Ian Bolton <ian.bolton@arm.com>
e67ed0e8
AM		 368 Laurent Desnogues <laurent.desnogues@arm.com>
369 Jim MacArthur <jim.macarthur@arm.com>
370 Marcus Shawcroft <marcus.shawcroft@arm.com>
371 Nigel Stephens <nigel.stephens@arm.com>
372 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
373 Richard Earnshaw <rearnsha@arm.com>
374 Sofiane Naci <sofiane.naci@arm.com>
375 Tejas Belagod <tejas.belagod@arm.com>
376 Yufeng Zhang <yufeng.zhang@arm.com>
a06ea964
NC		 377
378 * Makefile.am: Add AArch64.
379 * Makefile.in: Regenerate.
380 * aarch64-asm.c: New file.
381 * aarch64-asm.h: New file.
382 * aarch64-dis.c: New file.
383 * aarch64-dis.h: New file.
384 * aarch64-gen.c: New file.
385 * aarch64-opc.c: New file.
386 * aarch64-opc.h: New file.
387 * aarch64-tbl.h: New file.
388 * configure.in: Add AArch64.
389 * configure: Regenerate.
390 * disassemble.c: Add AArch64.
391 * aarch64-asm-2.c: New file (automatically generated).
392 * aarch64-dis-2.c: New file (automatically generated).
393 * aarch64-opc-2.c: New file (automatically generated).
394 * po/POTFILES.in: Regenerate.
395
35d0a169
MR		 3962012-08-13 Maciej W. Rozycki <macro@codesourcery.com>
397
398 * micromips-opc.c (micromips_opcodes): Update comment.
399 * mips-opc.c (mips_builtin_opcodes): Likewise. Mark coprocessor
400 instructions for IOCT as appropriate.
401 * mips-dis.c (print_insn_mips): Replace OPCODE_IS_MEMBER with
402 opcode_is_member.
403 * configure.in: Substitute NO_WMISSING_FIELD_INITIALIZERS with
404 the result of a check for the -Wno-missing-field-initializers
405 GCC option.
406 * Makefile.am (NO_WMISSING_FIELD_INITIALIZERS): New variable.
407 (mips-opc.lo): Pass $(NO_WMISSING_FIELD_INITIALIZERS) to
408 compilation.
409 (mips16-opc.lo): Likewise.
410 (micromips-opc.lo): Likewise.
411 * aclocal.m4: Regenerate.
412 * configure: Regenerate.
413 * Makefile.in: Regenerate.
414
5c5acbbd
L		 4152012-08-11 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
416
417 PR gas/14423
418 * i386-gen.c (cpu_flag_init): Add CpuFMA in CPU_BDVER2_FLAGS.
419 * i386-init.h: Regenerated.
420
3c892704
NC		 4212012-08-09 Nick Clifton <nickc@redhat.com>
422
423 * po/vi.po: Updated Vietnamese translation.
424
d7189fa5
RM		 4252012-08-07 Roland McGrath <mcgrathr@google.com>
426
427 * i386-dis.c (reg_table): Fill out REG_0F0D table with
428 AMD-reserved cases as "prefetch".
429 (MOD_0F18_REG_4, MOD_0F18_REG_5): New enum constants.
430 (MOD_0F18_REG_6, MOD_0F18_REG_7): Likewise.
431 (reg_table): Use those under REG_0F18.
432 (mod_table): Add those cases as "nop/reserved".
433
4c692bc7
JB		 4342012-08-07 Jan Beulich <jbeulich@suse.com>
435
436 * i386-opc.tbl: Remove "FIXME" comments from SVME instructions.
437
de882298
RM		 4382012-08-06 Roland McGrath <mcgrathr@google.com>
439
440 * i386-dis.c (print_insn): Print spaces between multiple excess
441 prefixes. Return actual number of excess prefixes consumed,
442 not always one.
443
444 * i386-dis.c (OP_REG): Ignore REX_B for segment register cases.
445
7bb15c6f
RM		 4462012-08-06 Roland McGrath <mcgrathr@google.com>
447 Victor Khimenko <khim@google.com>
448 H.J. Lu <hongjiu.lu@intel.com>
449
450 * i386-dis.c (OP_sI): In b_T_mode and v_mode, REX_W trumps DFLAG.
451 (putop): For 'T', 'U', and 'V', treat REX_W like DFLAG.
452 (intel_operand_size): For stack_v_mode, treat REX_W like DFLAG.
453 (OP_E_register): Likewise.
454 (OP_REG): For low 8 whole registers, treat REX_W like DFLAG.
455
3843081d
JBG		 4562012-08-02 Jan-Benedict Glaw <jbglaw@lug-owl.de>
457
458 * configure.in: Formatting.
459 * configure: Regenerate.
460
48891606
AM		 4612012-08-01 Alan Modra <amodra@gmail.com>
462
463 * h8300-dis.c: Fix printf arg warnings.
464 * i960-dis.c: Likewise.
465 * mips-dis.c: Likewise.
466 * pdp11-dis.c: Likewise.
467 * sh-dis.c: Likewise.
468 * v850-dis.c: Likewise.
469 * configure.in: Formatting.
470 * configure: Regenerate.
471 * rl78-decode.c: Regenerate.
472 * po/POTFILES.in: Regenerate.
473
03f66e8a 4742012-07-31 Chao-Ying Fu <fu@mips.com>
e67ed0e8
AM		 475 Catherine Moore <clm@codesourcery.com>
476 Maciej W. Rozycki <macro@codesourcery.com>
03f66e8a
MR		 477
478 * micromips-opc.c (WR_a, RD_a, MOD_a): New macros.
479 (DSP_VOLA): Likewise.
480 (D32, D33): Likewise.
481 (micromips_opcodes): Add DSP ASE instructions.
48891606 482 * mips-dis.c (print_insn_micromips) <'2', '3'>: New cases.
03f66e8a
MR		 483 <'4', '5', '6', '7', '8', '0', '^', '@'>: Likewise.
484
94948e64
JB		 4852012-07-31 Jan Beulich <jbeulich@suse.com>
486
487 * i386-opc.tbl (vmovntdqa): Move up into 256-bit integer AVX2
488 instruction group. Mark as requiring AVX2.
489 * i386-tbl.h: Re-generate.
490
a6dc81d2
NC		 4912012-07-30 Nick Clifton <nickc@redhat.com>
492
493 * po/opcodes.pot: Updated template.
494 * po/es.po: Updated Spanish translation.
495 * po/fi.po: Updated Finnish translation.
496
c4dd807e
MF		 4972012-07-27 Mike Frysinger <vapier@gentoo.org>
498
499 * configure.in (BFD_VERSION): Run bfd/configure --version and
500 parse the output of that.
501 * configure: Regenerate.
502
03edbe3b
JL		 5032012-07-25 James Lemke <jwlemke@codesourcery.com>
504
505 * ppc-opc.c (powerpc_opcodes): Add/remove PPCVLE for some 32-bit insns.
506
63d08c68
NC		 5072012-07-24 Stephan McCamant <smcc@cs.berkeley.edu>
508 Dr David Alan Gilbert <dave@treblig.org>
d908c8af
NC		 509
510 PR binutils/13135
511 * arm-dis.c: Add necessary casts for printing integer values.
512 Use %s when printing string values.
513 * hppa-dis.c: Likewise.
514 * m68k-dis.c: Likewise.
515 * microblaze-dis.c: Likewise.
516 * mips-dis.c: Likewise.
517 * sparc-dis.c: Likewise.
518
ff688e1f
L		 5192012-07-19 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
520
521 PR binutils/14355
522 * i386-dis.c (VEX_LEN_0FXOP_08_CC): New.
523 (VEX_LEN_0FXOP_08_CD): Likewise.
524 (VEX_LEN_0FXOP_08_CE): Likewise.
525 (VEX_LEN_0FXOP_08_CF): Likewise.
526 (VEX_LEN_0FXOP_08_EC): Likewise.
527 (VEX_LEN_0FXOP_08_ED): Likewise.
528 (VEX_LEN_0FXOP_08_EE): Likewise.
529 (VEX_LEN_0FXOP_08_EF): Likewise.
530 (xop_table): Fix entries for vpcomb, vpcomw, vpcomd, vpcomq,
531 vpcomub, vpcomuw, vpcomud, vpcomuq.
532 (vex_len_table): Add entries for VEX_LEN_0FXOP_08_CC,
533 VEX_LEN_0FXOP_08_CD, VEX_LEN_0FXOP_08_CE, VEX_LEN_0FXOP_08_CF,
534 VEX_LEN_0FXOP_08_EC, VEX_LEN_0FXOP_08_ED, VEX_LEN_0FXOP_08_EE,
535 VEX_LEN_0FXOP_08_EF.
536
e2e1fcde
L		 5372012-07-16 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
538
539 * i386-dis.c (PREFIX_0F38F6): New.
540 (prefix_table): Add adcx, adox instructions.
541 (three_byte_table): Use PREFIX_0F38F6.
542 (mod_table): Add rdseed instruction.
543 * i386-gen.c (cpu_flag_init): Add CpuADX, CpuRDSEED, CpuPRFCHW.
544 (cpu_flags): Likewise.
545 * i386-opc.h: Add CpuADX, CpuRDSEED, CpuPRFCHW.
546 (i386_cpu_flags): Add fields cpurdseed, cpuadx, cpuprfchw.
547 * i386-opc.tbl: Add instrcutions adcx, adox, rdseed. Extend
548 prefetchw.
549 * i386-tbl.h: Regenerate.
550 * i386-init.h: Likewise.
551
8b99bf0b
TS		 5522012-07-05 Thomas Schwinge <thomas@codesourcery.com>
553
f4263ca2 554 * mips-dis.c: Remove gratuitous newline.
8b99bf0b 555
416cf80a
SK		 5562012-07-05 Sean Keys <skeys@ipdatasys.com>
557
558 * xgate-dis.c: Removed an IF statement that will
e67ed0e8
AM		 559 always be false due to overlapping operand masks.
560 * xgate-opc.c: Corrected 'com' opcode entry and
561 fixed spacing.
416cf80a 562
9fa0f14a
RM		 5632012-07-02 Roland McGrath <mcgrathr@google.com>
564
565 * i386-opc.tbl: Add RepPrefixOk to nop.
566 * i386-tbl.h: Regenerate.
567
4c6a93d3
NC		 5682012-06-28 Nick Clifton <nickc@redhat.com>
569
570 * po/vi.po: Updated Vietnamese translation.
571
29c048b6
RM		 5722012-06-22 Roland McGrath <mcgrathr@google.com>
573
fe13e45b
RM		 574 * i386-opc.tbl: Add RepPrefixOk to ret.
575 * i386-tbl.h: Regenerate.
576
29c048b6
RM		 577 * i386-opc.h (RepPrefixOk): New enum constant.
578 (i386_opcode_modifier): New bitfield 'repprefixok'.
579 * i386-gen.c (opcode_modifiers): Add RepPrefixOk.
580 * i386-opc.tbl: Add RepPrefixOk to bsf, bsr, and to all
581 instructions that have IsString.
582 * i386-tbl.h: Regenerate.
583
c7a8dbf9
AS		 5842012-06-11 Andreas Schwab <schwab@linux-m68k.org>
585
586 * ppc-opc.c (lvsl, lvebx, isellt, icbt, ldepx, lwepx, lvsr, lvehx)
587 (iselgt, lvewx, iseleq, isel, dcbst, dcbstep, dcbfl, dcbf, lbepx)
588 (lvx, dcbfep, dcbtstls, stvebx, dcbtstlse, stdepx, stwepx, dcbtls)
589 (stvehx, dcbtlse, stvewx, stbepx, icblc, stvx, dcbtstt, dcbtst)
590 (dcbtst, dcbtstep, dcbtt, dcbt, dcbt, lhepx, eciwx, dcbtep)
591 (dcread, lxvdsx, lvxl, dcblc, sthepx, ecowx, dcbi, dcread, icbtls)
592 (stvxl, lxsdx, lfdepx, stxsdx, stfdepx, dcba, dcbal, lxvw4x)
593 (tlbivax, lfdpx, lxvd2x, tlbsrx., stxvw4x, tlbsx, tlbsx., stfdpx)
594 (stfqx, stxvd2x, icbi, icbiep, icread, dcbzep): Change RA to RA0.
595
94caa966
AM		 5962012-05-19 Alan Modra <amodra@gmail.com>
597
598 * ppc-dis.c: Don't include elf32-ppc.h, do include elf/ppc.h.
599 (get_powerpc_dialect): Detect VLE sections from ELF sh_flags.
600
5eb3690e
AM		 6012012-05-18 Alan Modra <amodra@gmail.com>
602
71fe7bab
AM		 603 * ia64-opc.c: Remove #include "ansidecl.h".
604 * z8kgen.c: Include sysdep.h first.
605
5eb3690e
AM		 606 * arc-dis.c: Include sysdep.h first, remove some redundant includes.
607 * bfin-dis.c: Likewise.
608 * i860-dis.c: Likewise.
609 * ia64-dis.c: Likewise.
610 * ia64-gen.c: Likewise.
611 * m68hc11-dis.c: Likewise.
612 * mmix-dis.c: Likewise.
613 * msp430-dis.c: Likewise.
614 * or32-dis.c: Likewise.
615 * rl78-dis.c: Likewise.
616 * rx-dis.c: Likewise.
617 * tic4x-dis.c: Likewise.
618 * tilegx-opc.c: Likewise.
619 * tilepro-opc.c: Likewise.
620 * rx-decode.c: Regenerate.
621
a4ebc835
AM		 6222012-05-17 James Lemke <jwlemke@codesourcery.com>
623
624 * ppc-opc.c (powerpc_macros): Add entries for e_extlwi to e_clrlslwi.
625
98c76446
AM		 6262012-05-17 James Lemke <jwlemke@codesourcery.com>
627
628 * ppc-opc.c (extract_sprg): Use ALLOW8_SPRG to include VLE.
629
df7b86aa
NC		 6302012-05-17 Daniel Richard G. <skunk@iskunk.org>
631 Nick Clifton <nickc@redhat.com>
632
633 PR 14072
634 * configure.in: Add check that sysdep.h has been included before
635 any system header files.
636 * configure: Regenerate.
637 * config.in: Regenerate.
638 * sysdep.h: Generate an error if included before config.h.
639 * alpha-opc.c: Include sysdep.h before any other header file.
640 * alpha-dis.c: Likewise.
641 * avr-dis.c: Likewise.
642 * cgen-opc.c: Likewise.
643 * cr16-dis.c: Likewise.
644 * cris-dis.c: Likewise.
645 * crx-dis.c: Likewise.
646 * d10v-dis.c: Likewise.
647 * d10v-opc.c: Likewise.
648 * d30v-dis.c: Likewise.
649 * d30v-opc.c: Likewise.
650 * h8500-dis.c: Likewise.
651 * i370-dis.c: Likewise.
652 * i370-opc.c: Likewise.
653 * m10200-dis.c: Likewise.
654 * m10300-dis.c: Likewise.
655 * micromips-opc.c: Likewise.
656 * mips-opc.c: Likewise.
657 * mips61-opc.c: Likewise.
658 * moxie-dis.c: Likewise.
659 * or32-opc.c: Likewise.
660 * pj-dis.c: Likewise.
661 * ppc-dis.c: Likewise.
662 * ppc-opc.c: Likewise.
663 * s390-dis.c: Likewise.
664 * sh-dis.c: Likewise.
665 * sh64-dis.c: Likewise.
666 * sparc-dis.c: Likewise.
667 * sparc-opc.c: Likewise.
668 * spu-dis.c: Likewise.
669 * tic30-dis.c: Likewise.
670 * tic54x-dis.c: Likewise.
671 * tic80-dis.c: Likewise.
672 * tic80-opc.c: Likewise.
673 * tilegx-dis.c: Likewise.
674 * tilepro-dis.c: Likewise.
675 * v850-dis.c: Likewise.
676 * v850-opc.c: Likewise.
677 * vax-dis.c: Likewise.
678 * w65-dis.c: Likewise.
679 * xgate-dis.c: Likewise.
680 * xtensa-dis.c: Likewise.
681 * rl78-decode.opc: Likewise.
682 * rl78-decode.c: Regenerate.
683 * rx-decode.opc: Likewise.
684 * rx-decode.c: Regenerate.
685
e1dad58d
AM		 6862012-05-17 Alan Modra <amodra@gmail.com>
687
688 * ppc_dis.c: Don't include elf/ppc.h.
689
101af531
NC		 6902012-05-16 Meador Inge <meadori@codesourcery.com>
691
692 * arm-dis.c (arm_opcodes): Don't disassemble STMFD/LDMIA sp!, {reg}
693 to PUSH/POP {reg}.
694
6927f982
NC		 6952012-05-15 James Murray <jsm@jsm-net.demon.co.uk>
696 Stephane Carrez <stcarrez@nerim.fr>
697
698 * configure.in: Add S12X and XGATE co-processor support to m68hc11
699 target.
700 * disassemble.c: Likewise.
701 * configure: Regenerate.
702 * m68hc11-dis.c: Make objdump output more consistent, use hex
703 instead of decimal and use 0x prefix for hex.
704 * m68hc11-opc.c: Add S12X and XGATE opcodes.
705
b9c361e0
JL		 7062012-05-14 James Lemke <jwlemke@codesourcery.com>
707
708 * ppc-dis.c (get_powerpc_dialect): Use is_ppc_vle.
709 (PPC_OPCD_SEGS, VLE_OPCD_SEGS): New defines.
710 (vle_opcd_indices): New array.
711 (lookup_vle): New function.
712 (disassemble_init_powerpc): Revise for second (VLE) opcode table.
713 (print_insn_powerpc): Likewise.
714 * ppc-opc.c: Likewise.
715
7162012-05-14 Catherine Moore <clm@codesourcery.com>
717 Maciej W. Rozycki <macro@codesourcery.com>
718 Rhonda Wittels <rhonda@codesourcery.com>
719 Nathan Froyd <froydnj@codesourcery.com>
720
721 * ppc-opc.c (insert_arx, extract_arx): New functions.
722 (insert_ary, extract_ary): New functions.
723 (insert_li20, extract_li20): New functions.
724 (insert_rx, extract_rx): New functions.
725 (insert_ry, extract_ry): New functions.
726 (insert_sci8, extract_sci8): New functions.
727 (insert_sci8n, extract_sci8n): New functions.
728 (insert_sd4h, extract_sd4h): New functions.
729 (insert_sd4w, extract_sd4w): New functions.
730 (insert_vlesi, extract_vlesi): New functions.
731 (insert_vlensi, extract_vlensi): New functions.
732 (insert_vleui, extract_vleui): New functions.
733 (insert_vleil, extract_vleil): New functions.
734 (BI_MASK, BB_MASK, BT): Use PPC_OPERAND_CR_BIT.
735 (BI16, BI32, BO32, B8): New.
736 (B15, B24, CRD32, CRS): New.
737 (CRD, OBF, BFA, CR, CRFS): Use PPC_OPERAND_CR_REG.
738 (DB, IMM20, RD, Rx, ARX, RY, RZ): New.
739 (ARY, SCLSCI8, SCLSCI8N, SE_SD, SE_SDH): New.
740 (SH6_MASK): Use PPC_OPSHIFT_INV.
741 (SI8, UI5, OIMM5, UI7, BO16): New.
742 (VLESIMM, VLENSIMM, VLEUIMM, VLEUIMML): New.
743 (XT6, XA6, XB6, XB6S, XC6): Use PPC_OPSHIFT_INV.
744 (ALLOW8_SPRG): New.
745 (insert_sprg, extract_sprg): Check ALLOW8_SPRG.
746 (OPVUP, OPVUP_MASK OPVUP): New
747 (BD8, BD8_MASK, BD8IO, BD8IO_MASK): New.
748 (EBD8IO, EBD8IO1_MASK, EBD8IO2_MASK, EBD8IO3_MASK): New.
749 (BD15, BD15_MASK, EBD15, EBD15_MASK, EBD15BI, EBD15BI_MASK): New.
750 (BD24,BD24_MASK, C_LK, C_LK_MASK, C, C_MASK): New.
751 (IA16, IA16_MASK, I16A, I16A_MASK, I16L, I16L_MASK): New.
752 (IM7, IM7_MASK, LI20, LI20_MASK, SCI8, SCI8_MASK): New.
753 (SCI8BF, SCI8BF_MASK, SD4, SD4_MASK): New.
754 (SE_IM5, SE_IM5_MASK): New.
755 (SE_R, SE_R_MASK, SE_RR, SE_RR_MASK): New.
756 (EX, EX_MASK, BO16F, BO16T, BO32F, BO32T): New.
757 (BO32DNZ, BO32DZ): New.
758 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW): Include PPC_OPCODE_VLE.
759 (PPCVLE): New.
760 (powerpc_opcodes): Add new VLE instructions. Update existing
761 instruction to include PPCVLE if supported.
762 * ppc-dis.c (ppc_opts): Add vle entry.
763 (get_powerpc_dialect): New function.
764 (powerpc_init_dialect): VLE support.
765 (print_insn_big_powerpc): Call get_powerpc_dialect.
766 (print_insn_little_powerpc): Likewise.
767 (operand_value_powerpc): Handle negative shift counts.
768 (print_insn_powerpc): Handle 2-byte instruction lengths.
769
208a4923
NC		 7702012-05-11 Daniel Richard G. <skunk@iskunk.org>
771
772 PR binutils/14028
773 * configure.in: Invoke ACX_HEADER_STRING.
774 * configure: Regenerate.
775 * config.in: Regenerate.
776 * sysdep.h: If STRINGS_WITH_STRING is defined then include both
777 string.h and strings.h.
778
6750a3a7
NC		 7792012-05-11 Nick Clifton <nickc@redhat.com>
780
781 PR binutils/14006
782 * arm-dis.c (print_insn): Fix detection of instruction mode in
783 files containing multiple executable sections.
784
f6c1a2d5
NC		 7852012-05-03 Sean Keys <skeys@ipdatasys.com>
786
787 * Makefile.in, configure: regenerate
788 * disassemble.c (disassembler): Recognize ARCH_XGATE.
789 * xgate-dis.c (read_memory, print_insn, print_insn_xgate):
790 New functions.
791 * configure.in: Recognize xgate.
792 * xgate-dis.c, xgate-opc.c: New files for support of xgate
793 * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly
794 and opcode generation for xgate.
795
78e98aab
DD		 7962012-04-30 DJ Delorie <dj@redhat.com>
797
798 * rx-decode.opc (MOV): Do not sign-extend immediates which are
799 already the maximum bit size.
800 * rx-decode.c: Regenerate.
801
ec668d69
DM		 8022012-04-27 David S. Miller <davem@davemloft.net>
803
2e52845b
DM		 804 * sparc-dis.c (v9a_asr_reg_names): Add 'cfr'.
805 * sparc-opc.c (sparc_opcodes): Add rd/wr cases for %cfr.
806
58004e23
DM		 807 * sparc-opc.c (sparc_opcodes): Add 'wr X, %pause' and 'pause'.
808 * sparc-dis.c (v9a_asr_reg_names): Add 'pause'.
809
698544e1
DM		 810 * sparc-opc.c (CBCOND): New define.
811 (CBCOND_XCC): Likewise.
812 (cbcond): New helper macro.
813 (sparc_opcodes): Add compare-and-branch instructions.
814
6cda1326
DM		 815 * sparc-dis.c (print_insn_sparc): Handle ')'.
816 * sparc-opc.c (sparc_opcodes): Add crypto instructions.
817
ec668d69
DM		 818 * sparc-opc.c (sparc_opcodes): Rework table to put HWCAP values
819 into new struct sparc_opcode 'hwcaps' field instead of 'flags'.
820
2615994e
DM		 8212012-04-12 David S. Miller <davem@davemloft.net>
822
823 * sparc-dis.c (X_DISP10): Define.
824 (print_insn_sparc): Handle '='.
825
5de10af0
MF		 8262012-04-01 Mike Frysinger <vapier@gentoo.org>
827
828 * bfin-dis.c (fmtconst): Replace decimal handling with a single
829 sprintf call and the '*' field width.
830
55a36193
MK		 8312012-03-23 Maxim Kuvyrkov <maxim@codesourcery.com>
832
833 * mips-dis.c (mips_arch_choices): Add entry for Broadcom XLP.
834
d6688282
AM		 8352012-03-16 Alan Modra <amodra@gmail.com>
836
837 * ppc-dis.c (PPC_OPC_SEGS, PPC_OP_TO_SEG): Delete.
838 (powerpc_opcd_indices): Bump array size.
839 (disassemble_init_powerpc): Set powerpc_opcd_indices entries
840 corresponding to unused opcodes to following entry.
841 (lookup_powerpc): New function, extracted and optimised from..
842 (print_insn_powerpc): ..here.
843
b240011a
AM		 8442012-03-15 Alan Modra <amodra@gmail.com>
845 James Lemke <jwlemke@codesourcery.com>
846
847 * disassemble.c (disassemble_init_for_target): Handle ppc init.
848 * ppc-dis.c (private): New var.
849 (powerpc_init_dialect): Don't return calloc failure, instead use
850 private.
851 (PPC_OPCD_SEGS, PPC_OP_TO_SEG): Define.
852 (powerpc_opcd_indices): New array.
853 (disassemble_init_powerpc): New function.
854 (print_insn_big_powerpc): Don't init dialect here.
855 (print_insn_little_powerpc): Likewise.
856 (print_insn_powerpc): Start search using powerpc_opcd_indices.
857
aea77599
AM		 8582012-03-10 Edmar Wienskoski <edmar@freescale.com>
859
860 * ppc-dis.c (ppc_opts): Add entries for "e5500" and "e6500".
861 * ppc-opc.c (insert_ls, TMR, ESYNC, XSYNCLE_MASK): New.
862 (PPCVEC2, PPCTMR, E6500): New short names.
863 (powerpc_opcodes): Add vabsdub, vabsduh, vabsduw, dni, mvidsplt,
864 mviwsplt, icblq., mftmr, mttmr, dcblq., miso, lvexbx, lvexhx,
865 lvexwx, stvexbx, stvexhx, stvexwx, lvepx, lvepxl, stvepx, stvepxl,
866 lvtrx, lvtrxl, lvtlx, lvtlxl, stvfrx, stvfrxl, stvflx, stvflxl,
867 lvswx, lvswxl, stvswx, stvswxl, lvsm mnemonics. Accept LS, ESYNC
868 optional operands on sync instruction for E6500 target.
869
5333187a
AK		 8702012-03-08 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
871
872 * s390-opc.txt: Set instruction type of pku to SS_L2RDRD.
873
a597d2d3
AM		 8742012-02-27 Alan Modra <amodra@gmail.com>
875
876 * mt-dis.c: Regenerate.
877
3f26eb3a
AM		 8782012-02-27 Alan Modra <amodra@gmail.com>
879
880 * v850-opc.c (extract_v8): Rearrange to make it obvious this
881 is the inverse of corresponding insert function.
882 (extract_d22, extract_u9, extract_r4): Likewise.
883 (extract_d9): Correct sign extension.
884 (extract_d16_15): Don't assume "long" is 32 bits, and don't
885 rely on implementation defined behaviour for shift right of
886 signed types.
887 (extract_d16_16, extract_d17_16, extract_i9): Likewise.
888 (extract_d23): Likewise, and correct mask.
889
1f42f8b3
AM		 8902012-02-27 Alan Modra <amodra@gmail.com>
891
892 * crx-dis.c (print_arg): Mask constant to 32 bits.
893 * crx-opc.c (cst4_map): Use int array.
894
cdb06235
AM		 8952012-02-27 Alan Modra <amodra@gmail.com>
896
897 * arc-dis.c (BITS): Don't use shifts to mask off bits.
898 (FIELDD): Sign extend with xor,sub.
899
6f7be959
WL		 9002012-02-25 Walter Lee <walt@tilera.com>
901
902 * tilegx-opc.c: Handle TILEGX_OPC_LD4S_TLS and TILEGX_OPC_LD_TLS.
903 * tilepro-opc.c: Handle TILEPRO_OPC_LW_TLS and
904 TILEPRO_OPC_LW_TLS_SN.
905
82c2def5
L		 9062012-02-21 H.J. Lu <hongjiu.lu@intel.com>
907
908 * i386-opc.h (HLEPrefixNone): New.
909 (HLEPrefixLock): Likewise.
910 (HLEPrefixAny): Likewise.
911 (HLEPrefixRelease): Likewise.
912
42164a71
L		 9132012-02-08 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386-dis.c (HLE_Fixup1): New.
916 (HLE_Fixup2): Likewise.
917 (HLE_Fixup3): Likewise.
918 (Ebh1): Likewise.
919 (Evh1): Likewise.
920 (Ebh2): Likewise.
921 (Evh2): Likewise.
922 (Ebh3): Likewise.
923 (Evh3): Likewise.
924 (MOD_C6_REG_7): Likewise.
925 (MOD_C7_REG_7): Likewise.
926 (RM_C6_REG_7): Likewise.
927 (RM_C7_REG_7): Likewise.
928 (XACQUIRE_PREFIX): Likewise.
929 (XRELEASE_PREFIX): Likewise.
930 (dis386): Use Ebh1/Evh1 on add, adc, and, btc, btr, bts,
931 cmpxchg, dec, inc, neg, not, or, sbb, sub, xor and xadd. Use
932 Ebh2/Evh2 on xchg. Use Ebh3/Evh3 on mov.
933 (reg_table): Use Ebh1/Evh1 on add, adc, and, dec, inc, neg,
934 not, or, sbb, sub and xor. Use Ebh3/Evh3 on mov. Use
935 MOD_C6_REG_7 and MOD_C7_REG_7.
936 (mod_table): Add MOD_C6_REG_7 and MOD_C7_REG_7.
937 (rm_table): Add RM_C6_REG_7 and RM_C7_REG_7. Add xend and
938 xtest.
939 (prefix_name): Handle XACQUIRE_PREFIX and XRELEASE_PREFIX.
940 (CMPXCHG8B_Fixup): Handle HLE prefix on cmpxchg8b.
941
942 * i386-gen.c (cpu_flag_init): Add CPU_HLE_FLAGS and
943 CPU_RTM_FLAGS.
944 (cpu_flags): Add CpuHLE and CpuRTM.
945 (opcode_modifiers): Add HLEPrefixOk.
946
947 * i386-opc.h (CpuHLE): New.
948 (CpuRTM): Likewise.
949 (HLEPrefixOk): Likewise.
950 (i386_cpu_flags): Add cpuhle and cpurtm.
951 (i386_opcode_modifier): Add hleprefixok.
952
953 * i386-opc.tbl: Add HLEPrefixOk=3 to mov. Add HLEPrefixOk to
954 add, adc, and, btc, btr, bts, cmpxchg, dec, inc, neg, not, or,
955 sbb, sub, xor and xadd. Add HLEPrefixOk=2 to xchg with memory
956 operand. Add xacquire, xrelease, xabort, xbegin, xend and
957 xtest.
958 * i386-init.h: Regenerated.
959 * i386-tbl.h: Likewise.
960
21abe33a
DD		 9612012-01-24 DJ Delorie <dj@redhat.com>
962
963 * rl78-decode.opc (rl78_decode_opcode): Add NOT1.
964 * rl78-decode.c: Regenerate.
965
e20cc039
AM		 9662012-01-17 James Murray <jsm@jsm-net.demon.co.uk>
967
968 PR binutils/10173
969 * cr16-dis.c (print_arg): Test symtab_size not num_symbols.
970
e143d25c
AS		 9712012-01-17 Andreas Schwab <schwab@linux-m68k.org>
972
973 * m68k-opc.c (m68k_opcodes): Fix entries for pmove with BADx/BACx
974 register and move them after pmove with PSR/PCSR register.
975
8729a6f6
L		 9762012-01-13 H.J. Lu <hongjiu.lu@intel.com>
977
978 * i386-dis.c (mod_table): Add vmfunc.
979
980 * i386-gen.c (cpu_flag_init): Add CPU_VMFUNC_FLAGS.
981 (cpu_flags): CpuVMFUNC.
982
983 * i386-opc.h (CpuVMFUNC): New.
984 (i386_cpu_flags): Add cpuvmfunc.
985
986 * i386-opc.tbl: Add vmfunc.
987 * i386-init.h: Regenerated.
988 * i386-tbl.h: Likewise.
5011093d 989
23e1d329 990For older changes see ChangeLog-2011
252b5132
RH		 991\f
992Local Variables:
2f6d2f85
NC		 993mode: change-log
994left-margin: 8
995fill-column: 74
252b5132
RH		 996version-control: never
997End:
GDB Binutils - Deliverables
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