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Fix compile time warnings from a GCC 4.0 compiler
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3ec2b351
NC		 12005-07-05 Nick Clifton <nickc@redhat.com>
2
3 * iq2000-asm.c: Regenerate.
4 * ms1-asm.c: Regenerate.
5
30123838
JB		 62005-07-05 Jan Beulich <jbeulich@novell.com>
7
8 * i386-dis.c (SVME_Fixup): New.
9 (grps): Use it for the lidt entry.
10 (PNI_Fixup): Call OP_M rather than OP_E.
11 (INVLPG_Fixup): Likewise.
12
b0eec63e
L		 132005-07-04 H.J. Lu <hongjiu.lu@intel.com>
14
15 * tic30-dis.c (cnvt_tmsfloat_ieee): Use HUGE_VALF if defined.
16
47b0e7ad
NC		 172005-07-01 Nick Clifton <nickc@redhat.com>
18
19 * a29k-dis.c: Update to ISO C90 style function declarations and
20 fix formatting.
21 * alpha-opc.c: Likewise.
22 * arc-dis.c: Likewise.
23 * arc-opc.c: Likewise.
24 * avr-dis.c: Likewise.
25 * cgen-asm.in: Likewise.
26 * cgen-dis.in: Likewise.
27 * cgen-ibld.in: Likewise.
28 * cgen-opc.c: Likewise.
29 * cris-dis.c: Likewise.
30 * d10v-dis.c: Likewise.
31 * d30v-dis.c: Likewise.
32 * d30v-opc.c: Likewise.
33 * dis-buf.c: Likewise.
34 * dlx-dis.c: Likewise.
35 * h8300-dis.c: Likewise.
36 * h8500-dis.c: Likewise.
37 * hppa-dis.c: Likewise.
38 * i370-dis.c: Likewise.
39 * i370-opc.c: Likewise.
40 * m10200-dis.c: Likewise.
41 * m10300-dis.c: Likewise.
42 * m68k-dis.c: Likewise.
43 * m88k-dis.c: Likewise.
44 * mips-dis.c: Likewise.
45 * mmix-dis.c: Likewise.
46 * msp430-dis.c: Likewise.
47 * ns32k-dis.c: Likewise.
48 * or32-dis.c: Likewise.
49 * or32-opc.c: Likewise.
50 * pdp11-dis.c: Likewise.
51 * pj-dis.c: Likewise.
52 * s390-dis.c: Likewise.
53 * sh-dis.c: Likewise.
54 * sh64-dis.c: Likewise.
55 * sparc-dis.c: Likewise.
56 * sparc-opc.c: Likewise.
57 * sysdep.h: Likewise.
58 * tic30-dis.c: Likewise.
59 * tic4x-dis.c: Likewise.
60 * tic80-dis.c: Likewise.
61 * v850-dis.c: Likewise.
62 * v850-opc.c: Likewise.
63 * vax-dis.c: Likewise.
64 * w65-dis.c: Likewise.
65 * z8kgen.c: Likewise.
66
67 * fr30-*: Regenerate.
68 * frv-*: Regenerate.
69 * ip2k-*: Regenerate.
70 * iq2000-*: Regenerate.
71 * m32r-*: Regenerate.
72 * ms1-*: Regenerate.
73 * openrisc-*: Regenerate.
74 * xstormy16-*: Regenerate.
75
cc16ba8c
BE		 762005-06-23 Ben Elliston <bje@gnu.org>
77
78 * m68k-dis.c: Use ISC C90.
79 * m68k-opc.c: Formatting fixes.
80
4b185e97
DU		 812005-06-16 David Ung <davidu@mips.com>
82
83 * mips16-opc.c (mips16_opcodes): Add the following MIPS16e
84 instructions to the table; seb/seh/sew/zeb/zeh/zew.
85
ac188222
DB		 862005-06-15 Dave Brolley <brolley@redhat.com>
87
88 Contribute Morpho ms1 on behalf of Red Hat
89 * ms1-asm.c, ms1-desc.c, ms1-dis.c, ms1-ibld.c, ms1-opc.c,
90 ms1-opc.h: New files, Morpho ms1 target.
91
92 2004-05-14 Stan Cox <scox@redhat.com>
93
94 * disassemble.c (ARCH_ms1): Define.
95 (disassembler): Handle bfd_arch_ms1
96
97 2004-05-13 Michael Snyder <msnyder@redhat.com>
98
99 * Makefile.am, Makefile.in: Add ms1 target.
100 * configure.in: Ditto.
101
6b5d3a4d
ZW		 1022005-06-08 Zack Weinberg <zack@codesourcery.com>
103
104 * arm-opc.h: Delete; fold contents into ...
105 * arm-dis.c: ... here. Move includes of internal COFF headers
106 next to includes of internal ELF headers.
107 (streq, WORD_ADDRESS, BDISP, BDISP23): Delete, unused.
108 (struct arm_opcode): Rename struct opcode32. Make 'assembler' const.
109 (struct thumb_opcode): Rename struct opcode16. Make 'assembler' const.
110 (arm_conditional, arm_fp_const, arm_shift, arm_regname, regnames)
111 (iwmmxt_wwnames, iwmmxt_wwssnames):
112 Make const.
113 (regnames): Remove iWMMXt coprocessor register sets.
114 (iwmmxt_regnames, iwmmxt_cregnames): New statics.
115 (get_arm_regnames): Adjust fourth argument to match above changes.
116 (set_iwmmxt_regnames): Delete.
117 (print_insn_arm): Constify 'c'. Use ISO syntax for function
118 pointer calls. Expand sole use of BDISP. Use iwmmxt_regnames
119 and iwmmxt_cregnames, not set_iwmmxt_regnames.
120 (print_insn_thumb16, print_insn_thumb32): Constify 'c'. Use
121 ISO syntax for function pointer calls.
122
4a5329c6
ZW		 1232005-06-07 Zack Weinberg <zack@codesourcery.com>
124
125 * arm-dis.c: Split up the comments describing the format codes, so
126 that the ARM and 16-bit Thumb opcode tables each have comments
127 preceding them that describe all the codes, and only the codes,
128 valid in those tables. (32-bit Thumb table is already like this.)
129 Reorder the lists in all three comments to match the order in
130 which the codes are implemented.
131 Remove all forward declarations of static functions. Convert all
132 function definitions to ISO C format.
133 (print_insn_arm, print_insn_thumb16, print_insn_thumb32):
134 Return nothing.
135 (print_insn_thumb16): Remove unused case 'I'.
136 (print_insn): Update for changed calling convention of subroutines.
137
3d456fa1
JB		 1382005-05-25 Jan Beulich <jbeulich@novell.com>
139
140 * i386-dis.c (OP_E): In Intel mode, display 32-bit displacements in
141 hex (but retain it being displayed as signed). Remove redundant
142 checks. Add handling of displacements for 16-bit addressing in Intel
143 mode.
144
2888cb7a
JB		 1452005-05-25 Jan Beulich <jbeulich@novell.com>
146
147 * i386-dis.c (prefix_name): Remove pointless mode_64bit check.
148 (OP_E): Remove redundant REX_EXTZ handling. Remove pointless
149 masking of 'rm' in 16-bit memory address handling.
150
1ed8e1e4
AM		 1512005-05-19 Anton Blanchard <anton@samba.org>
152
153 * ppc-dis.c (powerpc_dialect): Handle "-Mpower5".
154 (print_ppc_disassembler_options): Document it.
155 * ppc-opc.c (SVC_LEV): Define.
156 (LEV): Allow optional operand.
157 (POWER5): Define.
158 (powerpc_opcodes): Extend "sc". Adjust "svc" and "svcl". Add
159 "hrfid", "popcntb", "fsqrtes", "fsqrtes.", "fre" and "fre.".
160
49cc2e69
KC		 1612005-05-19 Kelley Cook <kcook@gcc.gnu.org>
162
163 * Makefile.in: Regenerate.
164
c19d1205
ZW		 1652005-05-17 Zack Weinberg <zack@codesourcery.com>
166
167 * arm-dis.c (thumb_opcodes): Add disassembly for V6T2 16-bit
168 instructions. Adjust disassembly of some opcodes to match
169 unified syntax.
170 (thumb32_opcodes): New table.
171 (print_insn_thumb): Rename print_insn_thumb16; don't handle
172 two-halfword branches here.
173 (print_insn_thumb32): New function.
174 (print_insn): Choose among print_insn_arm, print_insn_thumb16,
175 and print_insn_thumb32. Be consistent about order of
176 halfwords when printing 32-bit instructions.
177
003519a7
L		 1782005-05-07 H.J. Lu <hongjiu.lu@intel.com>
179
180 PR 843
181 * i386-dis.c (branch_v_mode): New.
182 (indirEv): Use branch_v_mode instead of v_mode.
183 (OP_E): Handle branch_v_mode.
184
920a34a7
L		 1852005-05-07 H.J. Lu <hongjiu.lu@intel.com>
186
187 * d10v-dis.c (dis_2_short): Support 64bit host.
188
5de773c1
NC		 1892005-05-07 Nick Clifton <nickc@redhat.com>
190
191 * po/nl.po: Updated translation.
192
f4321104
NC		 1932005-05-07 Nick Clifton <nickc@redhat.com>
194
195 * Update the address and phone number of the FSF organization in
196 the GPL notices in the following files:
197 a29k-dis.c, aclocal.m4, alpha-dis.c, alpha-opc.c, arc-dis.c,
198 arc-dis.h, arc-ext.c, arc-ext.h, arc-opc.c, arm-dis.c, arm-opc.h,
199 avr-dis.c, cgen-asm.c, cgen-asm.in, cgen-dis.c, cgen-dis.in,
200 cgen-ibld.in, cgen-opc.c, cgen.sh, cris-dis.c, cris-opc.c,
201 crx-dis.c, crx-opc.c, d10v-dis.c, d10v-opc.c, d30v-dis.c,
202 d30v-opc.c, dis-buf.c, dis-init.c, disassemble.c, dlx-dis.c,
203 fr30-asm.c, fr30-desc.c, fr30-desc.h, fr30-dis.c, fr30-ibld.c,
204 fr30-opc.c, fr30-opc.h, frv-asm.c, frv-desc.c, frv-desc.h,
205 frv-dis.c, frv-ibld.c, frv-opc.c, frv-opc.h, h8300-dis.c,
206 h8500-dis.c, h8500-opc.h, hppa-dis.c, i370-dis.c, i370-opc.c,
207 i386-dis.c, i860-dis.c, i960-dis.c, ia64-asmtab.h, ia64-dis.c,
208 ia64-gen.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c,
209 ia64-opc-f.c, ia64-opc-i.c, ia64-opc-m.c, ia64-opc-x.c,
210 ia64-opc.c, ia64-opc.h, ip2k-asm.c, ip2k-desc.c, ip2k-desc.h,
211 ip2k-dis.c, ip2k-ibld.c, ip2k-opc.c, ip2k-opc.h, iq2000-asm.c,
212 iq2000-desc.c, iq2000-desc.h, iq2000-dis.c, iq2000-ibld.c,
213 iq2000-opc.c, iq2000-opc.h, m10200-dis.c, m10200-opc.c,
214 m10300-dis.c, m10300-opc.c, m32r-asm.c, m32r-desc.c, m32r-desc.h,
215 m32r-dis.c, m32r-ibld.c, m32r-opc.c, m32r-opc.h, m32r-opinst.c,
216 m68hc11-dis.c, m68hc11-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c,
217 maxq-dis.c, mcore-dis.c, mcore-opc.h, mips-dis.c, mips-opc.c,
218 mips16-opc.c, mmix-dis.c, mmix-opc.c, msp430-dis.c, ns32k-dis.c,
219 openrisc-asm.c, openrisc-desc.c, openrisc-desc.h, openrisc-dis.c,
220 openrisc-ibld.c, openrisc-opc.c, openrisc-opc.h, opintl.h,
221 or32-dis.c, or32-opc.c, pdp11-dis.c, pdp11-opc.c, pj-dis.c,
222 pj-opc.c, ppc-dis.c, ppc-opc.c, s390-dis.c, s390-mkopc.c,
223 s390-opc.c, sh-dis.c, sh-opc.h, sh64-dis.c, sh64-opc.c,
224 sh64-opc.h, sparc-dis.c, sparc-opc.c, sysdep.h, tic30-dis.c,
225 tic4x-dis.c, tic54x-dis.c, tic54x-opc.c, tic80-dis.c, tic80-opc.c,
226 v850-dis.c, v850-opc.c, vax-dis.c, w65-dis.c, w65-opc.h,
227 xstormy16-asm.c, xstormy16-desc.c, xstormy16-desc.h,
228 xstormy16-dis.c, xstormy16-ibld.c, xstormy16-opc.c,
229 xstormy16-opc.h, xtensa-dis.c, z8k-dis.c, z8kgen.c
230
10b076a2
JW		 2312005-05-05 James E Wilson <wilson@specifixinc.com>
232
233 * ia64-opc.c: Include sysdep.h before libiberty.h.
234
022716b6
NC		 2352005-05-05 Nick Clifton <nickc@redhat.com>
236
237 * configure.in (ALL_LINGUAS): Add vi.
238 * configure: Regenerate.
239 * po/vi.po: New.
240
db5152b4
JG		 2412005-04-26 Jerome Guitton <guitton@gnat.com>
242
243 * configure.in: Fix the check for basename declaration.
244 * configure: Regenerate.
245
eed0d89a
AM		 2462005-04-19 Alan Modra <amodra@bigpond.net.au>
247
248 * ppc-opc.c (RTO): Define.
249 (powerpc_opcodes <tlbsx, tlbsx., tlbre>): Combine PPC403 and BOOKE
250 entries to suit PPC440.
251
791fe849
MK		 2522005-04-18 Mark Kettenis <kettenis@gnu.org>
253
254 * i386-dis.c: Insert hyphens into selected VIA PadLock extensions.
255 Add xcrypt-ctr.
256
ffe58f7c
NC		 2572005-04-14 Nick Clifton <nickc@redhat.com>
258
259 * po/fi.po: New translation: Finnish.
260 * configure.in (ALL_LINGUAS): Add fi.
261 * configure: Regenerate.
262
9e9b66a9
AM		 2632005-04-14 Alan Modra <amodra@bigpond.net.au>
264
265 * Makefile.am (NO_WERROR): Define.
266 * configure.in: Invoke AM_BINUTILS_WARNINGS.
267 * Makefile.in: Regenerate.
268 * aclocal.m4: Regenerate.
269 * configure: Regenerate.
270
9494d739
NC		 2712005-04-04 Nick Clifton <nickc@redhat.com>
272
273 * fr30-asm.c: Regenerate.
274 * frv-asm.c: Regenerate.
275 * iq2000-asm.c: Regenerate.
276 * m32r-asm.c: Regenerate.
277 * openrisc-asm.c: Regenerate.
278
6128c599
JB		 2792005-04-01 Jan Beulich <jbeulich@novell.com>
280
281 * i386-dis.c (PNI_Fixup): Neither mwait nor monitor have any
282 visible operands in Intel mode. The first operand of monitor is
283 %rax in 64-bit mode.
284
373ff435
JB		 2852005-04-01 Jan Beulich <jbeulich@novell.com>
286
287 * i386-dis.c (INVLPG_Fixup): Decode rdtscp; change code to allow for
288 easier future additions.
289
4bd60896
JG		 2902005-03-31 Jerome Guitton <guitton@gnat.com>
291
292 * configure.in: Check for basename.
293 * configure: Regenerate.
294 * config.in: Ditto.
295
4cc91dba
L		 2962005-03-29 H.J. Lu <hongjiu.lu@intel.com>
297
298 * i386-dis.c (SEG_Fixup): New.
299 (Sv): New.
300 (dis386): Use "Sv" for 0x8c and 0x8e.
301
ec72cfe5
NC		 3022005-03-21 Jan-Benedict Glaw <jbglaw@lug-owl.de>
303 Nick Clifton <nickc@redhat.com>
c19d1205 304
ec72cfe5
NC		 305 * vax-dis.c: (entry_addr): New varible: An array of user supplied
306 function entry mask addresses.
307 (entry_addr_occupied_slots): New variable: The number of occupied
c19d1205 308 elements in entry_addr.
ec72cfe5
NC		 309 (entry_addr_total_slots): New variable: The total number of
310 elements in entry_addr.
311 (parse_disassembler_options): New function. Fills in the entry_addr
312 array.
313 (free_entry_array): New function. Release the memory used by the
314 entry addr array. Suppressed because there is no way to call it.
315 (is_function_entry): Check if a given address is a function's
316 start address by looking at supplied entry mask addresses and
317 symbol information, if available.
318 (print_insn_vax): Use parse_disassembler_options and is_function_entry.
319
85064c79
L		 3202005-03-23 H.J. Lu <hongjiu.lu@intel.com>
321
322 * cris-dis.c (print_with_operands): Use ~31L for long instead
323 of ~31.
324
de7141c7
L		 3252005-03-20 H.J. Lu <hongjiu.lu@intel.com>
326
327 * mmix-opc.c (O): Revert the last change.
328 (Z): Likewise.
329
e493ab45
L		 3302005-03-19 H.J. Lu <hongjiu.lu@intel.com>
331
332 * mmix-opc.c (O): Use 24UL instead of 24 for unsigned long.
333 (Z): Likewise.
334
d8d7c459
HPN		 3352005-03-19 Hans-Peter Nilsson <hp@bitrange.com>
336
337 * mmix-opc.c (O, Z): Force expression as unsigned long.
338
ebdb0383
NC		 3392005-03-18 Nick Clifton <nickc@redhat.com>
340
341 * ip2k-asm.c: Regenerate.
342 * op/opcodes.pot: Regenerate.
343
1ad12f97
NC		 3442005-03-16 Nick Clifton <nickc@redhat.com>
345 Ben Elliston <bje@au.ibm.com>
346
569acd2c 347 * configure.in (werror): New switch: Add -Werror to the
1ad12f97 348 compiler command line. Enabled by default. Disable via
569acd2c 349 --disable-werror.
1ad12f97
NC		 350 * configure: Regenerate.
351
4eb30afc
AM		 3522005-03-16 Alan Modra <amodra@bigpond.net.au>
353
354 * ppc-dis.c (powerpc_dialect): Don't set PPC_OPCODE_ALTIVEC when
355 BOOKE.
356
ea8409f7
AM		 3572005-03-15 Alan Modra <amodra@bigpond.net.au>
358
729ae8d2
AM		 359 * po/es.po: Commit new Spanish translation.
360
ea8409f7
AM		 361 * po/fr.po: Commit new French translation.
362
4f495e61
NC		 3632005-03-14 Jan-Benedict Glaw <jbglaw@lug-owl.de>
364
365 * vax-dis.c: Fix spelling error
366 (print_insn_vax): Use ".word 0x0012 # Entry mask: r1 r2 >" instead
367 of just "Entry mask: < r1 ... >"
368
0a003adc
ZW		 3692005-03-12 Zack Weinberg <zack@codesourcery.com>
370
371 * arm-dis.c (arm_opcodes): Document %E and %V.
372 Add entries for v6T2 ARM instructions:
373 bfc bfi mls strht ldrht ldrsht ldrsbt movw movt rbit ubfx sbfx.
374 (print_insn_arm): Add support for %E and %V.
885fc257 375 (thumb_opcodes): Add ARMv6K instructions nop, sev, wfe, wfi, yield.
0a003adc 376
da99ee72
AM		 3772005-03-10 Jeff Baker <jbaker@qnx.com>
378 Alan Modra <amodra@bigpond.net.au>
379
380 * ppc-opc.c (insert_sprg, extract_sprg): New Functions.
381 (powerpc_operands <SPRG>): Call the above. Bit field is 5 bits.
382 (SPRG_MASK): Delete.
383 (XSPRG_MASK): Mask off extra bits now part of sprg field.
0a003adc 384 (powerpc_opcodes): Asjust mfsprg and mtsprg to suit new mask. Move
da99ee72
AM		 385 mfsprg4..7 after msprg and consolidate.
386
220abb21
AM		 3872005-03-09 Jan-Benedict Glaw <jbglaw@lug-owl.de>
388
389 * vax-dis.c (entry_mask_bit): New array.
390 (print_insn_vax): Decode function entry mask.
391
0e06657a
AH		 3922005-03-07 Aldy Hernandez <aldyh@redhat.com>
393
394 * ppc-opc.c (powerpc_opcodes): Fix encoding of efscfd.
395
06647dfd
AM		 3962005-03-05 Alan Modra <amodra@bigpond.net.au>
397
398 * po/opcodes.pot: Regenerate.
399
82b829a7
RR		 4002005-03-03 Ramana Radhakrishnan <ramana.radhakrishnan@codito.com>
401
220abb21 402 * arc-dis.c (a4_decoding_class): New enum.
06647dfd
AM		 403 (dsmOneArcInst): Use the enum values for the decoding class.
404 Remove redundant case in the switch for decodingClass value 11.
82b829a7 405
c4a530c5
JB		 4062005-03-02 Jan Beulich <jbeulich@novell.com>
407
408 * i386-dis.c (print_insn): Suppress lock prefix printing for cr8...15
409 accesses.
410 (OP_C): Consider lock prefix in non-64-bit modes.
411
47d8304e
AM		 4122005-02-24 Alan Modra <amodra@bigpond.net.au>
413
414 * cris-dis.c (format_hex): Remove ineffective warning fix.
415 * crx-dis.c (make_instruction): Warning fix.
416 * frv-asm.c: Regenerate.
417
ec36c4a4
NC		 4182005-02-23 Nick Clifton <nickc@redhat.com>
419
33b71eeb
NC		 420 * cgen-dis.in: Use bfd_byte for buffers that are passed to
421 read_memory.
06647dfd 422
33b71eeb 423 * ia64-opc.c (locate_opcode_ent): Initialise opval array.
06647dfd 424
ec36c4a4
NC		 425 * crx-dis.c (make_instruction): Move argument structure into inner
426 scope and ensure that all of its fields are initialised before
427 they are used.
428
33b71eeb
NC		 429 * fr30-asm.c: Regenerate.
430 * fr30-dis.c: Regenerate.
431 * frv-asm.c: Regenerate.
432 * frv-dis.c: Regenerate.
433 * ip2k-asm.c: Regenerate.
434 * ip2k-dis.c: Regenerate.
435 * iq2000-asm.c: Regenerate.
436 * iq2000-dis.c: Regenerate.
437 * m32r-asm.c: Regenerate.
438 * m32r-dis.c: Regenerate.
439 * openrisc-asm.c: Regenerate.
440 * openrisc-dis.c: Regenerate.
441 * xstormy16-asm.c: Regenerate.
442 * xstormy16-dis.c: Regenerate.
443
53c9ebc5
AM		 4442005-02-22 Alan Modra <amodra@bigpond.net.au>
445
446 * arc-ext.c: Warning fixes.
447 * arc-ext.h: Likewise.
448 * cgen-opc.c: Likewise.
449 * ia64-gen.c: Likewise.
450 * maxq-dis.c: Likewise.
451 * ns32k-dis.c: Likewise.
452 * w65-dis.c: Likewise.
453 * ia64-asmtab.c: Regenerate.
454
610ad19b
AM		 4552005-02-22 Alan Modra <amodra@bigpond.net.au>
456
457 * fr30-desc.c: Regenerate.
458 * fr30-desc.h: Regenerate.
459 * fr30-opc.c: Regenerate.
460 * fr30-opc.h: Regenerate.
461 * frv-desc.c: Regenerate.
462 * frv-desc.h: Regenerate.
463 * frv-opc.c: Regenerate.
464 * frv-opc.h: Regenerate.
465 * ip2k-desc.c: Regenerate.
466 * ip2k-desc.h: Regenerate.
467 * ip2k-opc.c: Regenerate.
468 * ip2k-opc.h: Regenerate.
469 * iq2000-desc.c: Regenerate.
470 * iq2000-desc.h: Regenerate.
471 * iq2000-opc.c: Regenerate.
472 * iq2000-opc.h: Regenerate.
473 * m32r-desc.c: Regenerate.
474 * m32r-desc.h: Regenerate.
475 * m32r-opc.c: Regenerate.
476 * m32r-opc.h: Regenerate.
477 * m32r-opinst.c: Regenerate.
478 * openrisc-desc.c: Regenerate.
479 * openrisc-desc.h: Regenerate.
480 * openrisc-opc.c: Regenerate.
481 * openrisc-opc.h: Regenerate.
482 * xstormy16-desc.c: Regenerate.
483 * xstormy16-desc.h: Regenerate.
484 * xstormy16-opc.c: Regenerate.
485 * xstormy16-opc.h: Regenerate.
486
db9db6f2
AM		 4872005-02-21 Alan Modra <amodra@bigpond.net.au>
488
489 * Makefile.am: Run "make dep-am"
490 * Makefile.in: Regenerate.
491
bf143b25
NC		 4922005-02-15 Nick Clifton <nickc@redhat.com>
493
494 * cgen-dis.in (print_address): Add an ATTRIBUTE_UNUSED to prevent
495 compile time warnings.
496 (print_keyword): Likewise.
497 (default_print_insn): Likewise.
498
499 * fr30-desc.c: Regenerated.
500 * fr30-desc.h: Regenerated.
501 * fr30-dis.c: Regenerated.
502 * fr30-opc.c: Regenerated.
503 * fr30-opc.h: Regenerated.
504 * frv-desc.c: Regenerated.
505 * frv-dis.c: Regenerated.
506 * frv-opc.c: Regenerated.
507 * ip2k-asm.c: Regenerated.
508 * ip2k-desc.c: Regenerated.
509 * ip2k-desc.h: Regenerated.
510 * ip2k-dis.c: Regenerated.
511 * ip2k-opc.c: Regenerated.
512 * ip2k-opc.h: Regenerated.
513 * iq2000-desc.c: Regenerated.
514 * iq2000-dis.c: Regenerated.
515 * iq2000-opc.c: Regenerated.
516 * m32r-asm.c: Regenerated.
517 * m32r-desc.c: Regenerated.
518 * m32r-desc.h: Regenerated.
519 * m32r-dis.c: Regenerated.
520 * m32r-opc.c: Regenerated.
521 * m32r-opc.h: Regenerated.
522 * m32r-opinst.c: Regenerated.
523 * openrisc-desc.c: Regenerated.
524 * openrisc-desc.h: Regenerated.
525 * openrisc-dis.c: Regenerated.
526 * openrisc-opc.c: Regenerated.
527 * openrisc-opc.h: Regenerated.
528 * xstormy16-desc.c: Regenerated.
529 * xstormy16-desc.h: Regenerated.
530 * xstormy16-dis.c: Regenerated.
531 * xstormy16-opc.c: Regenerated.
532 * xstormy16-opc.h: Regenerated.
533
d6098898
L		 5342005-02-14 H.J. Lu <hongjiu.lu@intel.com>
535
536 * dis-buf.c (perror_memory): Use sprintf_vma to print out
537 address.
538
5a84f3e0
NC		 5392005-02-11 Nick Clifton <nickc@redhat.com>
540
bc18c937
NC		 541 * iq2000-asm.c: Regenerate.
542
5a84f3e0
NC		 543 * frv-dis.c: Regenerate.
544
0a40490e
JB		 5452005-02-07 Jim Blandy <jimb@redhat.com>
546
547 * Makefile.am (CGEN): Load guile.scm before calling the main
548 application script.
549 * Makefile.in: Regenerated.
550 * cgen.sh: Be prepared for the 'cgen' argument to contain spaces.
551 Simply pass the cgen-opc.scm path to ${cgen} as its first
552 argument; ${cgen} itself now contains the '-s', or whatever is
553 appropriate for the Scheme being used.
554
c46f8c51
AC		 5552005-01-31 Andrew Cagney <cagney@gnu.org>
556
557 * configure: Regenerate to track ../gettext.m4.
558
60b9a617
JB		 5592005-01-31 Jan Beulich <jbeulich@novell.com>
560
561 * ia64-gen.c (NELEMS): Define.
562 (shrink): Generate alias with missing second predicate register when
563 opcode has two outputs and these are both predicates.
564 * ia64-opc-i.c (FULL17): Define.
565 (ia64_opcodes_i): Add mov-to-pr alias without second input. Use FULL17
566 here to generate output template.
567 (TBITCM, TNATCM): Undefine after use.
568 * ia64-opc-m.c (ia64_opcodes_i): Add alloc alias without ar.pfs as
569 first input. Add ld16 aliases without ar.csd as second output. Add
570 st16 aliases without ar.csd as second input. Add cmpxchg aliases
571 without ar.ccv as third input. Add cmp8xchg16 aliases without ar.csd/
572 ar.ccv as third/fourth inputs. Consolidate through...
573 (CMPXCHG_acq, CMPXCHG_rel, CMPXCHG_1, CMPXCHG_2, CMPXCHG_4, CMPXCHG_8,
574 CMPXCHGn, CMP8XCHG16, CMPXCHG_ALL): Define.
575 * ia64-asmtab.c: Regenerate.
576
a53bf506
AC		 5772005-01-27 Andrew Cagney <cagney@gnu.org>
578
579 * configure: Regenerate to track ../gettext.m4 change.
580
90219bd0
AO		 5812005-01-25 Alexandre Oliva <aoliva@redhat.com>
582
583 2004-11-10 Alexandre Oliva <aoliva@redhat.com>
584 * frv-asm.c: Rebuilt.
585 * frv-desc.c: Rebuilt.
586 * frv-desc.h: Rebuilt.
587 * frv-dis.c: Rebuilt.
588 * frv-ibld.c: Rebuilt.
589 * frv-opc.c: Rebuilt.
590 * frv-opc.h: Rebuilt.
591
45181ed1
AC		 5922005-01-24 Andrew Cagney <cagney@gnu.org>
593
594 * configure: Regenerate, ../gettext.m4 was updated.
595
9e836e3d
FF		 5962005-01-21 Fred Fish <fnf@specifixinc.com>
597
598 * mips-opc.c: Change INSN_ALIAS to INSN2_ALIAS.
599 Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC.
600 Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC.
601 * mips-dis.c: Ditto.
602
5e8cb021
AM		 6032005-01-20 Alan Modra <amodra@bigpond.net.au>
604
605 * ppc-opc.c (powerpc_opcodes): Add optional 'l' arg to tlbiel.
606
986e18a5
FF		 6072005-01-19 Fred Fish <fnf@specifixinc.com>
608
609 * mips-dis.c (no_aliases): New disassembly option flag.
610 (set_default_mips_dis_options): Init no_aliases to zero.
611 (parse_mips_dis_option): Handle no-aliases option.
612 (print_insn_mips): Ignore table entries that are aliases
613 if no_aliases is set.
614 (print_insn_mips16): Ditto.
615 * mips-opc.c (mips_builtin_opcodes): Add initializer column for
616 new pinfo2 member and add INSN_ALIAS initializers as needed. Also
617 move WR_MACC and RD_MACC initializers from pinfo to pinfo2.
618 * mips16-opc.c (mips16_opcodes): Ditto.
619
e38bc3b5
NC		 6202005-01-17 Andrew Stubbs <andrew.stubbs@st.com>
621
622 * sh-opc.h (arch_sh2a_or_sh3e,arch_sh2a_or_sh4): Correct definition.
623 (inheritance diagram): Add missing edge.
624 (arch_sh1_up): Rename arch_sh_up to match external name to make life
625 easier for the testsuite.
626 (arch_sh4_nofp_up): Likewise, rename arch_sh4_nofpu_up.
627 (arch_sh4a_nofp_up): Likewise, rename arch_sh4a_nofpu_up.
610ad19b 628 (arch_sh2a_nofpu_or_sh4_nommu_nofpu_up): Add missing
e38bc3b5
NC		 629 arch_sh2a_or_sh4_up child.
630 (sh_table): Do renaming as above.
631 Correct comment for ldc.l for gas testsuite to read.
632 Remove rogue mul.l from sh1 (duplicate of the one for sh2).
633 Correct comments for movy.w and movy.l for gas testsuite to read.
634 Correct comments for fmov.d and fmov.s for gas testsuite to read.
635
9df48ba9
L		 6362005-01-12 H.J. Lu <hongjiu.lu@intel.com>
637
638 * i386-dis.c (OP_E): Don't ignore scale in SIB for 64 bit mode.
639
2033b4b9
L		 6402005-01-12 H.J. Lu <hongjiu.lu@intel.com>
641
642 * i386-dis.c (OP_E): Ignore scale when index == 0x4 in SIB.
643
0bcb06d2
AS		 6442005-01-10 Andreas Schwab <schwab@suse.de>
645
646 * disassemble.c (disassemble_init_for_target) <case
647 bfd_arch_ia64>: Set skip_zeroes to 16.
648 <case bfd_arch_tic4x>: Set skip_zeroes to 32.
649
47add74d
TL		 6502004-12-23 Tomer Levi <Tomer.Levi@nsc.com>
651
652 * crx-opc.c: Mark 'bcop' instruction as RELAXABLE.
653
246f4c05
SS		 6542004-12-14 Svein E. Seldal <Svein.Seldal@solidas.com>
655
656 * avr-dis.c: Prettyprint. Added printing of symbol names in all
657 memory references. Convert avr_operand() to C90 formatting.
658
0e1200e5
TL		 6592004-12-05 Tomer Levi <Tomer.Levi@nsc.com>
660
661 * crx-dis.c (print_arg): Use 'info->print_address_func' for address printing.
662
89a649f7
TL		 6632004-11-29 Tomer Levi <Tomer.Levi@nsc.com>
664
665 * crx-opc.c (crx_optab): Mark all rbase_disps* operands as signed.
666 (no_op_insn): Initialize array with instructions that have no
667 operands.
668 * crx-dis.c (make_instruction): Get rid of COP_BRANCH_INS operand swapping.
669
6255809c
RE		 6702004-11-29 Richard Earnshaw <rearnsha@arm.com>
671
672 * arm-dis.c: Correct top-level comment.
673
2fbad815
RE		 6742004-11-27 Richard Earnshaw <rearnsha@arm.com>
675
676 * arm-opc.h (arm_opcode, thumb_opcode): Add extra field for the
677 architecuture defining the insn.
678 (arm_opcodes, thumb_opcodes): Delete. Move to ...
6b8725b9
RE		 679 * arm-dis.c (arm_opcodes, thumb_opcodes): Here. Add architecutre
680 field.
2fbad815
RE		 681 Also include opcode/arm.h.
682 * Makefile.am (arm-dis.lo): Update dependency list.
683 * Makefile.in: Regenerate.
684
d81acc42
NC		 6852004-11-22 Ravi Ramaseshan <ravi.ramaseshan@codito.com>
686
687 * opcode/arc-opc.c (insert_base): Modify ls_operand[LS_OFFSET] to
688 reflect the change to the short immediate syntax.
689
ca4f2377
AM		 6902004-11-19 Alan Modra <amodra@bigpond.net.au>
691
5da8bf1b
AM		 692 * or32-opc.c (debug): Warning fix.
693 * po/POTFILES.in: Regenerate.
694
ca4f2377
AM		 695 * maxq-dis.c: Formatting.
696 (print_insn): Warning fix.
697
b7693d02
DJ		 6982004-11-17 Daniel Jacobowitz <dan@codesourcery.com>
699
700 * arm-dis.c (WORD_ADDRESS): Define.
701 (print_insn): Use it. Correct big-endian end-of-section handling.
702
300dac7e
NC		 7032004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com>
704 Vineet Sharma <vineets@noida.hcltech.com>
705
706 * maxq-dis.c: New file.
707 * disassemble.c (ARCH_maxq): Define.
610ad19b 708 (disassembler): Add 'print_insn_maxq_little' for handling maxq
300dac7e
NC		 709 instructions..
710 * configure.in: Add case for bfd_maxq_arch.
711 * configure: Regenerate.
712 * Makefile.am: Add support for maxq-dis.c
713 * Makefile.in: Regenerate.
714 * aclocal.m4: Regenerate.
715
42048ee7
TL		 7162004-11-05 Tomer Levi <Tomer.Levi@nsc.com>
717
718 * crx-opc.c (crx_optab): Rename 'arg_icr' to 'arg_idxr' for Index register
719 mode.
720 * crx-dis.c: Likewise.
721
bd21e58e
HPN		 7222004-11-04 Hans-Peter Nilsson <hp@axis.com>
723
724 Generally, handle CRISv32.
725 * cris-dis.c (TRACE_CASE): Define as (disdata->trace_case).
726 (struct cris_disasm_data): New type.
727 (format_reg, format_hex, cris_constraint, print_flags)
728 (get_opcode_entry): Add struct cris_disasm_data * parameter. All
729 callers changed.
730 (format_sup_reg, print_insn_crisv32_with_register_prefix)
731 (print_insn_crisv32_without_register_prefix)
732 (print_insn_crisv10_v32_with_register_prefix)
733 (print_insn_crisv10_v32_without_register_prefix)
734 (cris_parse_disassembler_options): New functions.
735 (bytes_to_skip, cris_spec_reg): Add enum cris_disass_family
736 parameter. All callers changed.
737 (get_opcode_entry): Call malloc, not xmalloc. Return NULL on
738 failure.
739 (cris_constraint) <case 'Y', 'U'>: New cases.
740 (bytes_to_skip): Handle 'Y' and 'N' as 's'. Skip size is 4 bytes
741 for constraint 'n'.
742 (print_with_operands) <case 'Y'>: New case.
743 (print_with_operands) <case 'T', 'A', '[', ']', 'd', 'n', 'u'>
744 <case 'N', 'Y', 'Q'>: New cases.
745 (print_insn_cris_generic): Emit "bcc ." for zero and CRISv32.
746 (print_insn_cris_with_register_prefix)
747 (print_insn_cris_without_register_prefix): Call
748 cris_parse_disassembler_options.
749 * cris-opc.c (cris_spec_regs): Mention that this table isn't used
750 for CRISv32 and the size of immediate operands. New v32-only
751 entries for bz, pid, srs, wz, exs, eda, dz, ebp, erp, nrp, ccs and
752 spc. Add v32-only 4-byte entries for p2, p3, p5 and p6. Change
753 ccr, ibr, irp to be v0..v10. Change bar, dccr to be v8..v10.
754 Change brp to be v3..v10.
755 (cris_support_regs): New vector.
756 (cris_opcodes): Update head comment. New format characters '[',
757 ']', space, 'A', 'd', 'N', 'n', 'Q', 'T', 'u', 'U', 'Y'.
758 Add new opcodes for v32 and adjust existing opcodes to accommodate
759 differences to earlier variants.
760 (cris_cond15s): New vector.
761
9306ca4a
JB		 7622004-11-04 Jan Beulich <jbeulich@novell.com>
763
764 * i386-dis.c (Eq, Edqw, indirEp, Gdq, I1): Define.
765 (indirEb): Remove.
766 (Mp): Use f_mode rather than none at all.
767 (t_mode, dq_mode, dqw_mode, f_mode, const_1_mode): Define. t_mode
768 replaces what previously was x_mode; x_mode now means 128-bit SSE
769 operands.
770 (dis386): Make far jumps and calls have an 'l' prefix only in AT&T
771 mode. movmskpX's, pextrw's, and pmovmskb's first operands are Gdq.
772 pinsrw's second operand is Edqw.
773 (grps): 1-bit shifts' and rotates' second operands are I1. cmpxchg8b's
774 operand is Eq. movntq's and movntdq's first operands are EM. s[gi]dt,
775 fldenv, frstor, fsave, fstenv all should also have suffixes in Intel
776 mode when an operand size override is present or always suffixing.
777 More instructions will need to be added to this group.
778 (putop): Handle new macro chars 'C' (short/long suffix selector),
779 'I' (Intel mode override for following macro char), and 'J' (for
780 adding the 'l' prefix to far branches in AT&T mode). When an
781 alternative was specified in the template, honor macro character when
782 specified for Intel mode.
783 (OP_E): Handle new *_mode values. Correct pointer specifications for
784 memory operands. Consolidate output of index register.
785 (OP_G): Handle new *_mode values.
786 (OP_I): Handle const_1_mode.
787 (OP_ESreg, OP_DSreg): Generate pointer specifications. Indicate
788 respective opcode prefix bits have been consumed.
789 (OP_EM, OP_EX): Provide some default handling for generating pointer
790 specifications.
791
f39c96a9
TL		 7922004-10-28 Tomer Levi <Tomer.Levi@nsc.com>
793
794 * crx-opc.c (REV_COP_INST): New macro, reverse operand order of
795 COP_INST macro.
796
812337be
TL		 7972004-10-27 Tomer Levi <Tomer.Levi@nsc.com>
798
799 * crx-dis.c (enum REG_ARG_TYPE): New, replacing COP_ARG_TYPE.
800 (getregliststring): Support HI/LO and user registers.
610ad19b 801 * crx-opc.c (crx_instruction): Update data structure according to the
812337be
TL		 802 rearrangement done in CRX opcode header file.
803 (crx_regtab): Likewise.
804 (crx_optab): Likewise.
610ad19b 805 (crx_instruction): Reorder load/stor instructions, remove unsupported
812337be
TL		 806 formats.
807 support new Co-Processor instruction 'cpi'.
808
4030fa5a
NC		 8092004-10-27 Nick Clifton <nickc@redhat.com>
810
811 * opcodes/iq2000-asm.c: Regenerate.
812 * opcodes/iq2000-desc.c: Regenerate.
813 * opcodes/iq2000-desc.h: Regenerate.
814 * opcodes/iq2000-dis.c: Regenerate.
815 * opcodes/iq2000-ibld.c: Regenerate.
816 * opcodes/iq2000-opc.c: Regenerate.
817 * opcodes/iq2000-opc.h: Regenerate.
818
fc3d45e8
TL		 8192004-10-21 Tomer Levi <Tomer.Levi@nsc.com>
820
821 * crx-opc.c (crx_instruction): Replace i3, i4, i5 with us3,
822 us4, us5 (respectively).
823 Remove unsupported 'popa' instruction.
824 Reverse operands order in store co-processor instructions.
825
3c55da70
AM		 8262004-10-15 Alan Modra <amodra@bigpond.net.au>
827
828 * Makefile.am: Run "make dep-am"
829 * Makefile.in: Regenerate.
830
7fa3d080
BW		 8312004-10-12 Bob Wilson <bob.wilson@acm.org>
832
833 * xtensa-dis.c: Use ISO C90 formatting.
834
e612bb4d
AM		 8352004-10-09 Alan Modra <amodra@bigpond.net.au>
836
837 * ppc-opc.c: Revert 2004-09-09 change.
838
43cd72b9
BW		 8392004-10-07 Bob Wilson <bob.wilson@acm.org>
840
841 * xtensa-dis.c (state_names): Delete.
842 (fetch_data): Use xtensa_isa_maxlength.
843 (print_xtensa_operand): Replace operand parameter with opcode/operand
844 pair. Remove print_sr_name parameter. Use new xtensa-isa.h functions.
845 (print_insn_xtensa): Use new xtensa-isa.h functions. Handle multislot
846 instruction bundles. Use xmalloc instead of malloc.
847
bbac1f2a
NC		 8482004-10-07 David Gibson <david@gibson.dropbear.id.au>
849
850 * ppc-opc.c: Replace literal "0"s with NULLs in pointer
851 initializers.
852
48c9f030
NC		 8532004-10-07 Tomer Levi <Tomer.Levi@nsc.com>
854
855 * crx-opc.c (crx_instruction): Support Co-processor insns.
856 * crx-dis.c (COP_ARG_TYPE): New enum for CO-Processor arguments.
857 (getregliststring): Change function to use the above enum.
858 (print_arg): Handle CO-Processor insns.
859 (crx_cinvs): Add 'b' option to invalidate the branch-target
860 cache.
861
12c64a4e
AH		 8622004-10-06 Aldy Hernandez <aldyh@redhat.com>
863
864 * ppc-opc.c (powerpc_opcodes): Add efscfd, efdabs, efdnabs,
865 efdneg, efdadd, efdsub, efdmul, efddiv, efdcmpgt, efdcmplt,
866 efdcmpeq, efdtstgt, efdtstlt, efdtsteq, efdcfsi, efdcfsid,
867 efdcfui, efdcfuid, efdcfsf, efdcfuf, efdctsi, efdctsidz, efdctsiz,
868 efdctui, efdctuidz, efdctuiz, efdctsf, efdctuf, efdctuf, efdcfs.
869
14127cc4
NC		 8702004-10-01 Bill Farmer <Bill@the-farmers.freeserve.co.uk>
871
872 * pdp11-dis.c (print_insn_pdp11): Subtract the SOB's displacement
873 rather than add it.
874
0dd132b6
NC		 8752004-09-30 Paul Brook <paul@codesourcery.com>
876
877 * arm-dis.c (print_insn_arm): Handle 'e' for SMI instruction.
878 * arm-opc.h: Document %e. Add ARMv6ZK instructions.
879
3f85e526
L		 8802004-09-17 H.J. Lu <hongjiu.lu@intel.com>
881
882 * Makefile.am (AUTOMAKE_OPTIONS): Require 1.9.
883 (CONFIG_STATUS_DEPENDENCIES): New.
884 (Makefile): Removed.
885 (config.status): Likewise.
886 * Makefile.in: Regenerated.
887
8ae85421
AM		 8882004-09-17 Alan Modra <amodra@bigpond.net.au>
889
890 * Makefile.am: Run "make dep-am".
891 * Makefile.in: Regenerate.
892 * aclocal.m4: Regenerate.
893 * configure: Regenerate.
894 * po/POTFILES.in: Regenerate.
895 * po/opcodes.pot: Regenerate.
896
24443139
AS		 8972004-09-11 Andreas Schwab <schwab@suse.de>
898
899 * configure: Rebuild.
900
2a309db0
AM		 9012004-09-09 Segher Boessenkool <segher@kernel.crashing.org>
902
903 * ppc-opc.c (L): Make this field not optional.
904
42851540
NC		 9052004-09-03 Tomer Levi <Tomer.Levi@nsc.com>
906
907 * opc-crx.c: Rename 'popma' to 'popa', remove 'pushma'.
908 Fix parameter to 'm[t|f]csr' insns.
909
979273e3
NN		 9102004-08-30 Nathanael Nerode <neroden@gcc.gnu.org>
911
912 * configure.in: Autoupdate to autoconf 2.59.
913 * aclocal.m4: Rebuild with aclocal 1.4p6.
914 * configure: Rebuild with autoconf 2.59.
915 * Makefile.in: Rebuild with automake 1.4p6 (picking up
916 bfd changes for autoconf 2.59 on the way).
917 * config.in: Rebuild with autoheader 2.59.
918
ac28a1cb
RS		 9192004-08-27 Richard Sandiford <rsandifo@redhat.com>
920
921 * frv-desc.[ch], frv-opc.[ch]: Regenerated.
922
30d1c836
ML		 9232004-07-30 Michal Ludvig <mludvig@suse.cz>
924
925 * i386-dis.c (GRPPADLCK): Renamed to GRPPADLCK1
926 (GRPPADLCK2): New define.
927 (twobyte_has_modrm): True for 0xA6.
928 (grps): GRPPADLCK2 for opcode 0xA6.
929
0b0ac059
AO		 9302004-07-29 Alexandre Oliva <aoliva@redhat.com>
931
932 Introduce SH2a support.
933 * sh-opc.h (arch_sh2a_base): Renumber.
934 (arch_sh2a_nofpu_base): Remove.
935 (arch_sh_base_mask): Adjust.
936 (arch_opann_mask): New.
937 (arch_sh2a, arch_sh2a_nofpu): Adjust.
938 (arch_sh2a_up, arch_sh2a_nofpu_up): Likewise.
939 (sh_table): Adjust whitespace.
940 2004-02-24 Corinna Vinschen <vinschen@redhat.com>
941 * sh-opc.h (arch_sh2a_nofpu_up): New. Use instead of arch_sh2a_up in
942 instruction list throughout.
943 (arch_sh2a_up): Redefine to include fpu instruction set. Use instead
944 of arch_sh2a in instruction list throughout.
945 (arch_sh2e_up): Accomodate above changes.
946 (arch_sh2_up): Ditto.
947 2004-02-20 Corinna Vinschen <vinschen@redhat.com>
948 * sh-opc.h: Add arch_sh2a_nofpu to arch_sh2_up.
949 2004-02-18 Corinna Vinschen <vinschen@redhat.com>
950 * sh-dis.c (print_insn_sh): Add bfd_mach_sh2a_nofpu handling.
951 * sh-opc.h (arch_sh2a_nofpu): New.
952 (arch_sh2a_up): New, defines sh2a and sh2a_nofpu.
953 (sh_table): Change all arch_sh2a to arch_sh2a_up unless FPU
954 instruction.
955 2004-01-20 DJ Delorie <dj@redhat.com>
956 * sh-dis.c (print_insn_sh): SH2A does not have 'X' fp regs.
957 2003-12-29 DJ Delorie <dj@redhat.com>
958 * sh-opc.c (sh_nibble_type, sh_arg_type, arch_2a, arch_2e_up,
959 sh_opcode_info, sh_table): Add sh2a support.
960 (arch_op32): New, to tag 32-bit opcodes.
961 * sh-dis.c (print_insn_sh): Support sh2a opcodes.
962 2003-12-02 Michael Snyder <msnyder@redhat.com>
963 * sh-opc.h (arch_sh2a): Add.
964 * sh-dis.c (arch_sh2a): Handle.
965 * sh-opc.h (arch_sh2_up): Fix up to include arch_sh2a.
966
670ec21d
NC		 9672004-07-27 Tomer Levi <Tomer.Levi@nsc.com>
968
969 * crx-opc.c: Add popx,pushx insns. Indent code, fix comments.
970
ed049af3
NC		 9712004-07-22 Nick Clifton <nickc@redhat.com>
972
973 PR/280
974 * h8300-dis.c (bfd_h8_disassemble): Do not dump raw bytes for the
975 insns - this is done by objdump itself.
976 * h8500-dis.c (print_insn_h8500): Likewise.
977
20f0a1fc
NC		 9782004-07-21 Jan Beulich <jbeulich@novell.com>
979
980 * i386-dis.c (OP_E): Show rip-relative addressing in 64-bit mode
981 regardless of address size prefix in effect.
982 (ptr_reg): Size or address registers does not depend on rex64, but
983 on the presence of an address size override.
984 (OP_MMX): Use rex.x only for xmm registers.
985 (OP_EM): Use rex.z only for xmm registers.
986
6f14957b
MR		 9872004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
988
989 * mips-opc.c (mips_builtin_opcodes): Move coprocessor 2
990 move/branch operations to the bottom so that VR5400 multimedia
991 instructions take precedence in disassembly.
992
1586d91e
MR		 9932004-07-20 Maciej W. Rozycki <macro@linux-mips.org>
994
995 * mips-opc.c (mips_builtin_opcodes): Remove the MIPS32
996 ISA-specific "break" encoding.
997
982de27a
NC		 9982004-07-13 Elvis Chiang <elvisfb@gmail.com>
999
1000 * arm-opc.h: Fix typo in comment.
1001
4300ab10
AS		 10022004-07-11 Andreas Schwab <schwab@suse.de>
1003
1004 * m68k-dis.c (m68k_valid_ea): Fix typos in last change.
1005
8577e690
AS		 10062004-07-09 Andreas Schwab <schwab@suse.de>
1007
1008 * m68k-dis.c (m68k_valid_ea): Check validity of all codes.
1009
1fe1f39c
NC		 10102004-07-07 Tomer Levi <Tomer.Levi@nsc.com>
1011
1012 * Makefile.am (CFILES): Add crx-dis.c, crx-opc.c.
1013 (ALL_MACHINES): Add crx-dis.lo, crx-opc.lo.
1014 (crx-dis.lo): New target.
1015 (crx-opc.lo): Likewise.
1016 * Makefile.in: Regenerate.
1017 * configure.in: Handle bfd_crx_arch.
1018 * configure: Regenerate.
1019 * crx-dis.c: New file.
1020 * crx-opc.c: New file.
1021 * disassemble.c (ARCH_crx): Define.
1022 (disassembler): Handle ARCH_crx.
1023
7a33b495
JW		 10242004-06-29 James E Wilson <wilson@specifixinc.com>
1025
1026 * ia64-opc-a.c (ia64_opcodes_a): Delete mov immediate pseudo for adds.
1027 * ia64-asmtab.c: Regnerate.
1028
98e69875
AM		 10292004-06-28 Alan Modra <amodra@bigpond.net.au>
1030
1031 * ppc-opc.c (insert_fxm): Handle mfocrf and mtocrf.
1032 (extract_fxm): Don't test dialect.
1033 (XFXFXM_MASK): Include the power4 bit.
1034 (XFXM): Add p4 param.
1035 (powerpc_opcodes): Add mfocrf and mtocrf. Adjust mtcr.
1036
a53b85e2
AO		 10372004-06-27 Alexandre Oliva <aoliva@redhat.com>
1038
1039 2003-07-21 Richard Sandiford <rsandifo@redhat.com>
1040 * disassemble.c (disassembler): Handle bfd_mach_h8300sxn.
1041
d0618d1c
AM		 10422004-06-26 Alan Modra <amodra@bigpond.net.au>
1043
1044 * ppc-opc.c (BH, XLBH_MASK): Define.
1045 (powerpc_opcodes): Allow BH field on bclr, bclrl, bcctr, bcctrl.
1046
1d9f512f
AM		 10472004-06-24 Alan Modra <amodra@bigpond.net.au>
1048
1049 * i386-dis.c (x_mode): Comment.
1050 (two_source_ops): File scope.
1051 (float_mem): Correct fisttpll and fistpll.
1052 (float_mem_mode): New table.
1053 (dofloat): Use it.
1054 (OP_E): Correct intel mode PTR output.
1055 (ptr_reg): Use open_char and close_char.
1056 (PNI_Fixup): Handle possible suffix on sidt. Use op1out etc. for
1057 operands. Set two_source_ops.
1058
52886d70
AM		 10592004-06-15 Alan Modra <amodra@bigpond.net.au>
1060
1061 * arc-ext.c (build_ARC_extmap): Use bfd_get_section_size
1062 instead of _raw_size.
1063
bad9ceea
JJ		 10642004-06-08 Jakub Jelinek <jakub@redhat.com>
1065
1066 * ia64-gen.c (in_iclass): Handle more postinc st
1067 and ld variants.
1068 * ia64-asmtab.c: Rebuilt.
1069
0451f5df
MS		 10702004-06-01 Martin Schwidefsky <schwidefsky@de.ibm.com>
1071
1072 * s390-opc.txt: Correct architecture mask for some opcodes.
1073 lrv, lrvh, strv, ml, dl, alc, slb rll and mvclu are available
1074 in the esa mode as well.
1075
f6f9408f
JR		 10762004-05-28 Andrew Stubbs <andrew.stubbs@superh.com>
1077
1078 * sh-dis.c (target_arch): Make unsigned.
1079 (print_insn_sh): Replace (most of) switch with a call to
1080 sh_get_arch_from_bfd_mach(). Also use new architecture flags system.
1081 * sh-opc.h: Redefine architecture flags values.
1082 Add sh3-nommu architecture.
1083 Reorganise <arch>_up macros so they make more visual sense.
1084 (SH_MERGE_ARCH_SET): Define new macro.
1085 (SH_VALID_BASE_ARCH_SET): Likewise.
1086 (SH_VALID_MMU_ARCH_SET): Likewise.
1087 (SH_VALID_CO_ARCH_SET): Likewise.
1088 (SH_VALID_ARCH_SET): Likewise.
1089 (SH_MERGE_ARCH_SET_VALID): Likewise.
1090 (SH_ARCH_SET_HAS_FPU): Likewise.
1091 (SH_ARCH_SET_HAS_DSP): Likewise.
1092 (SH_ARCH_UNKNOWN_ARCH): Likewise.
1093 (sh_get_arch_from_bfd_mach): Add prototype.
1094 (sh_get_arch_up_from_bfd_mach): Likewise.
1095 (sh_get_bfd_mach_from_arch_set): Likewise.
1096 (sh_merge_bfd_arc): Likewise.
1097
be8c092b
NC		 10982004-05-24 Peter Barada <peter@the-baradas.com>
1099
1100 * m68k-dis.c(print_insn_m68k): Strip body of diassembly out
610ad19b
AM		 1101 into new match_insn_m68k function. Loop over canidate
1102 matches and select first that completely matches.
be8c092b
NC		 1103 * m68k-dis.c(print_insn_arg): Fix 'g' case to only extract 1 bit.
1104 * m68k-dis.c(print_insn_arg): Call new function m68k_valid_ea
610ad19b 1105 to verify addressing for MAC/EMAC.
be8c092b
NC		 1106 * m68k-dis.c(print_insn_arg): Use reg_half_names for MAC/EMAC
1107 reigster halves since 'fpu' and 'spl' look misleading.
1108 * m68k-dis.c(fetch_arg): Fix 'G', 'H', 'I', 'f', 'M', 'N' cases.
1109 * m68k-opc.c: Rearragne mac/emac cases to use longest for
1110 first, tighten up match masks.
1111 * m68k-opc.c: Add 'size' field to struct m68k_opcode. Produce
1112 'size' from special case code in print_insn_m68k to
1113 determine decode size of insns.
1114
a30e9cc4
AM		 11152004-05-19 Alan Modra <amodra@bigpond.net.au>
1116
1117 * ppc-opc.c (insert_fxm): Enable two operand mfcr when -many as
1118 well as when -mpower4.
1119
9598fbe5
NC		 11202004-05-13 Nick Clifton <nickc@redhat.com>
1121
1122 * po/fr.po: Updated French translation.
1123
6b6e92f4
NC		 11242004-05-05 Peter Barada <peter@the-baradas.com>
1125
1126 * m68k-dis.c(print_insn_m68k): Add new chips, use core
1127 variants in arch_mask. Only set m68881/68851 for 68k chips.
1128 * m68k-op.c: Switch from ColdFire chips to core variants.
1129
a404d431
AM		 11302004-05-05 Alan Modra <amodra@bigpond.net.au>
1131
a30e9cc4 1132 PR 147.
a404d431
AM		 1133 * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC.
1134
f3806e43
BE		 11352004-04-29 Ben Elliston <bje@au.ibm.com>
1136
520ceea4
BE		 1137 * ppc-opc.c (XCMPL): Renmame to XOPL. Update users.
1138 (powerpc_opcodes): Add "dbczl" instruction for PPC970.
f3806e43 1139
1f1799d5
KK		 11402004-04-22 Kaz Kojima <kkojima@rr.iij4u.or.jp>
1141
1142 * sh-dis.c (print_insn_sh): Print the value in constant pool
1143 as a symbol if it looks like a symbol.
1144
fd99574b
NC		 11452004-04-22 Peter Barada <peter@the-baradas.com>
1146
1147 * m68k-dis.c(print_insn_m68k): Set mfcmac/mcfemac on
1148 appropriate ColdFire architectures.
1149 (print_insn_m68k): Handle EMAC, MAC/EMAC scalefactor, and MAC/EMAC
1150 mask addressing.
1151 Add EMAC instructions, fix MAC instructions. Remove
1152 macmw/macml/msacmw/msacml instructions since mask addressing now
1153 supported.
1154
b4781d44
JJ		 11552004-04-20 Jakub Jelinek <jakub@redhat.com>
1156
1157 * sparc-opc.c (fmoviccx, fmovfccx, fmovccx): Define.
1158 (fmovicc, fmovfcc, fmovcc): Remove fpsize argument, change opcode to
1159 suffix. Use fmov*x macros, create all 3 fpsize variants in one
1160 macro. Adjust all users.
1161
91809fda 11622004-04-15 Anil Paranjpe <anilp1@kpitcummins.com>
610ad19b 1163
91809fda
NC		 1164 * h8300-dis.c (bfd_h8_disassemble) : Treat "adds" & "subs"
1165 separately.
1166
f4453dfa
NC		 11672004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
1168
1169 * m32r-asm.c: Regenerate.
1170
9b0de91a
SS		 11712004-03-29 Stan Shebs <shebs@apple.com>
1172
1173 * mpw-config.in, mpw-make.sed: Remove MPW support files, no longer
1174 used.
1175
e20c0b3d
AM		 11762004-03-19 Alan Modra <amodra@bigpond.net.au>
1177
1178 * aclocal.m4: Regenerate.
1179 * config.in: Regenerate.
1180 * configure: Regenerate.
1181 * po/POTFILES.in: Regenerate.
1182 * po/opcodes.pot: Regenerate.
1183
fdd12ef3
AM		 11842004-03-16 Alan Modra <amodra@bigpond.net.au>
1185
1186 * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle
1187 PPC_OPERANDS_GPR_0.
1188 * ppc-opc.c (RA0): Define.
1189 (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0.
1190 (RAOPT): Rename from RAO. Update all uses.
a9c3619e 1191 (powerpc_opcodes): Use RA0 as appropriate.
fdd12ef3 1192
2dc111b3 11932004-03-15 Aldy Hernandez <aldyh@redhat.com>
fdd12ef3
AM		 1194
1195 * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg.
2dc111b3 1196
7bfeee7b
AM		 11972004-03-15 Alan Modra <amodra@bigpond.net.au>
1198
1199 * sparc-dis.c (print_insn_sparc): Update getword prototype.
1200
7ffdda93
ML		 12012004-03-12 Michal Ludvig <mludvig@suse.cz>
1202
1203 * i386-dis.c (GRPPLOCK): Delete.
7bfeee7b 1204 (grps): Delete GRPPLOCK entry.
7ffdda93 1205
cc0ec051
AM		 12062004-03-12 Alan Modra <amodra@bigpond.net.au>
1207
1208 * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions.
1209 (M, Mp): Use OP_M.
1210 (None, PADLOCK_SPECIAL, PADLOCK_0): Delete.
1211 (GRPPADLCK): Define.
1212 (dis386): Use NOP_Fixup on "nop".
1213 (dis386_twobyte): Use GRPPADLCK on opcode 0xa7.
1214 (twobyte_has_modrm): Set for 0xa7.
1215 (padlock_table): Delete. Move to..
1216 (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence
1217 and clflush.
1218 (print_insn): Revert PADLOCK_SPECIAL code.
1219 (OP_E): Delete sfence, lfence, mfence checks.
1220
4fd61dcb
JJ		 12212004-03-12 Jakub Jelinek <jakub@redhat.com>
1222
1223 * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg.
1224 (INVLPG_Fixup): New function.
1225 (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag.
1226
0f10071e
ML		 12272004-03-12 Michal Ludvig <mludvig@suse.cz>
1228
1229 * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines.
1230 (dis386_twobyte): Opcode 0xa7 is PADLOCK_0.
1231 (padlock_table): New struct with PadLock instructions.
1232 (print_insn): Handle PADLOCK_SPECIAL.
1233
c02908d2
AM		 12342004-03-12 Alan Modra <amodra@bigpond.net.au>
1235
1236 * i386-dis.c (grps): Use clflush by default for 0x0fae/7.
1237 (OP_E): Twiddle clflush to sfence here.
1238
d5bb7600
NC		 12392004-03-08 Nick Clifton <nickc@redhat.com>
1240
1241 * po/de.po: Updated German translation.
1242
ae51a426
JR		 12432003-03-03 Andrew Stubbs <andrew.stubbs@superh.com>
1244
1245 * sh-dis.c (print_insn_sh): Don't disassemble fp instructions in
1246 nofpu mode. Add BFD type bfd_mach_sh4_nommu_nofpu.
1247 * sh-opc.h: Add sh4_nommu_nofpu architecture and adjust instructions
1248 accordingly.
1249
676a64f4
RS		 12502004-03-01 Richard Sandiford <rsandifo@redhat.com>
1251
1252 * frv-asm.c: Regenerate.
1253 * frv-desc.c: Regenerate.
1254 * frv-desc.h: Regenerate.
1255 * frv-dis.c: Regenerate.
1256 * frv-ibld.c: Regenerate.
1257 * frv-opc.c: Regenerate.
1258 * frv-opc.h: Regenerate.
1259
c7a48b9a
RS		 12602004-03-01 Richard Sandiford <rsandifo@redhat.com>
1261
1262 * frv-desc.c, frv-opc.c: Regenerate.
1263
8ae0baa2
RS		 12642004-03-01 Richard Sandiford <rsandifo@redhat.com>
1265
1266 * frv-desc.c, frv-opc.c, frv-opc.h: Regenerate.
1267
ce11586c
JR		 12682004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1269
1270 * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4.
1271 Also correct mistake in the comment.
1272
6a5709a5
JR		 12732004-02-26 Andrew Stubbs <andrew.stubbs@superh.com>
1274
1275 * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to
1276 ensure that double registers have even numbers.
1277 Add REG_N_B01 for nn01 (binary 01) nibble to ensure
1278 that reserved instruction 0xfffd does not decode the same
1279 as 0xfdfd (ftrv).
1280 * sh-opc.h: Add REG_N_D nibble type and use it whereever
1281 REG_N refers to a double register.
1282 Add REG_N_B01 nibble type and use it instead of REG_NM
1283 in ftrv.
1284 Adjust the bit patterns in a few comments.
1285
e5d2b64f 12862004-02-25 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1287
1288 * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst.
e5d2b64f 1289
1f04b05f
AH		 12902004-02-20 Aldy Hernandez <aldyh@redhat.com>
1291
1292 * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat.
1293
2f3b8700
AH		 12942004-02-20 Aldy Hernandez <aldyh@redhat.com>
1295
1296 * ppc-opc.c (powerpc_opcodes): Add m*ivor35.
1297
f0b26da6 12982004-02-20 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1299
1300 * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34,
1301 mtivor32, mtivor33, mtivor34.
f0b26da6 1302
23d59c56 13032004-02-19 Aldy Hernandez <aldyh@redhat.com>
7bfeee7b
AM		 1304
1305 * ppc-opc.c (powerpc_opcodes): Add mfmcar.
23d59c56 1306
34920d91
NC		 13072004-02-10 Petko Manolov <petkan@nucleusys.com>
1308
1309 * arm-opc.h Maverick accumulator register opcode fixes.
1310
44d86481
BE		 13112004-02-13 Ben Elliston <bje@wasabisystems.com>
1312
1313 * m32r-dis.c: Regenerate.
1314
17707c23
MS		 13152004-01-27 Michael Snyder <msnyder@redhat.com>
1316
1317 * sh-opc.h (sh_table): "fsrra", not "fssra".
1318
fe3a9bc4
NC		 13192004-01-23 Andrew Over <andrew.over@cs.anu.edu.au>
1320
1321 * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten
1322 contraints.
1323
ff24f124
JJ		 13242004-01-19 Andrew Over <andrew.over@cs.anu.edu.au>
1325
1326 * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args.
1327
a02a862a
AM		 13282004-01-19 Alan Modra <amodra@bigpond.net.au>
1329
1330 * i386-dis.c (OP_E): Print scale factor on intel mode sib when not
1331 1. Don't print scale factor on AT&T mode when index missing.
1332
d164ea7f
AO		 13332004-01-16 Alexandre Oliva <aoliva@redhat.com>
1334
1335 * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended
1336 when loaded into XR registers.
1337
cb10e79a
RS		 13382004-01-14 Richard Sandiford <rsandifo@redhat.com>
1339
1340 * frv-desc.h: Regenerate.
1341 * frv-desc.c: Regenerate.
1342 * frv-opc.c: Regenerate.
1343
f532f3fa
MS		 13442004-01-13 Michael Snyder <msnyder@redhat.com>
1345
1346 * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn.
1347
e45d0630
PB		 13482004-01-09 Paul Brook <paul@codesourcery.com>
1349
1350 * arm-opc.h (arm_opcodes): Move generic mcrr after known
1351 specific opcodes.
1352
3ba7a1aa
DJ		 13532004-01-07 Daniel Jacobowitz <drow@mvista.com>
1354
1355 * Makefile.am (libopcodes_la_DEPENDENCIES)
1356 (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory
1357 comment about the problem.
1358 * Makefile.in: Regenerate.
1359
ba2d3f07
AO		 13602004-01-06 Alexandre Oliva <aoliva@redhat.com>
1361
1362 2003-12-19 Alexandre Oliva <aoliva@redhat.com>
1363 * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some
1364 cut&paste errors in shifting/truncating numerical operands.
1365 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1366 * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo.
1367 (parse_uslo16): Likewise.
1368 (parse_uhi16): Parse gotoffhi and gotofffuncdeschi.
1369 (parse_d12): Parse gotoff12 and gotofffuncdesc12.
1370 (parse_s12): Likewise.
1371 2003-08-04 Alexandre Oliva <aoliva@redhat.com>
1372 * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo.
1373 (parse_uslo16): Likewise.
1374 (parse_uhi16): Parse gothi and gotfuncdeschi.
1375 (parse_d12): Parse got12 and gotfuncdesc12.
1376 (parse_s12): Likewise.
1377
3ab48931
NC		 13782004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl>
1379
1380 * msp430-dis.c (msp430_doubleoperand): Check for an 'add'
1381 instruction which looks similar to an 'rla' instruction.
a0bd404e 1382
c9e214e5 1383For older changes see ChangeLog-0203
252b5132
RH		 1384\f
1385Local Variables:
2f6d2f85
NC		 1386mode: change-log
1387left-margin: 8
1388fill-column: 74
252b5132
RH		 1389version-control: never
1390End:
GDB Binutils - Deliverables
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