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df58fc94
RS		 12011-07-24 Chao-ying Fu <fu@mips.com>
2 Maciej W. Rozycki <macro@codesourcery.com>
3
4 * micromips-opc.c: New file.
5 * mips-dis.c (micromips_to_32_reg_b_map): New array.
6 (micromips_to_32_reg_c_map, micromips_to_32_reg_d_map): Likewise.
7 (micromips_to_32_reg_e_map, micromips_to_32_reg_f_map): Likewise.
8 (micromips_to_32_reg_g_map, micromips_to_32_reg_l_map): Likewise.
9 (micromips_to_32_reg_q_map): Likewise.
10 (micromips_imm_b_map, micromips_imm_c_map): Likewise.
11 (micromips_ase): New variable.
12 (is_micromips): New function.
13 (set_default_mips_dis_options): Handle microMIPS ASE.
14 (print_insn_micromips): New function.
15 (is_compressed_mode_p): Likewise.
16 (_print_insn_mips): Handle microMIPS instructions.
17 * Makefile.am (CFILES): Add micromips-opc.c.
18 * configure.in (bfd_mips_arch): Add micromips-opc.lo.
19 * Makefile.in: Regenerate.
20 * configure: Regenerate.
21
22 * mips-dis.c (micromips_to_32_reg_h_map): New variable.
23 (micromips_to_32_reg_i_map): Likewise.
24 (micromips_to_32_reg_m_map): Likewise.
25 (micromips_to_32_reg_n_map): New macro.
26
bcd530a7
RS		 272011-07-24 Maciej W. Rozycki <macro@codesourcery.com>
28
29 * mips-opc.c (NODS): New macro.
30 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
31 (DSP_VOLA): Likewise.
32 (mips_builtin_opcodes): Add NODS annotation to "deret" and
33 "eret". Replace INSN_SYNC with NODS throughout. Use NODS in
34 place of TRAP for "wait", "waiti" and "yield".
35 * mips16-opc.c (NODS): New macro.
36 (TRAP): Adjust for the rename of INSN_TRAP to INSN_NO_DELAY_SLOT.
37 (mips16_opcodes): Use NODS in place of TRAP for "jalrc", "jrc",
38 "restore" and "save".
39
7a9068fe
L		 402011-07-22 H.J. Lu <hongjiu.lu@intel.com>
41
42 * configure.in: Handle bfd_k1om_arch.
43 * configure: Regenerated.
44
45 * disassemble.c (disassembler): Handle bfd_k1om_arch.
46
47 * i386-dis.c (print_insn): Handle bfd_mach_k1om and
48 bfd_mach_k1om_intel_syntax.
49
50 * i386-gen.c (cpu_flag_init): Set CPU_UNKNOWN_FLAGS to
51 ~(CpuL1OM|CpuK1OM). Add CPU_K1OM_FLAGS.
52 (cpu_flags): Add CpuK1OM.
53
54 * i386-opc.h (CpuK1OM): New.
55 (i386_cpu_flags): Add cpuk1om.
56
57 * i386-init.h: Regenerated.
58 * i386-tbl.h: Likewise.
59
1b93226d
NC		 602011-07-12 Nick Clifton <nickc@redhat.com>
61
62 * arm-dis.c (print_insn_arm): Revert previous, undocumented,
63 accidental change.
64
5d73b1f1
NC		 652011-07-01 Nick Clifton <nickc@redhat.com>
66
67 PR binutils/12329
68 * avr-dis.c (avr_operand): Fix disassembly of ELPM, LPM and SPM
69 insns using post-increment addressing.
70
182ae480
L		 712011-06-30 H.J. Lu <hongjiu.lu@intel.com>
72
73 * i386-dis.c (vex_len_table): Update rorxS.
74
4cb0953d
L		 752011-06-30 H.J. Lu <hongjiu.lu@intel.com>
76
77 AVX Programming Reference (June, 2011)
78 * i386-dis.c (vex_len_table): Correct rorxS.
79
80 * i386-opc.tbl: Correct rorx.
81 * i386-tbl.h: Regenerated.
82
906efcbc
L		 832011-06-29 H.J. Lu <hongjiu.lu@intel.com>
84
85 * tilegx-opc.c (find_opcode): Replace "index" with "i".
86 * tilepro-opc.c (find_opcode): Likewise.
87
ceb94aa5
RS		 882011-06-29 Richard Sandiford <rdsandiford@googlemail.com>
89
90 * mips16-opc.c (jalrc, jrc): Move earlier in file.
91
f7002f42
L		 922011-06-21 H.J. Lu <hongjiu.lu@intel.com>
93
94 * i386-dis.c (prefix_table): Re-indent PREFIX_VEX_0F388C and
95 PREFIX_VEX_0F388E.
96
56300268
AS		 972011-06-17 Andreas Schwab <schwab@redhat.com>
98
99 * Makefile.am (MAINTAINERCLEANFILES): Move s390-opc.tab ...
100 (MOSTLYCLEANFILES): ... here.
101 * Makefile.in: Regenerate.
102
bcf2cf9f
AM		 1032011-06-14 Alan Modra <amodra@gmail.com>
104
105 * Makefile.in: Regenerate.
106
aa137e4d
NC		 1072011-06-13 Walter Lee <walt@tilera.com>
108
109 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tilegx-dis.c,
110 tilegx-opc.c, tilepro-dis.c, and tilepro-opc.c.
111 * Makefile.in: Regenerate.
112 * configure.in: Handle bfd_tilegx_arch and bfd_tilepro_arch.
113 * configure: Regenerate.
114 * disassemble.c (disassembler): Add ARCH_tilegx and ARCH_tilepro.
115 * po/POTFILES.in: Regenerate.
116 * tilegx-dis.c: New file.
117 * tilegx-opc.c: New file.
118 * tilepro-dis.c: New file.
119 * tilepro-opc.c: New file.
120
6c30d220
L		 1212011-06-10 H.J. Lu <hongjiu.lu@intel.com>
122
123 AVX Programming Reference (June, 2011)
124 * i386-dis.c (XMGatherQ): New.
125 * i386-dis.c (EXxmm_mb): New.
126 (EXxmm_mb): Likewise.
127 (EXxmm_mw): Likewise.
128 (EXxmm_md): Likewise.
129 (EXxmm_mq): Likewise.
130 (EXxmmdw): Likewise.
131 (EXxmmqd): Likewise.
132 (VexGatherQ): Likewise.
133 (MVexVSIBDWpX): Likewise.
134 (MVexVSIBQWpX): Likewise.
135 (xmm_mb_mode): Likewise.
136 (xmm_mw_mode): Likewise.
137 (xmm_md_mode): Likewise.
138 (xmm_mq_mode): Likewise.
139 (xmmdw_mode): Likewise.
140 (xmmqd_mode): Likewise.
141 (ymmxmm_mode): Likewise.
142 (vex_vsib_d_w_dq_mode): Likewise.
143 (vex_vsib_q_w_dq_mode): Likewise.
144 (MOD_VEX_0F385A_PREFIX_2): Likewise.
145 (MOD_VEX_0F388C_PREFIX_2): Likewise.
146 (MOD_VEX_0F388E_PREFIX_2): Likewise.
147 (PREFIX_0F3882): Likewise.
148 (PREFIX_VEX_0F3816): Likewise.
149 (PREFIX_VEX_0F3836): Likewise.
150 (PREFIX_VEX_0F3845): Likewise.
151 (PREFIX_VEX_0F3846): Likewise.
152 (PREFIX_VEX_0F3847): Likewise.
153 (PREFIX_VEX_0F3858): Likewise.
154 (PREFIX_VEX_0F3859): Likewise.
155 (PREFIX_VEX_0F385A): Likewise.
156 (PREFIX_VEX_0F3878): Likewise.
157 (PREFIX_VEX_0F3879): Likewise.
158 (PREFIX_VEX_0F388C): Likewise.
159 (PREFIX_VEX_0F388E): Likewise.
160 (PREFIX_VEX_0F3890..PREFIX_VEX_0F3893): Likewise.
161 (PREFIX_VEX_0F38F5): Likewise.
162 (PREFIX_VEX_0F38F6): Likewise.
163 (PREFIX_VEX_0F3A00): Likewise.
164 (PREFIX_VEX_0F3A01): Likewise.
165 (PREFIX_VEX_0F3A02): Likewise.
166 (PREFIX_VEX_0F3A38): Likewise.
167 (PREFIX_VEX_0F3A39): Likewise.
168 (PREFIX_VEX_0F3A46): Likewise.
169 (PREFIX_VEX_0F3AF0): Likewise.
170 (VEX_LEN_0F3816_P_2): Likewise.
171 (VEX_LEN_0F3819_P_2): Likewise.
172 (VEX_LEN_0F3836_P_2): Likewise.
173 (VEX_LEN_0F385A_P_2_M_0): Likewise.
174 (VEX_LEN_0F38F5_P_0): Likewise.
175 (VEX_LEN_0F38F5_P_1): Likewise.
176 (VEX_LEN_0F38F5_P_3): Likewise.
177 (VEX_LEN_0F38F6_P_3): Likewise.
178 (VEX_LEN_0F38F7_P_1): Likewise.
179 (VEX_LEN_0F38F7_P_2): Likewise.
180 (VEX_LEN_0F38F7_P_3): Likewise.
181 (VEX_LEN_0F3A00_P_2): Likewise.
182 (VEX_LEN_0F3A01_P_2): Likewise.
183 (VEX_LEN_0F3A38_P_2): Likewise.
184 (VEX_LEN_0F3A39_P_2): Likewise.
185 (VEX_LEN_0F3A46_P_2): Likewise.
186 (VEX_LEN_0F3AF0_P_3): Likewise.
187 (VEX_W_0F3816_P_2): Likewise.
188 (VEX_W_0F3818_P_2): Likewise.
189 (VEX_W_0F3819_P_2): Likewise.
190 (VEX_W_0F3836_P_2): Likewise.
191 (VEX_W_0F3846_P_2): Likewise.
192 (VEX_W_0F3858_P_2): Likewise.
193 (VEX_W_0F3859_P_2): Likewise.
194 (VEX_W_0F385A_P_2_M_0): Likewise.
195 (VEX_W_0F3878_P_2): Likewise.
196 (VEX_W_0F3879_P_2): Likewise.
197 (VEX_W_0F3A00_P_2): Likewise.
198 (VEX_W_0F3A01_P_2): Likewise.
199 (VEX_W_0F3A02_P_2): Likewise.
200 (VEX_W_0F3A38_P_2): Likewise.
201 (VEX_W_0F3A39_P_2): Likewise.
202 (VEX_W_0F3A46_P_2): Likewise.
203 (MOD_VEX_0F3818_PREFIX_2): Removed.
204 (MOD_VEX_0F3819_PREFIX_2): Likewise.
205 (VEX_LEN_0F60_P_2..VEX_LEN_0F6D_P_2): Likewise.
206 (VEX_LEN_0F70_P_1..VEX_LEN_0F76_P_2): Likewise.
207 (VEX_LEN_0FD1_P_2..VEX_LEN_0FD5_P_2): Likewise.
208 (VEX_LEN_0FD7_P_2_M_1..VEX_LEN_0F3819_P_2_M_0): Likewise.
209 (VEX_LEN_0F381C_P_2..VEX_LEN_0F3840_P_2): Likewise.
210 (VEX_LEN_0F3A0E_P_2): Likewise.
211 (VEX_LEN_0F3A0F_P_2): Likewise.
212 (VEX_LEN_0F3A42_P_2): Likewise.
213 (VEX_LEN_0F3A4C_P_2): Likewise.
214 (VEX_W_0F3818_P_2_M_0): Likewise.
215 (VEX_W_0F3819_P_2_M_0): Likewise.
216 (prefix_table): Updated.
217 (three_byte_table): Likewise.
218 (vex_table): Likewise.
219 (vex_len_table): Likewise.
220 (vex_w_table): Likewise.
221 (mod_table): Likewise.
222 (putop): Handle "LW".
223 (intel_operand_size): Handle xmm_mb_mode, xmm_mw_mode,
224 xmm_md_mode, xmm_mq_mode, xmmdw_mode, xmmqd_mode, ymmxmm_mode,
225 vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode.
226 (OP_EX): Likewise.
227 (OP_E_memory): Handle vex_vsib_d_w_dq_mode and
228 vex_vsib_q_w_dq_mode.
229 (OP_XMM): Handle vex_vsib_q_w_dq_mode.
230 (OP_VEX): Likewise.
231
232 * i386-gen.c (cpu_flag_init): Add CpuAVX2 to CPU_ANY_SSE_FLAGS
233 and CPU_ANY_AVX_FLAGS. Add CPU_BMI2_FLAGS, CPU_LZCNT_FLAGS,
234 CPU_INVPCID_FLAGS and CPU_AVX2_FLAGS.
235 (cpu_flags): Add CpuAVX2, CpuBMI2, CpuLZCNT and CpuINVPCID.
236 (opcode_modifiers): Add VecSIB.
237
238 * i386-opc.h (CpuAVX2): New.
239 (CpuBMI2): Likewise.
240 (CpuLZCNT): Likewise.
241 (CpuINVPCID): Likewise.
242 (VecSIB128): Likewise.
243 (VecSIB256): Likewise.
244 (VecSIB): Likewise.
245 (i386_cpu_flags): Add cpuavx2, cpubmi2, cpulzcnt and cpuinvpcid.
246 (i386_opcode_modifier): Add vecsib.
247
248 * i386-opc.tbl: Add invpcid, AVX2 and BMI2 instructions.
249 * i386-init.h: Regenerated.
250 * i386-tbl.h: Likewise.
251
d535accd
QN		 2522011-06-03 Quentin Neill <quentin.neill@amd.com>
253
254 * i386-gen.c (cpu_flag_init): Add CpuF16C to CPU_BDVER2_FLAGS.
255 * i386-init.h: Regenerated.
256
f8b960bc
NC		 2572011-06-03 Nick Clifton <nickc@redhat.com>
258
259 PR binutils/12752
260 * arm-dis.c (print_insn_coprocessor): Use bfd_vma type for
261 computing address offsets.
262 (print_arm_address): Likewise.
263 (print_insn_arm): Likewise.
264 (print_insn_thumb16): Likewise.
265 (print_insn_thumb32): Likewise.
266
26d97720
NS		 2672011-06-02 Jie Zhang <jie@codesourcery.com>
268 Nathan Sidwell <nathan@codesourcery.com>
269 Maciej Rozycki <macro@codesourcery.com>
270
271 * arm-dis.c (print_insn_coprocessor): Explicitly print #-0
272 as address offset.
273 (print_arm_address): Likewise. Elide positive #0 appropriately.
274 (print_insn_arm): Likewise.
275
f8b960bc
NC		 2762011-06-02 Nick Clifton <nickc@redhat.com>
277
278 PR gas/12752
279 * arm-dis.c (print_insn_thumb32): Do not sign extend addresses
280 passed to print_address_func.
281
cc643b88
NC		 2822011-06-02 Nick Clifton <nickc@redhat.com>
283
284 * arm-dis.c: Fix spelling mistakes.
285 * op/opcodes.pot: Regenerate.
286
c8fa16ed
AK		 2872011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
288
289 * s390-opc.c: Replace S390_OPERAND_REG_EVEN with
290 S390_OPERAND_REG_PAIR. Fix INSTR_RRF_0UFEF instruction type.
291 * s390-opc.txt: Fix cxr instruction type.
292
5e4b319c
AK		 2932011-05-24 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
294
295 * s390-opc.c: Add new instruction types marking register pair
296 operands.
297 * s390-opc.txt: Match instructions having register pair operands
298 to the new instruction types.
299
fda544a2
NC		 3002011-05-19 Nick Clifton <nickc@redhat.com>
301
302 * v850-opc.c (cmpf.[sd]): Reverse the order of the reg1 and reg2
303 operands.
304
4cab4add
QN		 3052011-05-10 Quentin Neill <quentin.neill@amd.com>
306
307 * i386-gen.c (cpu_flag_init): Add new CPU_BDVER2_FLAGS.
308 * i386-init.h: Regenerated.
309
b4e7b885
NC		 3102011-04-27 Nick Clifton <nickc@redhat.com>
311
312 * po/da.po: Updated Danish translation.
313
2f7f7710
AM		 3142011-04-26 Anton Blanchard <anton@samba.org>
315
316 * ppc-opc.c: (powerpc_opcodes): Enable icswx for POWER7.
317
9887672f
DD		 3182011-04-21 DJ Delorie <dj@redhat.com>
319
320 * rx-decode.opc (rx_decode_opcode): Set the syntax for multi-byte NOPs.
321 * rx-decode.c: Regenerate.
322
3251b375
L		 3232011-04-20 H.J. Lu <hongjiu.lu@intel.com>
324
325 * i386-init.h: Regenerated.
326
b13a3ca6
QN		 3272011-04-19 Quentin Neill <quentin.neill@amd.com>
328
329 * i386-gen.c (cpu_flag_init): Remove 3dnow and 3dnowa bits
330 from bdver1 flags.
331
7d063384
NC		 3322011-04-13 Nick Clifton <nickc@redhat.com>
333
334 * v850-dis.c (disassemble): Always print a closing square brace if
335 an opening square brace was printed.
336
32a94698
NC		 3372011-04-12 Nick Clifton <nickc@redhat.com>
338
339 PR binutils/12534
340 * arm-dis.c (thumb32_opcodes): Add %L suffix to LDRD and STRD insn
341 patterns.
342 (print_insn_thumb32): Handle %L.
343
d2cd1205
JB		 3442011-04-11 Julian Brown <julian@codesourcery.com>
345
346 * arm-dis.c (psr_name): Fix typo for BASEPRI_MAX.
347 (print_insn_thumb32): Add APSR bitmask support.
348
1fbaefec
PB		 3492011-04-07 Paul Carroll<pcarroll@codesourcery.com>
350
351 * arm-dis.c (print_insn): init vars moved into private_data structure.
352
67171547
MF		 3532011-03-24 Mike Frysinger <vapier@gentoo.org>
354
355 * bfin-dis.c (decode_dsp32mac_0): Move MM zeroing down to MAC0 logic.
356
8cc66334
EW		 3572011-03-22 Eric B. Weddington <eric.weddington@atmel.com>
358
359 * avr-dis.c (avr_operand): Add opcode_str parameter. Check for
360 post-increment to support LPM Z+ instruction. Add support for 'E'
361 constraint for DES instruction.
362 (print_insn_avr): Adjust calls to avr_operand. Rename variable.
363
34e77a92
RS		 3642011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
365
366 * arm-dis.c (get_sym_code_type): Treat STT_GNU_IFUNCs as code.
367
35fc36a8
RS		 3682011-03-14 Richard Sandiford <richard.sandiford@linaro.org>
369
370 * arm-dis.c (get_sym_code_type): Don't check for STT_ARM_TFUNC.
371 Use branch types instead.
372 (print_insn): Likewise.
373
0067d8fc
MR		 3742011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
375
376 * mips-opc.c (mips_builtin_opcodes): Correct register use
377 annotation of "alnv.ps".
378
3eebd5eb
MR		 3792011-02-28 Maciej W. Rozycki <macro@codesourcery.com>
380
381 * mips-opc.c (mips_builtin_opcodes): Add "pref" macro.
382
500cccad
MF		 3832011-02-22 Mike Frysinger <vapier@gentoo.org>
384
385 * bfin-dis.c (OUTS): Remove p NULL check and txt NUL check.
386
f5caf9f4
MF		 3872011-02-22 Mike Frysinger <vapier@gentoo.org>
388
389 * bfin-dis.c (print_insn_bfin): Change outf->fprintf_func to OUTS.
390
e5bc4265
MF		 3912011-02-19 Mike Frysinger <vapier@gentoo.org>
392
393 * bfin-dis.c (saved_state): Mark static. Change a[01]x to ax[] and
394 a[01]w to aw[]. Delete ac0, ac0_copy, ac1, an, aq, av0, av0s, av1,
395 av1s, az, cc, v, v_copy, vs, rnd_mod, v_internal, pc, ticks, insts,
396 exception, end_of_registers, msize, memory, bfd_mach.
397 (CCREG, PCREG, A0XREG, A0WREG, A1XREG, A1WREG, LC0REG, LT0REG,
398 LB0REG, LC1REG, LT1REG, LB1REG): Delete
399 (AXREG, AWREG, LCREG, LTREG, LBREG): Define.
400 (get_allreg): Change to new defines. Fallback to abort().
401
602427c4
MF		 4022011-02-14 Mike Frysinger <vapier@gentoo.org>
403
404 * bfin-dis.c: Add whitespace/parenthesis where needed.
405
298c1ec2
MF		 4062011-02-14 Mike Frysinger <vapier@gentoo.org>
407
408 * bfin-dis.c (decode_LoopSetup_0): Return when reg is greater
409 than 7.
410
822ce8ee
RW		 4112011-02-13 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
412
413 * configure: Regenerate.
414
13c02f06
MF		 4152011-02-13 Mike Frysinger <vapier@gentoo.org>
416
417 * bfin-dis.c (decode_dsp32alu_0): Fix typo with A1 reg.
418
4db66394
MF		 4192011-02-13 Mike Frysinger <vapier@gentoo.org>
420
421 * bfin-dis.c (decode_dsp32mult_0): Add 1 to dst for mac1. Output
422 dregs only when P is set, and dregs_lo otherwise.
423
36f44611
MF		 4242011-02-13 Mike Frysinger <vapier@gentoo.org>
425
426 * bfin-dis.c (decode_dsp32alu_0): Delete BYTEOP2M code.
427
9805c0a5
MF		 4282011-02-12 Mike Frysinger <vapier@gentoo.org>
429
430 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after PRNT.
431
43a6aa65
MF		 4322011-02-12 Mike Frysinger <vapier@gentoo.org>
433
434 * bfin-dis.c (machine_registers): Delete REG_GP.
435 (reg_names): Delete "GP".
436 (decode_allregs): Change REG_GP to REG_LASTREG.
437
26bb3ddd
MF		 4382011-02-12 Mike Frysinger <vapier@gentoo.org>
439
89c0d58c
MR		 440 * bfin-dis.c (M_S2RND, M_T, M_W32, M_FU, M_TFU, M_IS, M_ISS2,
441 M_IH, M_IU): Delete.
26bb3ddd 442
69b8ea4a
MF		 4432011-02-11 Mike Frysinger <vapier@gentoo.org>
444
445 * bfin-dis.c (reg_names): Add const.
446 (decode_dregs_lo, decode_dregs_hi, decode_dregs, decode_dregs_byte,
447 decode_pregs, decode_iregs, decode_mregs, decode_dpregs, decode_gregs,
448 decode_regs, decode_regs_lo, decode_regs_hi, decode_statbits,
449 decode_counters, decode_allregs): Likewise.
450
42d5f9c6
MS		 4512011-02-09 Michael Snyder <msnyder@vmware.com>
452
56300268 453 * i386-dis.c (OP_J): Parenthesize expression to prevent
42d5f9c6
MS		 454 truncated addresses.
455 (print_insn): Fix indentation off-by-one.
456
4be0c941
NC		 4572011-02-01 Nick Clifton <nickc@redhat.com>
458
459 * po/da.po: Updated Danish translation.
460
6b069ee7
AM		 4612011-01-21 Dave Murphy <davem@devkitpro.org>
462
463 * ppc-opc.c (NON32, NO371): Remove PPC_OPCODE_PPCPS.
464
e3949f17
L		 4652011-01-18 H.J. Lu <hongjiu.lu@intel.com>
466
467 * i386-dis.c (sIbT): New.
468 (b_T_mode): Likewise.
469 (dis386): Replace sIb with sIbT on "pushT".
470 (x86_64_table): Replace sIb with Ib on "aam" and "aad".
471 (OP_sI): Handle b_T_mode. Properly sign-extend byte.
472
752573b2
JK		 4732011-01-18 Jan Kratochvil <jan.kratochvil@redhat.com>
474
475 * i386-init.h: Regenerated.
476 * i386-tbl.h: Regenerated
477
2a2a0f38
QN		 4782011-01-17 Quentin Neill <quentin.neill@amd.com>
479
480 * i386-dis.c (REG_XOP_TBM_01): New.
481 (REG_XOP_TBM_02): New.
482 (reg_table): Add REG_XOP_TBM_01 and REG_XOP_TBM_02 tables.
483 (xop_table): Redirect to REG_XOP_TBM_01 and REG_XOP_TBM_02
484 entries, and add bextr instruction.
485
486 * i386-gen.c (cpu_flag_init): Add CPU_TBM_FLAGS, CpuTBM.
487 (cpu_flags): Add CpuTBM.
488
489 * i386-opc.h (CpuTBM) New.
490 (i386_cpu_flags): Add bit cputbm.
491
492 * i386-opc.tbl: Add bextr, blcfill, blci, blcic, blcmsk,
493 blcs, blsfill, blsic, t1mskc, and tzmsk.
494
90d6ff62
DD		 4952011-01-12 DJ Delorie <dj@redhat.com>
496
497 * rx-dis.c (print_insn_rx): Support RX_Operand_TwoReg.
498
c95354ed
MX		 4992011-01-11 Mingjie Xing <mingjie.xing@gmail.com>
500
501 * mips-dis.c (print_insn_args): Adjust the value to print the real
502 offset for "+c" argument.
503
f7465604
NC		 5042011-01-10 Nick Clifton <nickc@redhat.com>
505
506 * po/da.po: Updated Danish translation.
507
639e30d2
NS		 5082011-01-05 Nathan Sidwell <nathan@codesourcery.com>
509
510 * arm-dis.c (thumb32_opcodes): BLX must have bit zero clear.
511
f12dc422
L		 5122011-01-04 H.J. Lu <hongjiu.lu@intel.com>
513
514 * i386-dis.c (REG_VEX_38F3): New.
515 (PREFIX_0FBC): Likewise.
516 (PREFIX_VEX_38F2): Likewise.
517 (PREFIX_VEX_38F3_REG_1): Likewise.
518 (PREFIX_VEX_38F3_REG_2): Likewise.
519 (PREFIX_VEX_38F3_REG_3): Likewise.
520 (PREFIX_VEX_38F7): Likewise.
521 (VEX_LEN_38F2_P_0): Likewise.
522 (VEX_LEN_38F3_R_1_P_0): Likewise.
523 (VEX_LEN_38F3_R_2_P_0): Likewise.
524 (VEX_LEN_38F3_R_3_P_0): Likewise.
525 (VEX_LEN_38F7_P_0): Likewise.
526 (dis386_twobyte): Use PREFIX_0FBC.
527 (reg_table): Add REG_VEX_38F3.
528 (prefix_table): Add PREFIX_0FBC, PREFIX_VEX_38F2,
529 PREFIX_VEX_38F3_REG_1, PREFIX_VEX_38F3_REG_2,
530 PREFIX_VEX_38F3_REG_3 and PREFIX_VEX_38F7.
531 (vex_table): Use PREFIX_VEX_38F2, REG_VEX_38F3 and
532 PREFIX_VEX_38F7.
533 (vex_len_table): Add VEX_LEN_38F2_P_0, VEX_LEN_38F3_R_1_P_0,
534 VEX_LEN_38F3_R_2_P_0, VEX_LEN_38F3_R_3_P_0 and
535 VEX_LEN_38F7_P_0.
536
537 * i386-gen.c (cpu_flag_init): Add CPU_BMI_FLAGS.
538 (cpu_flags): Add CpuBMI.
539
540 * i386-opc.h (CpuBMI): New.
541 (i386_cpu_flags): Add cpubmi.
542
543 * i386-opc.tbl: Add andn, bextr, blsi, blsmsk, blsr and tzcnt.
544 * i386-init.h: Regenerated.
545 * i386-tbl.h: Likewise.
546
cb21baef
L		 5472011-01-04 H.J. Lu <hongjiu.lu@intel.com>
548
549 * i386-dis.c (VexGdq): New.
550 (OP_VEX): Handle dq_mode.
551
0db46eb4
L		 5522011-01-01 H.J. Lu <hongjiu.lu@intel.com>
553
554 * i386-gen.c (process_copyright): Update copyright to 2011.
555
9e9e0820 556For older changes see ChangeLog-2010
252b5132
RH		 557\f
558Local Variables:
2f6d2f85
NC		 559mode: change-log
560left-margin: 8
561fill-column: 74
252b5132
RH		 562version-control: never
563End:
GDB Binutils - Deliverables
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