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Add Intel AVX-512 support
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
43234a1e
L		 12013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
2 Alexander Ivchenko <alexander.ivchenko@intel.com>
3 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
4 Sergey Lega <sergey.s.lega@intel.com>
5 Anna Tikhonova <anna.tikhonova@intel.com>
6 Ilya Tocar <ilya.tocar@intel.com>
7 Andrey Turetskiy <andrey.turetskiy@intel.com>
8 Ilya Verbin <ilya.verbin@intel.com>
9 Kirill Yukhin <kirill.yukhin@intel.com>
10 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
11
12 * i386-dis-evex.h: New.
13 * i386-dis.c (OP_Rounding): New.
14 (VPCMP_Fixup): New.
15 (OP_Mask): New.
16 (Rdq): New.
17 (XMxmmq): New.
18 (EXdScalarS): New.
19 (EXymm): New.
20 (EXEvexHalfBcstXmmq): New.
21 (EXxmm_mdq): New.
22 (EXEvexXGscat): New.
23 (EXEvexXNoBcst): New.
24 (VPCMP): New.
25 (EXxEVexR): New.
26 (EXxEVexS): New.
27 (XMask): New.
28 (MaskG): New.
29 (MaskE): New.
30 (MaskR): New.
31 (MaskVex): New.
32 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
33 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
34 evex_rounding_mode, evex_sae_mode, mask_mode.
35 (USE_EVEX_TABLE): New.
36 (EVEX_TABLE): New.
37 (EVEX enum): New.
38 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
39 REG_EVEX_0F38C7.
40 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
41 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
42 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
43 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
44 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
45 MOD_EVEX_0F38C7_REG_6.
46 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
47 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
48 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
49 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
50 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
51 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
52 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
53 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
54 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
55 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
56 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
57 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
58 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
59 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
60 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
61 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
62 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
63 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
64 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
65 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
66 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
67 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
68 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
69 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
70 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
71 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
72 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
73 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
74 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
75 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
76 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
77 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
78 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
79 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
80 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
81 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
82 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
83 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
84 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
85 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
86 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
87 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
88 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
89 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
90 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
91 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
92 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
93 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
94 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
95 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
96 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
97 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
98 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
99 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
100 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
101 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
102 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
103 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
104 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
105 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
106 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
107 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
108 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
109 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
110 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
111 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
112 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
113 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
114 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
115 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
116 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
117 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
118 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
119 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
120 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
121 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
122 PREFIX_EVEX_0F3A55.
123 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
124 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
125 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
126 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
127 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
128 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
129 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
130 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
131 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
132 VEX_W_0F3A32_P_2_LEN_0.
133 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
134 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
135 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
136 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
137 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
138 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
139 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
140 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
141 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
142 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
143 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
144 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
145 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
146 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
147 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
148 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
149 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
150 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
151 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
152 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
153 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
154 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
155 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
156 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
157 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
158 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
159 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
160 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
161 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
162 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
163 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
164 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
165 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
166 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
167 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
168 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
169 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
170 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
171 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
172 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
173 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
174 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
175 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
176 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
177 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
178 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
179 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
180 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
181 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
182 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
183 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
184 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
185 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
186 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
187 (struct vex): Add fields evex, r, v, mask_register_specifier,
188 zeroing, ll, b.
189 (intel_names_xmm): Add upper 16 registers.
190 (att_names_xmm): Ditto.
191 (intel_names_ymm): Ditto.
192 (att_names_ymm): Ditto.
193 (names_zmm): New.
194 (intel_names_zmm): Ditto.
195 (att_names_zmm): Ditto.
196 (names_mask): Ditto.
197 (intel_names_mask): Ditto.
198 (att_names_mask): Ditto.
199 (names_rounding): Ditto.
200 (names_broadcast): Ditto.
201 (x86_64_table): Add escape to evex-table.
202 (reg_table): Include reg_table evex-entries from
203 i386-dis-evex.h. Fix prefetchwt1 instruction.
204 (prefix_table): Add entries for new instructions.
205 (vex_table): Ditto.
206 (vex_len_table): Ditto.
207 (vex_w_table): Ditto.
208 (mod_table): Ditto.
209 (get_valid_dis386): Properly handle new instructions.
210 (print_insn): Handle zmm and mask registers, print mask operand.
211 (intel_operand_size): Support EVEX, new modes and sizes.
212 (OP_E_register): Handle new modes.
213 (OP_E_memory): Ditto.
214 (OP_G): Ditto.
215 (OP_XMM): Ditto.
216 (OP_EX): Ditto.
217 (OP_VEX): Ditto.
218 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
219 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
220 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
221 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
222 CpuAVX512PF and CpuVREX.
223 (operand_type_init): Add OPERAND_TYPE_REGZMM,
224 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
225 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
226 StaticRounding, SAE, Disp8MemShift, NoDefMask.
227 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
228 * i386-init.h: Regenerate.
229 * i386-opc.h (CpuAVX512F): New.
230 (CpuAVX512CD): New.
231 (CpuAVX512ER): New.
232 (CpuAVX512PF): New.
233 (CpuVREX): New.
234 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
235 cpuavx512pf and cpuvrex fields.
236 (VecSIB): Add VecSIB512.
237 (EVex): New.
238 (Masking): New.
239 (VecESize): New.
240 (Broadcast): New.
241 (StaticRounding): New.
242 (SAE): New.
243 (Disp8MemShift): New.
244 (NoDefMask): New.
245 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
246 staticrounding, sae, disp8memshift and nodefmask.
247 (RegZMM): New.
248 (Zmmword): Ditto.
249 (Vec_Disp8): Ditto.
250 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
251 fields.
252 (RegVRex): New.
253 * i386-opc.tbl: Add AVX512 instructions.
254 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
255 registers, mask registers.
256 * i386-tbl.h: Regenerate.
257
1d2db237
RS		 2582013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
259
260 PR gas/15220
261 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
262 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
263
a0046408
L		 2642013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
265
266 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
267 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
268 PREFIX_0F3ACC.
269 (prefix_table): Updated.
270 (three_byte_table): Likewise.
271 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
272 (cpu_flags): Add CpuSHA.
273 (i386_cpu_flags): Add cpusha.
274 * i386-init.h: Regenerate.
275 * i386-opc.h (CpuSHA): New.
276 (CpuUnused): Restored.
277 (i386_cpu_flags): Add cpusha.
278 * i386-opc.tbl: Add SHA instructions.
279 * i386-tbl.h: Regenerate.
280
7e8b059b
L		 2812013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
282 Kirill Yukhin <kirill.yukhin@intel.com>
283 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
284
285 * i386-dis.c (BND_Fixup): New.
286 (Ebnd): New.
287 (Ev_bnd): New.
288 (Gbnd): New.
289 (BND): New.
290 (v_bnd_mode): New.
291 (bnd_mode): New.
c623f86c
L		 292 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
293 MOD_0F1B_PREFIX_1.
294 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 295 (dis tables): Replace XX with BND for near branch and call
296 instructions.
297 (prefix_table): Add new entries.
298 (mod_table): Likewise.
299 (names_bnd): New.
300 (intel_names_bnd): New.
301 (att_names_bnd): New.
302 (BND_PREFIX): New.
303 (prefix_name): Handle BND_PREFIX.
304 (print_insn): Initialize names_bnd.
305 (intel_operand_size): Handle new modes.
306 (OP_E_register): Likewise.
307 (OP_E_memory): Likewise.
308 (OP_G): Likewise.
309 * i386-gen.c (cpu_flag_init): Add CpuMPX.
310 (cpu_flags): Add CpuMPX.
311 (operand_type_init): Add RegBND.
312 (opcode_modifiers): Add BNDPrefixOk.
313 (operand_types): Add RegBND.
314 * i386-init.h: Regenerate.
315 * i386-opc.h (CpuMPX): New.
316 (CpuUnused): Comment out.
317 (i386_cpu_flags): Add cpumpx.
318 (BNDPrefixOk): New.
319 (i386_opcode_modifier): Add bndprefixok.
320 (RegBND): New.
321 (i386_operand_type): Add regbnd.
322 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
323 Add MPX instructions and bnd prefix.
324 * i386-reg.tbl: Add bnd0-bnd3 registers.
325 * i386-tbl.h: Regenerate.
326
b56e23fb
RS		 3272013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
328
329 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
330 ATTRIBUTE_UNUSED.
331
e7ae278d
RS		 3322013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
333
334 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
335 special rules.
336 * Makefile.in: Regenerate.
337 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
338 all fields. Reformat.
339
c3c07478
RS		 3402013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
341
342 * mips16-opc.c: Include mips-formats.h.
343 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
344 static arrays.
345 (decode_mips16_operand): New function.
346 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
347 (print_insn_arg): Handle OP_ENTRY_EXIT list.
348 Abort for OP_SAVE_RESTORE_LIST.
349 (print_mips16_insn_arg): Change interface. Use mips_operand
350 structures. Delete GET_OP_S. Move GET_OP definition to...
351 (print_insn_mips16): ...here. Call init_print_arg_state.
352 Update the call to print_mips16_insn_arg.
353
ab902481
RS		 3542013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
355
356 * mips-formats.h: New file.
357 * mips-opc.c: Include mips-formats.h.
358 (reg_0_map): New static array.
359 (decode_mips_operand): New function.
360 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
361 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
362 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
363 (int_c_map): New static arrays.
364 (decode_micromips_operand): New function.
365 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
366 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
367 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
368 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
369 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
370 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
371 (micromips_imm_b_map, micromips_imm_c_map): Delete.
372 (print_reg): New function.
373 (mips_print_arg_state): New structure.
374 (init_print_arg_state, print_insn_arg): New functions.
375 (print_insn_args): Change interface and use mips_operand structures.
376 Delete GET_OP_S. Move GET_OP definition to...
377 (print_insn_mips): ...here. Update the call to print_insn_args.
378 (print_insn_micromips): Use print_insn_args.
379
cc537e56
RS		 3802013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
381
382 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
383 in macros.
384
7a5f87ce
RS		 3852013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
386
387 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
388 ADDA.S, MULA.S and SUBA.S.
389
41741fa4
L		 3902013-07-08 H.J. Lu <hongjiu.lu@intel.com>
391
392 PR gas/13572
393 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
394 * i386-tbl.h: Regenerated.
395
f2ae14a1
RS		 3962013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
397
398 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
399 and SD A(B) macros up.
400 * micromips-opc.c (micromips_opcodes): Likewise.
401
04c9d415
RS		 4022013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
403
404 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
405 instructions.
406
5c324c16
RS		 4072013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
408
409 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
410 MDMX-like instructions.
411 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
412 printing "Q" operands for INSN_5400 instructions.
413
23e69e47
RS		 4142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
415
416 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
417 "+S" for "cins".
418 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
419 Combine cases.
420
27c5c572
RS		 4212013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
422
423 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
424 "jalx".
425 * mips16-opc.c (mips16_opcodes): Likewise.
426 * micromips-opc.c (micromips_opcodes): Likewise.
427 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
428 (print_insn_mips16): Handle "+i".
429 (print_insn_micromips): Likewise. Conditionally preserve the
430 ISA bit for "a" but not for "+i".
431
e76ff5ab
RS		 4322013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
433
434 * micromips-opc.c (WR_mhi): Rename to..
435 (WR_mh): ...this.
436 (micromips_opcodes): Update "movep" entry accordingly. Replace
437 "mh,mi" with "mh".
438 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
439 (micromips_to_32_reg_h_map1): ...this.
440 (micromips_to_32_reg_i_map): Rename to...
441 (micromips_to_32_reg_h_map2): ...this.
442 (print_micromips_insn): Remove "mi" case. Print both registers
443 in the pair for "mh".
444
fa7616a4
RS		 4452013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
446
447 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
448 * micromips-opc.c (micromips_opcodes): Likewise.
449 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
450 and "+T" handling. Check for a "0" suffix when deciding whether to
451 use coprocessor 0 names. In that case, also check for ",H" selectors.
452
fb798c50
AK		 4532013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
454
455 * s390-opc.c (J12_12, J24_24): New macros.
456 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
457 (MASK_MII_UPI): Rename to MASK_MII_UPP.
458 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
459
58ae08f2
AM		 4602013-07-04 Alan Modra <amodra@gmail.com>
461
462 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
463
b5e04c2b
NC		 4642013-06-26 Nick Clifton <nickc@redhat.com>
465
466 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
467 field when checking for type 2 nop.
468 * rx-decode.c: Regenerate.
469
833794fc
MR		 4702013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
471
472 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
473 and "movep" macros.
474
1bbce132
MR		 4752013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
476
477 * mips-dis.c (is_mips16_plt_tail): New function.
478 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
479 word.
480 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
481
34c911a4
NC		 4822013-06-21 DJ Delorie <dj@redhat.com>
483
484 * msp430-decode.opc: New.
485 * msp430-decode.c: New/generated.
486 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
487 (MAINTAINER_CLEANFILES): Likewise.
488 Add rule to build msp430-decode.c frommsp430decode.opc
489 using the opc2c program.
490 * Makefile.in: Regenerate.
491 * configure.in: Add msp430-decode.lo to msp430 architecture files.
492 * configure: Regenerate.
493
b9eead84
YZ		 4942013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
495
496 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
497 (SYMTAB_AVAILABLE): Removed.
498 (#include "elf/aarch64.h): Ditto.
499
7f3c4072
CM		 5002013-06-17 Catherine Moore <clm@codesourcery.com>
501 Maciej W. Rozycki <macro@codesourcery.com>
502 Chao-Ying Fu <fu@mips.com>
503
504 * micromips-opc.c (EVA): Define.
505 (TLBINV): Define.
506 (micromips_opcodes): Add EVA opcodes.
507 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
508 (print_insn_args): Handle EVA offsets.
509 (print_insn_micromips): Likewise.
510 * mips-opc.c (EVA): Define.
511 (TLBINV): Define.
512 (mips_builtin_opcodes): Add EVA opcodes.
513
de40ceb6
AM		 5142013-06-17 Alan Modra <amodra@gmail.com>
515
516 * Makefile.am (mips-opc.lo): Add rules to create automatic
517 dependency files. Pass archdefs.
518 (micromips-opc.lo, mips16-opc.lo): Likewise.
519 * Makefile.in: Regenerate.
520
3531d549
DD		 5212013-06-14 DJ Delorie <dj@redhat.com>
522
523 * rx-decode.opc (rx_decode_opcode): Bit operations on
524 registers are 32-bit operations, not 8-bit operations.
525 * rx-decode.c: Regenerate.
526
ba92f7fb
CF		 5272013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
528
529 * micromips-opc.c (IVIRT): New define.
530 (IVIRT64): New define.
531 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
532 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
533
534 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
535 dmtgc0 to print cp0 names.
536
9daf7bab
SL		 5372013-06-09 Sandra Loosemore <sandra@codesourcery.com>
538
539 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
540 argument.
541
d301a56b
RS		 5422013-06-08 Catherine Moore <clm@codesourcery.com>
543 Richard Sandiford <rdsandiford@googlemail.com>
544
545 * micromips-opc.c (D32, D33, MC): Update definitions.
546 (micromips_opcodes): Initialize ase field.
547 * mips-dis.c (mips_arch_choice): Add ase field.
548 (mips_arch_choices): Initialize ase field.
549 (set_default_mips_dis_options): Declare and setup mips_ase.
550 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
551 MT32, MC): Update definitions.
552 (mips_builtin_opcodes): Initialize ase field.
553
a3dcb6c5
RS		 5542013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
555
556 * s390-opc.txt (flogr): Require a register pair destination.
557
6cf1d90c
AK		 5582013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
559
560 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
561 instruction format.
562
c77c0862
RS		 5632013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
564
565 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
566
c0637f3a
PB		 5672013-05-20 Peter Bergner <bergner@vnet.ibm.com>
568
569 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
570 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
571 XLS_MASK, PPCVSX2): New defines.
572 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
573 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
574 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
575 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
576 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
577 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
578 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
579 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
580 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
581 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
582 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
583 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
584 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
585 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
586 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
587 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
588 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
589 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
590 <lxvx, stxvx>: New extended mnemonics.
591
4934fdaf
AM		 5922013-05-17 Alan Modra <amodra@gmail.com>
593
594 * ia64-raw.tbl: Replace non-ASCII char.
595 * ia64-waw.tbl: Likewise.
596 * ia64-asmtab.c: Regenerate.
597
6091d651
SE		 5982013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
599
600 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
601 * i386-init.h: Regenerated.
602
d2865ed3
YZ		 6032013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
604
605 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
606 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
607 check from [0, 255] to [-128, 255].
608
b015e599
AP		 6092013-05-09 Andrew Pinski <apinski@cavium.com>
610
611 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
612 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
613 (parse_mips_dis_option): Handle the virt option.
614 (print_insn_args): Handle "+J".
615 (print_mips_disassembler_options): Print out message about virt64.
616 * mips-opc.c (IVIRT): New define.
617 (IVIRT64): New define.
618 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
619 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
620 Move rfe to the bottom as it conflicts with tlbgp.
621
9f0682fe
AM		 6222013-05-09 Alan Modra <amodra@gmail.com>
623
624 * ppc-opc.c (extract_vlesi): Properly sign extend.
625 (extract_vlensi): Likewise. Comment reason for setting invalid.
626
13761a11
NC		 6272013-05-02 Nick Clifton <nickc@redhat.com>
628
629 * msp430-dis.c: Add support for MSP430X instructions.
630
e3031850
SL		 6312013-04-24 Sandra Loosemore <sandra@codesourcery.com>
632
633 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
634 to "eccinj".
635
17310e56
NC		 6362013-04-17 Wei-chen Wang <cole945@gmail.com>
637
638 PR binutils/15369
639 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
640 of CGEN_CPU_ENDIAN.
641 (hash_insns_list): Likewise.
642
731df338
JK		 6432013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
644
645 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
646 warning workaround.
647
5f77db52
JB		 6482013-04-08 Jan Beulich <jbeulich@suse.com>
649
650 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
651 * i386-tbl.h: Re-generate.
652
0afd1215
DM		 6532013-04-06 David S. Miller <davem@davemloft.net>
654
655 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
656 of an opcode, prefer the one with F_PREFERRED set.
657 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
658 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
659 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
660 mark existing mnenomics as aliases. Add "cc" suffix to edge
661 instructions generating condition codes, mark existing mnenomics
662 as aliases. Add "fp" prefix to VIS compare instructions, mark
663 existing mnenomics as aliases.
664
41702d50
NC		 6652013-04-03 Nick Clifton <nickc@redhat.com>
666
667 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
668 destination address by subtracting the operand from the current
669 address.
670 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
671 a positive value in the insn.
672 (extract_u16_loop): Do not negate the returned value.
673 (D16_LOOP): Add V850_INVERSE_PCREL flag.
674
675 (ceilf.sw): Remove duplicate entry.
676 (cvtf.hs): New entry.
677 (cvtf.sh): Likewise.
678 (fmaf.s): Likewise.
679 (fmsf.s): Likewise.
680 (fnmaf.s): Likewise.
681 (fnmsf.s): Likewise.
682 (maddf.s): Restrict to E3V5 architectures.
683 (msubf.s): Likewise.
684 (nmaddf.s): Likewise.
685 (nmsubf.s): Likewise.
686
55cf16e1
L		 6872013-03-27 H.J. Lu <hongjiu.lu@intel.com>
688
689 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
690 check address mode.
691 (print_insn): Pass sizeflag to get_sib.
692
51dcdd4d
NC		 6932013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
694
695 PR binutils/15068
696 * tic6x-dis.c: Add support for displaying 16-bit insns.
697
795b8e6b
NC		 6982013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
699
700 PR gas/15095
701 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
702 individual msb and lsb halves in src1 & src2 fields. Discard the
703 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
704 follow what Ti SDK does in that case as any value in the src1
705 field yields the same output with SDK disassembler.
706
314d60dd
ME		 7072013-03-12 Michael Eager <eager@eagercon.com>
708
795b8e6b 709 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 710
dad60f8e
SL		 7112013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
712
713 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
714
f5cb796a
SL		 7152013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
716
717 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
718
21fde85c
SL		 7192013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
720
721 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
722
dd5181d5
KT		 7232013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
724
725 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
726 (thumb32_opcodes): Likewise.
727 (print_insn_thumb32): Handle 'S' control char.
728
87a8d6cb
NC		 7292013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
730
731 * lm32-desc.c: Regenerate.
732
99dce992
L		 7332013-03-01 H.J. Lu <hongjiu.lu@intel.com>
734
735 * i386-reg.tbl (riz): Add RegRex64.
736 * i386-tbl.h: Regenerated.
737
e60bb1dd
YZ		 7382013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
739
740 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
741 (aarch64_feature_crc): New static.
742 (CRC): New macro.
743 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
744 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
745 * aarch64-asm-2.c: Re-generate.
746 * aarch64-dis-2.c: Ditto.
747 * aarch64-opc-2.c: Ditto.
748
c7570fcd
AM		 7492013-02-27 Alan Modra <amodra@gmail.com>
750
751 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
752 * rl78-decode.c: Regenerate.
753
151fa98f
NC		 7542013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
755
756 * rl78-decode.opc: Fix encoding of DIVWU insn.
757 * rl78-decode.c: Regenerate.
758
5c111e37
L		 7592013-02-19 H.J. Lu <hongjiu.lu@intel.com>
760
761 PR gas/15159
762 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
763
764 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
765 (cpu_flags): Add CpuSMAP.
766
767 * i386-opc.h (CpuSMAP): New.
768 (i386_cpu_flags): Add cpusmap.
769
770 * i386-opc.tbl: Add clac and stac.
771
772 * i386-init.h: Regenerated.
773 * i386-tbl.h: Likewise.
774
9d1df426
NC		 7752013-02-15 Markos Chandras <markos.chandras@imgtec.com>
776
777 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
778 which also makes the disassembler output be in little
779 endian like it should be.
780
a1ccaec9
YZ		 7812013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
782
783 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
784 fields to NULL.
785 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
786
ef068ef4 7872013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 788
789 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
790 section disassembled.
791
6fe6ded9
RE		 7922013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
793
794 * arm-dis.c: Update strht pattern.
795
0aa27725
RS		 7962013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
797
798 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
799 single-float. Disable ll, lld, sc and scd for EE. Disable the
800 trunc.w.s macro for EE.
801
36591ba1
SL		 8022013-02-06 Sandra Loosemore <sandra@codesourcery.com>
803 Andrew Jenner <andrew@codesourcery.com>
804
805 Based on patches from Altera Corporation.
806
807 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
808 nios2-opc.c.
809 * Makefile.in: Regenerated.
810 * configure.in: Add case for bfd_nios2_arch.
811 * configure: Regenerated.
812 * disassemble.c (ARCH_nios2): Define.
813 (disassembler): Add case for bfd_arch_nios2.
814 * nios2-dis.c: New file.
815 * nios2-opc.c: New file.
816
545093a4
AM		 8172013-02-04 Alan Modra <amodra@gmail.com>
818
819 * po/POTFILES.in: Regenerate.
820 * rl78-decode.c: Regenerate.
821 * rx-decode.c: Regenerate.
822
e30181a5
YZ		 8232013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
824
825 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
826 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
827 * aarch64-asm.c (convert_xtl_to_shll): New function.
828 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
829 calling convert_xtl_to_shll.
830 * aarch64-dis.c (convert_shll_to_xtl): New function.
831 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
832 calling convert_shll_to_xtl.
833 * aarch64-gen.c: Update copyright year.
834 * aarch64-asm-2.c: Re-generate.
835 * aarch64-dis-2.c: Re-generate.
836 * aarch64-opc-2.c: Re-generate.
837
78c8d46c
NC		 8382013-01-24 Nick Clifton <nickc@redhat.com>
839
840 * v850-dis.c: Add support for e3v5 architecture.
841 * v850-opc.c: Likewise.
842
f5555712
YZ		 8432013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
844
845 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
846 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
847 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 848 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 849 alignment check; change to call set_sft_amount_out_of_range_error
850 instead of set_imm_out_of_range_error.
851 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
852 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
853 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
854 SIMD_IMM_SFT.
855
2f81ff92
L		 8562013-01-16 H.J. Lu <hongjiu.lu@intel.com>
857
858 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
859
860 * i386-init.h: Regenerated.
861 * i386-tbl.h: Likewise.
862
dd42f060
NC		 8632013-01-15 Nick Clifton <nickc@redhat.com>
864
865 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
866 values.
867 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
868
a4533ed8
NC		 8692013-01-14 Will Newton <will.newton@imgtec.com>
870
871 * metag-dis.c (REG_WIDTH): Increase to 64.
872
5817ffd1
PB		 8732013-01-10 Peter Bergner <bergner@vnet.ibm.com>
874
875 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
876 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
877 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
878 (SH6): Update.
879 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
880 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
881 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
882 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
883
a3c62988
NC		 8842013-01-10 Will Newton <will.newton@imgtec.com>
885
886 * Makefile.am: Add Meta.
887 * configure.in: Add Meta.
888 * disassemble.c: Add Meta support.
889 * metag-dis.c: New file.
890 * Makefile.in: Regenerate.
891 * configure: Regenerate.
892
73335eae
NC		 8932013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
894
895 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
896 (match_opcode): Rename to cr16_match_opcode.
897
e407c74b
NC		 8982013-01-04 Juergen Urban <JuergenUrban@gmx.de>
899
900 * mips-dis.c: Add names for CP0 registers of r5900.
901 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
902 instructions sq and lq.
903 Add support for MIPS r5900 CPU.
904 Add support for 128 bit MMI (Multimedia Instructions).
905 Add support for EE instructions (Emotion Engine).
906 Disable unsupported floating point instructions (64 bit and
907 undefined compare operations).
908 Enable instructions of MIPS ISA IV which are supported by r5900.
909 Disable 64 bit co processor instructions.
910 Disable 64 bit multiplication and division instructions.
911 Disable instructions for co-processor 2 and 3, because these are
912 not supported (preparation for later VU0 support (Vector Unit)).
913 Disable cvt.w.s because this behaves like trunc.w.s and the
914 correct execution can't be ensured on r5900.
915 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
916 will confuse less developers and compilers.
917
a32c3ff8
NC		 9182013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
919
fb098a1e
YZ		 920 * aarch64-opc.c (aarch64_print_operand): Change to print
921 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
922 in comment.
923 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
924 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
925 OP_MOV_IMM_WIDE.
926
9272013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
928
929 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
930 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 931
62658407
L		 9322013-01-02 H.J. Lu <hongjiu.lu@intel.com>
933
934 * i386-gen.c (process_copyright): Update copyright year to 2013.
935
bab4becb 9362013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 937
bab4becb
NC		 938 * cr16-dis.c (match_opcode,make_instruction): Remove static
939 declaration.
940 (dwordU,wordU): Moved typedefs to opcode/cr16.h
941 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 942
bab4becb 943For older changes see ChangeLog-2012
252b5132 944\f
bab4becb 945Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 946
947Copying and distribution of this file, with or without modification,
948are permitted in any medium without royalty provided the copyright
949notice and this notice are preserved.
950
252b5132 951Local Variables:
2f6d2f85
NC		 952mode: change-log
953left-margin: 8
954fill-column: 74
252b5132
RH		 955version-control: never
956End:
GDB Binutils - Deliverables
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