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2013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
[deliverable/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
45099dfa
CF		 12013-10-07 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
2
3 * micromips-opc.c (micromips_opcodes): Fix dmfgc0 and dmtgc0.
4
916fae91
L		 52013-09-30 H.J. Lu <hongjiu.lu@intel.com>
6
7 * i386-opc.tbl: Add Size64 to movq/vmovq with Reg64 operand.
8 * i386-init.h: Regenerated.
9
c7b0bd56
SE		 102013-09-30 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
11
12 * i386-gen.c (cpu_flag_init): Add CPU_BDVER4_FLAGS.
13 * i386-init.h: Regenerated.
14
cc9afea3
AM		 152013-09-20 Alan Modra <amodra@gmail.com>
16
17 * configure: Regenerate.
18
e3f9e852
RS		 192013-09-17 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
20
21 * s390-opc.txt (clih): Make the immediate unsigned.
22
74db7efb
NC		 232013-09-04 Roland McGrath <mcgrathr@google.com>
24
25 PR gas/15914
26 * arm-dis.c (arm_opcodes): Add udf.
27 (thumb_opcodes): Use "udf" mnemonic rather than UNDEFINED_INSTRUCTION.
28 (thumb32_opcodes): Add udf.w.
29 (print_insn_thumb32): Handle %H as the thumb32_opcodes comment says.
30
c8094e01
AK		 312013-09-02 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
32
33 * s390-opc.txt: Fix description for fiebra, fidbra, and fixbra.
34 For the load fp integer instructions only the suppression flag was
35 new with z196 version.
36
7e105031
NC		 372013-08-28 Nick Clifton <nickc@redhat.com>
38
39 * aarch64-opc.c (aarch64_logical_immediate_p): Return FALSE if the
40 immediate is not suitable for the 32-bit ABI.
41
fb6f3895
MR		 422013-08-23 Maciej W. Rozycki <macro@codesourcery.com>
43
44 * micromips-opc.c (micromips_opcodes): Use RD_4 for "alnv.ps",
45 replacing NODS.
46
9aff4b7a
NC		 472013-08-23 Yuri Chornoivan <yurchor@ukr.net>
48
49 PR binutils/15834
50 * aarch64-asm.c: Fix typos.
51 * aarch64-dis.c: Likewise.
52 * msp430-dis.c: Likewise.
53
5e0dc5ba
RS		 542013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
55
56 * micromips-opc.c (micromips_opcodes): Replace "dext" and "dins"
57 macro entries with "dextm", "dextu", "dinsm" and "dinsu" aliases.
58 Use +H rather than +C for the real "dext".
59 * mips-opc.c (mips_builtin_opcodes): Likewise.
60
0f35dbc4
RS		 612013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
62
63 * mips-formats.h (OPTIONAL_REG, OPTIONAL_MAPPED_REG): New macros.
64 * micromips-opc.c (decode_micromips_operand): Use OPTIONAL_REG
65 and OPTIONAL_MAPPED_REG.
66 * mips-opc.c (decode_mips_operand): Likewise.
67 * mips16-opc.c (decode_mips16_operand): Likewise.
68 * mips-dis.c (print_insn_arg): Handle OP_OPTIONAL_REG.
69
79ceb7cb
L		 702013-08-19 H.J. Lu <hongjiu.lu@intel.com>
71
72 * i386-dis.c (PREFIX_EVEX_0F3A3E): Removed.
73 (PREFIX_EVEX_0F3A3F): Likewise.
74 * i386-dis-evex.h (evex_table): Updated.
75
ee5734f0
RS		 762013-08-06 Jürgen Urban <JuergenUrban@gmx.de>
77
78 * mips-opc.c (mips_builtin_opcodes): Add a suffixless version of
79 VCLIPW.
80
d6787ef9
EB		 812013-08-05 Eric Botcazou <ebotcazou@adacore.com>
82 Konrad Eisele <konrad@gaisler.com>
83
84 * sparc-dis.c (compute_arch_mask): Set SPARC_OPCODE_ARCH_LEON bit for
85 bfd_mach_sparc.
86 * sparc-opc.c (MASK_LEON): Define.
87 (v6, v6notlet, v7, v8, v6notv9): Add MASK_LEON.
88 (letandleon): New macro.
89 (v9andleon): Likewise.
90 (sparc_opc): Add leon.
91 (umac): Enable for letandleon.
92 (smac): Likewise.
93 (casa): Enable for v9andleon.
94 (cas): Likewise.
95 (casl): Likewise.
96
14daeee3
RS		 972013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
98 Richard Sandiford <rdsandiford@googlemail.com>
99
100 * mips-dis.c (print_reg): Handle OP_REG_VI, OP_REG_VF, OP_REG_R5900_I,
101 OP_REG_R5900_Q, OP_REG_R5900_R and OP_REG_R5900_ACC.
102 (print_vu0_channel): New function.
103 (print_insn_arg): Handle OP_VU0_SUFFIX and OP_VU0_MATCH_SUFFIX.
104 (print_insn_args): Handle '#'.
105 (print_insn_mips): Handle INSN2_VU0_CHANNEL_SUFFIX.
106 * mips-opc.c (mips_vu0_channel_mask): New constant.
107 (decode_mips_operand): Handle new VU0 operand types.
108 (VU0, VU0CH): New macros.
109 (mips_builtin_opcodes): Add VU0 opcodes. Use "+7" rather than "E"
110 for LQC2 and SQC2. Use "+9" rather than "G" for EE CFC2 and CTC2.
111 Use "+6" rather than "G" for QMFC2 and QMTC2.
112
3ccad066
RS		 1132013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
114
115 * mips-formats.h (PCREL): Reorder parameters and update the definition
116 to match new mips_pcrel_operand layout.
117 (JUMP, JALX, BRANCH): Update accordingly.
118 * mips16-opc.c (decode_mips16_operand): Likewise.
119
df34fbcc
RS		 1202013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
121
122 * micromips-opc.c (WR_s): Delete.
123
fc76e730
RS		 1242013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
125
126 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
127 New macros.
128 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
129 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
130 (mips_builtin_opcodes): Use the new position-based read-write flags
131 instead of field-based ones. Use UDI for "udi..." instructions.
132 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
133 New macros.
134 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
135 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
136 (WR_SP, RD_16): New macros.
137 (RD_SP): Redefine as an INSN2_* flag.
138 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
139 (mips16_opcodes): Use the new position-based read-write flags
140 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
141 pinfo2 field.
142 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
143 New macros.
144 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
145 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
146 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
147 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
148 (micromips_opcodes): Use the new position-based read-write flags
149 instead of field-based ones.
150 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
151 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
152 of field-based flags.
153
26545944
RS		 1542013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
155
156 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
157 (WR_SP): Replace with...
158 (MOD_SP): ...this.
159 (mips16_opcodes): Update accordingly.
160 * mips-dis.c (print_insn_mips16): Likewise.
161
a8d92fc6
RS		 1622013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
163
164 * mips16-opc.c (mips16_opcodes): Reformat.
165
6a819047
RS		 1662013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
167
168 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
169 for operands that are hard-coded to $0.
170 * micromips-opc.c (micromips_opcodes): Likewise.
171
344c74a6
RS		 1722013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
173
174 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
175 for the single-operand forms of JALR and JALR.HB.
176 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
177 and JALRS.HB.
178
41989114
RS		 1792013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
180
181 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
182 instructions. Fix them to use WR_MACC instead of WR_CC and
183 add missing RD_MACCs.
184
6d075bce
RS		 1852013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
186
187 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
188
4f6ffcd3
PB		 1892013-07-29 Peter Bergner <bergner@vnet.ibm.com>
190
191 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
192
43234a1e
L		 1932013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
194 Alexander Ivchenko <alexander.ivchenko@intel.com>
195 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
196 Sergey Lega <sergey.s.lega@intel.com>
197 Anna Tikhonova <anna.tikhonova@intel.com>
198 Ilya Tocar <ilya.tocar@intel.com>
199 Andrey Turetskiy <andrey.turetskiy@intel.com>
200 Ilya Verbin <ilya.verbin@intel.com>
201 Kirill Yukhin <kirill.yukhin@intel.com>
202 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
203
204 * i386-dis-evex.h: New.
205 * i386-dis.c (OP_Rounding): New.
206 (VPCMP_Fixup): New.
207 (OP_Mask): New.
208 (Rdq): New.
209 (XMxmmq): New.
210 (EXdScalarS): New.
211 (EXymm): New.
212 (EXEvexHalfBcstXmmq): New.
213 (EXxmm_mdq): New.
214 (EXEvexXGscat): New.
215 (EXEvexXNoBcst): New.
216 (VPCMP): New.
217 (EXxEVexR): New.
218 (EXxEVexS): New.
219 (XMask): New.
220 (MaskG): New.
221 (MaskE): New.
222 (MaskR): New.
223 (MaskVex): New.
224 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
225 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
226 evex_rounding_mode, evex_sae_mode, mask_mode.
227 (USE_EVEX_TABLE): New.
228 (EVEX_TABLE): New.
229 (EVEX enum): New.
230 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
231 REG_EVEX_0F38C7.
232 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
233 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
234 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
235 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
236 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
237 MOD_EVEX_0F38C7_REG_6.
238 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
239 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
240 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
241 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
242 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
243 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
244 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
245 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
246 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
247 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
248 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
249 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
250 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
251 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
252 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
253 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
254 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
255 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
256 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
257 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
258 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
259 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
260 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
261 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
262 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
263 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
264 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
265 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
266 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
267 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
268 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
269 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
270 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
271 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
272 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
273 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
274 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
275 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
276 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
277 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
278 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
279 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
280 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
281 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
282 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
283 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
284 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
285 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
286 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
287 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
288 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
289 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
290 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
291 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
292 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
293 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
294 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
295 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
296 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
297 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
298 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
299 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
300 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
301 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
302 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
303 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
304 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
305 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
306 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
307 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
308 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
309 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
310 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
311 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
312 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
313 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
314 PREFIX_EVEX_0F3A55.
315 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
316 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
317 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
318 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
319 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
320 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
321 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
322 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
323 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
324 VEX_W_0F3A32_P_2_LEN_0.
325 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
326 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
327 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
328 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
329 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
330 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
331 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
332 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
333 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
334 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
335 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
336 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
337 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
338 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
339 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
340 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
341 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
342 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
343 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
344 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
345 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
346 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
347 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
348 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
349 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
350 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
351 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
352 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
353 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
354 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
355 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
356 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
357 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
358 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
359 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
360 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
361 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
362 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
363 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
364 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
365 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
366 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
367 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
368 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
369 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
370 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
371 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
372 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
373 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
374 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
375 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
376 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
377 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
378 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
379 (struct vex): Add fields evex, r, v, mask_register_specifier,
380 zeroing, ll, b.
381 (intel_names_xmm): Add upper 16 registers.
382 (att_names_xmm): Ditto.
383 (intel_names_ymm): Ditto.
384 (att_names_ymm): Ditto.
385 (names_zmm): New.
386 (intel_names_zmm): Ditto.
387 (att_names_zmm): Ditto.
388 (names_mask): Ditto.
389 (intel_names_mask): Ditto.
390 (att_names_mask): Ditto.
391 (names_rounding): Ditto.
392 (names_broadcast): Ditto.
393 (x86_64_table): Add escape to evex-table.
394 (reg_table): Include reg_table evex-entries from
395 i386-dis-evex.h. Fix prefetchwt1 instruction.
396 (prefix_table): Add entries for new instructions.
397 (vex_table): Ditto.
398 (vex_len_table): Ditto.
399 (vex_w_table): Ditto.
400 (mod_table): Ditto.
401 (get_valid_dis386): Properly handle new instructions.
402 (print_insn): Handle zmm and mask registers, print mask operand.
403 (intel_operand_size): Support EVEX, new modes and sizes.
404 (OP_E_register): Handle new modes.
405 (OP_E_memory): Ditto.
406 (OP_G): Ditto.
407 (OP_XMM): Ditto.
408 (OP_EX): Ditto.
409 (OP_VEX): Ditto.
410 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
411 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
412 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
413 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
414 CpuAVX512PF and CpuVREX.
415 (operand_type_init): Add OPERAND_TYPE_REGZMM,
416 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
417 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
418 StaticRounding, SAE, Disp8MemShift, NoDefMask.
419 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
420 * i386-init.h: Regenerate.
421 * i386-opc.h (CpuAVX512F): New.
422 (CpuAVX512CD): New.
423 (CpuAVX512ER): New.
424 (CpuAVX512PF): New.
425 (CpuVREX): New.
426 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
427 cpuavx512pf and cpuvrex fields.
428 (VecSIB): Add VecSIB512.
429 (EVex): New.
430 (Masking): New.
431 (VecESize): New.
432 (Broadcast): New.
433 (StaticRounding): New.
434 (SAE): New.
435 (Disp8MemShift): New.
436 (NoDefMask): New.
437 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
438 staticrounding, sae, disp8memshift and nodefmask.
439 (RegZMM): New.
440 (Zmmword): Ditto.
441 (Vec_Disp8): Ditto.
442 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
443 fields.
444 (RegVRex): New.
445 * i386-opc.tbl: Add AVX512 instructions.
446 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
447 registers, mask registers.
448 * i386-tbl.h: Regenerate.
449
1d2db237
RS		 4502013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
451
452 PR gas/15220
453 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
454 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
455
a0046408
L		 4562013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
457
458 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
459 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
460 PREFIX_0F3ACC.
461 (prefix_table): Updated.
462 (three_byte_table): Likewise.
463 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
464 (cpu_flags): Add CpuSHA.
465 (i386_cpu_flags): Add cpusha.
466 * i386-init.h: Regenerate.
467 * i386-opc.h (CpuSHA): New.
468 (CpuUnused): Restored.
469 (i386_cpu_flags): Add cpusha.
470 * i386-opc.tbl: Add SHA instructions.
471 * i386-tbl.h: Regenerate.
472
7e8b059b
L		 4732013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
474 Kirill Yukhin <kirill.yukhin@intel.com>
475 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
476
477 * i386-dis.c (BND_Fixup): New.
478 (Ebnd): New.
479 (Ev_bnd): New.
480 (Gbnd): New.
481 (BND): New.
482 (v_bnd_mode): New.
483 (bnd_mode): New.
c623f86c
L		 484 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
485 MOD_0F1B_PREFIX_1.
486 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 487 (dis tables): Replace XX with BND for near branch and call
488 instructions.
489 (prefix_table): Add new entries.
490 (mod_table): Likewise.
491 (names_bnd): New.
492 (intel_names_bnd): New.
493 (att_names_bnd): New.
494 (BND_PREFIX): New.
495 (prefix_name): Handle BND_PREFIX.
496 (print_insn): Initialize names_bnd.
497 (intel_operand_size): Handle new modes.
498 (OP_E_register): Likewise.
499 (OP_E_memory): Likewise.
500 (OP_G): Likewise.
501 * i386-gen.c (cpu_flag_init): Add CpuMPX.
502 (cpu_flags): Add CpuMPX.
503 (operand_type_init): Add RegBND.
504 (opcode_modifiers): Add BNDPrefixOk.
505 (operand_types): Add RegBND.
506 * i386-init.h: Regenerate.
507 * i386-opc.h (CpuMPX): New.
508 (CpuUnused): Comment out.
509 (i386_cpu_flags): Add cpumpx.
510 (BNDPrefixOk): New.
511 (i386_opcode_modifier): Add bndprefixok.
512 (RegBND): New.
513 (i386_operand_type): Add regbnd.
514 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
515 Add MPX instructions and bnd prefix.
516 * i386-reg.tbl: Add bnd0-bnd3 registers.
517 * i386-tbl.h: Regenerate.
518
b56e23fb
RS		 5192013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
520
521 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
522 ATTRIBUTE_UNUSED.
523
e7ae278d
RS		 5242013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
525
526 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
527 special rules.
528 * Makefile.in: Regenerate.
529 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
530 all fields. Reformat.
531
c3c07478
RS		 5322013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
533
534 * mips16-opc.c: Include mips-formats.h.
535 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
536 static arrays.
537 (decode_mips16_operand): New function.
538 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
539 (print_insn_arg): Handle OP_ENTRY_EXIT list.
540 Abort for OP_SAVE_RESTORE_LIST.
541 (print_mips16_insn_arg): Change interface. Use mips_operand
542 structures. Delete GET_OP_S. Move GET_OP definition to...
543 (print_insn_mips16): ...here. Call init_print_arg_state.
544 Update the call to print_mips16_insn_arg.
545
ab902481
RS		 5462013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
547
548 * mips-formats.h: New file.
549 * mips-opc.c: Include mips-formats.h.
550 (reg_0_map): New static array.
551 (decode_mips_operand): New function.
552 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
553 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
554 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
555 (int_c_map): New static arrays.
556 (decode_micromips_operand): New function.
557 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
558 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
559 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
560 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
561 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
562 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
563 (micromips_imm_b_map, micromips_imm_c_map): Delete.
564 (print_reg): New function.
565 (mips_print_arg_state): New structure.
566 (init_print_arg_state, print_insn_arg): New functions.
567 (print_insn_args): Change interface and use mips_operand structures.
568 Delete GET_OP_S. Move GET_OP definition to...
569 (print_insn_mips): ...here. Update the call to print_insn_args.
570 (print_insn_micromips): Use print_insn_args.
571
cc537e56
RS		 5722013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
573
574 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
575 in macros.
576
7a5f87ce
RS		 5772013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
578
579 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
580 ADDA.S, MULA.S and SUBA.S.
581
41741fa4
L		 5822013-07-08 H.J. Lu <hongjiu.lu@intel.com>
583
584 PR gas/13572
585 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
586 * i386-tbl.h: Regenerated.
587
f2ae14a1
RS		 5882013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
589
590 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
591 and SD A(B) macros up.
592 * micromips-opc.c (micromips_opcodes): Likewise.
593
04c9d415
RS		 5942013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
595
596 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
597 instructions.
598
5c324c16
RS		 5992013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
600
601 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
602 MDMX-like instructions.
603 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
604 printing "Q" operands for INSN_5400 instructions.
605
23e69e47
RS		 6062013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
607
608 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
609 "+S" for "cins".
610 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
611 Combine cases.
612
27c5c572
RS		 6132013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
614
615 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
616 "jalx".
617 * mips16-opc.c (mips16_opcodes): Likewise.
618 * micromips-opc.c (micromips_opcodes): Likewise.
619 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
620 (print_insn_mips16): Handle "+i".
621 (print_insn_micromips): Likewise. Conditionally preserve the
622 ISA bit for "a" but not for "+i".
623
e76ff5ab
RS		 6242013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
625
626 * micromips-opc.c (WR_mhi): Rename to..
627 (WR_mh): ...this.
628 (micromips_opcodes): Update "movep" entry accordingly. Replace
629 "mh,mi" with "mh".
630 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
631 (micromips_to_32_reg_h_map1): ...this.
632 (micromips_to_32_reg_i_map): Rename to...
633 (micromips_to_32_reg_h_map2): ...this.
634 (print_micromips_insn): Remove "mi" case. Print both registers
635 in the pair for "mh".
636
fa7616a4
RS		 6372013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
638
639 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
640 * micromips-opc.c (micromips_opcodes): Likewise.
641 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
642 and "+T" handling. Check for a "0" suffix when deciding whether to
643 use coprocessor 0 names. In that case, also check for ",H" selectors.
644
fb798c50
AK		 6452013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
646
647 * s390-opc.c (J12_12, J24_24): New macros.
648 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
649 (MASK_MII_UPI): Rename to MASK_MII_UPP.
650 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
651
58ae08f2
AM		 6522013-07-04 Alan Modra <amodra@gmail.com>
653
654 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
655
b5e04c2b
NC		 6562013-06-26 Nick Clifton <nickc@redhat.com>
657
658 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
659 field when checking for type 2 nop.
660 * rx-decode.c: Regenerate.
661
833794fc
MR		 6622013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
663
664 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
665 and "movep" macros.
666
1bbce132
MR		 6672013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
668
669 * mips-dis.c (is_mips16_plt_tail): New function.
670 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
671 word.
672 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
673
34c911a4
NC		 6742013-06-21 DJ Delorie <dj@redhat.com>
675
676 * msp430-decode.opc: New.
677 * msp430-decode.c: New/generated.
678 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
679 (MAINTAINER_CLEANFILES): Likewise.
680 Add rule to build msp430-decode.c frommsp430decode.opc
681 using the opc2c program.
682 * Makefile.in: Regenerate.
683 * configure.in: Add msp430-decode.lo to msp430 architecture files.
684 * configure: Regenerate.
685
b9eead84
YZ		 6862013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
687
688 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
689 (SYMTAB_AVAILABLE): Removed.
690 (#include "elf/aarch64.h): Ditto.
691
7f3c4072
CM		 6922013-06-17 Catherine Moore <clm@codesourcery.com>
693 Maciej W. Rozycki <macro@codesourcery.com>
694 Chao-Ying Fu <fu@mips.com>
695
696 * micromips-opc.c (EVA): Define.
697 (TLBINV): Define.
698 (micromips_opcodes): Add EVA opcodes.
699 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
700 (print_insn_args): Handle EVA offsets.
701 (print_insn_micromips): Likewise.
702 * mips-opc.c (EVA): Define.
703 (TLBINV): Define.
704 (mips_builtin_opcodes): Add EVA opcodes.
705
de40ceb6
AM		 7062013-06-17 Alan Modra <amodra@gmail.com>
707
708 * Makefile.am (mips-opc.lo): Add rules to create automatic
709 dependency files. Pass archdefs.
710 (micromips-opc.lo, mips16-opc.lo): Likewise.
711 * Makefile.in: Regenerate.
712
3531d549
DD		 7132013-06-14 DJ Delorie <dj@redhat.com>
714
715 * rx-decode.opc (rx_decode_opcode): Bit operations on
716 registers are 32-bit operations, not 8-bit operations.
717 * rx-decode.c: Regenerate.
718
ba92f7fb
CF		 7192013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
720
721 * micromips-opc.c (IVIRT): New define.
722 (IVIRT64): New define.
723 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
724 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
725
726 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
727 dmtgc0 to print cp0 names.
728
9daf7bab
SL		 7292013-06-09 Sandra Loosemore <sandra@codesourcery.com>
730
731 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
732 argument.
733
d301a56b
RS		 7342013-06-08 Catherine Moore <clm@codesourcery.com>
735 Richard Sandiford <rdsandiford@googlemail.com>
736
737 * micromips-opc.c (D32, D33, MC): Update definitions.
738 (micromips_opcodes): Initialize ase field.
739 * mips-dis.c (mips_arch_choice): Add ase field.
740 (mips_arch_choices): Initialize ase field.
741 (set_default_mips_dis_options): Declare and setup mips_ase.
742 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
743 MT32, MC): Update definitions.
744 (mips_builtin_opcodes): Initialize ase field.
745
a3dcb6c5
RS		 7462013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
747
748 * s390-opc.txt (flogr): Require a register pair destination.
749
6cf1d90c
AK		 7502013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
751
752 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
753 instruction format.
754
c77c0862
RS		 7552013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
756
757 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
758
c0637f3a
PB		 7592013-05-20 Peter Bergner <bergner@vnet.ibm.com>
760
761 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
762 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
763 XLS_MASK, PPCVSX2): New defines.
764 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
765 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
766 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
767 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
768 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
769 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
770 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
771 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
772 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
773 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
774 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
775 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
776 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
777 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
778 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
779 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
780 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
781 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
782 <lxvx, stxvx>: New extended mnemonics.
783
4934fdaf
AM		 7842013-05-17 Alan Modra <amodra@gmail.com>
785
786 * ia64-raw.tbl: Replace non-ASCII char.
787 * ia64-waw.tbl: Likewise.
788 * ia64-asmtab.c: Regenerate.
789
6091d651
SE		 7902013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
791
792 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
793 * i386-init.h: Regenerated.
794
d2865ed3
YZ		 7952013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
796
797 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
798 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
799 check from [0, 255] to [-128, 255].
800
b015e599
AP		 8012013-05-09 Andrew Pinski <apinski@cavium.com>
802
803 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
804 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
805 (parse_mips_dis_option): Handle the virt option.
806 (print_insn_args): Handle "+J".
807 (print_mips_disassembler_options): Print out message about virt64.
808 * mips-opc.c (IVIRT): New define.
809 (IVIRT64): New define.
810 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
811 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
812 Move rfe to the bottom as it conflicts with tlbgp.
813
9f0682fe
AM		 8142013-05-09 Alan Modra <amodra@gmail.com>
815
816 * ppc-opc.c (extract_vlesi): Properly sign extend.
817 (extract_vlensi): Likewise. Comment reason for setting invalid.
818
13761a11
NC		 8192013-05-02 Nick Clifton <nickc@redhat.com>
820
821 * msp430-dis.c: Add support for MSP430X instructions.
822
e3031850
SL		 8232013-04-24 Sandra Loosemore <sandra@codesourcery.com>
824
825 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
826 to "eccinj".
827
17310e56
NC		 8282013-04-17 Wei-chen Wang <cole945@gmail.com>
829
830 PR binutils/15369
831 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
832 of CGEN_CPU_ENDIAN.
833 (hash_insns_list): Likewise.
834
731df338
JK		 8352013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
836
837 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
838 warning workaround.
839
5f77db52
JB		 8402013-04-08 Jan Beulich <jbeulich@suse.com>
841
842 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
843 * i386-tbl.h: Re-generate.
844
0afd1215
DM		 8452013-04-06 David S. Miller <davem@davemloft.net>
846
847 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
848 of an opcode, prefer the one with F_PREFERRED set.
849 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
850 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
851 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
852 mark existing mnenomics as aliases. Add "cc" suffix to edge
853 instructions generating condition codes, mark existing mnenomics
854 as aliases. Add "fp" prefix to VIS compare instructions, mark
855 existing mnenomics as aliases.
856
41702d50
NC		 8572013-04-03 Nick Clifton <nickc@redhat.com>
858
859 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
860 destination address by subtracting the operand from the current
861 address.
862 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
863 a positive value in the insn.
864 (extract_u16_loop): Do not negate the returned value.
865 (D16_LOOP): Add V850_INVERSE_PCREL flag.
866
867 (ceilf.sw): Remove duplicate entry.
868 (cvtf.hs): New entry.
869 (cvtf.sh): Likewise.
870 (fmaf.s): Likewise.
871 (fmsf.s): Likewise.
872 (fnmaf.s): Likewise.
873 (fnmsf.s): Likewise.
874 (maddf.s): Restrict to E3V5 architectures.
875 (msubf.s): Likewise.
876 (nmaddf.s): Likewise.
877 (nmsubf.s): Likewise.
878
55cf16e1
L		 8792013-03-27 H.J. Lu <hongjiu.lu@intel.com>
880
881 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
882 check address mode.
883 (print_insn): Pass sizeflag to get_sib.
884
51dcdd4d
NC		 8852013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
886
887 PR binutils/15068
888 * tic6x-dis.c: Add support for displaying 16-bit insns.
889
795b8e6b
NC		 8902013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
891
892 PR gas/15095
893 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
894 individual msb and lsb halves in src1 & src2 fields. Discard the
895 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
896 follow what Ti SDK does in that case as any value in the src1
897 field yields the same output with SDK disassembler.
898
314d60dd
ME		 8992013-03-12 Michael Eager <eager@eagercon.com>
900
795b8e6b 901 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 902
dad60f8e
SL		 9032013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
904
905 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
906
f5cb796a
SL		 9072013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
908
909 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
910
21fde85c
SL		 9112013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
912
913 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
914
dd5181d5
KT		 9152013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
916
917 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
918 (thumb32_opcodes): Likewise.
919 (print_insn_thumb32): Handle 'S' control char.
920
87a8d6cb
NC		 9212013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
922
923 * lm32-desc.c: Regenerate.
924
99dce992
L		 9252013-03-01 H.J. Lu <hongjiu.lu@intel.com>
926
927 * i386-reg.tbl (riz): Add RegRex64.
928 * i386-tbl.h: Regenerated.
929
e60bb1dd
YZ		 9302013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
931
932 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
933 (aarch64_feature_crc): New static.
934 (CRC): New macro.
935 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
936 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
937 * aarch64-asm-2.c: Re-generate.
938 * aarch64-dis-2.c: Ditto.
939 * aarch64-opc-2.c: Ditto.
940
c7570fcd
AM		 9412013-02-27 Alan Modra <amodra@gmail.com>
942
943 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
944 * rl78-decode.c: Regenerate.
945
151fa98f
NC		 9462013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
947
948 * rl78-decode.opc: Fix encoding of DIVWU insn.
949 * rl78-decode.c: Regenerate.
950
5c111e37
L		 9512013-02-19 H.J. Lu <hongjiu.lu@intel.com>
952
953 PR gas/15159
954 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
955
956 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
957 (cpu_flags): Add CpuSMAP.
958
959 * i386-opc.h (CpuSMAP): New.
960 (i386_cpu_flags): Add cpusmap.
961
962 * i386-opc.tbl: Add clac and stac.
963
964 * i386-init.h: Regenerated.
965 * i386-tbl.h: Likewise.
966
9d1df426
NC		 9672013-02-15 Markos Chandras <markos.chandras@imgtec.com>
968
969 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
970 which also makes the disassembler output be in little
971 endian like it should be.
972
a1ccaec9
YZ		 9732013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
974
975 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
976 fields to NULL.
977 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
978
ef068ef4 9792013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 980
981 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
982 section disassembled.
983
6fe6ded9
RE		 9842013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
985
986 * arm-dis.c: Update strht pattern.
987
0aa27725
RS		 9882013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
989
990 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
991 single-float. Disable ll, lld, sc and scd for EE. Disable the
992 trunc.w.s macro for EE.
993
36591ba1
SL		 9942013-02-06 Sandra Loosemore <sandra@codesourcery.com>
995 Andrew Jenner <andrew@codesourcery.com>
996
997 Based on patches from Altera Corporation.
998
999 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
1000 nios2-opc.c.
1001 * Makefile.in: Regenerated.
1002 * configure.in: Add case for bfd_nios2_arch.
1003 * configure: Regenerated.
1004 * disassemble.c (ARCH_nios2): Define.
1005 (disassembler): Add case for bfd_arch_nios2.
1006 * nios2-dis.c: New file.
1007 * nios2-opc.c: New file.
1008
545093a4
AM		 10092013-02-04 Alan Modra <amodra@gmail.com>
1010
1011 * po/POTFILES.in: Regenerate.
1012 * rl78-decode.c: Regenerate.
1013 * rx-decode.c: Regenerate.
1014
e30181a5
YZ		 10152013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
1016
1017 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
1018 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
1019 * aarch64-asm.c (convert_xtl_to_shll): New function.
1020 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1021 calling convert_xtl_to_shll.
1022 * aarch64-dis.c (convert_shll_to_xtl): New function.
1023 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
1024 calling convert_shll_to_xtl.
1025 * aarch64-gen.c: Update copyright year.
1026 * aarch64-asm-2.c: Re-generate.
1027 * aarch64-dis-2.c: Re-generate.
1028 * aarch64-opc-2.c: Re-generate.
1029
78c8d46c
NC		 10302013-01-24 Nick Clifton <nickc@redhat.com>
1031
1032 * v850-dis.c: Add support for e3v5 architecture.
1033 * v850-opc.c: Likewise.
1034
f5555712
YZ		 10352013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
1036
1037 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
1038 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
1039 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 1040 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 1041 alignment check; change to call set_sft_amount_out_of_range_error
1042 instead of set_imm_out_of_range_error.
1043 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
1044 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
1045 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
1046 SIMD_IMM_SFT.
1047
2f81ff92
L		 10482013-01-16 H.J. Lu <hongjiu.lu@intel.com>
1049
1050 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
1051
1052 * i386-init.h: Regenerated.
1053 * i386-tbl.h: Likewise.
1054
dd42f060
NC		 10552013-01-15 Nick Clifton <nickc@redhat.com>
1056
1057 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
1058 values.
1059 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
1060
a4533ed8
NC		 10612013-01-14 Will Newton <will.newton@imgtec.com>
1062
1063 * metag-dis.c (REG_WIDTH): Increase to 64.
1064
5817ffd1
PB		 10652013-01-10 Peter Bergner <bergner@vnet.ibm.com>
1066
1067 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
1068 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
1069 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
1070 (SH6): Update.
1071 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
1072 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
1073 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
1074 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
1075
a3c62988
NC		 10762013-01-10 Will Newton <will.newton@imgtec.com>
1077
1078 * Makefile.am: Add Meta.
1079 * configure.in: Add Meta.
1080 * disassemble.c: Add Meta support.
1081 * metag-dis.c: New file.
1082 * Makefile.in: Regenerate.
1083 * configure: Regenerate.
1084
73335eae
NC		 10852013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
1086
1087 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
1088 (match_opcode): Rename to cr16_match_opcode.
1089
e407c74b
NC		 10902013-01-04 Juergen Urban <JuergenUrban@gmx.de>
1091
1092 * mips-dis.c: Add names for CP0 registers of r5900.
1093 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
1094 instructions sq and lq.
1095 Add support for MIPS r5900 CPU.
1096 Add support for 128 bit MMI (Multimedia Instructions).
1097 Add support for EE instructions (Emotion Engine).
1098 Disable unsupported floating point instructions (64 bit and
1099 undefined compare operations).
1100 Enable instructions of MIPS ISA IV which are supported by r5900.
1101 Disable 64 bit co processor instructions.
1102 Disable 64 bit multiplication and division instructions.
1103 Disable instructions for co-processor 2 and 3, because these are
1104 not supported (preparation for later VU0 support (Vector Unit)).
1105 Disable cvt.w.s because this behaves like trunc.w.s and the
1106 correct execution can't be ensured on r5900.
1107 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
1108 will confuse less developers and compilers.
1109
a32c3ff8
NC		 11102013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1111
fb098a1e
YZ		 1112 * aarch64-opc.c (aarch64_print_operand): Change to print
1113 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
1114 in comment.
1115 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
1116 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
1117 OP_MOV_IMM_WIDE.
1118
11192013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
1120
1121 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
1122 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1123
62658407
L		 11242013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1125
1126 * i386-gen.c (process_copyright): Update copyright year to 2013.
1127
bab4becb 11282013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1129
bab4becb
NC		 1130 * cr16-dis.c (match_opcode,make_instruction): Remove static
1131 declaration.
1132 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1133 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1134
bab4becb 1135For older changes see ChangeLog-2012
252b5132 1136\f
bab4becb 1137Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1138
1139Copying and distribution of this file, with or without modification,
1140are permitted in any medium without royalty provided the copyright
1141notice and this notice are preserved.
1142
252b5132 1143Local Variables:
2f6d2f85
NC		 1144mode: change-log
1145left-margin: 8
1146fill-column: 74
252b5132
RH		 1147version-control: never
1148End:
GDB Binutils - Deliverables
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