projects / deliverable / binutils-gdb.git / blame
| Commit | Line | Data |
|---|---|---|
| 67d888f5 PD |
1 | 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com> |
| 2 | ||
| 3 | * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias. | |
| 4 | ||
| e3c2f928 AF |
5 | 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com> |
| 6 | Edmar Wienskoski <edmar.wienskoski@nxp.com> | |
| 7 | ||
| 8 | * ppc-opc.c (insert_evuimm2_ex0): New function. | |
| 9 | (extract_evuimm2_ex0): Likewise. | |
| 10 | (insert_evuimm4_ex0): Likewise. | |
| 11 | (extract_evuimm4_ex0): Likewise. | |
| 12 | (insert_evuimm8_ex0): Likewise. | |
| 13 | (extract_evuimm8_ex0): Likewise. | |
| 14 | (insert_evuimm_lt16): Likewise. | |
| 15 | (extract_evuimm_lt16): Likewise. | |
| 16 | (insert_rD_rS_even): Likewise. | |
| 17 | (extract_rD_rS_even): Likewise. | |
| 18 | (insert_off_lsp): Likewise. | |
| 19 | (extract_off_lsp): Likewise. | |
| 20 | (RD_EVEN): New operand. | |
| 21 | (RS_EVEN): Likewise. | |
| 22 | (RSQ): Adjust. | |
| 23 | (EVUIMM_LT16): New operand. | |
| 24 | (HTM_SI): Adjust. | |
| 25 | (EVUIMM_2_EX0): New operand. | |
| 26 | (EVUIMM_4): Adjust. | |
| 27 | (EVUIMM_4_EX0): New operand. | |
| 28 | (EVUIMM_8): Adjust. | |
| 29 | (EVUIMM_8_EX0): New operand. | |
| 30 | (WS): Adjust. | |
| 31 | (VX_OFF): New operand. | |
| 32 | (VX_LSP): New macro. | |
| 33 | (VX_LSP_MASK): Likewise. | |
| 34 | (VX_LSP_OFF_MASK): Likewise. | |
| 35 | (PPC_OPCODE_LSP): Likewise. | |
| 36 | (vle_opcodes): Add LSP opcodes. | |
| 37 | * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry. | |
| 38 | ||
| cc4a945a JW |
39 | 2017-08-09 Jiong Wang <jiong.wang@arm.com> |
| 40 | ||
| 41 | * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for | |
| 42 | register operands in CRC instructions. | |
| 43 | (print_insn_thumb32): Remove "<bitfield>S" support. Updated the | |
| 44 | comments. | |
| 45 | ||
| b28b8b5e L |
46 | 2017-08-07 H.J. Lu <hongjiu.lu@intel.com> |
| 47 | ||
| 48 | * disassemble.c (disassembler): Mark big and mach with | |
| 49 | ATTRIBUTE_UNUSED. | |
| 50 | ||
| e347efc3 MR |
51 | 2017-08-07 Maciej W. Rozycki <macro@imgtec.com> |
| 52 | ||
| 53 | * disassemble.c (disassembler): Remove arch/mach/endian | |
| 54 | assertions. | |
| 55 | ||
| 7cbc739c NC |
56 | 2017-07-25 Nick Clifton <nickc@redhat.com> |
| 57 | ||
| 58 | PR 21739 | |
| 59 | * arc-opc.c (insert_rhv2): Use lower case first letter in error | |
| 60 | message. | |
| 61 | (insert_r0): Likewise. | |
| 62 | (insert_r1): Likewise. | |
| 63 | (insert_r2): Likewise. | |
| 64 | (insert_r3): Likewise. | |
| 65 | (insert_sp): Likewise. | |
| 66 | (insert_gp): Likewise. | |
| 67 | (insert_pcl): Likewise. | |
| 68 | (insert_blink): Likewise. | |
| 69 | (insert_ilink1): Likewise. | |
| 70 | (insert_ilink2): Likewise. | |
| 71 | (insert_ras): Likewise. | |
| 72 | (insert_rbs): Likewise. | |
| 73 | (insert_rcs): Likewise. | |
| 74 | (insert_simm3s): Likewise. | |
| 75 | (insert_rrange): Likewise. | |
| 76 | (insert_r13el): Likewise. | |
| 77 | (insert_fpel): Likewise. | |
| 78 | (insert_blinkel): Likewise. | |
| 79 | (insert_pclel): Likewise. | |
| 80 | (insert_nps_bitop_size_2b): Likewise. | |
| 81 | (insert_nps_imm_offset): Likewise. | |
| 82 | (insert_nps_imm_entry): Likewise. | |
| 83 | (insert_nps_size_16bit): Likewise. | |
| 84 | (insert_nps_##NAME##_pos): Likewise. | |
| 85 | (insert_nps_##NAME): Likewise. | |
| 86 | (insert_nps_bitop_ins_ext): Likewise. | |
| 87 | (insert_nps_##NAME): Likewise. | |
| 88 | (insert_nps_min_hofs): Likewise. | |
| 89 | (insert_nps_##NAME): Likewise. | |
| 90 | (insert_nps_rbdouble_64): Likewise. | |
| 91 | (insert_nps_misc_imm_offset): Likewise. | |
| 92 | * riscv-dis.c (print_riscv_disassembler_options): Fix typo in | |
| 93 | option description. | |
| 94 | ||
| 7684e580 JW |
95 | 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com> |
| 96 | Jiong Wang <jiong.wang@arm.com> | |
| 97 | ||
| 98 | * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to | |
| 99 | correct the print. | |
| 100 | * aarch64-dis-2.c: Regenerated. | |
| 101 | ||
| 47826cdb AK |
102 | 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 103 | ||
| 104 | * s390-mkopc.c (main): Enable z14 as CPU string in the opcode | |
| 105 | table. | |
| 106 | ||
| 2d2dbad0 NC |
107 | 2017-07-20 Nick Clifton <nickc@redhat.com> |
| 108 | ||
| 109 | * po/de.po: Updated German translation. | |
| 110 | ||
| 70b448ba | 111 | 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> |
| 112 | ||
| 113 | * arc-regs.h (sec_stat): New aux register. | |
| 114 | (aux_kernel_sp): Likewise. | |
| 115 | (aux_sec_u_sp): Likewise. | |
| 116 | (aux_sec_k_sp): Likewise. | |
| 117 | (sec_vecbase_build): Likewise. | |
| 118 | (nsc_table_top): Likewise. | |
| 119 | (nsc_table_base): Likewise. | |
| 120 | (ersec_stat): Likewise. | |
| 121 | (aux_sec_except): Likewise. | |
| 122 | ||
| 7179e0e6 CZ |
123 | 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> |
| 124 | ||
| 125 | * arc-opc.c (extract_uimm12_20): New function. | |
| 126 | (UIMM12_20): New operand. | |
| 127 | (SIMM3_5_S): Adjust. | |
| 128 | * arc-tbl.h (sjli): Add new instruction. | |
| 129 | ||
| 684d5a10 JEM |
130 | 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com> |
| 131 | John Eric Martin <John.Martin@emmicro-us.com> | |
| 132 | ||
| 133 | * arc-opc.c (UIMM10_6_S_JLIOFF): Define. | |
| 134 | (UIMM3_23): Adjust accordingly. | |
| 135 | * arc-regs.h: Add/correct jli_base register. | |
| 136 | * arc-tbl.h (jli_s): Likewise. | |
| 137 | ||
| de194d85 YC |
138 | 2017-07-18 Nick Clifton <nickc@redhat.com> |
| 139 | ||
| 140 | PR 21775 | |
| 141 | * aarch64-opc.c: Fix spelling typos. | |
| 142 | * i386-dis.c: Likewise. | |
| 143 | ||
| 0f6329bd RB |
144 | 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com> |
| 145 | ||
| 146 | * dis-buf.c (buffer_read_memory): Change type of end_addr_offset, | |
| 147 | max_addr_offset and octets variables to size_t. | |
| 148 | ||
| 429d795d AM |
149 | 2017-07-12 Alan Modra <amodra@gmail.com> |
| 150 | ||
| 151 | * po/da.po: Update from translationproject.org/latest/opcodes/. | |
| 152 | * po/de.po: Likewise. | |
| 153 | * po/es.po: Likewise. | |
| 154 | * po/fi.po: Likewise. | |
| 155 | * po/fr.po: Likewise. | |
| 156 | * po/id.po: Likewise. | |
| 157 | * po/it.po: Likewise. | |
| 158 | * po/nl.po: Likewise. | |
| 159 | * po/pt_BR.po: Likewise. | |
| 160 | * po/ro.po: Likewise. | |
| 161 | * po/sv.po: Likewise. | |
| 162 | * po/tr.po: Likewise. | |
| 163 | * po/uk.po: Likewise. | |
| 164 | * po/vi.po: Likewise. | |
| 165 | * po/zh_CN.po: Likewise. | |
| 166 | ||
| 4162bb66 AM |
167 | 2017-07-11 Yao Qi <yao.qi@linaro.org> |
| 168 | Alan Modra <amodra@gmail.com> | |
| 169 | ||
| 170 | * cgen.sh: Mark generated files read-only. | |
| 171 | * epiphany-asm.c: Regenerate. | |
| 172 | * epiphany-desc.c: Regenerate. | |
| 173 | * epiphany-desc.h: Regenerate. | |
| 174 | * epiphany-dis.c: Regenerate. | |
| 175 | * epiphany-ibld.c: Regenerate. | |
| 176 | * epiphany-opc.c: Regenerate. | |
| 177 | * epiphany-opc.h: Regenerate. | |
| 178 | * fr30-asm.c: Regenerate. | |
| 179 | * fr30-desc.c: Regenerate. | |
| 180 | * fr30-desc.h: Regenerate. | |
| 181 | * fr30-dis.c: Regenerate. | |
| 182 | * fr30-ibld.c: Regenerate. | |
| 183 | * fr30-opc.c: Regenerate. | |
| 184 | * fr30-opc.h: Regenerate. | |
| 185 | * frv-asm.c: Regenerate. | |
| 186 | * frv-desc.c: Regenerate. | |
| 187 | * frv-desc.h: Regenerate. | |
| 188 | * frv-dis.c: Regenerate. | |
| 189 | * frv-ibld.c: Regenerate. | |
| 190 | * frv-opc.c: Regenerate. | |
| 191 | * frv-opc.h: Regenerate. | |
| 192 | * ip2k-asm.c: Regenerate. | |
| 193 | * ip2k-desc.c: Regenerate. | |
| 194 | * ip2k-desc.h: Regenerate. | |
| 195 | * ip2k-dis.c: Regenerate. | |
| 196 | * ip2k-ibld.c: Regenerate. | |
| 197 | * ip2k-opc.c: Regenerate. | |
| 198 | * ip2k-opc.h: Regenerate. | |
| 199 | * iq2000-asm.c: Regenerate. | |
| 200 | * iq2000-desc.c: Regenerate. | |
| 201 | * iq2000-desc.h: Regenerate. | |
| 202 | * iq2000-dis.c: Regenerate. | |
| 203 | * iq2000-ibld.c: Regenerate. | |
| 204 | * iq2000-opc.c: Regenerate. | |
| 205 | * iq2000-opc.h: Regenerate. | |
| 206 | * lm32-asm.c: Regenerate. | |
| 207 | * lm32-desc.c: Regenerate. | |
| 208 | * lm32-desc.h: Regenerate. | |
| 209 | * lm32-dis.c: Regenerate. | |
| 210 | * lm32-ibld.c: Regenerate. | |
| 211 | * lm32-opc.c: Regenerate. | |
| 212 | * lm32-opc.h: Regenerate. | |
| 213 | * lm32-opinst.c: Regenerate. | |
| 214 | * m32c-asm.c: Regenerate. | |
| 215 | * m32c-desc.c: Regenerate. | |
| 216 | * m32c-desc.h: Regenerate. | |
| 217 | * m32c-dis.c: Regenerate. | |
| 218 | * m32c-ibld.c: Regenerate. | |
| 219 | * m32c-opc.c: Regenerate. | |
| 220 | * m32c-opc.h: Regenerate. | |
| 221 | * m32r-asm.c: Regenerate. | |
| 222 | * m32r-desc.c: Regenerate. | |
| 223 | * m32r-desc.h: Regenerate. | |
| 224 | * m32r-dis.c: Regenerate. | |
| 225 | * m32r-ibld.c: Regenerate. | |
| 226 | * m32r-opc.c: Regenerate. | |
| 227 | * m32r-opc.h: Regenerate. | |
| 228 | * m32r-opinst.c: Regenerate. | |
| 229 | * mep-asm.c: Regenerate. | |
| 230 | * mep-desc.c: Regenerate. | |
| 231 | * mep-desc.h: Regenerate. | |
| 232 | * mep-dis.c: Regenerate. | |
| 233 | * mep-ibld.c: Regenerate. | |
| 234 | * mep-opc.c: Regenerate. | |
| 235 | * mep-opc.h: Regenerate. | |
| 236 | * mt-asm.c: Regenerate. | |
| 237 | * mt-desc.c: Regenerate. | |
| 238 | * mt-desc.h: Regenerate. | |
| 239 | * mt-dis.c: Regenerate. | |
| 240 | * mt-ibld.c: Regenerate. | |
| 241 | * mt-opc.c: Regenerate. | |
| 242 | * mt-opc.h: Regenerate. | |
| 243 | * or1k-asm.c: Regenerate. | |
| 244 | * or1k-desc.c: Regenerate. | |
| 245 | * or1k-desc.h: Regenerate. | |
| 246 | * or1k-dis.c: Regenerate. | |
| 247 | * or1k-ibld.c: Regenerate. | |
| 248 | * or1k-opc.c: Regenerate. | |
| 249 | * or1k-opc.h: Regenerate. | |
| 250 | * or1k-opinst.c: Regenerate. | |
| 251 | * xc16x-asm.c: Regenerate. | |
| 252 | * xc16x-desc.c: Regenerate. | |
| 253 | * xc16x-desc.h: Regenerate. | |
| 254 | * xc16x-dis.c: Regenerate. | |
| 255 | * xc16x-ibld.c: Regenerate. | |
| 256 | * xc16x-opc.c: Regenerate. | |
| 257 | * xc16x-opc.h: Regenerate. | |
| 258 | * xstormy16-asm.c: Regenerate. | |
| 259 | * xstormy16-desc.c: Regenerate. | |
| 260 | * xstormy16-desc.h: Regenerate. | |
| 261 | * xstormy16-dis.c: Regenerate. | |
| 262 | * xstormy16-ibld.c: Regenerate. | |
| 263 | * xstormy16-opc.c: Regenerate. | |
| 264 | * xstormy16-opc.h: Regenerate. | |
| 265 | ||
| 7639175c AM |
266 | 2017-07-07 Alan Modra <amodra@gmail.com> |
| 267 | ||
| 268 | * cgen-dis.in: Include disassemble.h, not dis-asm.h. | |
| 269 | * m32c-dis.c: Regenerate. | |
| 270 | * mep-dis.c: Regenerate. | |
| 271 | ||
| e4bdd679 BP |
272 | 2017-07-05 Borislav Petkov <bp@suse.de> |
| 273 | ||
| 274 | * i386-dis.c: Enable ModRM.reg /6 aliases. | |
| 275 | ||
| 60c96dbf RR |
276 | 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com> |
| 277 | ||
| 278 | * opcodes/arm-dis.c: Support MVFR2 in disassembly | |
| 279 | with vmrs and vmsr. | |
| 280 | ||
| 0d702cfe TG |
281 | 2017-07-04 Tristan Gingold <gingold@adacore.com> |
| 282 | ||
| 283 | * configure: Regenerate. | |
| 284 | ||
| 15e6ed8c TG |
285 | 2017-07-03 Tristan Gingold <gingold@adacore.com> |
| 286 | ||
| 287 | * po/opcodes.pot: Regenerate. | |
| 288 | ||
| b1d3c886 MR |
289 | 2017-06-30 Maciej W. Rozycki <macro@imgtec.com> |
| 290 | ||
| 291 | * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa" | |
| 292 | entries to the MSA ASE instruction block. | |
| 293 | ||
| 909b4e3d MR |
294 | 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com> |
| 295 | Maciej W. Rozycki <macro@imgtec.com> | |
| 296 | ||
| 297 | * micromips-opc.c (XPA, XPAVZ): New macros. | |
| 298 | (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and | |
| 299 | "mthgc0". | |
| 300 | ||
| f5b2fd52 MR |
301 | 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com> |
| 302 | Maciej W. Rozycki <macro@imgtec.com> | |
| 303 | ||
| 304 | * micromips-opc.c (I36): New macro. | |
| 305 | (micromips_opcodes): Add "eretnc". | |
| 306 | ||
| 9785fc2a MR |
307 | 2017-06-30 Maciej W. Rozycki <macro@imgtec.com> |
| 308 | Andrew Bennett <andrew.bennett@imgtec.com> | |
| 309 | ||
| 310 | * mips-dis.c (mips_calculate_combination_ases): Handle the | |
| 311 | ASE_XPA_VIRT flag. | |
| 312 | (parse_mips_ase_option): New function. | |
| 313 | (parse_mips_dis_option): Factor out ASE option handling to the | |
| 314 | new function. Call `mips_calculate_combination_ases'. | |
| 315 | * mips-opc.c (XPAVZ): New macro. | |
| 316 | (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0", | |
| 317 | "mfhgc0", "mthc0" and "mthgc0". | |
| 318 | ||
| 60804c53 MR |
319 | 2017-06-29 Maciej W. Rozycki <macro@imgtec.com> |
| 320 | ||
| 321 | * mips-dis.c (mips_calculate_combination_ases): New function. | |
| 322 | (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT | |
| 323 | calculation to the new function. | |
| 324 | (set_default_mips_dis_options): Call the new function. | |
| 325 | ||
| 2e74f9dd AK |
326 | 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com> |
| 327 | ||
| 328 | * arc-dis.c (parse_disassembler_options): Use | |
| 329 | FOR_EACH_DISASSEMBLER_OPTION. | |
| 330 | ||
| e1e94c49 AK |
331 | 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com> |
| 332 | ||
| 333 | * arc-dis.c (parse_option): Use disassembler_options_cmp to compare | |
| 334 | disassembler option strings. | |
| 335 | (parse_cpu_option): Likewise. | |
| 336 | ||
| 65a55fbb TC |
337 | 2017-06-28 Tamar Christina <tamar.christina@arm.com> |
| 338 | ||
| 339 | * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod. | |
| 340 | * aarch64-dis.c (aarch64_ext_reglane): Likewise. | |
| 341 | * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New. | |
| 342 | (aarch64_feature_dotprod, DOT_INSN): New. | |
| 343 | (udot, sdot): New. | |
| 344 | * aarch64-dis-2.c: Regenerated. | |
| 345 | ||
| c604a79a JW |
346 | 2017-06-28 Jiong Wang <jiong.wang@arm.com> |
| 347 | ||
| 348 | * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot. | |
| 349 | ||
| 38bf472a MR |
350 | 2017-06-28 Maciej W. Rozycki <macro@imgtec.com> |
| 351 | Matthew Fortune <matthew.fortune@imgtec.com> | |
| 4151f684 | 352 | Andrew Bennett <andrew.bennett@imgtec.com> |
| 38bf472a MR |
353 | |
| 354 | * mips-formats.h (INT_BIAS): New macro. | |
| 355 | (INT_ADJ): Redefine in INT_BIAS terms. | |
| 356 | * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry. | |
| 357 | (mips_print_save_restore): New function. | |
| 358 | (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment. | |
| 359 | (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort' | |
| 360 | call. | |
| 361 | (print_insn_args): Handle OP_SAVE_RESTORE_LIST. | |
| 362 | (print_mips16_insn_arg): Call `mips_print_save_restore' for | |
| 363 | OP_SAVE_RESTORE_LIST handling, factored out from here. | |
| 364 | * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case. | |
| 365 | (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros. | |
| 366 | (mips_builtin_opcodes): Add "restore" and "save" entries. | |
| 367 | * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases. | |
| 368 | (IAMR2): New macro. | |
| 369 | (mips16_opcodes): Add "copyw" and "ucopyw" entries. | |
| 370 | ||
| 9bdfdbf9 AW |
371 | 2017-06-23 Andrew Waterman <andrew@sifive.com> |
| 372 | ||
| 373 | * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an | |
| 374 | alias; do not mark SLTI instruction as an alias. | |
| 375 | ||
| 2234eee6 L |
376 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| 377 | ||
| 378 | * i386-dis.c (RM_0FAE_REG_5): Removed. | |
| 379 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. | |
| 380 | (PREFIX_MOD_3_0F01_REG_5_RM_0): New. | |
| 381 | (PREFIX_MOD_3_0FAE_REG_5): Likewise. | |
| 382 | (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add | |
| 383 | PREFIX_MOD_3_0F01_REG_5_RM_0. | |
| 384 | (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add | |
| 385 | PREFIX_MOD_3_0FAE_REG_5. | |
| 386 | (mod_table): Update MOD_0FAE_REG_5. | |
| 387 | (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5. | |
| 388 | * i386-opc.tbl: Update incsspd, incsspq and setssbsy. | |
| 389 | * i386-tbl.h: Regenerated. | |
| 390 | ||
| c2f76402 L |
391 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| 392 | ||
| 393 | * i386-dis.c (prefix_table): Replace savessp with saveprevssp. | |
| 394 | * i386-opc.tbl: Likewise. | |
| 395 | * i386-tbl.h: Regenerated. | |
| 396 | ||
| 9fef80d6 L |
397 | 2017-06-21 H.J. Lu <hongjiu.lu@intel.com> |
| 398 | ||
| 399 | * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}" | |
| 400 | and "jmp{&|}". | |
| 401 | (NOTRACK_Fixup): Support memory indirect branch with NOTRACK | |
| 402 | prefix. | |
| 403 | ||
| 0f6d864d NC |
404 | 2017-06-19 Nick Clifton <nickc@redhat.com> |
| 405 | ||
| 406 | PR binutils/21614 | |
| 407 | * score-dis.c (score_opcodes): Add sentinel. | |
| 408 | ||
| e197589b AM |
409 | 2017-06-16 Alan Modra <amodra@gmail.com> |
| 410 | ||
| 411 | * rx-decode.c: Regenerate. | |
| 412 | ||
| 0d96e4df L |
413 | 2017-06-15 H.J. Lu <hongjiu.lu@intel.com> |
| 414 | ||
| 415 | PR binutils/21594 | |
| 416 | * i386-dis.c (OP_E_register): Check valid bnd register. | |
| 417 | (OP_G): Likewise. | |
| 418 | ||
| cd3ea7c6 NC |
419 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| 420 | ||
| 421 | PR binutils/21595 | |
| 422 | * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of | |
| 423 | range value. | |
| 424 | ||
| 63323b5b NC |
425 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| 426 | ||
| 427 | PR binutils/21588 | |
| 428 | * rl78-decode.opc (OP_BUF_LEN): Define. | |
| 429 | (GETBYTE): Check for the index exceeding OP_BUF_LEN. | |
| 430 | (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf | |
| 431 | array. | |
| 432 | * rl78-decode.c: Regenerate. | |
| 433 | ||
| 08c7881b NC |
434 | 2017-06-15 Nick Clifton <nickc@redhat.com> |
| 435 | ||
| 436 | PR binutils/21586 | |
| 437 | * bfin-dis.c (gregs): Clip index to prevent overflow. | |
| 438 | (regs): Likewise. | |
| 439 | (regs_lo): Likewise. | |
| 440 | (regs_hi): Likewise. | |
| 441 | ||
| e64519d1 NC |
442 | 2017-06-14 Nick Clifton <nickc@redhat.com> |
| 443 | ||
| 444 | PR binutils/21576 | |
| 445 | * score7-dis.c (score_opcodes): Add sentinel. | |
| 446 | ||
| 6394c606 YQ |
447 | 2017-06-14 Yao Qi <yao.qi@linaro.org> |
| 448 | ||
| 449 | * aarch64-dis.c: Include disassemble.h instead of dis-asm.h. | |
| 450 | * arm-dis.c: Likewise. | |
| 451 | * ia64-dis.c: Likewise. | |
| 452 | * mips-dis.c: Likewise. | |
| 453 | * spu-dis.c: Likewise. | |
| 454 | * disassemble.h (print_insn_aarch64): New declaration, moved from | |
| 455 | include/dis-asm.h. | |
| 456 | (print_insn_big_arm, print_insn_big_mips): Likewise. | |
| 457 | (print_insn_i386, print_insn_ia64): Likewise. | |
| 458 | (print_insn_little_arm, print_insn_little_mips): Likewise. | |
| 459 | ||
| db5fa770 NC |
460 | 2017-06-14 Nick Clifton <nickc@redhat.com> |
| 461 | ||
| 462 | PR binutils/21587 | |
| 463 | * rx-decode.opc: Include libiberty.h | |
| 464 | (GET_SCALE): New macro - validates access to SCALE array. | |
| 465 | (GET_PSCALE): New macro - validates access to PSCALE array. | |
| 466 | (DIs, SIs, S2Is, rx_disp): Use new macros. | |
| 467 | * rx-decode.c: Regenerate. | |
| 468 | ||
| 05c966f3 AV |
469 | 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com> |
| 470 | ||
| 471 | * arm-dis.c (print_insn_arm): Remove bogus entry for bx. | |
| 472 | ||
| 10045478 AK |
473 | 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com> |
| 474 | ||
| 475 | * arc-dis.c (enforced_isa_mask): Declare. | |
| 476 | (cpu_types): Likewise. | |
| 477 | (parse_cpu_option): New function. | |
| 478 | (parse_disassembler_options): Use it. | |
| 479 | (print_insn_arc): Use enforced_isa_mask. | |
| 480 | (print_arc_disassembler_options): Document new options. | |
| 481 | ||
| 88c1242d YQ |
482 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 483 | ||
| 484 | * alpha-dis.c: Include disassemble.h, don't include | |
| 485 | dis-asm.h. | |
| 486 | * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise. | |
| 487 | * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise. | |
| 488 | * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise. | |
| 489 | * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise. | |
| 490 | * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise. | |
| 491 | * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise. | |
| 492 | * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise. | |
| 493 | * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise. | |
| 494 | * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise. | |
| 495 | * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise. | |
| 496 | * moxie-dis.c, msp430-dis.c, mt-dis.c: | |
| 497 | * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise. | |
| 498 | * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise. | |
| 499 | * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise. | |
| 500 | * rl78-dis.c, s390-dis.c, score-dis.c: Likewise. | |
| 501 | * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise. | |
| 502 | * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise. | |
| 503 | * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise. | |
| 504 | * v850-dis.c, vax-dis.c, visium-dis.c: Likewise. | |
| 505 | * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise. | |
| 506 | * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise. | |
| 507 | * z80-dis.c, z8k-dis.c: Likewise. | |
| 508 | * disassemble.h: New file. | |
| 509 | ||
| ab20fa4a YQ |
510 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 511 | ||
| 512 | * rl78-dis.c (rl78_get_disassembler): If parameter abfd | |
| 513 | is NULL, set cpu to E_FLAG_RL78_ANY_CPU. | |
| 514 | ||
| 003ca0fd YQ |
515 | 2017-05-24 Yao Qi <yao.qi@linaro.org> |
| 516 | ||
| 517 | * disassemble.c (disassembler): Add arguments a, big and mach. | |
| 518 | Use them. | |
| 519 | ||
| 04ef582a L |
520 | 2017-05-22 H.J. Lu <hongjiu.lu@intel.com> |
| 521 | ||
| 522 | * i386-dis.c (NOTRACK_Fixup): New. | |
| 523 | (NOTRACK): Likewise. | |
| 524 | (NOTRACK_PREFIX): Likewise. | |
| 525 | (last_active_prefix): Likewise. | |
| 526 | (reg_table): Use NOTRACK on indirect call and jmp. | |
| 527 | (ckprefix): Set last_active_prefix. | |
| 528 | (prefix_name): Return "notrack" for NOTRACK_PREFIX. | |
| 529 | * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk. | |
| 530 | * i386-opc.h (NoTrackPrefixOk): New. | |
| 531 | (i386_opcode_modifier): Add notrackprefixok. | |
| 532 | * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp. | |
| 533 | Add notrack. | |
| 534 | * i386-tbl.h: Regenerated. | |
| 535 | ||
| 64517994 JM |
536 | 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 537 | ||
| 538 | * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8. | |
| 539 | (X_IMM2): Define. | |
| 540 | (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and | |
| 541 | bfd_mach_sparc_v9m8. | |
| 542 | (print_insn_sparc): Handle new operand types. | |
| 543 | * sparc-opc.c (MASK_M8): Define. | |
| 544 | (v6): Add MASK_M8. | |
| 545 | (v6notlet): Likewise. | |
| 546 | (v7): Likewise. | |
| 547 | (v8): Likewise. | |
| 548 | (v9): Likewise. | |
| 549 | (v9a): Likewise. | |
| 550 | (v9b): Likewise. | |
| 551 | (v9c): Likewise. | |
| 552 | (v9d): Likewise. | |
| 553 | (v9e): Likewise. | |
| 554 | (v9v): Likewise. | |
| 555 | (v9m): Likewise. | |
| 556 | (v9andleon): Likewise. | |
| 557 | (m8): Define. | |
| 558 | (HWS_VM8): Define. | |
| 559 | (HWS2_VM8): Likewise. | |
| 560 | (sparc_opcode_archs): Add entry for "m8". | |
| 561 | (sparc_opcodes): Add OSA2017 and M8 instructions | |
| 562 | dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl, | |
| 563 | fpx{ll,ra,rl}64x, | |
| 564 | ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d}, | |
| 565 | ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb, | |
| 566 | revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x}, | |
| 567 | stm{h,w,x}a, stmf{s,d}, stmf{s,d}a. | |
| 568 | (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT, | |
| 569 | ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR, | |
| 570 | ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL, | |
| 571 | ASI_CORE_SELECT_COMMIT_NHT. | |
| 572 | ||
| 535b785f AM |
573 | 2017-05-18 Alan Modra <amodra@gmail.com> |
| 574 | ||
| 575 | * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE. | |
| 576 | * aarch64-dis.c: Likewise. | |
| 577 | * aarch64-gen.c: Likewise. | |
| 578 | * aarch64-opc.c: Likewise. | |
| 579 | ||
| 25499ac7 MR |
580 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
| 581 | Matthew Fortune <matthew.fortune@imgtec.com> | |
| 582 | ||
| 583 | * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and | |
| 584 | ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry. | |
| 585 | (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag. | |
| 586 | (print_insn_arg) <OP_REG28>: Add handler. | |
| 587 | (validate_insn_args) <OP_REG28>: Handle. | |
| 588 | (print_mips16_insn_arg): Handle MIPS16 instructions that require | |
| 589 | 32-bit encoding and 9-bit immediates. | |
| 590 | (print_insn_mips16): Handle MIPS16 instructions that require | |
| 591 | 32-bit encoding and MFC0/MTC0 operand decoding. | |
| 592 | * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'> | |
| 593 | <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers. | |
| 594 | (RD_C0, WR_C0, E2, E2MT): New macros. | |
| 595 | (mips16_opcodes): Add entries for MIPS16e2 instructions: | |
| 596 | GP-relative "addiu" and its "addu" spelling, "andi", "cache", | |
| 597 | "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh", | |
| 598 | "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0", | |
| 599 | "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause", | |
| 600 | "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw" | |
| 601 | instructions, "swl", "swr", "sync" and its "sync_acquire", | |
| 602 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases, | |
| 603 | "xori", "dmt", "dvpe", "emt" and "evpe". Add split | |
| 604 | regular/extended entries for original MIPS16 ISA revision | |
| 605 | instructions whose extended forms are subdecoded in the MIPS16e2 | |
| 606 | ISA revision: "li", "sll" and "srl". | |
| 607 | ||
| fdfb4752 MR |
608 | 2017-05-15 Maciej W. Rozycki <macro@imgtec.com> |
| 609 | ||
| 610 | * mips-dis.c (print_insn_args) <default>: Remove an MT ASE | |
| 611 | reference in CP0 move operand decoding. | |
| 612 | ||
| a4f89915 MR |
613 | 2017-05-12 Maciej W. Rozycki <macro@imgtec.com> |
| 614 | ||
| 615 | * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand | |
| 616 | type to hexadecimal. | |
| 617 | (mips16_opcodes): Add operandless "break" and "sdbbp" entries. | |
| 618 | ||
| 99e2d67a MR |
619 | 2017-05-11 Maciej W. Rozycki <macro@imgtec.com> |
| 620 | ||
| 621 | * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs", | |
| 622 | "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release", | |
| 623 | "sync_rmb" and "sync_wmb" as aliases. | |
| 624 | * micromips-opc.c (micromips_opcodes): Mark "sync_acquire", | |
| 625 | "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases. | |
| 626 | ||
| 53a346d8 CZ |
627 | 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com> |
| 628 | ||
| 629 | * arc-dis.c (parse_option): Update quarkse_em option.. | |
| 630 | * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to | |
| 631 | QUARKSE1. | |
| 632 | (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2. | |
| 633 | ||
| f91d48de KC |
634 | 2017-05-03 Kito Cheng <kito.cheng@gmail.com> |
| 635 | ||
| 636 | * riscv-dis.c (print_insn_args): Handle 'Co' operands. | |
| 637 | ||
| 43e379d7 MC |
638 | 2017-05-01 Michael Clark <michaeljclark@mac.com> |
| 639 | ||
| 640 | * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary | |
| 641 | register. | |
| 642 | ||
| a4ddc54e MR |
643 | 2017-05-02 Maciej W. Rozycki <macro@imgtec.com> |
| 644 | ||
| 645 | * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps | |
| 646 | and branches and not synthetic data instructions. | |
| 647 | ||
| fe50e98c BE |
648 | 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de> |
| 649 | ||
| 650 | * arm-dis.c (print_insn_thumb32): Fix value_in_comment. | |
| 651 | ||
| 126124cc CZ |
652 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| 653 | ||
| 654 | * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics. | |
| 655 | * arc-opc.c (insert_r13el): New function. | |
| 656 | (R13_EL): Define. | |
| 657 | * arc-tbl.h: Add new enter/leave variants. | |
| 658 | ||
| be6a24d8 CZ |
659 | 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com> |
| 660 | ||
| 661 | * arc-tbl.h: Reorder NOP entry to be before MOV instructions. | |
| 662 | ||
| 0348fd79 MR |
663 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| 664 | ||
| 665 | * mips-dis.c (print_mips_disassembler_options): Add | |
| 666 | `no-aliases'. | |
| 667 | ||
| 6e3d1f07 MR |
668 | 2017-04-25 Maciej W. Rozycki <macro@imgtec.com> |
| 669 | ||
| 670 | * mips16-opc.c (AL): New macro. | |
| 671 | (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms | |
| 672 | of "ld" and "lw" as aliases. | |
| 673 | ||
| 957f6b39 TC |
674 | 2017-04-24 Tamar Christina <tamar.christina@arm.com> |
| 675 | ||
| 676 | * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE | |
| 677 | arguments. | |
| 678 | ||
| a8cc8a54 AM |
679 | 2017-04-22 Alexander Fedotov <alfedotov@gmail.com> |
| 680 | Alan Modra <amodra@gmail.com> | |
| 681 | ||
| 682 | * ppc-opc.c (ELEV): Define. | |
| 683 | (vle_opcodes): Add se_rfgi and e_sc. | |
| 684 | (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx | |
| 685 | for E200Z4. | |
| 686 | ||
| 3ab87b68 JM |
687 | 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com> |
| 688 | ||
| 689 | * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9. | |
| 690 | ||
| 792f174f NC |
691 | 2017-04-21 Nick Clifton <nickc@redhat.com> |
| 692 | ||
| 693 | PR binutils/21380 | |
| 694 | * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R, | |
| 695 | LD3R and LD4R. | |
| 696 | ||
| 42742084 AM |
697 | 2017-04-13 Alan Modra <amodra@gmail.com> |
| 698 | ||
| 699 | * epiphany-desc.c: Regenerate. | |
| 700 | * fr30-desc.c: Regenerate. | |
| 701 | * frv-desc.c: Regenerate. | |
| 702 | * ip2k-desc.c: Regenerate. | |
| 703 | * iq2000-desc.c: Regenerate. | |
| 704 | * lm32-desc.c: Regenerate. | |
| 705 | * m32c-desc.c: Regenerate. | |
| 706 | * m32r-desc.c: Regenerate. | |
| 707 | * mep-desc.c: Regenerate. | |
| 708 | * mt-desc.c: Regenerate. | |
| 709 | * or1k-desc.c: Regenerate. | |
| 710 | * xc16x-desc.c: Regenerate. | |
| 711 | * xstormy16-desc.c: Regenerate. | |
| 712 | ||
| 9a85b496 AM |
713 | 2017-04-11 Alan Modra <amodra@gmail.com> |
| 714 | ||
| ef85eab0 | 715 | * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2, |
| c03dc33b AM |
716 | PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set |
| 717 | PPC_OPCODE_TMR for e6500. | |
| 9a85b496 AM |
718 | * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500. |
| 719 | (PPCVEC3): Define as PPC_OPCODE_POWER9. | |
| 9570835e AM |
720 | (PPCVSX2): Define as PPC_OPCODE_POWER8. |
| 721 | (PPCVSX3): Define as PPC_OPCODE_POWER9. | |
| ef85eab0 | 722 | (PPCHTM): Define as PPC_OPCODE_POWER8. |
| c03dc33b | 723 | (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500. |
| 9a85b496 | 724 | |
| 62adc510 AM |
725 | 2017-04-10 Alan Modra <amodra@gmail.com> |
| 726 | ||
| 727 | * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440. | |
| 728 | * ppc-opc.c (MULHW): Add PPC_OPCODE_476. | |
| 729 | (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit | |
| 730 | removal of PPC_OPCODE_440 from ppc476 cpu selection bits. | |
| 731 | ||
| aa808707 PC |
732 | 2017-04-09 Pip Cet <pipcet@gmail.com> |
| 733 | ||
| 734 | * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify | |
| 735 | appropriate floating-point precision directly. | |
| 736 | ||
| ac8f0f72 AM |
737 | 2017-04-07 Alan Modra <amodra@gmail.com> |
| 738 | ||
| 739 | * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl, | |
| 740 | lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx, | |
| 741 | lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx, | |
| 742 | lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only | |
| 743 | vector instructions with E6500 not PPCVEC2. | |
| 744 | ||
| 62ecb94c PC |
745 | 2017-04-06 Pip Cet <pipcet@gmail.com> |
| 746 | ||
| 747 | * Makefile.am: Add wasm32-dis.c. | |
| 748 | * configure.ac: Add wasm32-dis.c to wasm32 target. | |
| 749 | * disassemble.c: Add wasm32 disassembler code. | |
| 750 | * wasm32-dis.c: New file. | |
| 751 | * Makefile.in: Regenerate. | |
| 752 | * configure: Regenerate. | |
| 753 | * po/POTFILES.in: Regenerate. | |
| 754 | * po/opcodes.pot: Regenerate. | |
| 755 | ||
| f995bbe8 PA |
756 | 2017-04-05 Pedro Alves <palves@redhat.com> |
| 757 | ||
| 758 | * arc-dis.c (parse_option, parse_disassembler_options): Constify. | |
| 759 | * arm-dis.c (parse_arm_disassembler_options): Constify. | |
| 760 | * ppc-dis.c (powerpc_init_dialect): Constify local. | |
| 761 | * vax-dis.c (parse_disassembler_options): Constify. | |
| 762 | ||
| b5292032 PD |
763 | 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com> |
| 764 | ||
| 765 | * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to | |
| 766 | RISCV_GP_SYMBOL. | |
| 767 | ||
| f96bd6c2 PC |
768 | 2017-03-30 Pip Cet <pipcet@gmail.com> |
| 769 | ||
| 770 | * configure.ac: Add (empty) bfd_wasm32_arch target. | |
| 771 | * configure: Regenerate | |
| 772 | * po/opcodes.pot: Regenerate. | |
| 773 | ||
| f7c514a3 JM |
774 | 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com> |
| 775 | ||
| 776 | Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, & | |
| 777 | OSA2015. | |
| 778 | * opcodes/sparc-opc.c (asi_table): New ASIs. | |
| 779 | ||
| 52be03fd AM |
780 | 2017-03-29 Alan Modra <amodra@gmail.com> |
| 781 | ||
| 782 | * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add | |
| 783 | "raw" option. | |
| 784 | (lookup_powerpc): Don't special case -1 dialect. Handle | |
| 785 | PPC_OPCODE_RAW. | |
| 786 | (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first | |
| 787 | lookup_powerpc call, pass it on second. | |
| 788 | ||
| 9b753937 AM |
789 | 2017-03-27 Alan Modra <amodra@gmail.com> |
| 790 | ||
| 791 | PR 21303 | |
| 792 | * ppc-dis.c (struct ppc_mopt): Comment. | |
| 793 | (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu. | |
| 794 | ||
| c0c31e91 RZ |
795 | 2017-03-27 Rinat Zelig <rinat@mellanox.com> |
| 796 | ||
| 797 | * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format. | |
| 798 | * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR, | |
| 799 | F_NPS_M, F_NPS_CORE, F_NPS_ALL. | |
| 800 | (insert_nps_misc_imm_offset): New function. | |
| 801 | (extract_nps_misc imm_offset): New function. | |
| 802 | (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T. | |
| 803 | (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T. | |
| 804 | ||
| 2253c8f0 AK |
805 | 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
| 806 | ||
| 807 | * s390-mkopc.c (main): Remove vx2 check. | |
| 808 | * s390-opc.txt: Remove vx2 instruction flags. | |
| 809 | ||
| 645d3342 RZ |
810 | 2017-03-21 Rinat Zelig <rinat@mellanox.com> |
| 811 | ||
| 812 | * arc-nps400-tbl.h: Add cp32/cp16 instructions format. | |
| 813 | * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET. | |
| 814 | (insert_nps_imm_offset): New function. | |
| 815 | (extract_nps_imm_offset): New function. | |
| 816 | (insert_nps_imm_entry): New function. | |
| 817 | (extract_nps_imm_entry): New function. | |
| 818 | ||
| 4b94dd2d AM |
819 | 2017-03-17 Alan Modra <amodra@gmail.com> |
| 820 | ||
| 821 | PR 21248 | |
| 822 | * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33, | |
| 823 | mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after | |
| 824 | those spr mnemonics they alias. Similarly for mtibatl, mtibatu. | |
| 825 | ||
| b416fe87 KC |
826 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 827 | ||
| 828 | * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding. | |
| 829 | <c.andi>: Likewise. | |
| 830 | <c.addiw> Likewise. | |
| 831 | ||
| 03b039a5 KC |
832 | 2017-03-14 Kito Cheng <kito.cheng@gmail.com> |
| 833 | ||
| 834 | * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode. | |
| 835 | ||
| 2c232b83 AW |
836 | 2017-03-13 Andrew Waterman <andrew@sifive.com> |
| 837 | ||
| 838 | * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode. | |
| 839 | <srl> Likewise. | |
| 840 | <srai> Likewise. | |
| 841 | <sra> Likewise. | |
| 842 | ||
| 86fa6981 L |
843 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 844 | ||
| 845 | * i386-gen.c (opcode_modifiers): Replace S with Load. | |
| 846 | * i386-opc.h (S): Removed. | |
| 847 | (Load): New. | |
| 848 | (i386_opcode_modifier): Replace s with load. | |
| 849 | * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3} | |
| 850 | and {evex}. Replace S with Load. | |
| 851 | * i386-tbl.h: Regenerated. | |
| 852 | ||
| c1fe188b L |
853 | 2017-03-09 H.J. Lu <hongjiu.lu@intel.com> |
| 854 | ||
| 855 | * i386-opc.tbl: Use CpuCET on rdsspq. | |
| 856 | * i386-tbl.h: Regenerated. | |
| 857 | ||
| 4b8b687e PB |
858 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| 859 | ||
| 860 | * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2; | |
| 861 | <vsx>: Do not use PPC_OPCODE_VSX3; | |
| 862 | ||
| 1437d063 PB |
863 | 2017-03-08 Peter Bergner <bergner@vnet.ibm.com> |
| 864 | ||
| 865 | * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic. | |
| 866 | ||
| 603555e5 L |
867 | 2017-03-06 H.J. Lu <hongjiu.lu@intel.com> |
| 868 | ||
| 869 | * i386-dis.c (REG_0F1E_MOD_3): New enum. | |
| 870 | (MOD_0F1E_PREFIX_1): Likewise. | |
| 871 | (MOD_0F38F5_PREFIX_2): Likewise. | |
| 872 | (MOD_0F38F6_PREFIX_0): Likewise. | |
| 873 | (RM_0F1E_MOD_3_REG_7): Likewise. | |
| 874 | (PREFIX_MOD_0_0F01_REG_5): Likewise. | |
| 875 | (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise. | |
| 876 | (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise. | |
| 877 | (PREFIX_0F1E): Likewise. | |
| 878 | (PREFIX_MOD_0_0FAE_REG_5): Likewise. | |
| 879 | (PREFIX_0F38F5): Likewise. | |
| 880 | (dis386_twobyte): Use PREFIX_0F1E. | |
| 881 | (reg_table): Add REG_0F1E_MOD_3. | |
| 882 | (prefix_table): Add PREFIX_MOD_0_0F01_REG_5, | |
| 883 | PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2, | |
| 884 | PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update | |
| 885 | PREFIX_0FAE_REG_6 and PREFIX_0F38F6. | |
| 886 | (three_byte_table): Use PREFIX_0F38F5. | |
| 887 | (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5. | |
| 888 | Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0. | |
| 889 | (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0, | |
| 890 | RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and | |
| 891 | PREFIX_MOD_3_0F01_REG_5_RM_2. | |
| 892 | * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS. | |
| 893 | (cpu_flags): Add CpuCET. | |
| 894 | * i386-opc.h (CpuCET): New enum. | |
| 895 | (CpuUnused): Commented out. | |
| 896 | (i386_cpu_flags): Add cpucet. | |
| 897 | * i386-opc.tbl: Add Intel CET instructions. | |
| 898 | * i386-init.h: Regenerated. | |
| 899 | * i386-tbl.h: Likewise. | |
| 900 | ||
| 73f07bff AM |
901 | 2017-03-06 Alan Modra <amodra@gmail.com> |
| 902 | ||
| 903 | PR 21124 | |
| 904 | * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram) | |
| 905 | (extract_raq, extract_ras, extract_rbx): New functions. | |
| 906 | (powerpc_operands): Use opposite corresponding insert function. | |
| 907 | (Q_MASK): Define. | |
| 908 | (powerpc_opcodes): Apply Q_MASK to all quad insns with even | |
| 909 | register restriction. | |
| 910 | ||
| 65b48a81 PB |
911 | 2017-02-28 Peter Bergner <bergner@vnet.ibm.com> |
| 912 | ||
| 913 | * disassemble.c Include "safe-ctype.h". | |
| 914 | (disassemble_init_for_target): Handle s390 init. | |
| 915 | (remove_whitespace_and_extra_commas): New function. | |
| 916 | (disassembler_options_cmp): Likewise. | |
| 917 | * arm-dis.c: Include "libiberty.h". | |
| 918 | (NUM_ELEM): Delete. | |
| 919 | (regnames): Use long disassembler style names. | |
| 920 | Add force-thumb and no-force-thumb options. | |
| 921 | (NUM_ARM_REGNAMES): Rename from this... | |
| 922 | (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE. | |
| 923 | (get_arm_regname_num_options): Delete. | |
| 924 | (set_arm_regname_option): Likewise. | |
| 925 | (get_arm_regnames): Likewise. | |
| 926 | (parse_disassembler_options): Likewise. | |
| 927 | (parse_arm_disassembler_option): Rename from this... | |
| 928 | (parse_arm_disassembler_options): ...to this. Make static. | |
| 929 | Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options. | |
| 930 | (print_insn): Use parse_arm_disassembler_options. | |
| 931 | (disassembler_options_arm): New function. | |
| 932 | (print_arm_disassembler_options): Handle updated regnames. | |
| 933 | * ppc-dis.c: Include "libiberty.h". | |
| 934 | (ppc_opts): Add "32" and "64" entries. | |
| 935 | (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp. | |
| 936 | (powerpc_init_dialect): Add break to switch statement. | |
| 937 | Use new FOR_EACH_DISASSEMBLER_OPTION macro. | |
| 938 | (disassembler_options_powerpc): New function. | |
| 939 | (print_ppc_disassembler_options): Use ARRAY_SIZE. | |
| 940 | Remove printing of "32" and "64". | |
| 941 | * s390-dis.c: Include "libiberty.h". | |
| 942 | (init_flag): Remove unneeded variable. | |
| 943 | (struct s390_options_t): New structure type. | |
| 944 | (options): New structure. | |
| 945 | (init_disasm): Rename from this... | |
| 946 | (disassemble_init_s390): ...to this. Add initializations for | |
| 947 | current_arch_mask and option_use_insn_len_bits_p. Remove init_flag. | |
| 948 | (print_insn_s390): Delete call to init_disasm. | |
| 949 | (disassembler_options_s390): New function. | |
| 950 | (print_s390_disassembler_options): Print using information from | |
| 951 | struct 'options'. | |
| 952 | * po/opcodes.pot: Regenerate. | |
| 953 | ||
| 15c7c1d8 JB |
954 | 2017-02-28 Jan Beulich <jbeulich@suse.com> |
| 955 | ||
| 956 | * i386-dis.c (PCMPESTR_Fixup): New. | |
| 957 | (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete. | |
| 958 | (prefix_table): Use PCMPESTR_Fixup. | |
| 959 | (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use | |
| 960 | PCMPESTR_Fixup. | |
| 961 | (vex_w_table): Delete VPCMPESTR{I,M} entries. | |
| 962 | * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm): | |
| 963 | Split 64-bit and non-64-bit variants. | |
| 964 | * opcodes/i386-tbl.h: Re-generate. | |
| 965 | ||
| 582e12bf RS |
966 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| 967 | ||
| 968 | * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD) | |
| 969 | (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD) | |
| 970 | (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S) | |
| 971 | (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H) | |
| 972 | (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH) | |
| 973 | (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD) | |
| 974 | (OP_SVE_V_HSD): New macros. | |
| 975 | (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD) | |
| 976 | (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD) | |
| 977 | (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete. | |
| 978 | (aarch64_opcode_table): Add new SVE instructions. | |
| 979 | (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate | |
| 980 | for rotation operands. Add new SVE operands. | |
| 981 | * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter. | |
| 982 | (ins_sve_quad_index): Likewise. | |
| 983 | (ins_imm_rotate): Split into... | |
| 984 | (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters. | |
| 985 | * aarch64-asm.c (aarch64_ins_imm_rotate): Split into... | |
| 986 | (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two | |
| 987 | functions. | |
| 988 | (aarch64_ins_sve_addr_ri_s4): New function. | |
| 989 | (aarch64_ins_sve_quad_index): Likewise. | |
| 990 | (do_misc_encoding): Handle "MOV Zn.Q, Qm". | |
| 991 | * aarch64-asm-2.c: Regenerate. | |
| 992 | * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor. | |
| 993 | (ext_sve_quad_index): Likewise. | |
| 994 | (ext_imm_rotate): Split into... | |
| 995 | (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors. | |
| 996 | * aarch64-dis.c (aarch64_ext_imm_rotate): Split into... | |
| 997 | (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two | |
| 998 | functions. | |
| 999 | (aarch64_ext_sve_addr_ri_s4): New function. | |
| 1000 | (aarch64_ext_sve_quad_index): Likewise. | |
| 1001 | (aarch64_ext_sve_index): Allow quad indices. | |
| 1002 | (do_misc_decoding): Likewise. | |
| 1003 | * aarch64-dis-2.c: Regenerate. | |
| 1004 | * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New | |
| 1005 | aarch64_field_kinds. | |
| 1006 | (OPD_F_OD_MASK): Widen by one bit. | |
| 1007 | (OPD_F_NO_ZR): Bump accordingly. | |
| 1008 | (get_operand_field_width): New function. | |
| 1009 | * aarch64-opc.c (fields): Add new SVE fields. | |
| 1010 | (operand_general_constraint_met_p): Handle new SVE operands. | |
| 1011 | (aarch64_print_operand): Likewise. | |
| 1012 | * aarch64-opc-2.c: Regenerate. | |
| 1013 | ||
| f482d304 RS |
1014 | 2017-02-24 Richard Sandiford <richard.sandiford@arm.com> |
| 1015 | ||
| 1016 | * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with... | |
| 1017 | (aarch64_feature_compnum): ...this. | |
| 1018 | (SIMD_V8_3): Replace with... | |
| 1019 | (COMPNUM): ...this. | |
| 1020 | (CNUM_INSN): New macro. | |
| 1021 | (aarch64_opcode_table): Use it for the complex number instructions. | |
| 1022 | ||
| 7db2c588 JB |
1023 | 2017-02-24 Jan Beulich <jbeulich@suse.com> |
| 1024 | ||
| 1025 | * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST. | |
| 1026 | ||
| 1e9d41d4 SL |
1027 | 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com> |
| 1028 | ||
| 1029 | Add support for associating SPARC ASIs with an architecture level. | |
| 1030 | * include/opcode/sparc.h (sparc_asi): New sparc_asi struct. | |
| 1031 | * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/ | |
| 1032 | decoding of SPARC ASIs. | |
| 1033 | ||
| 53c4d625 JB |
1034 | 2017-02-23 Jan Beulich <jbeulich@suse.com> |
| 1035 | ||
| 1036 | * i386-dis.c (get_valid_dis386): Don't special case VEX opcode | |
| 1037 | 82. For 3-byte VEX only special case opcode 77 in VEX_0F space. | |
| 1038 | ||
| 11648de5 JB |
1039 | 2017-02-21 Jan Beulich <jbeulich@suse.com> |
| 1040 | ||
| 1041 | * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand | |
| 1042 | 1 (instead of to itself). Correct typo. | |
| 1043 | ||
| f98d33be AW |
1044 | 2017-02-14 Andrew Waterman <andrew@sifive.com> |
| 1045 | ||
| 1046 | * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and | |
| 1047 | pseudoinstructions. | |
| 1048 | ||
| 773fb663 RS |
1049 | 2017-02-15 Richard Sandiford <richard.sandiford@arm.com> |
| 1050 | ||
| 1051 | * aarch64-opc.c (aarch64_sys_regs): Add SVE registers. | |
| 1052 | (aarch64_sys_reg_supported_p): Handle them. | |
| 1053 | ||
| cc07cda6 CZ |
1054 | 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com> |
| 1055 | ||
| 1056 | * arc-opc.c (UIMM6_20R): Define. | |
| 1057 | (SIMM12_20): Use above. | |
| 1058 | (SIMM12_20R): Define. | |
| 1059 | (SIMM3_5_S): Use above. | |
| 1060 | (UIMM7_A32_11R_S): Define. | |
| 1061 | (UIMM7_9_S): Use above. | |
| 1062 | (UIMM3_13R_S): Define. | |
| 1063 | (SIMM11_A32_7_S): Use above. | |
| 1064 | (SIMM9_8R): Define. | |
| 1065 | (UIMM10_A32_8_S): Use above. | |
| 1066 | (UIMM8_8R_S): Define. | |
| 1067 | (W6): Use above. | |
| 1068 | (arc_relax_opcodes): Use all above defines. | |
| 1069 | ||
| 66a5a740 VG |
1070 | 2017-02-15 Vineet Gupta <vgupta@synopsys.com> |
| 1071 | ||
| 1072 | * arc-regs.h: Distinguish some of the registers different on | |
| 1073 | ARC700 and HS38 cpus. | |
| 1074 | ||
| 7e0de605 AM |
1075 | 2017-02-14 Alan Modra <amodra@gmail.com> |
| 1076 | ||
| 1077 | PR 21118 | |
| 1078 | * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries | |
| 1079 | with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR. | |
| 1080 | ||
| 54064fdb AM |
1081 | 2017-02-11 Stafford Horne <shorne@gmail.com> |
| 1082 | Alan Modra <amodra@gmail.com> | |
| 1083 | ||
| 1084 | * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps. | |
| 1085 | Use insn_bytes_value and insn_int_value directly instead. Don't | |
| 1086 | free allocated memory until function exit. | |
| 1087 | ||
| dce75bf9 NP |
1088 | 2017-02-10 Nicholas Piggin <npiggin@gmail.com> |
| 1089 | ||
| 1090 | * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics. | |
| 1091 | ||
| 1b7e3d2f NC |
1092 | 2017-02-03 Nick Clifton <nickc@redhat.com> |
| 1093 | ||
| 1094 | PR 21096 | |
| 1095 | * aarch64-opc.c (print_register_list): Ensure that the register | |
| 1096 | list index will fir into the tb buffer. | |
| 1097 | (print_register_offset_address): Likewise. | |
| 1098 | * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf. | |
| 1099 | ||
| 8ec5cf65 AD |
1100 | 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com> |
| 1101 | ||
| 1102 | PR 21056 | |
| 1103 | * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel | |
| 1104 | instructions when the previous fetch packet ends with a 32-bit | |
| 1105 | instruction. | |
| 1106 | ||
| a1aa5e81 DD |
1107 | 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu> |
| 1108 | ||
| 1109 | * pru-opc.c: Remove vague reference to a future GDB port. | |
| 1110 | ||
| add3afb2 NC |
1111 | 2017-01-20 Nick Clifton <nickc@redhat.com> |
| 1112 | ||
| 1113 | * po/ga.po: Updated Irish translation. | |
| 1114 | ||
| c13a63b0 SN |
1115 | 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 1116 | ||
| 1117 | * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly. | |
| 1118 | ||
| 9608051a YQ |
1119 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| 1120 | ||
| 1121 | * m68k-dis.c (match_insn_m68k): Extend comments. Return -1 | |
| 1122 | if FETCH_DATA returns 0. | |
| 1123 | (m68k_scan_mask): Likewise. | |
| 1124 | (print_insn_m68k): Update code to handle -1 return value. | |
| 1125 | ||
| f622ea96 YQ |
1126 | 2017-01-13 Yao Qi <yao.qi@linaro.org> |
| 1127 | ||
| 1128 | * m68k-dis.c (enum print_insn_arg_error): New. | |
| 1129 | (NEXTBYTE): Replace -3 with | |
| 1130 | PRINT_INSN_ARG_MEMORY_ERROR. | |
| 1131 | (NEXTULONG): Likewise. | |
| 1132 | (NEXTSINGLE): Likewise. | |
| 1133 | (NEXTDOUBLE): Likewise. | |
| 1134 | (NEXTDOUBLE): Likewise. | |
| 1135 | (NEXTPACKED): Likewise. | |
| 1136 | (FETCH_ARG): Likewise. | |
| 1137 | (FETCH_DATA): Update comments. | |
| 1138 | (print_insn_arg): Update comments. Replace magic numbers with | |
| 1139 | enum. | |
| 1140 | (match_insn_m68k): Likewise. | |
| 1141 | ||
| 620214f7 IT |
1142 | 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com> |
| 1143 | ||
| 1144 | * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2. | |
| 1145 | * i386-dis-evex.h (evex_table): Updated. | |
| 1146 | * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS, | |
| 1147 | CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS. | |
| 1148 | (cpu_flags): Add CpuAVX512_VPOPCNTDQ. | |
| 1149 | * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New. | |
| 1150 | (i386_cpu_flags): Add cpuavx512_vpopcntdq. | |
| 1151 | * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions. | |
| 1152 | * i386-init.h: Regenerate. | |
| 1153 | * i386-tbl.h: Ditto. | |
| 1154 | ||
| d95014a2 YQ |
1155 | 2017-01-12 Yao Qi <yao.qi@linaro.org> |
| 1156 | ||
| 1157 | * msp430-dis.c (msp430_singleoperand): Return -1 if | |
| 1158 | msp430dis_opcode_signed returns false. | |
| 1159 | (msp430_doubleoperand): Likewise. | |
| 1160 | (msp430_branchinstr): Return -1 if | |
| 1161 | msp430dis_opcode_unsigned returns false. | |
| 1162 | (msp430x_calla_instr): Likewise. | |
| 1163 | (print_insn_msp430): Likewise. | |
| 1164 | ||
| 0ae60c3e NC |
1165 | 2017-01-05 Nick Clifton <nickc@redhat.com> |
| 1166 | ||
| 1167 | PR 20946 | |
| 1168 | * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name | |
| 1169 | could not be matched. | |
| 1170 | (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning | |
| 1171 | NULL. | |
| 1172 | ||
| d74d4880 SN |
1173 | 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com> |
| 1174 | ||
| 1175 | * aarch64-tbl.h (RCPC, RCPC_INSN): Define. | |
| 1176 | (aarch64_opcode_table): Use RCPC_INSN. | |
| 1177 | ||
| cc917fd9 KC |
1178 | 2017-01-03 Kito Cheng <kito.cheng@gmail.com> |
| 1179 | ||
| 1180 | * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA | |
| 1181 | extension. | |
| 1182 | * riscv-opcodes/all-opcodes: Likewise. | |
| 1183 | ||
| b52d3cfc DP |
1184 | 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org> |
| 1185 | ||
| 1186 | * riscv-dis.c (print_insn_args): Add fall through comment. | |
| 1187 | ||
| f90c58d5 NC |
1188 | 2017-01-03 Nick Clifton <nickc@redhat.com> |
| 1189 | ||
| 1190 | * po/sr.po: New Serbian translation. | |
| 1191 | * configure.ac (ALL_LINGUAS): Add sr. | |
| 1192 | * configure: Regenerate. | |
| 1193 | ||
| f47b0d4a AM |
1194 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| 1195 | ||
| 1196 | * epiphany-desc.h: Regenerate. | |
| 1197 | * epiphany-opc.h: Regenerate. | |
| 1198 | * fr30-desc.h: Regenerate. | |
| 1199 | * fr30-opc.h: Regenerate. | |
| 1200 | * frv-desc.h: Regenerate. | |
| 1201 | * frv-opc.h: Regenerate. | |
| 1202 | * ip2k-desc.h: Regenerate. | |
| 1203 | * ip2k-opc.h: Regenerate. | |
| 1204 | * iq2000-desc.h: Regenerate. | |
| 1205 | * iq2000-opc.h: Regenerate. | |
| 1206 | * lm32-desc.h: Regenerate. | |
| 1207 | * lm32-opc.h: Regenerate. | |
| 1208 | * m32c-desc.h: Regenerate. | |
| 1209 | * m32c-opc.h: Regenerate. | |
| 1210 | * m32r-desc.h: Regenerate. | |
| 1211 | * m32r-opc.h: Regenerate. | |
| 1212 | * mep-desc.h: Regenerate. | |
| 1213 | * mep-opc.h: Regenerate. | |
| 1214 | * mt-desc.h: Regenerate. | |
| 1215 | * mt-opc.h: Regenerate. | |
| 1216 | * or1k-desc.h: Regenerate. | |
| 1217 | * or1k-opc.h: Regenerate. | |
| 1218 | * xc16x-desc.h: Regenerate. | |
| 1219 | * xc16x-opc.h: Regenerate. | |
| 1220 | * xstormy16-desc.h: Regenerate. | |
| 1221 | * xstormy16-opc.h: Regenerate. | |
| 1222 | ||
| 2571583a AM |
1223 | 2017-01-02 Alan Modra <amodra@gmail.com> |
| 1224 | ||
| 1225 | Update year range in copyright notice of all files. | |
| 1226 | ||
| 5c1ad6b5 | 1227 | For older changes see ChangeLog-2016 |
| 3499769a | 1228 | \f |
| 5c1ad6b5 | 1229 | Copyright (C) 2017 Free Software Foundation, Inc. |
| 3499769a AM |
1230 | |
| 1231 | Copying and distribution of this file, with or without modification, | |
| 1232 | are permitted in any medium without royalty provided the copyright | |
| 1233 | notice and this notice are preserved. | |
| 1234 | ||
| 1235 | Local Variables: | |
| 1236 | mode: change-log | |
| 1237 | left-margin: 8 | |
| 1238 | fill-column: 74 | |
| 1239 | version-control: never | |
| 1240 | End: |